machdep.c revision 227442
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 227442 2011-11-11 04:10:36Z kib $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57#include "opt_kdtrace.h" 58 59#include <sys/param.h> 60#include <sys/proc.h> 61#include <sys/systm.h> 62#include <sys/bio.h> 63#include <sys/buf.h> 64#include <sys/bus.h> 65#include <sys/callout.h> 66#include <sys/cons.h> 67#include <sys/cpu.h> 68#include <sys/eventhandler.h> 69#include <sys/exec.h> 70#include <sys/imgact.h> 71#include <sys/kdb.h> 72#include <sys/kernel.h> 73#include <sys/ktr.h> 74#include <sys/linker.h> 75#include <sys/lock.h> 76#include <sys/malloc.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/sched.h> 83#include <sys/signalvar.h> 84#ifdef SMP 85#include <sys/smp.h> 86#endif 87#include <sys/syscallsubr.h> 88#include <sys/sysctl.h> 89#include <sys/sysent.h> 90#include <sys/sysproto.h> 91#include <sys/ucontext.h> 92#include <sys/vmmeter.h> 93 94#include <vm/vm.h> 95#include <vm/vm_extern.h> 96#include <vm/vm_kern.h> 97#include <vm/vm_page.h> 98#include <vm/vm_map.h> 99#include <vm/vm_object.h> 100#include <vm/vm_pager.h> 101#include <vm/vm_param.h> 102 103#ifdef DDB 104#ifndef KDB 105#error KDB must be enabled in order for DDB to work! 106#endif 107#include <ddb/ddb.h> 108#include <ddb/db_sym.h> 109#endif 110 111#include <net/netisr.h> 112 113#include <machine/clock.h> 114#include <machine/cpu.h> 115#include <machine/cputypes.h> 116#include <machine/intr_machdep.h> 117#include <x86/mca.h> 118#include <machine/md_var.h> 119#include <machine/metadata.h> 120#include <machine/mp_watchdog.h> 121#include <machine/pc/bios.h> 122#include <machine/pcb.h> 123#include <machine/proc.h> 124#include <machine/reg.h> 125#include <machine/sigframe.h> 126#include <machine/specialreg.h> 127#ifdef PERFMON 128#include <machine/perfmon.h> 129#endif 130#include <machine/tss.h> 131#ifdef SMP 132#include <machine/smp.h> 133#endif 134 135#ifdef DEV_ATPIC 136#include <x86/isa/icu.h> 137#else 138#include <machine/apicvar.h> 139#endif 140 141#include <isa/isareg.h> 142#include <isa/rtc.h> 143 144/* Sanity check for __curthread() */ 145CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 146 147extern u_int64_t hammer_time(u_int64_t, u_int64_t); 148 149extern void printcpuinfo(void); /* XXX header file */ 150extern void identify_cpu(void); 151extern void panicifcpuunsupported(void); 152 153#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 154#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 155 156static void cpu_startup(void *); 157static void get_fpcontext(struct thread *td, mcontext_t *mcp); 158static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 159SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 160 161/* 162 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 163 * the physical address at which the kernel is loaded. 164 */ 165extern char kernphys[]; 166#ifdef DDB 167extern vm_offset_t ksym_start, ksym_end; 168#endif 169 170struct msgbuf *msgbufp; 171 172/* Intel ICH registers */ 173#define ICH_PMBASE 0x400 174#define ICH_SMI_EN ICH_PMBASE + 0x30 175 176int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 177 178int cold = 1; 179 180long Maxmem = 0; 181long realmem = 0; 182 183/* 184 * The number of PHYSMAP entries must be one less than the number of 185 * PHYSSEG entries because the PHYSMAP entry that spans the largest 186 * physical address that is accessible by ISA DMA is split into two 187 * PHYSSEG entries. 188 */ 189#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 190 191vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 192vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 193 194/* must be 2 less so 0 0 can signal end of chunks */ 195#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 196#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 197 198struct kva_md_info kmi; 199 200static struct trapframe proc0_tf; 201struct region_descriptor r_gdt, r_idt; 202 203struct pcpu __pcpu[MAXCPU]; 204 205struct mtx icu_lock; 206 207struct mtx dt_lock; /* lock for GDT and LDT */ 208 209static void 210cpu_startup(dummy) 211 void *dummy; 212{ 213 uintmax_t memsize; 214 char *sysenv; 215 216 /* 217 * On MacBooks, we need to disallow the legacy USB circuit to 218 * generate an SMI# because this can cause several problems, 219 * namely: incorrect CPU frequency detection and failure to 220 * start the APs. 221 * We do this by disabling a bit in the SMI_EN (SMI Control and 222 * Enable register) of the Intel ICH LPC Interface Bridge. 223 */ 224 sysenv = getenv("smbios.system.product"); 225 if (sysenv != NULL) { 226 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 227 strncmp(sysenv, "MacBook3,1", 10) == 0 || 228 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 229 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 230 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 231 strncmp(sysenv, "Macmini1,1", 10) == 0) { 232 if (bootverbose) 233 printf("Disabling LEGACY_USB_EN bit on " 234 "Intel ICH.\n"); 235 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 236 } 237 freeenv(sysenv); 238 } 239 240 /* 241 * Good {morning,afternoon,evening,night}. 242 */ 243 startrtclock(); 244 printcpuinfo(); 245 panicifcpuunsupported(); 246#ifdef PERFMON 247 perfmon_init(); 248#endif 249 realmem = Maxmem; 250 251 /* 252 * Display physical memory if SMBIOS reports reasonable amount. 253 */ 254 memsize = 0; 255 sysenv = getenv("smbios.memory.enabled"); 256 if (sysenv != NULL) { 257 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 258 freeenv(sysenv); 259 } 260 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 261 memsize = ptoa((uintmax_t)Maxmem); 262 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 263 264 /* 265 * Display any holes after the first chunk of extended memory. 266 */ 267 if (bootverbose) { 268 int indx; 269 270 printf("Physical memory chunk(s):\n"); 271 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 272 vm_paddr_t size; 273 274 size = phys_avail[indx + 1] - phys_avail[indx]; 275 printf( 276 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 277 (uintmax_t)phys_avail[indx], 278 (uintmax_t)phys_avail[indx + 1] - 1, 279 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 280 } 281 } 282 283 vm_ksubmap_init(&kmi); 284 285 printf("avail memory = %ju (%ju MB)\n", 286 ptoa((uintmax_t)cnt.v_free_count), 287 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 288 289 /* 290 * Set up buffers, so they can be used to read disk labels. 291 */ 292 bufinit(); 293 vm_pager_bufferinit(); 294 295 cpu_setregs(); 296} 297 298/* 299 * Send an interrupt to process. 300 * 301 * Stack is set up to allow sigcode stored 302 * at top to call routine, followed by call 303 * to sigreturn routine below. After sigreturn 304 * resets the signal mask, the stack, and the 305 * frame pointer, it returns to the user 306 * specified pc, psl. 307 */ 308void 309sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 310{ 311 struct sigframe sf, *sfp; 312 struct pcb *pcb; 313 struct proc *p; 314 struct thread *td; 315 struct sigacts *psp; 316 char *sp; 317 struct trapframe *regs; 318 int sig; 319 int oonstack; 320 321 td = curthread; 322 pcb = td->td_pcb; 323 p = td->td_proc; 324 PROC_LOCK_ASSERT(p, MA_OWNED); 325 sig = ksi->ksi_signo; 326 psp = p->p_sigacts; 327 mtx_assert(&psp->ps_mtx, MA_OWNED); 328 regs = td->td_frame; 329 oonstack = sigonstack(regs->tf_rsp); 330 331 /* Save user context. */ 332 bzero(&sf, sizeof(sf)); 333 sf.sf_uc.uc_sigmask = *mask; 334 sf.sf_uc.uc_stack = td->td_sigstk; 335 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 336 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 337 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 338 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 339 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 340 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 341 fpstate_drop(td); 342 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 343 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 344 bzero(sf.sf_uc.uc_mcontext.mc_spare, 345 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 346 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 347 348 /* Allocate space for the signal handler context. */ 349 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 350 SIGISMEMBER(psp->ps_sigonstack, sig)) { 351 sp = td->td_sigstk.ss_sp + 352 td->td_sigstk.ss_size - sizeof(struct sigframe); 353#if defined(COMPAT_43) 354 td->td_sigstk.ss_flags |= SS_ONSTACK; 355#endif 356 } else 357 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 358 /* Align to 16 bytes. */ 359 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 360 361 /* Translate the signal if appropriate. */ 362 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 363 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 364 365 /* Build the argument list for the signal handler. */ 366 regs->tf_rdi = sig; /* arg 1 in %rdi */ 367 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 368 bzero(&sf.sf_si, sizeof(sf.sf_si)); 369 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 370 /* Signal handler installed with SA_SIGINFO. */ 371 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 372 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 373 374 /* Fill in POSIX parts */ 375 sf.sf_si = ksi->ksi_info; 376 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 377 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 378 } else { 379 /* Old FreeBSD-style arguments. */ 380 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 381 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 382 sf.sf_ahu.sf_handler = catcher; 383 } 384 mtx_unlock(&psp->ps_mtx); 385 PROC_UNLOCK(p); 386 387 /* 388 * Copy the sigframe out to the user's stack. 389 */ 390 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 391#ifdef DEBUG 392 printf("process %ld has trashed its stack\n", (long)p->p_pid); 393#endif 394 PROC_LOCK(p); 395 sigexit(td, SIGILL); 396 } 397 398 regs->tf_rsp = (long)sfp; 399 regs->tf_rip = p->p_sysent->sv_sigcode_base; 400 regs->tf_rflags &= ~(PSL_T | PSL_D); 401 regs->tf_cs = _ucodesel; 402 regs->tf_ds = _udatasel; 403 regs->tf_es = _udatasel; 404 regs->tf_fs = _ufssel; 405 regs->tf_gs = _ugssel; 406 regs->tf_flags = TF_HASSEGS; 407 set_pcb_flags(pcb, PCB_FULL_IRET); 408 PROC_LOCK(p); 409 mtx_lock(&psp->ps_mtx); 410} 411 412/* 413 * System call to cleanup state after a signal 414 * has been taken. Reset signal mask and 415 * stack state from context left by sendsig (above). 416 * Return to previous pc and psl as specified by 417 * context left by sendsig. Check carefully to 418 * make sure that the user has not modified the 419 * state to gain improper privileges. 420 * 421 * MPSAFE 422 */ 423int 424sys_sigreturn(td, uap) 425 struct thread *td; 426 struct sigreturn_args /* { 427 const struct __ucontext *sigcntxp; 428 } */ *uap; 429{ 430 ucontext_t uc; 431 struct pcb *pcb; 432 struct proc *p; 433 struct trapframe *regs; 434 ucontext_t *ucp; 435 long rflags; 436 int cs, error, ret; 437 ksiginfo_t ksi; 438 439 pcb = td->td_pcb; 440 p = td->td_proc; 441 442 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 443 if (error != 0) { 444 uprintf("pid %d (%s): sigreturn copyin failed\n", 445 p->p_pid, td->td_name); 446 return (error); 447 } 448 ucp = &uc; 449 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 450 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 451 td->td_name, ucp->uc_mcontext.mc_flags); 452 return (EINVAL); 453 } 454 regs = td->td_frame; 455 rflags = ucp->uc_mcontext.mc_rflags; 456 /* 457 * Don't allow users to change privileged or reserved flags. 458 */ 459 /* 460 * XXX do allow users to change the privileged flag PSL_RF. 461 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 462 * should sometimes set it there too. tf_rflags is kept in 463 * the signal context during signal handling and there is no 464 * other place to remember it, so the PSL_RF bit may be 465 * corrupted by the signal handler without us knowing. 466 * Corruption of the PSL_RF bit at worst causes one more or 467 * one less debugger trap, so allowing it is fairly harmless. 468 */ 469 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 470 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 471 td->td_name, rflags); 472 return (EINVAL); 473 } 474 475 /* 476 * Don't allow users to load a valid privileged %cs. Let the 477 * hardware check for invalid selectors, excess privilege in 478 * other selectors, invalid %eip's and invalid %esp's. 479 */ 480 cs = ucp->uc_mcontext.mc_cs; 481 if (!CS_SECURE(cs)) { 482 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 483 td->td_name, cs); 484 ksiginfo_init_trap(&ksi); 485 ksi.ksi_signo = SIGBUS; 486 ksi.ksi_code = BUS_OBJERR; 487 ksi.ksi_trapno = T_PROTFLT; 488 ksi.ksi_addr = (void *)regs->tf_rip; 489 trapsignal(td, &ksi); 490 return (EINVAL); 491 } 492 493 ret = set_fpcontext(td, &ucp->uc_mcontext); 494 if (ret != 0) { 495 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 496 p->p_pid, td->td_name, ret); 497 return (ret); 498 } 499 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 500 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 501 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 502 503#if defined(COMPAT_43) 504 if (ucp->uc_mcontext.mc_onstack & 1) 505 td->td_sigstk.ss_flags |= SS_ONSTACK; 506 else 507 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 508#endif 509 510 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 511 set_pcb_flags(pcb, PCB_FULL_IRET); 512 return (EJUSTRETURN); 513} 514 515#ifdef COMPAT_FREEBSD4 516int 517freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 518{ 519 520 return sys_sigreturn(td, (struct sigreturn_args *)uap); 521} 522#endif 523 524 525/* 526 * Machine dependent boot() routine 527 * 528 * I haven't seen anything to put here yet 529 * Possibly some stuff might be grafted back here from boot() 530 */ 531void 532cpu_boot(int howto) 533{ 534} 535 536/* 537 * Flush the D-cache for non-DMA I/O so that the I-cache can 538 * be made coherent later. 539 */ 540void 541cpu_flush_dcache(void *ptr, size_t len) 542{ 543 /* Not applicable */ 544} 545 546/* Get current clock frequency for the given cpu id. */ 547int 548cpu_est_clockrate(int cpu_id, uint64_t *rate) 549{ 550 uint64_t tsc1, tsc2; 551 uint64_t acnt, mcnt, perf; 552 register_t reg; 553 554 if (pcpu_find(cpu_id) == NULL || rate == NULL) 555 return (EINVAL); 556 557 /* 558 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 559 * DELAY(9) based logic fails. 560 */ 561 if (tsc_is_invariant && !tsc_perf_stat) 562 return (EOPNOTSUPP); 563 564#ifdef SMP 565 if (smp_cpus > 1) { 566 /* Schedule ourselves on the indicated cpu. */ 567 thread_lock(curthread); 568 sched_bind(curthread, cpu_id); 569 thread_unlock(curthread); 570 } 571#endif 572 573 /* Calibrate by measuring a short delay. */ 574 reg = intr_disable(); 575 if (tsc_is_invariant) { 576 wrmsr(MSR_MPERF, 0); 577 wrmsr(MSR_APERF, 0); 578 tsc1 = rdtsc(); 579 DELAY(1000); 580 mcnt = rdmsr(MSR_MPERF); 581 acnt = rdmsr(MSR_APERF); 582 tsc2 = rdtsc(); 583 intr_restore(reg); 584 perf = 1000 * acnt / mcnt; 585 *rate = (tsc2 - tsc1) * perf; 586 } else { 587 tsc1 = rdtsc(); 588 DELAY(1000); 589 tsc2 = rdtsc(); 590 intr_restore(reg); 591 *rate = (tsc2 - tsc1) * 1000; 592 } 593 594#ifdef SMP 595 if (smp_cpus > 1) { 596 thread_lock(curthread); 597 sched_unbind(curthread); 598 thread_unlock(curthread); 599 } 600#endif 601 602 return (0); 603} 604 605/* 606 * Shutdown the CPU as much as possible 607 */ 608void 609cpu_halt(void) 610{ 611 for (;;) 612 halt(); 613} 614 615void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 616static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 617static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 618TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 619SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 620 0, "Use MONITOR/MWAIT for short idle"); 621 622#define STATE_RUNNING 0x0 623#define STATE_MWAIT 0x1 624#define STATE_SLEEPING 0x2 625 626static void 627cpu_idle_acpi(int busy) 628{ 629 int *state; 630 631 state = (int *)PCPU_PTR(monitorbuf); 632 *state = STATE_SLEEPING; 633 634 /* See comments in cpu_idle_hlt(). */ 635 disable_intr(); 636 if (sched_runnable()) 637 enable_intr(); 638 else if (cpu_idle_hook) 639 cpu_idle_hook(); 640 else 641 __asm __volatile("sti; hlt"); 642 *state = STATE_RUNNING; 643} 644 645static void 646cpu_idle_hlt(int busy) 647{ 648 int *state; 649 650 state = (int *)PCPU_PTR(monitorbuf); 651 *state = STATE_SLEEPING; 652 653 /* 654 * Since we may be in a critical section from cpu_idle(), if 655 * an interrupt fires during that critical section we may have 656 * a pending preemption. If the CPU halts, then that thread 657 * may not execute until a later interrupt awakens the CPU. 658 * To handle this race, check for a runnable thread after 659 * disabling interrupts and immediately return if one is 660 * found. Also, we must absolutely guarentee that hlt is 661 * the next instruction after sti. This ensures that any 662 * interrupt that fires after the call to disable_intr() will 663 * immediately awaken the CPU from hlt. Finally, please note 664 * that on x86 this works fine because of interrupts enabled only 665 * after the instruction following sti takes place, while IF is set 666 * to 1 immediately, allowing hlt instruction to acknowledge the 667 * interrupt. 668 */ 669 disable_intr(); 670 if (sched_runnable()) 671 enable_intr(); 672 else 673 __asm __volatile("sti; hlt"); 674 *state = STATE_RUNNING; 675} 676 677/* 678 * MWAIT cpu power states. Lower 4 bits are sub-states. 679 */ 680#define MWAIT_C0 0xf0 681#define MWAIT_C1 0x00 682#define MWAIT_C2 0x10 683#define MWAIT_C3 0x20 684#define MWAIT_C4 0x30 685 686static void 687cpu_idle_mwait(int busy) 688{ 689 int *state; 690 691 state = (int *)PCPU_PTR(monitorbuf); 692 *state = STATE_MWAIT; 693 694 /* See comments in cpu_idle_hlt(). */ 695 disable_intr(); 696 if (sched_runnable()) { 697 enable_intr(); 698 *state = STATE_RUNNING; 699 return; 700 } 701 cpu_monitor(state, 0, 0); 702 if (*state == STATE_MWAIT) 703 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 704 else 705 enable_intr(); 706 *state = STATE_RUNNING; 707} 708 709static void 710cpu_idle_spin(int busy) 711{ 712 int *state; 713 int i; 714 715 state = (int *)PCPU_PTR(monitorbuf); 716 *state = STATE_RUNNING; 717 718 /* 719 * The sched_runnable() call is racy but as long as there is 720 * a loop missing it one time will have just a little impact if any 721 * (and it is much better than missing the check at all). 722 */ 723 for (i = 0; i < 1000; i++) { 724 if (sched_runnable()) 725 return; 726 cpu_spinwait(); 727 } 728} 729 730/* 731 * C1E renders the local APIC timer dead, so we disable it by 732 * reading the Interrupt Pending Message register and clearing 733 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 734 * 735 * Reference: 736 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 737 * #32559 revision 3.00+ 738 */ 739#define MSR_AMDK8_IPM 0xc0010055 740#define AMDK8_SMIONCMPHALT (1ULL << 27) 741#define AMDK8_C1EONCMPHALT (1ULL << 28) 742#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 743 744static void 745cpu_probe_amdc1e(void) 746{ 747 748 /* 749 * Detect the presence of C1E capability mostly on latest 750 * dual-cores (or future) k8 family. 751 */ 752 if (cpu_vendor_id == CPU_VENDOR_AMD && 753 (cpu_id & 0x00000f00) == 0x00000f00 && 754 (cpu_id & 0x0fff0000) >= 0x00040000) { 755 cpu_ident_amdc1e = 1; 756 } 757} 758 759void (*cpu_idle_fn)(int) = cpu_idle_acpi; 760 761void 762cpu_idle(int busy) 763{ 764 uint64_t msr; 765 766 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 767 busy, curcpu); 768#ifdef MP_WATCHDOG 769 ap_watchdog(PCPU_GET(cpuid)); 770#endif 771 /* If we are busy - try to use fast methods. */ 772 if (busy) { 773 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 774 cpu_idle_mwait(busy); 775 goto out; 776 } 777 } 778 779 /* If we have time - switch timers into idle mode. */ 780 if (!busy) { 781 critical_enter(); 782 cpu_idleclock(); 783 } 784 785 /* Apply AMD APIC timer C1E workaround. */ 786 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 787 msr = rdmsr(MSR_AMDK8_IPM); 788 if (msr & AMDK8_CMPHALT) 789 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 790 } 791 792 /* Call main idle method. */ 793 cpu_idle_fn(busy); 794 795 /* Switch timers mack into active mode. */ 796 if (!busy) { 797 cpu_activeclock(); 798 critical_exit(); 799 } 800out: 801 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 802 busy, curcpu); 803} 804 805int 806cpu_idle_wakeup(int cpu) 807{ 808 struct pcpu *pcpu; 809 int *state; 810 811 pcpu = pcpu_find(cpu); 812 state = (int *)pcpu->pc_monitorbuf; 813 /* 814 * This doesn't need to be atomic since missing the race will 815 * simply result in unnecessary IPIs. 816 */ 817 if (*state == STATE_SLEEPING) 818 return (0); 819 if (*state == STATE_MWAIT) 820 *state = STATE_RUNNING; 821 return (1); 822} 823 824/* 825 * Ordered by speed/power consumption. 826 */ 827struct { 828 void *id_fn; 829 char *id_name; 830} idle_tbl[] = { 831 { cpu_idle_spin, "spin" }, 832 { cpu_idle_mwait, "mwait" }, 833 { cpu_idle_hlt, "hlt" }, 834 { cpu_idle_acpi, "acpi" }, 835 { NULL, NULL } 836}; 837 838static int 839idle_sysctl_available(SYSCTL_HANDLER_ARGS) 840{ 841 char *avail, *p; 842 int error; 843 int i; 844 845 avail = malloc(256, M_TEMP, M_WAITOK); 846 p = avail; 847 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 848 if (strstr(idle_tbl[i].id_name, "mwait") && 849 (cpu_feature2 & CPUID2_MON) == 0) 850 continue; 851 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 852 cpu_idle_hook == NULL) 853 continue; 854 p += sprintf(p, "%s%s", p != avail ? ", " : "", 855 idle_tbl[i].id_name); 856 } 857 error = sysctl_handle_string(oidp, avail, 0, req); 858 free(avail, M_TEMP); 859 return (error); 860} 861 862SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 863 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 864 865static int 866idle_sysctl(SYSCTL_HANDLER_ARGS) 867{ 868 char buf[16]; 869 int error; 870 char *p; 871 int i; 872 873 p = "unknown"; 874 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 875 if (idle_tbl[i].id_fn == cpu_idle_fn) { 876 p = idle_tbl[i].id_name; 877 break; 878 } 879 } 880 strncpy(buf, p, sizeof(buf)); 881 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 882 if (error != 0 || req->newptr == NULL) 883 return (error); 884 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 885 if (strstr(idle_tbl[i].id_name, "mwait") && 886 (cpu_feature2 & CPUID2_MON) == 0) 887 continue; 888 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 889 cpu_idle_hook == NULL) 890 continue; 891 if (strcmp(idle_tbl[i].id_name, buf)) 892 continue; 893 cpu_idle_fn = idle_tbl[i].id_fn; 894 return (0); 895 } 896 return (EINVAL); 897} 898 899SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 900 idle_sysctl, "A", "currently selected idle function"); 901 902/* 903 * Reset registers to default values on exec. 904 */ 905void 906exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 907{ 908 struct trapframe *regs = td->td_frame; 909 struct pcb *pcb = td->td_pcb; 910 911 mtx_lock(&dt_lock); 912 if (td->td_proc->p_md.md_ldt != NULL) 913 user_ldt_free(td); 914 else 915 mtx_unlock(&dt_lock); 916 917 pcb->pcb_fsbase = 0; 918 pcb->pcb_gsbase = 0; 919 clear_pcb_flags(pcb, PCB_32BIT | PCB_GS32BIT); 920 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 921 set_pcb_flags(pcb, PCB_FULL_IRET); 922 923 bzero((char *)regs, sizeof(struct trapframe)); 924 regs->tf_rip = imgp->entry_addr; 925 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 926 regs->tf_rdi = stack; /* argv */ 927 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 928 regs->tf_ss = _udatasel; 929 regs->tf_cs = _ucodesel; 930 regs->tf_ds = _udatasel; 931 regs->tf_es = _udatasel; 932 regs->tf_fs = _ufssel; 933 regs->tf_gs = _ugssel; 934 regs->tf_flags = TF_HASSEGS; 935 td->td_retval[1] = 0; 936 937 /* 938 * Reset the hardware debug registers if they were in use. 939 * They won't have any meaning for the newly exec'd process. 940 */ 941 if (pcb->pcb_flags & PCB_DBREGS) { 942 pcb->pcb_dr0 = 0; 943 pcb->pcb_dr1 = 0; 944 pcb->pcb_dr2 = 0; 945 pcb->pcb_dr3 = 0; 946 pcb->pcb_dr6 = 0; 947 pcb->pcb_dr7 = 0; 948 if (pcb == PCPU_GET(curpcb)) { 949 /* 950 * Clear the debug registers on the running 951 * CPU, otherwise they will end up affecting 952 * the next process we switch to. 953 */ 954 reset_dbregs(); 955 } 956 clear_pcb_flags(pcb, PCB_DBREGS); 957 } 958 959 /* 960 * Drop the FP state if we hold it, so that the process gets a 961 * clean FP state if it uses the FPU again. 962 */ 963 fpstate_drop(td); 964} 965 966void 967cpu_setregs(void) 968{ 969 register_t cr0; 970 971 cr0 = rcr0(); 972 /* 973 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 974 * BSP. See the comments there about why we set them. 975 */ 976 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 977 load_cr0(cr0); 978} 979 980/* 981 * Initialize amd64 and configure to run kernel 982 */ 983 984/* 985 * Initialize segments & interrupt table 986 */ 987 988struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 989static struct gate_descriptor idt0[NIDT]; 990struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 991 992static char dblfault_stack[PAGE_SIZE] __aligned(16); 993 994static char nmi0_stack[PAGE_SIZE] __aligned(16); 995CTASSERT(sizeof(struct nmi_pcpu) == 16); 996 997struct amd64tss common_tss[MAXCPU]; 998 999/* 1000 * Software prototypes -- in more palatable form. 1001 * 1002 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1003 * slots as corresponding segments for i386 kernel. 1004 */ 1005struct soft_segment_descriptor gdt_segs[] = { 1006/* GNULL_SEL 0 Null Descriptor */ 1007{ .ssd_base = 0x0, 1008 .ssd_limit = 0x0, 1009 .ssd_type = 0, 1010 .ssd_dpl = 0, 1011 .ssd_p = 0, 1012 .ssd_long = 0, 1013 .ssd_def32 = 0, 1014 .ssd_gran = 0 }, 1015/* GNULL2_SEL 1 Null Descriptor */ 1016{ .ssd_base = 0x0, 1017 .ssd_limit = 0x0, 1018 .ssd_type = 0, 1019 .ssd_dpl = 0, 1020 .ssd_p = 0, 1021 .ssd_long = 0, 1022 .ssd_def32 = 0, 1023 .ssd_gran = 0 }, 1024/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1025{ .ssd_base = 0x0, 1026 .ssd_limit = 0xfffff, 1027 .ssd_type = SDT_MEMRWA, 1028 .ssd_dpl = SEL_UPL, 1029 .ssd_p = 1, 1030 .ssd_long = 0, 1031 .ssd_def32 = 1, 1032 .ssd_gran = 1 }, 1033/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1034{ .ssd_base = 0x0, 1035 .ssd_limit = 0xfffff, 1036 .ssd_type = SDT_MEMRWA, 1037 .ssd_dpl = SEL_UPL, 1038 .ssd_p = 1, 1039 .ssd_long = 0, 1040 .ssd_def32 = 1, 1041 .ssd_gran = 1 }, 1042/* GCODE_SEL 4 Code Descriptor for kernel */ 1043{ .ssd_base = 0x0, 1044 .ssd_limit = 0xfffff, 1045 .ssd_type = SDT_MEMERA, 1046 .ssd_dpl = SEL_KPL, 1047 .ssd_p = 1, 1048 .ssd_long = 1, 1049 .ssd_def32 = 0, 1050 .ssd_gran = 1 }, 1051/* GDATA_SEL 5 Data Descriptor for kernel */ 1052{ .ssd_base = 0x0, 1053 .ssd_limit = 0xfffff, 1054 .ssd_type = SDT_MEMRWA, 1055 .ssd_dpl = SEL_KPL, 1056 .ssd_p = 1, 1057 .ssd_long = 1, 1058 .ssd_def32 = 0, 1059 .ssd_gran = 1 }, 1060/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1061{ .ssd_base = 0x0, 1062 .ssd_limit = 0xfffff, 1063 .ssd_type = SDT_MEMERA, 1064 .ssd_dpl = SEL_UPL, 1065 .ssd_p = 1, 1066 .ssd_long = 0, 1067 .ssd_def32 = 1, 1068 .ssd_gran = 1 }, 1069/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1070{ .ssd_base = 0x0, 1071 .ssd_limit = 0xfffff, 1072 .ssd_type = SDT_MEMRWA, 1073 .ssd_dpl = SEL_UPL, 1074 .ssd_p = 1, 1075 .ssd_long = 0, 1076 .ssd_def32 = 1, 1077 .ssd_gran = 1 }, 1078/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1079{ .ssd_base = 0x0, 1080 .ssd_limit = 0xfffff, 1081 .ssd_type = SDT_MEMERA, 1082 .ssd_dpl = SEL_UPL, 1083 .ssd_p = 1, 1084 .ssd_long = 1, 1085 .ssd_def32 = 0, 1086 .ssd_gran = 1 }, 1087/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1088{ .ssd_base = 0x0, 1089 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1090 .ssd_type = SDT_SYSTSS, 1091 .ssd_dpl = SEL_KPL, 1092 .ssd_p = 1, 1093 .ssd_long = 0, 1094 .ssd_def32 = 0, 1095 .ssd_gran = 0 }, 1096/* Actually, the TSS is a system descriptor which is double size */ 1097{ .ssd_base = 0x0, 1098 .ssd_limit = 0x0, 1099 .ssd_type = 0, 1100 .ssd_dpl = 0, 1101 .ssd_p = 0, 1102 .ssd_long = 0, 1103 .ssd_def32 = 0, 1104 .ssd_gran = 0 }, 1105/* GUSERLDT_SEL 11 LDT Descriptor */ 1106{ .ssd_base = 0x0, 1107 .ssd_limit = 0x0, 1108 .ssd_type = 0, 1109 .ssd_dpl = 0, 1110 .ssd_p = 0, 1111 .ssd_long = 0, 1112 .ssd_def32 = 0, 1113 .ssd_gran = 0 }, 1114/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1115{ .ssd_base = 0x0, 1116 .ssd_limit = 0x0, 1117 .ssd_type = 0, 1118 .ssd_dpl = 0, 1119 .ssd_p = 0, 1120 .ssd_long = 0, 1121 .ssd_def32 = 0, 1122 .ssd_gran = 0 }, 1123}; 1124 1125void 1126setidt(idx, func, typ, dpl, ist) 1127 int idx; 1128 inthand_t *func; 1129 int typ; 1130 int dpl; 1131 int ist; 1132{ 1133 struct gate_descriptor *ip; 1134 1135 ip = idt + idx; 1136 ip->gd_looffset = (uintptr_t)func; 1137 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1138 ip->gd_ist = ist; 1139 ip->gd_xx = 0; 1140 ip->gd_type = typ; 1141 ip->gd_dpl = dpl; 1142 ip->gd_p = 1; 1143 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1144} 1145 1146extern inthand_t 1147 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1148 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1149 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1150 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1151 IDTVEC(xmm), IDTVEC(dblfault), 1152#ifdef KDTRACE_HOOKS 1153 IDTVEC(dtrace_ret), 1154#endif 1155 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1156 1157#ifdef DDB 1158/* 1159 * Display the index and function name of any IDT entries that don't use 1160 * the default 'rsvd' entry point. 1161 */ 1162DB_SHOW_COMMAND(idt, db_show_idt) 1163{ 1164 struct gate_descriptor *ip; 1165 int idx; 1166 uintptr_t func; 1167 1168 ip = idt; 1169 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1170 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1171 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1172 db_printf("%3d\t", idx); 1173 db_printsym(func, DB_STGY_PROC); 1174 db_printf("\n"); 1175 } 1176 ip++; 1177 } 1178} 1179#endif 1180 1181void 1182sdtossd(sd, ssd) 1183 struct user_segment_descriptor *sd; 1184 struct soft_segment_descriptor *ssd; 1185{ 1186 1187 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1188 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1189 ssd->ssd_type = sd->sd_type; 1190 ssd->ssd_dpl = sd->sd_dpl; 1191 ssd->ssd_p = sd->sd_p; 1192 ssd->ssd_long = sd->sd_long; 1193 ssd->ssd_def32 = sd->sd_def32; 1194 ssd->ssd_gran = sd->sd_gran; 1195} 1196 1197void 1198ssdtosd(ssd, sd) 1199 struct soft_segment_descriptor *ssd; 1200 struct user_segment_descriptor *sd; 1201{ 1202 1203 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1204 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1205 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1206 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1207 sd->sd_type = ssd->ssd_type; 1208 sd->sd_dpl = ssd->ssd_dpl; 1209 sd->sd_p = ssd->ssd_p; 1210 sd->sd_long = ssd->ssd_long; 1211 sd->sd_def32 = ssd->ssd_def32; 1212 sd->sd_gran = ssd->ssd_gran; 1213} 1214 1215void 1216ssdtosyssd(ssd, sd) 1217 struct soft_segment_descriptor *ssd; 1218 struct system_segment_descriptor *sd; 1219{ 1220 1221 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1222 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1223 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1224 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1225 sd->sd_type = ssd->ssd_type; 1226 sd->sd_dpl = ssd->ssd_dpl; 1227 sd->sd_p = ssd->ssd_p; 1228 sd->sd_gran = ssd->ssd_gran; 1229} 1230 1231#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1232#include <isa/isavar.h> 1233#include <isa/isareg.h> 1234/* 1235 * Return a bitmap of the current interrupt requests. This is 8259-specific 1236 * and is only suitable for use at probe time. 1237 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1238 * It shouldn't be here. There should probably be an APIC centric 1239 * implementation in the apic driver code, if at all. 1240 */ 1241intrmask_t 1242isa_irq_pending(void) 1243{ 1244 u_char irr1; 1245 u_char irr2; 1246 1247 irr1 = inb(IO_ICU1); 1248 irr2 = inb(IO_ICU2); 1249 return ((irr2 << 8) | irr1); 1250} 1251#endif 1252 1253u_int basemem; 1254 1255static int 1256add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1257{ 1258 int i, insert_idx, physmap_idx; 1259 1260 physmap_idx = *physmap_idxp; 1261 1262 if (boothowto & RB_VERBOSE) 1263 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1264 smap->type, smap->base, smap->length); 1265 1266 if (smap->type != SMAP_TYPE_MEMORY) 1267 return (1); 1268 1269 if (smap->length == 0) 1270 return (0); 1271 1272 /* 1273 * Find insertion point while checking for overlap. Start off by 1274 * assuming the new entry will be added to the end. 1275 */ 1276 insert_idx = physmap_idx + 2; 1277 for (i = 0; i <= physmap_idx; i += 2) { 1278 if (smap->base < physmap[i + 1]) { 1279 if (smap->base + smap->length <= physmap[i]) { 1280 insert_idx = i; 1281 break; 1282 } 1283 if (boothowto & RB_VERBOSE) 1284 printf( 1285 "Overlapping memory regions, ignoring second region\n"); 1286 return (1); 1287 } 1288 } 1289 1290 /* See if we can prepend to the next entry. */ 1291 if (insert_idx <= physmap_idx && 1292 smap->base + smap->length == physmap[insert_idx]) { 1293 physmap[insert_idx] = smap->base; 1294 return (1); 1295 } 1296 1297 /* See if we can append to the previous entry. */ 1298 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1299 physmap[insert_idx - 1] += smap->length; 1300 return (1); 1301 } 1302 1303 physmap_idx += 2; 1304 *physmap_idxp = physmap_idx; 1305 if (physmap_idx == PHYSMAP_SIZE) { 1306 printf( 1307 "Too many segments in the physical address map, giving up\n"); 1308 return (0); 1309 } 1310 1311 /* 1312 * Move the last 'N' entries down to make room for the new 1313 * entry if needed. 1314 */ 1315 for (i = physmap_idx; i > insert_idx; i -= 2) { 1316 physmap[i] = physmap[i - 2]; 1317 physmap[i + 1] = physmap[i - 1]; 1318 } 1319 1320 /* Insert the new entry. */ 1321 physmap[insert_idx] = smap->base; 1322 physmap[insert_idx + 1] = smap->base + smap->length; 1323 return (1); 1324} 1325 1326/* 1327 * Populate the (physmap) array with base/bound pairs describing the 1328 * available physical memory in the system, then test this memory and 1329 * build the phys_avail array describing the actually-available memory. 1330 * 1331 * Total memory size may be set by the kernel environment variable 1332 * hw.physmem or the compile-time define MAXMEM. 1333 * 1334 * XXX first should be vm_paddr_t. 1335 */ 1336static void 1337getmemsize(caddr_t kmdp, u_int64_t first) 1338{ 1339 int i, physmap_idx, pa_indx, da_indx; 1340 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1341 u_long physmem_tunable, memtest; 1342 pt_entry_t *pte; 1343 struct bios_smap *smapbase, *smap, *smapend; 1344 u_int32_t smapsize; 1345 quad_t dcons_addr, dcons_size; 1346 1347 bzero(physmap, sizeof(physmap)); 1348 basemem = 0; 1349 physmap_idx = 0; 1350 1351 /* 1352 * get memory map from INT 15:E820, kindly supplied by the loader. 1353 * 1354 * subr_module.c says: 1355 * "Consumer may safely assume that size value precedes data." 1356 * ie: an int32_t immediately precedes smap. 1357 */ 1358 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1359 MODINFO_METADATA | MODINFOMD_SMAP); 1360 if (smapbase == NULL) 1361 panic("No BIOS smap info from loader!"); 1362 1363 smapsize = *((u_int32_t *)smapbase - 1); 1364 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1365 1366 for (smap = smapbase; smap < smapend; smap++) 1367 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1368 break; 1369 1370 /* 1371 * Find the 'base memory' segment for SMP 1372 */ 1373 basemem = 0; 1374 for (i = 0; i <= physmap_idx; i += 2) { 1375 if (physmap[i] == 0x00000000) { 1376 basemem = physmap[i + 1] / 1024; 1377 break; 1378 } 1379 } 1380 if (basemem == 0) 1381 panic("BIOS smap did not include a basemem segment!"); 1382 1383#ifdef SMP 1384 /* make hole for AP bootstrap code */ 1385 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1386#endif 1387 1388 /* 1389 * Maxmem isn't the "maximum memory", it's one larger than the 1390 * highest page of the physical address space. It should be 1391 * called something like "Maxphyspage". We may adjust this 1392 * based on ``hw.physmem'' and the results of the memory test. 1393 */ 1394 Maxmem = atop(physmap[physmap_idx + 1]); 1395 1396#ifdef MAXMEM 1397 Maxmem = MAXMEM / 4; 1398#endif 1399 1400 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1401 Maxmem = atop(physmem_tunable); 1402 1403 /* 1404 * By default keep the memtest enabled. Use a general name so that 1405 * one could eventually do more with the code than just disable it. 1406 */ 1407 memtest = 1; 1408 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1409 1410 /* 1411 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1412 * in the system. 1413 */ 1414 if (Maxmem > atop(physmap[physmap_idx + 1])) 1415 Maxmem = atop(physmap[physmap_idx + 1]); 1416 1417 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1418 (boothowto & RB_VERBOSE)) 1419 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1420 1421 /* call pmap initialization to make new kernel address space */ 1422 pmap_bootstrap(&first); 1423 1424 /* 1425 * Size up each available chunk of physical memory. 1426 */ 1427 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1428 pa_indx = 0; 1429 da_indx = 1; 1430 phys_avail[pa_indx++] = physmap[0]; 1431 phys_avail[pa_indx] = physmap[0]; 1432 dump_avail[da_indx] = physmap[0]; 1433 pte = CMAP1; 1434 1435 /* 1436 * Get dcons buffer address 1437 */ 1438 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1439 getenv_quad("dcons.size", &dcons_size) == 0) 1440 dcons_addr = 0; 1441 1442 /* 1443 * physmap is in bytes, so when converting to page boundaries, 1444 * round up the start address and round down the end address. 1445 */ 1446 for (i = 0; i <= physmap_idx; i += 2) { 1447 vm_paddr_t end; 1448 1449 end = ptoa((vm_paddr_t)Maxmem); 1450 if (physmap[i + 1] < end) 1451 end = trunc_page(physmap[i + 1]); 1452 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1453 int tmp, page_bad, full; 1454 int *ptr = (int *)CADDR1; 1455 1456 full = FALSE; 1457 /* 1458 * block out kernel memory as not available. 1459 */ 1460 if (pa >= (vm_paddr_t)kernphys && pa < first) 1461 goto do_dump_avail; 1462 1463 /* 1464 * block out dcons buffer 1465 */ 1466 if (dcons_addr > 0 1467 && pa >= trunc_page(dcons_addr) 1468 && pa < dcons_addr + dcons_size) 1469 goto do_dump_avail; 1470 1471 page_bad = FALSE; 1472 if (memtest == 0) 1473 goto skip_memtest; 1474 1475 /* 1476 * map page into kernel: valid, read/write,non-cacheable 1477 */ 1478 *pte = pa | PG_V | PG_RW | PG_N; 1479 invltlb(); 1480 1481 tmp = *(int *)ptr; 1482 /* 1483 * Test for alternating 1's and 0's 1484 */ 1485 *(volatile int *)ptr = 0xaaaaaaaa; 1486 if (*(volatile int *)ptr != 0xaaaaaaaa) 1487 page_bad = TRUE; 1488 /* 1489 * Test for alternating 0's and 1's 1490 */ 1491 *(volatile int *)ptr = 0x55555555; 1492 if (*(volatile int *)ptr != 0x55555555) 1493 page_bad = TRUE; 1494 /* 1495 * Test for all 1's 1496 */ 1497 *(volatile int *)ptr = 0xffffffff; 1498 if (*(volatile int *)ptr != 0xffffffff) 1499 page_bad = TRUE; 1500 /* 1501 * Test for all 0's 1502 */ 1503 *(volatile int *)ptr = 0x0; 1504 if (*(volatile int *)ptr != 0x0) 1505 page_bad = TRUE; 1506 /* 1507 * Restore original value. 1508 */ 1509 *(int *)ptr = tmp; 1510 1511skip_memtest: 1512 /* 1513 * Adjust array of valid/good pages. 1514 */ 1515 if (page_bad == TRUE) 1516 continue; 1517 /* 1518 * If this good page is a continuation of the 1519 * previous set of good pages, then just increase 1520 * the end pointer. Otherwise start a new chunk. 1521 * Note that "end" points one higher than end, 1522 * making the range >= start and < end. 1523 * If we're also doing a speculative memory 1524 * test and we at or past the end, bump up Maxmem 1525 * so that we keep going. The first bad page 1526 * will terminate the loop. 1527 */ 1528 if (phys_avail[pa_indx] == pa) { 1529 phys_avail[pa_indx] += PAGE_SIZE; 1530 } else { 1531 pa_indx++; 1532 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1533 printf( 1534 "Too many holes in the physical address space, giving up\n"); 1535 pa_indx--; 1536 full = TRUE; 1537 goto do_dump_avail; 1538 } 1539 phys_avail[pa_indx++] = pa; /* start */ 1540 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1541 } 1542 physmem++; 1543do_dump_avail: 1544 if (dump_avail[da_indx] == pa) { 1545 dump_avail[da_indx] += PAGE_SIZE; 1546 } else { 1547 da_indx++; 1548 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1549 da_indx--; 1550 goto do_next; 1551 } 1552 dump_avail[da_indx++] = pa; /* start */ 1553 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1554 } 1555do_next: 1556 if (full) 1557 break; 1558 } 1559 } 1560 *pte = 0; 1561 invltlb(); 1562 1563 /* 1564 * XXX 1565 * The last chunk must contain at least one page plus the message 1566 * buffer to avoid complicating other code (message buffer address 1567 * calculation, etc.). 1568 */ 1569 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1570 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1571 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1572 phys_avail[pa_indx--] = 0; 1573 phys_avail[pa_indx--] = 0; 1574 } 1575 1576 Maxmem = atop(phys_avail[pa_indx]); 1577 1578 /* Trim off space for the message buffer. */ 1579 phys_avail[pa_indx] -= round_page(msgbufsize); 1580 1581 /* Map the message buffer. */ 1582 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1583} 1584 1585u_int64_t 1586hammer_time(u_int64_t modulep, u_int64_t physfree) 1587{ 1588 caddr_t kmdp; 1589 int gsel_tss, x; 1590 struct pcpu *pc; 1591 struct nmi_pcpu *np; 1592 u_int64_t msr; 1593 char *env; 1594 size_t kstack0_sz; 1595 1596 thread0.td_kstack = physfree + KERNBASE; 1597 thread0.td_kstack_pages = KSTACK_PAGES; 1598 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1599 bzero((void *)thread0.td_kstack, kstack0_sz); 1600 physfree += kstack0_sz; 1601 thread0.td_pcb = (struct pcb *)(thread0.td_kstack + kstack0_sz) - 1; 1602 1603 /* 1604 * This may be done better later if it gets more high level 1605 * components in it. If so just link td->td_proc here. 1606 */ 1607 proc_linkup0(&proc0, &thread0); 1608 1609 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1610 preload_bootstrap_relocate(KERNBASE); 1611 kmdp = preload_search_by_type("elf kernel"); 1612 if (kmdp == NULL) 1613 kmdp = preload_search_by_type("elf64 kernel"); 1614 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1615 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1616#ifdef DDB 1617 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1618 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1619#endif 1620 1621 /* Init basic tunables, hz etc */ 1622 init_param1(); 1623 1624 /* 1625 * make gdt memory segments 1626 */ 1627 for (x = 0; x < NGDT; x++) { 1628 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1629 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1630 ssdtosd(&gdt_segs[x], &gdt[x]); 1631 } 1632 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1633 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1634 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1635 1636 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1637 r_gdt.rd_base = (long) gdt; 1638 lgdt(&r_gdt); 1639 pc = &__pcpu[0]; 1640 1641 wrmsr(MSR_FSBASE, 0); /* User value */ 1642 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1643 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1644 1645 pcpu_init(pc, 0, sizeof(struct pcpu)); 1646 dpcpu_init((void *)(physfree + KERNBASE), 0); 1647 physfree += DPCPU_SIZE; 1648 PCPU_SET(prvspace, pc); 1649 PCPU_SET(curthread, &thread0); 1650 PCPU_SET(curpcb, thread0.td_pcb); 1651 PCPU_SET(tssp, &common_tss[0]); 1652 PCPU_SET(commontssp, &common_tss[0]); 1653 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1654 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1655 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1656 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1657 1658 /* 1659 * Initialize mutexes. 1660 * 1661 * icu_lock: in order to allow an interrupt to occur in a critical 1662 * section, to set pcpu->ipending (etc...) properly, we 1663 * must be able to get the icu lock, so it can't be 1664 * under witness. 1665 */ 1666 mutex_init(); 1667 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1668 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1669 1670 /* exceptions */ 1671 for (x = 0; x < NIDT; x++) 1672 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1673 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1674 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1675 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1676 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1677 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1678 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1679 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1680 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1681 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1682 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1683 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1684 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1685 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1686 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1687 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1688 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1689 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1690 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1691 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1692#ifdef KDTRACE_HOOKS 1693 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1694#endif 1695 1696 r_idt.rd_limit = sizeof(idt0) - 1; 1697 r_idt.rd_base = (long) idt; 1698 lidt(&r_idt); 1699 1700 /* 1701 * Initialize the i8254 before the console so that console 1702 * initialization can use DELAY(). 1703 */ 1704 i8254_init(); 1705 1706 /* 1707 * Initialize the console before we print anything out. 1708 */ 1709 cninit(); 1710 1711#ifdef DEV_ISA 1712#ifdef DEV_ATPIC 1713 elcr_probe(); 1714 atpic_startup(); 1715#else 1716 /* Reset and mask the atpics and leave them shut down. */ 1717 atpic_reset(); 1718 1719 /* 1720 * Point the ICU spurious interrupt vectors at the APIC spurious 1721 * interrupt handler. 1722 */ 1723 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1724 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1725#endif 1726#else 1727#error "have you forgotten the isa device?"; 1728#endif 1729 1730 kdb_init(); 1731 1732#ifdef KDB 1733 if (boothowto & RB_KDB) 1734 kdb_enter(KDB_WHY_BOOTFLAGS, 1735 "Boot flags requested debugger"); 1736#endif 1737 1738 identify_cpu(); /* Final stage of CPU initialization */ 1739 initializecpu(); /* Initialize CPU registers */ 1740 initializecpucache(); 1741 1742 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1743 common_tss[0].tss_rsp0 = thread0.td_kstack + 1744 kstack0_sz - sizeof(struct pcb); 1745 /* Ensure the stack is aligned to 16 bytes */ 1746 common_tss[0].tss_rsp0 &= ~0xFul; 1747 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1748 1749 /* doublefault stack space, runs on ist1 */ 1750 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1751 1752 /* 1753 * NMI stack, runs on ist2. The pcpu pointer is stored just 1754 * above the start of the ist2 stack. 1755 */ 1756 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1757 np->np_pcpu = (register_t) pc; 1758 common_tss[0].tss_ist2 = (long) np; 1759 1760 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1761 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1762 IOPAGES * PAGE_SIZE; 1763 1764 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1765 ltr(gsel_tss); 1766 1767 /* Set up the fast syscall stuff */ 1768 msr = rdmsr(MSR_EFER) | EFER_SCE; 1769 wrmsr(MSR_EFER, msr); 1770 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1771 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1772 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1773 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1774 wrmsr(MSR_STAR, msr); 1775 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1776 1777 getmemsize(kmdp, physfree); 1778 init_param2(physmem); 1779 1780 /* now running on new page tables, configured,and u/iom is accessible */ 1781 1782 msgbufinit(msgbufp, msgbufsize); 1783 fpuinit(); 1784 1785 /* transfer to user mode */ 1786 1787 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1788 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1789 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1790 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1791 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1792 1793 load_ds(_udatasel); 1794 load_es(_udatasel); 1795 load_fs(_ufssel); 1796 1797 /* setup proc 0's pcb */ 1798 thread0.td_pcb->pcb_flags = 0; 1799 thread0.td_pcb->pcb_cr3 = KPML4phys; 1800 thread0.td_frame = &proc0_tf; 1801 1802 env = getenv("kernelname"); 1803 if (env != NULL) 1804 strlcpy(kernelname, env, sizeof(kernelname)); 1805 1806#ifdef XENHVM 1807 if (inw(0x10) == 0x49d2) { 1808 if (bootverbose) 1809 printf("Xen detected: disabling emulated block and network devices\n"); 1810 outw(0x10, 3); 1811 } 1812#endif 1813 1814 cpu_probe_amdc1e(); 1815 1816 /* Location of kernel stack for locore */ 1817 return ((u_int64_t)thread0.td_pcb); 1818} 1819 1820void 1821cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1822{ 1823 1824 pcpu->pc_acpi_id = 0xffffffff; 1825} 1826 1827void 1828spinlock_enter(void) 1829{ 1830 struct thread *td; 1831 register_t flags; 1832 1833 td = curthread; 1834 if (td->td_md.md_spinlock_count == 0) { 1835 flags = intr_disable(); 1836 td->td_md.md_spinlock_count = 1; 1837 td->td_md.md_saved_flags = flags; 1838 } else 1839 td->td_md.md_spinlock_count++; 1840 critical_enter(); 1841} 1842 1843void 1844spinlock_exit(void) 1845{ 1846 struct thread *td; 1847 register_t flags; 1848 1849 td = curthread; 1850 critical_exit(); 1851 flags = td->td_md.md_saved_flags; 1852 td->td_md.md_spinlock_count--; 1853 if (td->td_md.md_spinlock_count == 0) 1854 intr_restore(flags); 1855} 1856 1857/* 1858 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1859 * we want to start a backtrace from the function that caused us to enter 1860 * the debugger. We have the context in the trapframe, but base the trace 1861 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1862 * enough for a backtrace. 1863 */ 1864void 1865makectx(struct trapframe *tf, struct pcb *pcb) 1866{ 1867 1868 pcb->pcb_r12 = tf->tf_r12; 1869 pcb->pcb_r13 = tf->tf_r13; 1870 pcb->pcb_r14 = tf->tf_r14; 1871 pcb->pcb_r15 = tf->tf_r15; 1872 pcb->pcb_rbp = tf->tf_rbp; 1873 pcb->pcb_rbx = tf->tf_rbx; 1874 pcb->pcb_rip = tf->tf_rip; 1875 pcb->pcb_rsp = tf->tf_rsp; 1876} 1877 1878int 1879ptrace_set_pc(struct thread *td, unsigned long addr) 1880{ 1881 td->td_frame->tf_rip = addr; 1882 return (0); 1883} 1884 1885int 1886ptrace_single_step(struct thread *td) 1887{ 1888 td->td_frame->tf_rflags |= PSL_T; 1889 return (0); 1890} 1891 1892int 1893ptrace_clear_single_step(struct thread *td) 1894{ 1895 td->td_frame->tf_rflags &= ~PSL_T; 1896 return (0); 1897} 1898 1899int 1900fill_regs(struct thread *td, struct reg *regs) 1901{ 1902 struct trapframe *tp; 1903 1904 tp = td->td_frame; 1905 return (fill_frame_regs(tp, regs)); 1906} 1907 1908int 1909fill_frame_regs(struct trapframe *tp, struct reg *regs) 1910{ 1911 regs->r_r15 = tp->tf_r15; 1912 regs->r_r14 = tp->tf_r14; 1913 regs->r_r13 = tp->tf_r13; 1914 regs->r_r12 = tp->tf_r12; 1915 regs->r_r11 = tp->tf_r11; 1916 regs->r_r10 = tp->tf_r10; 1917 regs->r_r9 = tp->tf_r9; 1918 regs->r_r8 = tp->tf_r8; 1919 regs->r_rdi = tp->tf_rdi; 1920 regs->r_rsi = tp->tf_rsi; 1921 regs->r_rbp = tp->tf_rbp; 1922 regs->r_rbx = tp->tf_rbx; 1923 regs->r_rdx = tp->tf_rdx; 1924 regs->r_rcx = tp->tf_rcx; 1925 regs->r_rax = tp->tf_rax; 1926 regs->r_rip = tp->tf_rip; 1927 regs->r_cs = tp->tf_cs; 1928 regs->r_rflags = tp->tf_rflags; 1929 regs->r_rsp = tp->tf_rsp; 1930 regs->r_ss = tp->tf_ss; 1931 if (tp->tf_flags & TF_HASSEGS) { 1932 regs->r_ds = tp->tf_ds; 1933 regs->r_es = tp->tf_es; 1934 regs->r_fs = tp->tf_fs; 1935 regs->r_gs = tp->tf_gs; 1936 } else { 1937 regs->r_ds = 0; 1938 regs->r_es = 0; 1939 regs->r_fs = 0; 1940 regs->r_gs = 0; 1941 } 1942 return (0); 1943} 1944 1945int 1946set_regs(struct thread *td, struct reg *regs) 1947{ 1948 struct trapframe *tp; 1949 register_t rflags; 1950 1951 tp = td->td_frame; 1952 rflags = regs->r_rflags & 0xffffffff; 1953 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1954 return (EINVAL); 1955 tp->tf_r15 = regs->r_r15; 1956 tp->tf_r14 = regs->r_r14; 1957 tp->tf_r13 = regs->r_r13; 1958 tp->tf_r12 = regs->r_r12; 1959 tp->tf_r11 = regs->r_r11; 1960 tp->tf_r10 = regs->r_r10; 1961 tp->tf_r9 = regs->r_r9; 1962 tp->tf_r8 = regs->r_r8; 1963 tp->tf_rdi = regs->r_rdi; 1964 tp->tf_rsi = regs->r_rsi; 1965 tp->tf_rbp = regs->r_rbp; 1966 tp->tf_rbx = regs->r_rbx; 1967 tp->tf_rdx = regs->r_rdx; 1968 tp->tf_rcx = regs->r_rcx; 1969 tp->tf_rax = regs->r_rax; 1970 tp->tf_rip = regs->r_rip; 1971 tp->tf_cs = regs->r_cs; 1972 tp->tf_rflags = rflags; 1973 tp->tf_rsp = regs->r_rsp; 1974 tp->tf_ss = regs->r_ss; 1975 if (0) { /* XXXKIB */ 1976 tp->tf_ds = regs->r_ds; 1977 tp->tf_es = regs->r_es; 1978 tp->tf_fs = regs->r_fs; 1979 tp->tf_gs = regs->r_gs; 1980 tp->tf_flags = TF_HASSEGS; 1981 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 1982 } 1983 return (0); 1984} 1985 1986/* XXX check all this stuff! */ 1987/* externalize from sv_xmm */ 1988static void 1989fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1990{ 1991 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1992 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1993 int i; 1994 1995 /* pcb -> fpregs */ 1996 bzero(fpregs, sizeof(*fpregs)); 1997 1998 /* FPU control/status */ 1999 penv_fpreg->en_cw = penv_xmm->en_cw; 2000 penv_fpreg->en_sw = penv_xmm->en_sw; 2001 penv_fpreg->en_tw = penv_xmm->en_tw; 2002 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2003 penv_fpreg->en_rip = penv_xmm->en_rip; 2004 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2005 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2006 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2007 2008 /* FPU registers */ 2009 for (i = 0; i < 8; ++i) 2010 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2011 2012 /* SSE registers */ 2013 for (i = 0; i < 16; ++i) 2014 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2015} 2016 2017/* internalize from fpregs into sv_xmm */ 2018static void 2019set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2020{ 2021 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2022 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2023 int i; 2024 2025 /* fpregs -> pcb */ 2026 /* FPU control/status */ 2027 penv_xmm->en_cw = penv_fpreg->en_cw; 2028 penv_xmm->en_sw = penv_fpreg->en_sw; 2029 penv_xmm->en_tw = penv_fpreg->en_tw; 2030 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2031 penv_xmm->en_rip = penv_fpreg->en_rip; 2032 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2033 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2034 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2035 2036 /* FPU registers */ 2037 for (i = 0; i < 8; ++i) 2038 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2039 2040 /* SSE registers */ 2041 for (i = 0; i < 16; ++i) 2042 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2043} 2044 2045/* externalize from td->pcb */ 2046int 2047fill_fpregs(struct thread *td, struct fpreg *fpregs) 2048{ 2049 2050 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2051 P_SHOULDSTOP(td->td_proc), 2052 ("not suspended thread %p", td)); 2053 fpugetregs(td); 2054 fill_fpregs_xmm(&td->td_pcb->pcb_user_save, fpregs); 2055 return (0); 2056} 2057 2058/* internalize to td->pcb */ 2059int 2060set_fpregs(struct thread *td, struct fpreg *fpregs) 2061{ 2062 2063 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_user_save); 2064 fpuuserinited(td); 2065 return (0); 2066} 2067 2068/* 2069 * Get machine context. 2070 */ 2071int 2072get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2073{ 2074 struct pcb *pcb; 2075 struct trapframe *tp; 2076 2077 pcb = td->td_pcb; 2078 tp = td->td_frame; 2079 PROC_LOCK(curthread->td_proc); 2080 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2081 PROC_UNLOCK(curthread->td_proc); 2082 mcp->mc_r15 = tp->tf_r15; 2083 mcp->mc_r14 = tp->tf_r14; 2084 mcp->mc_r13 = tp->tf_r13; 2085 mcp->mc_r12 = tp->tf_r12; 2086 mcp->mc_r11 = tp->tf_r11; 2087 mcp->mc_r10 = tp->tf_r10; 2088 mcp->mc_r9 = tp->tf_r9; 2089 mcp->mc_r8 = tp->tf_r8; 2090 mcp->mc_rdi = tp->tf_rdi; 2091 mcp->mc_rsi = tp->tf_rsi; 2092 mcp->mc_rbp = tp->tf_rbp; 2093 mcp->mc_rbx = tp->tf_rbx; 2094 mcp->mc_rcx = tp->tf_rcx; 2095 mcp->mc_rflags = tp->tf_rflags; 2096 if (flags & GET_MC_CLEAR_RET) { 2097 mcp->mc_rax = 0; 2098 mcp->mc_rdx = 0; 2099 mcp->mc_rflags &= ~PSL_C; 2100 } else { 2101 mcp->mc_rax = tp->tf_rax; 2102 mcp->mc_rdx = tp->tf_rdx; 2103 } 2104 mcp->mc_rip = tp->tf_rip; 2105 mcp->mc_cs = tp->tf_cs; 2106 mcp->mc_rsp = tp->tf_rsp; 2107 mcp->mc_ss = tp->tf_ss; 2108 mcp->mc_ds = tp->tf_ds; 2109 mcp->mc_es = tp->tf_es; 2110 mcp->mc_fs = tp->tf_fs; 2111 mcp->mc_gs = tp->tf_gs; 2112 mcp->mc_flags = tp->tf_flags; 2113 mcp->mc_len = sizeof(*mcp); 2114 get_fpcontext(td, mcp); 2115 mcp->mc_fsbase = pcb->pcb_fsbase; 2116 mcp->mc_gsbase = pcb->pcb_gsbase; 2117 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2118 return (0); 2119} 2120 2121/* 2122 * Set machine context. 2123 * 2124 * However, we don't set any but the user modifiable flags, and we won't 2125 * touch the cs selector. 2126 */ 2127int 2128set_mcontext(struct thread *td, const mcontext_t *mcp) 2129{ 2130 struct pcb *pcb; 2131 struct trapframe *tp; 2132 long rflags; 2133 int ret; 2134 2135 pcb = td->td_pcb; 2136 tp = td->td_frame; 2137 if (mcp->mc_len != sizeof(*mcp) || 2138 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2139 return (EINVAL); 2140 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2141 (tp->tf_rflags & ~PSL_USERCHANGE); 2142 ret = set_fpcontext(td, mcp); 2143 if (ret != 0) 2144 return (ret); 2145 tp->tf_r15 = mcp->mc_r15; 2146 tp->tf_r14 = mcp->mc_r14; 2147 tp->tf_r13 = mcp->mc_r13; 2148 tp->tf_r12 = mcp->mc_r12; 2149 tp->tf_r11 = mcp->mc_r11; 2150 tp->tf_r10 = mcp->mc_r10; 2151 tp->tf_r9 = mcp->mc_r9; 2152 tp->tf_r8 = mcp->mc_r8; 2153 tp->tf_rdi = mcp->mc_rdi; 2154 tp->tf_rsi = mcp->mc_rsi; 2155 tp->tf_rbp = mcp->mc_rbp; 2156 tp->tf_rbx = mcp->mc_rbx; 2157 tp->tf_rdx = mcp->mc_rdx; 2158 tp->tf_rcx = mcp->mc_rcx; 2159 tp->tf_rax = mcp->mc_rax; 2160 tp->tf_rip = mcp->mc_rip; 2161 tp->tf_rflags = rflags; 2162 tp->tf_rsp = mcp->mc_rsp; 2163 tp->tf_ss = mcp->mc_ss; 2164 tp->tf_flags = mcp->mc_flags; 2165 if (tp->tf_flags & TF_HASSEGS) { 2166 tp->tf_ds = mcp->mc_ds; 2167 tp->tf_es = mcp->mc_es; 2168 tp->tf_fs = mcp->mc_fs; 2169 tp->tf_gs = mcp->mc_gs; 2170 } 2171 if (mcp->mc_flags & _MC_HASBASES) { 2172 pcb->pcb_fsbase = mcp->mc_fsbase; 2173 pcb->pcb_gsbase = mcp->mc_gsbase; 2174 } 2175 set_pcb_flags(pcb, PCB_FULL_IRET); 2176 return (0); 2177} 2178 2179static void 2180get_fpcontext(struct thread *td, mcontext_t *mcp) 2181{ 2182 2183 mcp->mc_ownedfp = fpugetregs(td); 2184 bcopy(&td->td_pcb->pcb_user_save, &mcp->mc_fpstate, 2185 sizeof(mcp->mc_fpstate)); 2186 mcp->mc_fpformat = fpuformat(); 2187} 2188 2189static int 2190set_fpcontext(struct thread *td, const mcontext_t *mcp) 2191{ 2192 struct savefpu *fpstate; 2193 2194 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2195 return (0); 2196 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2197 return (EINVAL); 2198 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2199 /* We don't care what state is left in the FPU or PCB. */ 2200 fpstate_drop(td); 2201 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2202 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2203 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2204 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2205 fpusetregs(td, fpstate); 2206 } else 2207 return (EINVAL); 2208 return (0); 2209} 2210 2211void 2212fpstate_drop(struct thread *td) 2213{ 2214 2215 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2216 critical_enter(); 2217 if (PCPU_GET(fpcurthread) == td) 2218 fpudrop(); 2219 /* 2220 * XXX force a full drop of the fpu. The above only drops it if we 2221 * owned it. 2222 * 2223 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2224 * drop. Dropping only to the pcb matches fnsave's behaviour. 2225 * We only need to drop to !PCB_INITDONE in sendsig(). But 2226 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2227 * have too many layers. 2228 */ 2229 clear_pcb_flags(curthread->td_pcb, 2230 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2231 critical_exit(); 2232} 2233 2234int 2235fill_dbregs(struct thread *td, struct dbreg *dbregs) 2236{ 2237 struct pcb *pcb; 2238 2239 if (td == NULL) { 2240 dbregs->dr[0] = rdr0(); 2241 dbregs->dr[1] = rdr1(); 2242 dbregs->dr[2] = rdr2(); 2243 dbregs->dr[3] = rdr3(); 2244 dbregs->dr[6] = rdr6(); 2245 dbregs->dr[7] = rdr7(); 2246 } else { 2247 pcb = td->td_pcb; 2248 dbregs->dr[0] = pcb->pcb_dr0; 2249 dbregs->dr[1] = pcb->pcb_dr1; 2250 dbregs->dr[2] = pcb->pcb_dr2; 2251 dbregs->dr[3] = pcb->pcb_dr3; 2252 dbregs->dr[6] = pcb->pcb_dr6; 2253 dbregs->dr[7] = pcb->pcb_dr7; 2254 } 2255 dbregs->dr[4] = 0; 2256 dbregs->dr[5] = 0; 2257 dbregs->dr[8] = 0; 2258 dbregs->dr[9] = 0; 2259 dbregs->dr[10] = 0; 2260 dbregs->dr[11] = 0; 2261 dbregs->dr[12] = 0; 2262 dbregs->dr[13] = 0; 2263 dbregs->dr[14] = 0; 2264 dbregs->dr[15] = 0; 2265 return (0); 2266} 2267 2268int 2269set_dbregs(struct thread *td, struct dbreg *dbregs) 2270{ 2271 struct pcb *pcb; 2272 int i; 2273 2274 if (td == NULL) { 2275 load_dr0(dbregs->dr[0]); 2276 load_dr1(dbregs->dr[1]); 2277 load_dr2(dbregs->dr[2]); 2278 load_dr3(dbregs->dr[3]); 2279 load_dr6(dbregs->dr[6]); 2280 load_dr7(dbregs->dr[7]); 2281 } else { 2282 /* 2283 * Don't let an illegal value for dr7 get set. Specifically, 2284 * check for undefined settings. Setting these bit patterns 2285 * result in undefined behaviour and can lead to an unexpected 2286 * TRCTRAP or a general protection fault right here. 2287 * Upper bits of dr6 and dr7 must not be set 2288 */ 2289 for (i = 0; i < 4; i++) { 2290 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2291 return (EINVAL); 2292 if (td->td_frame->tf_cs == _ucode32sel && 2293 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2294 return (EINVAL); 2295 } 2296 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2297 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2298 return (EINVAL); 2299 2300 pcb = td->td_pcb; 2301 2302 /* 2303 * Don't let a process set a breakpoint that is not within the 2304 * process's address space. If a process could do this, it 2305 * could halt the system by setting a breakpoint in the kernel 2306 * (if ddb was enabled). Thus, we need to check to make sure 2307 * that no breakpoints are being enabled for addresses outside 2308 * process's address space. 2309 * 2310 * XXX - what about when the watched area of the user's 2311 * address space is written into from within the kernel 2312 * ... wouldn't that still cause a breakpoint to be generated 2313 * from within kernel mode? 2314 */ 2315 2316 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2317 /* dr0 is enabled */ 2318 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2319 return (EINVAL); 2320 } 2321 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2322 /* dr1 is enabled */ 2323 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2324 return (EINVAL); 2325 } 2326 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2327 /* dr2 is enabled */ 2328 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2329 return (EINVAL); 2330 } 2331 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2332 /* dr3 is enabled */ 2333 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2334 return (EINVAL); 2335 } 2336 2337 pcb->pcb_dr0 = dbregs->dr[0]; 2338 pcb->pcb_dr1 = dbregs->dr[1]; 2339 pcb->pcb_dr2 = dbregs->dr[2]; 2340 pcb->pcb_dr3 = dbregs->dr[3]; 2341 pcb->pcb_dr6 = dbregs->dr[6]; 2342 pcb->pcb_dr7 = dbregs->dr[7]; 2343 2344 set_pcb_flags(pcb, PCB_DBREGS); 2345 } 2346 2347 return (0); 2348} 2349 2350void 2351reset_dbregs(void) 2352{ 2353 2354 load_dr7(0); /* Turn off the control bits first */ 2355 load_dr0(0); 2356 load_dr1(0); 2357 load_dr2(0); 2358 load_dr3(0); 2359 load_dr6(0); 2360} 2361 2362/* 2363 * Return > 0 if a hardware breakpoint has been hit, and the 2364 * breakpoint was in user space. Return 0, otherwise. 2365 */ 2366int 2367user_dbreg_trap(void) 2368{ 2369 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2370 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2371 int nbp; /* number of breakpoints that triggered */ 2372 caddr_t addr[4]; /* breakpoint addresses */ 2373 int i; 2374 2375 dr7 = rdr7(); 2376 if ((dr7 & 0x000000ff) == 0) { 2377 /* 2378 * all GE and LE bits in the dr7 register are zero, 2379 * thus the trap couldn't have been caused by the 2380 * hardware debug registers 2381 */ 2382 return 0; 2383 } 2384 2385 nbp = 0; 2386 dr6 = rdr6(); 2387 bp = dr6 & 0x0000000f; 2388 2389 if (!bp) { 2390 /* 2391 * None of the breakpoint bits are set meaning this 2392 * trap was not caused by any of the debug registers 2393 */ 2394 return 0; 2395 } 2396 2397 /* 2398 * at least one of the breakpoints were hit, check to see 2399 * which ones and if any of them are user space addresses 2400 */ 2401 2402 if (bp & 0x01) { 2403 addr[nbp++] = (caddr_t)rdr0(); 2404 } 2405 if (bp & 0x02) { 2406 addr[nbp++] = (caddr_t)rdr1(); 2407 } 2408 if (bp & 0x04) { 2409 addr[nbp++] = (caddr_t)rdr2(); 2410 } 2411 if (bp & 0x08) { 2412 addr[nbp++] = (caddr_t)rdr3(); 2413 } 2414 2415 for (i = 0; i < nbp; i++) { 2416 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2417 /* 2418 * addr[i] is in user space 2419 */ 2420 return nbp; 2421 } 2422 } 2423 2424 /* 2425 * None of the breakpoints are in user space. 2426 */ 2427 return 0; 2428} 2429 2430#ifdef KDB 2431 2432/* 2433 * Provide inb() and outb() as functions. They are normally only available as 2434 * inline functions, thus cannot be called from the debugger. 2435 */ 2436 2437/* silence compiler warnings */ 2438u_char inb_(u_short); 2439void outb_(u_short, u_char); 2440 2441u_char 2442inb_(u_short port) 2443{ 2444 return inb(port); 2445} 2446 2447void 2448outb_(u_short port, u_char data) 2449{ 2450 outb(port, data); 2451} 2452 2453#endif /* KDB */ 2454