machdep.c revision 224516
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 224516 2011-07-30 13:33:05Z bz $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_mp_watchdog.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57#include "opt_kdtrace.h" 58 59#include <sys/param.h> 60#include <sys/proc.h> 61#include <sys/systm.h> 62#include <sys/bio.h> 63#include <sys/buf.h> 64#include <sys/bus.h> 65#include <sys/callout.h> 66#include <sys/cons.h> 67#include <sys/cpu.h> 68#include <sys/eventhandler.h> 69#include <sys/exec.h> 70#include <sys/imgact.h> 71#include <sys/kdb.h> 72#include <sys/kernel.h> 73#include <sys/ktr.h> 74#include <sys/linker.h> 75#include <sys/lock.h> 76#include <sys/malloc.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/sched.h> 83#include <sys/signalvar.h> 84#ifdef SMP 85#include <sys/smp.h> 86#endif 87#include <sys/syscallsubr.h> 88#include <sys/sysctl.h> 89#include <sys/sysent.h> 90#include <sys/sysproto.h> 91#include <sys/ucontext.h> 92#include <sys/vmmeter.h> 93 94#include <vm/vm.h> 95#include <vm/vm_extern.h> 96#include <vm/vm_kern.h> 97#include <vm/vm_page.h> 98#include <vm/vm_map.h> 99#include <vm/vm_object.h> 100#include <vm/vm_pager.h> 101#include <vm/vm_param.h> 102 103#ifdef DDB 104#ifndef KDB 105#error KDB must be enabled in order for DDB to work! 106#endif 107#include <ddb/ddb.h> 108#include <ddb/db_sym.h> 109#endif 110 111#include <net/netisr.h> 112 113#include <machine/clock.h> 114#include <machine/cpu.h> 115#include <machine/cputypes.h> 116#include <machine/intr_machdep.h> 117#include <x86/mca.h> 118#include <machine/md_var.h> 119#include <machine/metadata.h> 120#include <machine/mp_watchdog.h> 121#include <machine/pc/bios.h> 122#include <machine/pcb.h> 123#include <machine/proc.h> 124#include <machine/reg.h> 125#include <machine/sigframe.h> 126#include <machine/specialreg.h> 127#ifdef PERFMON 128#include <machine/perfmon.h> 129#endif 130#include <machine/tss.h> 131#ifdef SMP 132#include <machine/smp.h> 133#endif 134 135#ifdef DEV_ATPIC 136#include <x86/isa/icu.h> 137#else 138#include <machine/apicvar.h> 139#endif 140 141#include <isa/isareg.h> 142#include <isa/rtc.h> 143 144/* Sanity check for __curthread() */ 145CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 146 147extern u_int64_t hammer_time(u_int64_t, u_int64_t); 148 149extern void printcpuinfo(void); /* XXX header file */ 150extern void identify_cpu(void); 151extern void panicifcpuunsupported(void); 152 153#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 154#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 155 156static void cpu_startup(void *); 157static void get_fpcontext(struct thread *td, mcontext_t *mcp); 158static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 159SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 160 161/* 162 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 163 * the physical address at which the kernel is loaded. 164 */ 165extern char kernphys[]; 166#ifdef DDB 167extern vm_offset_t ksym_start, ksym_end; 168#endif 169 170struct msgbuf *msgbufp; 171 172/* Intel ICH registers */ 173#define ICH_PMBASE 0x400 174#define ICH_SMI_EN ICH_PMBASE + 0x30 175 176int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 177 178int cold = 1; 179 180long Maxmem = 0; 181long realmem = 0; 182 183/* 184 * The number of PHYSMAP entries must be one less than the number of 185 * PHYSSEG entries because the PHYSMAP entry that spans the largest 186 * physical address that is accessible by ISA DMA is split into two 187 * PHYSSEG entries. 188 */ 189#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 190 191vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 192vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 193 194/* must be 2 less so 0 0 can signal end of chunks */ 195#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 196#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 197 198struct kva_md_info kmi; 199 200static struct trapframe proc0_tf; 201struct region_descriptor r_gdt, r_idt; 202 203struct pcpu __pcpu[MAXCPU]; 204 205struct mtx icu_lock; 206 207struct mtx dt_lock; /* lock for GDT and LDT */ 208 209static void 210cpu_startup(dummy) 211 void *dummy; 212{ 213 uintmax_t memsize; 214 char *sysenv; 215 216 /* 217 * On MacBooks, we need to disallow the legacy USB circuit to 218 * generate an SMI# because this can cause several problems, 219 * namely: incorrect CPU frequency detection and failure to 220 * start the APs. 221 * We do this by disabling a bit in the SMI_EN (SMI Control and 222 * Enable register) of the Intel ICH LPC Interface Bridge. 223 */ 224 sysenv = getenv("smbios.system.product"); 225 if (sysenv != NULL) { 226 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 227 strncmp(sysenv, "MacBook3,1", 10) == 0 || 228 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 229 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 230 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 231 strncmp(sysenv, "Macmini1,1", 10) == 0) { 232 if (bootverbose) 233 printf("Disabling LEGACY_USB_EN bit on " 234 "Intel ICH.\n"); 235 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 236 } 237 freeenv(sysenv); 238 } 239 240 /* 241 * Good {morning,afternoon,evening,night}. 242 */ 243 startrtclock(); 244 printcpuinfo(); 245 panicifcpuunsupported(); 246#ifdef PERFMON 247 perfmon_init(); 248#endif 249 realmem = Maxmem; 250 251 /* 252 * Display physical memory if SMBIOS reports reasonable amount. 253 */ 254 memsize = 0; 255 sysenv = getenv("smbios.memory.enabled"); 256 if (sysenv != NULL) { 257 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 258 freeenv(sysenv); 259 } 260 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 261 memsize = ptoa((uintmax_t)Maxmem); 262 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 263 264 /* 265 * Display any holes after the first chunk of extended memory. 266 */ 267 if (bootverbose) { 268 int indx; 269 270 printf("Physical memory chunk(s):\n"); 271 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 272 vm_paddr_t size; 273 274 size = phys_avail[indx + 1] - phys_avail[indx]; 275 printf( 276 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 277 (uintmax_t)phys_avail[indx], 278 (uintmax_t)phys_avail[indx + 1] - 1, 279 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 280 } 281 } 282 283 vm_ksubmap_init(&kmi); 284 285 printf("avail memory = %ju (%ju MB)\n", 286 ptoa((uintmax_t)cnt.v_free_count), 287 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 288 289 /* 290 * Set up buffers, so they can be used to read disk labels. 291 */ 292 bufinit(); 293 vm_pager_bufferinit(); 294 295 cpu_setregs(); 296} 297 298/* 299 * Send an interrupt to process. 300 * 301 * Stack is set up to allow sigcode stored 302 * at top to call routine, followed by call 303 * to sigreturn routine below. After sigreturn 304 * resets the signal mask, the stack, and the 305 * frame pointer, it returns to the user 306 * specified pc, psl. 307 */ 308void 309sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 310{ 311 struct sigframe sf, *sfp; 312 struct pcb *pcb; 313 struct proc *p; 314 struct thread *td; 315 struct sigacts *psp; 316 char *sp; 317 struct trapframe *regs; 318 int sig; 319 int oonstack; 320 321 td = curthread; 322 pcb = td->td_pcb; 323 p = td->td_proc; 324 PROC_LOCK_ASSERT(p, MA_OWNED); 325 sig = ksi->ksi_signo; 326 psp = p->p_sigacts; 327 mtx_assert(&psp->ps_mtx, MA_OWNED); 328 regs = td->td_frame; 329 oonstack = sigonstack(regs->tf_rsp); 330 331 /* Save user context. */ 332 bzero(&sf, sizeof(sf)); 333 sf.sf_uc.uc_sigmask = *mask; 334 sf.sf_uc.uc_stack = td->td_sigstk; 335 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 336 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 337 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 338 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 339 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 340 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 341 fpstate_drop(td); 342 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 343 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 344 bzero(sf.sf_uc.uc_mcontext.mc_spare, 345 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 346 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 347 348 /* Allocate space for the signal handler context. */ 349 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 350 SIGISMEMBER(psp->ps_sigonstack, sig)) { 351 sp = td->td_sigstk.ss_sp + 352 td->td_sigstk.ss_size - sizeof(struct sigframe); 353#if defined(COMPAT_43) 354 td->td_sigstk.ss_flags |= SS_ONSTACK; 355#endif 356 } else 357 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 358 /* Align to 16 bytes. */ 359 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 360 361 /* Translate the signal if appropriate. */ 362 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 363 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 364 365 /* Build the argument list for the signal handler. */ 366 regs->tf_rdi = sig; /* arg 1 in %rdi */ 367 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 368 bzero(&sf.sf_si, sizeof(sf.sf_si)); 369 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 370 /* Signal handler installed with SA_SIGINFO. */ 371 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 372 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 373 374 /* Fill in POSIX parts */ 375 sf.sf_si = ksi->ksi_info; 376 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 377 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 378 } else { 379 /* Old FreeBSD-style arguments. */ 380 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 381 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 382 sf.sf_ahu.sf_handler = catcher; 383 } 384 mtx_unlock(&psp->ps_mtx); 385 PROC_UNLOCK(p); 386 387 /* 388 * Copy the sigframe out to the user's stack. 389 */ 390 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 391#ifdef DEBUG 392 printf("process %ld has trashed its stack\n", (long)p->p_pid); 393#endif 394 PROC_LOCK(p); 395 sigexit(td, SIGILL); 396 } 397 398 regs->tf_rsp = (long)sfp; 399 regs->tf_rip = p->p_sysent->sv_sigcode_base; 400 regs->tf_rflags &= ~(PSL_T | PSL_D); 401 regs->tf_cs = _ucodesel; 402 regs->tf_ds = _udatasel; 403 regs->tf_es = _udatasel; 404 regs->tf_fs = _ufssel; 405 regs->tf_gs = _ugssel; 406 regs->tf_flags = TF_HASSEGS; 407 set_pcb_flags(pcb, PCB_FULL_IRET); 408 PROC_LOCK(p); 409 mtx_lock(&psp->ps_mtx); 410} 411 412/* 413 * System call to cleanup state after a signal 414 * has been taken. Reset signal mask and 415 * stack state from context left by sendsig (above). 416 * Return to previous pc and psl as specified by 417 * context left by sendsig. Check carefully to 418 * make sure that the user has not modified the 419 * state to gain improper privileges. 420 * 421 * MPSAFE 422 */ 423int 424sigreturn(td, uap) 425 struct thread *td; 426 struct sigreturn_args /* { 427 const struct __ucontext *sigcntxp; 428 } */ *uap; 429{ 430 ucontext_t uc; 431 struct pcb *pcb; 432 struct proc *p; 433 struct trapframe *regs; 434 ucontext_t *ucp; 435 long rflags; 436 int cs, error, ret; 437 ksiginfo_t ksi; 438 439 pcb = td->td_pcb; 440 p = td->td_proc; 441 442 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 443 if (error != 0) { 444 uprintf("pid %d (%s): sigreturn copyin failed\n", 445 p->p_pid, td->td_name); 446 return (error); 447 } 448 ucp = &uc; 449 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 450 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 451 td->td_name, ucp->uc_mcontext.mc_flags); 452 return (EINVAL); 453 } 454 regs = td->td_frame; 455 rflags = ucp->uc_mcontext.mc_rflags; 456 /* 457 * Don't allow users to change privileged or reserved flags. 458 */ 459 /* 460 * XXX do allow users to change the privileged flag PSL_RF. 461 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 462 * should sometimes set it there too. tf_rflags is kept in 463 * the signal context during signal handling and there is no 464 * other place to remember it, so the PSL_RF bit may be 465 * corrupted by the signal handler without us knowing. 466 * Corruption of the PSL_RF bit at worst causes one more or 467 * one less debugger trap, so allowing it is fairly harmless. 468 */ 469 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 470 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 471 td->td_name, rflags); 472 return (EINVAL); 473 } 474 475 /* 476 * Don't allow users to load a valid privileged %cs. Let the 477 * hardware check for invalid selectors, excess privilege in 478 * other selectors, invalid %eip's and invalid %esp's. 479 */ 480 cs = ucp->uc_mcontext.mc_cs; 481 if (!CS_SECURE(cs)) { 482 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 483 td->td_name, cs); 484 ksiginfo_init_trap(&ksi); 485 ksi.ksi_signo = SIGBUS; 486 ksi.ksi_code = BUS_OBJERR; 487 ksi.ksi_trapno = T_PROTFLT; 488 ksi.ksi_addr = (void *)regs->tf_rip; 489 trapsignal(td, &ksi); 490 return (EINVAL); 491 } 492 493 ret = set_fpcontext(td, &ucp->uc_mcontext); 494 if (ret != 0) { 495 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 496 p->p_pid, td->td_name, ret); 497 return (ret); 498 } 499 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 500 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 501 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 502 503#if defined(COMPAT_43) 504 if (ucp->uc_mcontext.mc_onstack & 1) 505 td->td_sigstk.ss_flags |= SS_ONSTACK; 506 else 507 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 508#endif 509 510 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 511 set_pcb_flags(pcb, PCB_FULL_IRET); 512 return (EJUSTRETURN); 513} 514 515#ifdef COMPAT_FREEBSD4 516int 517freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 518{ 519 520 return sigreturn(td, (struct sigreturn_args *)uap); 521} 522#endif 523 524 525/* 526 * Machine dependent boot() routine 527 * 528 * I haven't seen anything to put here yet 529 * Possibly some stuff might be grafted back here from boot() 530 */ 531void 532cpu_boot(int howto) 533{ 534} 535 536/* 537 * Flush the D-cache for non-DMA I/O so that the I-cache can 538 * be made coherent later. 539 */ 540void 541cpu_flush_dcache(void *ptr, size_t len) 542{ 543 /* Not applicable */ 544} 545 546/* Get current clock frequency for the given cpu id. */ 547int 548cpu_est_clockrate(int cpu_id, uint64_t *rate) 549{ 550 uint64_t tsc1, tsc2; 551 uint64_t acnt, mcnt, perf; 552 register_t reg; 553 554 if (pcpu_find(cpu_id) == NULL || rate == NULL) 555 return (EINVAL); 556 557 /* 558 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 559 * DELAY(9) based logic fails. 560 */ 561 if (tsc_is_invariant && !tsc_perf_stat) 562 return (EOPNOTSUPP); 563 564#ifdef SMP 565 if (smp_cpus > 1) { 566 /* Schedule ourselves on the indicated cpu. */ 567 thread_lock(curthread); 568 sched_bind(curthread, cpu_id); 569 thread_unlock(curthread); 570 } 571#endif 572 573 /* Calibrate by measuring a short delay. */ 574 reg = intr_disable(); 575 if (tsc_is_invariant) { 576 wrmsr(MSR_MPERF, 0); 577 wrmsr(MSR_APERF, 0); 578 tsc1 = rdtsc(); 579 DELAY(1000); 580 mcnt = rdmsr(MSR_MPERF); 581 acnt = rdmsr(MSR_APERF); 582 tsc2 = rdtsc(); 583 intr_restore(reg); 584 perf = 1000 * acnt / mcnt; 585 *rate = (tsc2 - tsc1) * perf; 586 } else { 587 tsc1 = rdtsc(); 588 DELAY(1000); 589 tsc2 = rdtsc(); 590 intr_restore(reg); 591 *rate = (tsc2 - tsc1) * 1000; 592 } 593 594#ifdef SMP 595 if (smp_cpus > 1) { 596 thread_lock(curthread); 597 sched_unbind(curthread); 598 thread_unlock(curthread); 599 } 600#endif 601 602 return (0); 603} 604 605/* 606 * Shutdown the CPU as much as possible 607 */ 608void 609cpu_halt(void) 610{ 611 for (;;) 612 __asm__ ("hlt"); 613} 614 615void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 616static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 617static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 618TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 619SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 620 0, "Use MONITOR/MWAIT for short idle"); 621 622#define STATE_RUNNING 0x0 623#define STATE_MWAIT 0x1 624#define STATE_SLEEPING 0x2 625 626static void 627cpu_idle_acpi(int busy) 628{ 629 int *state; 630 631 state = (int *)PCPU_PTR(monitorbuf); 632 *state = STATE_SLEEPING; 633 disable_intr(); 634 if (sched_runnable()) 635 enable_intr(); 636 else if (cpu_idle_hook) 637 cpu_idle_hook(); 638 else 639 __asm __volatile("sti; hlt"); 640 *state = STATE_RUNNING; 641} 642 643static void 644cpu_idle_hlt(int busy) 645{ 646 int *state; 647 648 state = (int *)PCPU_PTR(monitorbuf); 649 *state = STATE_SLEEPING; 650 /* 651 * We must absolutely guarentee that hlt is the next instruction 652 * after sti or we introduce a timing window. 653 */ 654 disable_intr(); 655 if (sched_runnable()) 656 enable_intr(); 657 else 658 __asm __volatile("sti; hlt"); 659 *state = STATE_RUNNING; 660} 661 662/* 663 * MWAIT cpu power states. Lower 4 bits are sub-states. 664 */ 665#define MWAIT_C0 0xf0 666#define MWAIT_C1 0x00 667#define MWAIT_C2 0x10 668#define MWAIT_C3 0x20 669#define MWAIT_C4 0x30 670 671static void 672cpu_idle_mwait(int busy) 673{ 674 int *state; 675 676 state = (int *)PCPU_PTR(monitorbuf); 677 *state = STATE_MWAIT; 678 if (!sched_runnable()) { 679 cpu_monitor(state, 0, 0); 680 if (*state == STATE_MWAIT) 681 cpu_mwait(0, MWAIT_C1); 682 } 683 *state = STATE_RUNNING; 684} 685 686static void 687cpu_idle_spin(int busy) 688{ 689 int *state; 690 int i; 691 692 state = (int *)PCPU_PTR(monitorbuf); 693 *state = STATE_RUNNING; 694 for (i = 0; i < 1000; i++) { 695 if (sched_runnable()) 696 return; 697 cpu_spinwait(); 698 } 699} 700 701/* 702 * C1E renders the local APIC timer dead, so we disable it by 703 * reading the Interrupt Pending Message register and clearing 704 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 705 * 706 * Reference: 707 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 708 * #32559 revision 3.00+ 709 */ 710#define MSR_AMDK8_IPM 0xc0010055 711#define AMDK8_SMIONCMPHALT (1ULL << 27) 712#define AMDK8_C1EONCMPHALT (1ULL << 28) 713#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 714 715static void 716cpu_probe_amdc1e(void) 717{ 718 719 /* 720 * Detect the presence of C1E capability mostly on latest 721 * dual-cores (or future) k8 family. 722 */ 723 if (cpu_vendor_id == CPU_VENDOR_AMD && 724 (cpu_id & 0x00000f00) == 0x00000f00 && 725 (cpu_id & 0x0fff0000) >= 0x00040000) { 726 cpu_ident_amdc1e = 1; 727 } 728} 729 730void (*cpu_idle_fn)(int) = cpu_idle_acpi; 731 732void 733cpu_idle(int busy) 734{ 735 uint64_t msr; 736 737 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 738 busy, curcpu); 739#ifdef MP_WATCHDOG 740 ap_watchdog(PCPU_GET(cpuid)); 741#endif 742 /* If we are busy - try to use fast methods. */ 743 if (busy) { 744 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 745 cpu_idle_mwait(busy); 746 goto out; 747 } 748 } 749 750 /* If we have time - switch timers into idle mode. */ 751 if (!busy) { 752 critical_enter(); 753 cpu_idleclock(); 754 } 755 756 /* Apply AMD APIC timer C1E workaround. */ 757 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 758 msr = rdmsr(MSR_AMDK8_IPM); 759 if (msr & AMDK8_CMPHALT) 760 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 761 } 762 763 /* Call main idle method. */ 764 cpu_idle_fn(busy); 765 766 /* Switch timers mack into active mode. */ 767 if (!busy) { 768 cpu_activeclock(); 769 critical_exit(); 770 } 771out: 772 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 773 busy, curcpu); 774} 775 776int 777cpu_idle_wakeup(int cpu) 778{ 779 struct pcpu *pcpu; 780 int *state; 781 782 pcpu = pcpu_find(cpu); 783 state = (int *)pcpu->pc_monitorbuf; 784 /* 785 * This doesn't need to be atomic since missing the race will 786 * simply result in unnecessary IPIs. 787 */ 788 if (*state == STATE_SLEEPING) 789 return (0); 790 if (*state == STATE_MWAIT) 791 *state = STATE_RUNNING; 792 return (1); 793} 794 795/* 796 * Ordered by speed/power consumption. 797 */ 798struct { 799 void *id_fn; 800 char *id_name; 801} idle_tbl[] = { 802 { cpu_idle_spin, "spin" }, 803 { cpu_idle_mwait, "mwait" }, 804 { cpu_idle_hlt, "hlt" }, 805 { cpu_idle_acpi, "acpi" }, 806 { NULL, NULL } 807}; 808 809static int 810idle_sysctl_available(SYSCTL_HANDLER_ARGS) 811{ 812 char *avail, *p; 813 int error; 814 int i; 815 816 avail = malloc(256, M_TEMP, M_WAITOK); 817 p = avail; 818 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 819 if (strstr(idle_tbl[i].id_name, "mwait") && 820 (cpu_feature2 & CPUID2_MON) == 0) 821 continue; 822 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 823 cpu_idle_hook == NULL) 824 continue; 825 p += sprintf(p, "%s%s", p != avail ? ", " : "", 826 idle_tbl[i].id_name); 827 } 828 error = sysctl_handle_string(oidp, avail, 0, req); 829 free(avail, M_TEMP); 830 return (error); 831} 832 833SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 834 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 835 836static int 837idle_sysctl(SYSCTL_HANDLER_ARGS) 838{ 839 char buf[16]; 840 int error; 841 char *p; 842 int i; 843 844 p = "unknown"; 845 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 846 if (idle_tbl[i].id_fn == cpu_idle_fn) { 847 p = idle_tbl[i].id_name; 848 break; 849 } 850 } 851 strncpy(buf, p, sizeof(buf)); 852 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 853 if (error != 0 || req->newptr == NULL) 854 return (error); 855 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 856 if (strstr(idle_tbl[i].id_name, "mwait") && 857 (cpu_feature2 & CPUID2_MON) == 0) 858 continue; 859 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 860 cpu_idle_hook == NULL) 861 continue; 862 if (strcmp(idle_tbl[i].id_name, buf)) 863 continue; 864 cpu_idle_fn = idle_tbl[i].id_fn; 865 return (0); 866 } 867 return (EINVAL); 868} 869 870SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 871 idle_sysctl, "A", "currently selected idle function"); 872 873/* 874 * Reset registers to default values on exec. 875 */ 876void 877exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 878{ 879 struct trapframe *regs = td->td_frame; 880 struct pcb *pcb = td->td_pcb; 881 882 mtx_lock(&dt_lock); 883 if (td->td_proc->p_md.md_ldt != NULL) 884 user_ldt_free(td); 885 else 886 mtx_unlock(&dt_lock); 887 888 pcb->pcb_fsbase = 0; 889 pcb->pcb_gsbase = 0; 890 clear_pcb_flags(pcb, PCB_32BIT | PCB_GS32BIT); 891 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 892 set_pcb_flags(pcb, PCB_FULL_IRET); 893 894 bzero((char *)regs, sizeof(struct trapframe)); 895 regs->tf_rip = imgp->entry_addr; 896 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 897 regs->tf_rdi = stack; /* argv */ 898 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 899 regs->tf_ss = _udatasel; 900 regs->tf_cs = _ucodesel; 901 regs->tf_ds = _udatasel; 902 regs->tf_es = _udatasel; 903 regs->tf_fs = _ufssel; 904 regs->tf_gs = _ugssel; 905 regs->tf_flags = TF_HASSEGS; 906 td->td_retval[1] = 0; 907 908 /* 909 * Reset the hardware debug registers if they were in use. 910 * They won't have any meaning for the newly exec'd process. 911 */ 912 if (pcb->pcb_flags & PCB_DBREGS) { 913 pcb->pcb_dr0 = 0; 914 pcb->pcb_dr1 = 0; 915 pcb->pcb_dr2 = 0; 916 pcb->pcb_dr3 = 0; 917 pcb->pcb_dr6 = 0; 918 pcb->pcb_dr7 = 0; 919 if (pcb == PCPU_GET(curpcb)) { 920 /* 921 * Clear the debug registers on the running 922 * CPU, otherwise they will end up affecting 923 * the next process we switch to. 924 */ 925 reset_dbregs(); 926 } 927 clear_pcb_flags(pcb, PCB_DBREGS); 928 } 929 930 /* 931 * Drop the FP state if we hold it, so that the process gets a 932 * clean FP state if it uses the FPU again. 933 */ 934 fpstate_drop(td); 935} 936 937void 938cpu_setregs(void) 939{ 940 register_t cr0; 941 942 cr0 = rcr0(); 943 /* 944 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 945 * BSP. See the comments there about why we set them. 946 */ 947 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 948 load_cr0(cr0); 949} 950 951/* 952 * Initialize amd64 and configure to run kernel 953 */ 954 955/* 956 * Initialize segments & interrupt table 957 */ 958 959struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 960static struct gate_descriptor idt0[NIDT]; 961struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 962 963static char dblfault_stack[PAGE_SIZE] __aligned(16); 964 965static char nmi0_stack[PAGE_SIZE] __aligned(16); 966CTASSERT(sizeof(struct nmi_pcpu) == 16); 967 968struct amd64tss common_tss[MAXCPU]; 969 970/* 971 * Software prototypes -- in more palatable form. 972 * 973 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 974 * slots as corresponding segments for i386 kernel. 975 */ 976struct soft_segment_descriptor gdt_segs[] = { 977/* GNULL_SEL 0 Null Descriptor */ 978{ .ssd_base = 0x0, 979 .ssd_limit = 0x0, 980 .ssd_type = 0, 981 .ssd_dpl = 0, 982 .ssd_p = 0, 983 .ssd_long = 0, 984 .ssd_def32 = 0, 985 .ssd_gran = 0 }, 986/* GNULL2_SEL 1 Null Descriptor */ 987{ .ssd_base = 0x0, 988 .ssd_limit = 0x0, 989 .ssd_type = 0, 990 .ssd_dpl = 0, 991 .ssd_p = 0, 992 .ssd_long = 0, 993 .ssd_def32 = 0, 994 .ssd_gran = 0 }, 995/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 996{ .ssd_base = 0x0, 997 .ssd_limit = 0xfffff, 998 .ssd_type = SDT_MEMRWA, 999 .ssd_dpl = SEL_UPL, 1000 .ssd_p = 1, 1001 .ssd_long = 0, 1002 .ssd_def32 = 1, 1003 .ssd_gran = 1 }, 1004/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1005{ .ssd_base = 0x0, 1006 .ssd_limit = 0xfffff, 1007 .ssd_type = SDT_MEMRWA, 1008 .ssd_dpl = SEL_UPL, 1009 .ssd_p = 1, 1010 .ssd_long = 0, 1011 .ssd_def32 = 1, 1012 .ssd_gran = 1 }, 1013/* GCODE_SEL 4 Code Descriptor for kernel */ 1014{ .ssd_base = 0x0, 1015 .ssd_limit = 0xfffff, 1016 .ssd_type = SDT_MEMERA, 1017 .ssd_dpl = SEL_KPL, 1018 .ssd_p = 1, 1019 .ssd_long = 1, 1020 .ssd_def32 = 0, 1021 .ssd_gran = 1 }, 1022/* GDATA_SEL 5 Data Descriptor for kernel */ 1023{ .ssd_base = 0x0, 1024 .ssd_limit = 0xfffff, 1025 .ssd_type = SDT_MEMRWA, 1026 .ssd_dpl = SEL_KPL, 1027 .ssd_p = 1, 1028 .ssd_long = 1, 1029 .ssd_def32 = 0, 1030 .ssd_gran = 1 }, 1031/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1032{ .ssd_base = 0x0, 1033 .ssd_limit = 0xfffff, 1034 .ssd_type = SDT_MEMERA, 1035 .ssd_dpl = SEL_UPL, 1036 .ssd_p = 1, 1037 .ssd_long = 0, 1038 .ssd_def32 = 1, 1039 .ssd_gran = 1 }, 1040/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1041{ .ssd_base = 0x0, 1042 .ssd_limit = 0xfffff, 1043 .ssd_type = SDT_MEMRWA, 1044 .ssd_dpl = SEL_UPL, 1045 .ssd_p = 1, 1046 .ssd_long = 0, 1047 .ssd_def32 = 1, 1048 .ssd_gran = 1 }, 1049/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1050{ .ssd_base = 0x0, 1051 .ssd_limit = 0xfffff, 1052 .ssd_type = SDT_MEMERA, 1053 .ssd_dpl = SEL_UPL, 1054 .ssd_p = 1, 1055 .ssd_long = 1, 1056 .ssd_def32 = 0, 1057 .ssd_gran = 1 }, 1058/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1059{ .ssd_base = 0x0, 1060 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1061 .ssd_type = SDT_SYSTSS, 1062 .ssd_dpl = SEL_KPL, 1063 .ssd_p = 1, 1064 .ssd_long = 0, 1065 .ssd_def32 = 0, 1066 .ssd_gran = 0 }, 1067/* Actually, the TSS is a system descriptor which is double size */ 1068{ .ssd_base = 0x0, 1069 .ssd_limit = 0x0, 1070 .ssd_type = 0, 1071 .ssd_dpl = 0, 1072 .ssd_p = 0, 1073 .ssd_long = 0, 1074 .ssd_def32 = 0, 1075 .ssd_gran = 0 }, 1076/* GUSERLDT_SEL 11 LDT Descriptor */ 1077{ .ssd_base = 0x0, 1078 .ssd_limit = 0x0, 1079 .ssd_type = 0, 1080 .ssd_dpl = 0, 1081 .ssd_p = 0, 1082 .ssd_long = 0, 1083 .ssd_def32 = 0, 1084 .ssd_gran = 0 }, 1085/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1086{ .ssd_base = 0x0, 1087 .ssd_limit = 0x0, 1088 .ssd_type = 0, 1089 .ssd_dpl = 0, 1090 .ssd_p = 0, 1091 .ssd_long = 0, 1092 .ssd_def32 = 0, 1093 .ssd_gran = 0 }, 1094}; 1095 1096void 1097setidt(idx, func, typ, dpl, ist) 1098 int idx; 1099 inthand_t *func; 1100 int typ; 1101 int dpl; 1102 int ist; 1103{ 1104 struct gate_descriptor *ip; 1105 1106 ip = idt + idx; 1107 ip->gd_looffset = (uintptr_t)func; 1108 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1109 ip->gd_ist = ist; 1110 ip->gd_xx = 0; 1111 ip->gd_type = typ; 1112 ip->gd_dpl = dpl; 1113 ip->gd_p = 1; 1114 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1115} 1116 1117extern inthand_t 1118 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1119 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1120 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1121 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1122 IDTVEC(xmm), IDTVEC(dblfault), 1123#ifdef KDTRACE_HOOKS 1124 IDTVEC(dtrace_ret), 1125#endif 1126 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1127 1128#ifdef DDB 1129/* 1130 * Display the index and function name of any IDT entries that don't use 1131 * the default 'rsvd' entry point. 1132 */ 1133DB_SHOW_COMMAND(idt, db_show_idt) 1134{ 1135 struct gate_descriptor *ip; 1136 int idx; 1137 uintptr_t func; 1138 1139 ip = idt; 1140 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1141 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1142 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1143 db_printf("%3d\t", idx); 1144 db_printsym(func, DB_STGY_PROC); 1145 db_printf("\n"); 1146 } 1147 ip++; 1148 } 1149} 1150#endif 1151 1152void 1153sdtossd(sd, ssd) 1154 struct user_segment_descriptor *sd; 1155 struct soft_segment_descriptor *ssd; 1156{ 1157 1158 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1159 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1160 ssd->ssd_type = sd->sd_type; 1161 ssd->ssd_dpl = sd->sd_dpl; 1162 ssd->ssd_p = sd->sd_p; 1163 ssd->ssd_long = sd->sd_long; 1164 ssd->ssd_def32 = sd->sd_def32; 1165 ssd->ssd_gran = sd->sd_gran; 1166} 1167 1168void 1169ssdtosd(ssd, sd) 1170 struct soft_segment_descriptor *ssd; 1171 struct user_segment_descriptor *sd; 1172{ 1173 1174 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1175 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1176 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1177 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1178 sd->sd_type = ssd->ssd_type; 1179 sd->sd_dpl = ssd->ssd_dpl; 1180 sd->sd_p = ssd->ssd_p; 1181 sd->sd_long = ssd->ssd_long; 1182 sd->sd_def32 = ssd->ssd_def32; 1183 sd->sd_gran = ssd->ssd_gran; 1184} 1185 1186void 1187ssdtosyssd(ssd, sd) 1188 struct soft_segment_descriptor *ssd; 1189 struct system_segment_descriptor *sd; 1190{ 1191 1192 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1193 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1194 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1195 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1196 sd->sd_type = ssd->ssd_type; 1197 sd->sd_dpl = ssd->ssd_dpl; 1198 sd->sd_p = ssd->ssd_p; 1199 sd->sd_gran = ssd->ssd_gran; 1200} 1201 1202#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1203#include <isa/isavar.h> 1204#include <isa/isareg.h> 1205/* 1206 * Return a bitmap of the current interrupt requests. This is 8259-specific 1207 * and is only suitable for use at probe time. 1208 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1209 * It shouldn't be here. There should probably be an APIC centric 1210 * implementation in the apic driver code, if at all. 1211 */ 1212intrmask_t 1213isa_irq_pending(void) 1214{ 1215 u_char irr1; 1216 u_char irr2; 1217 1218 irr1 = inb(IO_ICU1); 1219 irr2 = inb(IO_ICU2); 1220 return ((irr2 << 8) | irr1); 1221} 1222#endif 1223 1224u_int basemem; 1225 1226static int 1227add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1228{ 1229 int i, insert_idx, physmap_idx; 1230 1231 physmap_idx = *physmap_idxp; 1232 1233 if (boothowto & RB_VERBOSE) 1234 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1235 smap->type, smap->base, smap->length); 1236 1237 if (smap->type != SMAP_TYPE_MEMORY) 1238 return (1); 1239 1240 if (smap->length == 0) 1241 return (0); 1242 1243 /* 1244 * Find insertion point while checking for overlap. Start off by 1245 * assuming the new entry will be added to the end. 1246 */ 1247 insert_idx = physmap_idx + 2; 1248 for (i = 0; i <= physmap_idx; i += 2) { 1249 if (smap->base < physmap[i + 1]) { 1250 if (smap->base + smap->length <= physmap[i]) { 1251 insert_idx = i; 1252 break; 1253 } 1254 if (boothowto & RB_VERBOSE) 1255 printf( 1256 "Overlapping memory regions, ignoring second region\n"); 1257 return (1); 1258 } 1259 } 1260 1261 /* See if we can prepend to the next entry. */ 1262 if (insert_idx <= physmap_idx && 1263 smap->base + smap->length == physmap[insert_idx]) { 1264 physmap[insert_idx] = smap->base; 1265 return (1); 1266 } 1267 1268 /* See if we can append to the previous entry. */ 1269 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1270 physmap[insert_idx - 1] += smap->length; 1271 return (1); 1272 } 1273 1274 physmap_idx += 2; 1275 *physmap_idxp = physmap_idx; 1276 if (physmap_idx == PHYSMAP_SIZE) { 1277 printf( 1278 "Too many segments in the physical address map, giving up\n"); 1279 return (0); 1280 } 1281 1282 /* 1283 * Move the last 'N' entries down to make room for the new 1284 * entry if needed. 1285 */ 1286 for (i = physmap_idx; i > insert_idx; i -= 2) { 1287 physmap[i] = physmap[i - 2]; 1288 physmap[i + 1] = physmap[i - 1]; 1289 } 1290 1291 /* Insert the new entry. */ 1292 physmap[insert_idx] = smap->base; 1293 physmap[insert_idx + 1] = smap->base + smap->length; 1294 return (1); 1295} 1296 1297/* 1298 * Populate the (physmap) array with base/bound pairs describing the 1299 * available physical memory in the system, then test this memory and 1300 * build the phys_avail array describing the actually-available memory. 1301 * 1302 * Total memory size may be set by the kernel environment variable 1303 * hw.physmem or the compile-time define MAXMEM. 1304 * 1305 * XXX first should be vm_paddr_t. 1306 */ 1307static void 1308getmemsize(caddr_t kmdp, u_int64_t first) 1309{ 1310 int i, physmap_idx, pa_indx, da_indx; 1311 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1312 u_long physmem_tunable, memtest, tmpul; 1313 pt_entry_t *pte; 1314 struct bios_smap *smapbase, *smap, *smapend; 1315 u_int32_t smapsize; 1316 quad_t dcons_addr, dcons_size; 1317 1318 bzero(physmap, sizeof(physmap)); 1319 basemem = 0; 1320 physmap_idx = 0; 1321 1322 /* 1323 * get memory map from INT 15:E820, kindly supplied by the loader. 1324 * 1325 * subr_module.c says: 1326 * "Consumer may safely assume that size value precedes data." 1327 * ie: an int32_t immediately precedes smap. 1328 */ 1329 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1330 MODINFO_METADATA | MODINFOMD_SMAP); 1331 if (smapbase == NULL) 1332 panic("No BIOS smap info from loader!"); 1333 1334 smapsize = *((u_int32_t *)smapbase - 1); 1335 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1336 1337 for (smap = smapbase; smap < smapend; smap++) 1338 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1339 break; 1340 1341 /* 1342 * Find the 'base memory' segment for SMP 1343 */ 1344 basemem = 0; 1345 for (i = 0; i <= physmap_idx; i += 2) { 1346 if (physmap[i] == 0x00000000) { 1347 basemem = physmap[i + 1] / 1024; 1348 break; 1349 } 1350 } 1351 if (basemem == 0) 1352 panic("BIOS smap did not include a basemem segment!"); 1353 1354#ifdef SMP 1355 /* make hole for AP bootstrap code */ 1356 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1357#endif 1358 1359 /* 1360 * Maxmem isn't the "maximum memory", it's one larger than the 1361 * highest page of the physical address space. It should be 1362 * called something like "Maxphyspage". We may adjust this 1363 * based on ``hw.physmem'' and the results of the memory test. 1364 */ 1365 Maxmem = atop(physmap[physmap_idx + 1]); 1366 1367#ifdef MAXMEM 1368 Maxmem = MAXMEM / 4; 1369#endif 1370 1371 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1372 Maxmem = atop(physmem_tunable); 1373 1374 /* 1375 * By default keep the memtest enabled. Use a general name so that 1376 * one could eventually do more with the code than just disable it. 1377 */ 1378 memtest = 1; 1379 if (TUNABLE_ULONG_FETCH("hw.memtest.tests", &tmpul)) 1380 memtest = tmpul; 1381 1382 /* 1383 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1384 * in the system. 1385 */ 1386 if (Maxmem > atop(physmap[physmap_idx + 1])) 1387 Maxmem = atop(physmap[physmap_idx + 1]); 1388 1389 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1390 (boothowto & RB_VERBOSE)) 1391 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1392 1393 /* call pmap initialization to make new kernel address space */ 1394 pmap_bootstrap(&first); 1395 1396 /* 1397 * Size up each available chunk of physical memory. 1398 */ 1399 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1400 pa_indx = 0; 1401 da_indx = 1; 1402 phys_avail[pa_indx++] = physmap[0]; 1403 phys_avail[pa_indx] = physmap[0]; 1404 dump_avail[da_indx] = physmap[0]; 1405 pte = CMAP1; 1406 1407 /* 1408 * Get dcons buffer address 1409 */ 1410 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1411 getenv_quad("dcons.size", &dcons_size) == 0) 1412 dcons_addr = 0; 1413 1414 /* 1415 * physmap is in bytes, so when converting to page boundaries, 1416 * round up the start address and round down the end address. 1417 */ 1418 for (i = 0; i <= physmap_idx; i += 2) { 1419 vm_paddr_t end; 1420 1421 end = ptoa((vm_paddr_t)Maxmem); 1422 if (physmap[i + 1] < end) 1423 end = trunc_page(physmap[i + 1]); 1424 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1425 int tmp, page_bad, full; 1426 int *ptr = (int *)CADDR1; 1427 1428 full = FALSE; 1429 /* 1430 * block out kernel memory as not available. 1431 */ 1432 if (pa >= (vm_paddr_t)kernphys && pa < first) 1433 goto do_dump_avail; 1434 1435 /* 1436 * block out dcons buffer 1437 */ 1438 if (dcons_addr > 0 1439 && pa >= trunc_page(dcons_addr) 1440 && pa < dcons_addr + dcons_size) 1441 goto do_dump_avail; 1442 1443 page_bad = FALSE; 1444 if (memtest == 0) 1445 goto skip_memtest; 1446 1447 /* 1448 * map page into kernel: valid, read/write,non-cacheable 1449 */ 1450 *pte = pa | PG_V | PG_RW | PG_N; 1451 invltlb(); 1452 1453 tmp = *(int *)ptr; 1454 /* 1455 * Test for alternating 1's and 0's 1456 */ 1457 *(volatile int *)ptr = 0xaaaaaaaa; 1458 if (*(volatile int *)ptr != 0xaaaaaaaa) 1459 page_bad = TRUE; 1460 /* 1461 * Test for alternating 0's and 1's 1462 */ 1463 *(volatile int *)ptr = 0x55555555; 1464 if (*(volatile int *)ptr != 0x55555555) 1465 page_bad = TRUE; 1466 /* 1467 * Test for all 1's 1468 */ 1469 *(volatile int *)ptr = 0xffffffff; 1470 if (*(volatile int *)ptr != 0xffffffff) 1471 page_bad = TRUE; 1472 /* 1473 * Test for all 0's 1474 */ 1475 *(volatile int *)ptr = 0x0; 1476 if (*(volatile int *)ptr != 0x0) 1477 page_bad = TRUE; 1478 /* 1479 * Restore original value. 1480 */ 1481 *(int *)ptr = tmp; 1482 1483skip_memtest: 1484 /* 1485 * Adjust array of valid/good pages. 1486 */ 1487 if (page_bad == TRUE) 1488 continue; 1489 /* 1490 * If this good page is a continuation of the 1491 * previous set of good pages, then just increase 1492 * the end pointer. Otherwise start a new chunk. 1493 * Note that "end" points one higher than end, 1494 * making the range >= start and < end. 1495 * If we're also doing a speculative memory 1496 * test and we at or past the end, bump up Maxmem 1497 * so that we keep going. The first bad page 1498 * will terminate the loop. 1499 */ 1500 if (phys_avail[pa_indx] == pa) { 1501 phys_avail[pa_indx] += PAGE_SIZE; 1502 } else { 1503 pa_indx++; 1504 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1505 printf( 1506 "Too many holes in the physical address space, giving up\n"); 1507 pa_indx--; 1508 full = TRUE; 1509 goto do_dump_avail; 1510 } 1511 phys_avail[pa_indx++] = pa; /* start */ 1512 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1513 } 1514 physmem++; 1515do_dump_avail: 1516 if (dump_avail[da_indx] == pa) { 1517 dump_avail[da_indx] += PAGE_SIZE; 1518 } else { 1519 da_indx++; 1520 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1521 da_indx--; 1522 goto do_next; 1523 } 1524 dump_avail[da_indx++] = pa; /* start */ 1525 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1526 } 1527do_next: 1528 if (full) 1529 break; 1530 } 1531 } 1532 *pte = 0; 1533 invltlb(); 1534 1535 /* 1536 * XXX 1537 * The last chunk must contain at least one page plus the message 1538 * buffer to avoid complicating other code (message buffer address 1539 * calculation, etc.). 1540 */ 1541 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1542 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1543 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1544 phys_avail[pa_indx--] = 0; 1545 phys_avail[pa_indx--] = 0; 1546 } 1547 1548 Maxmem = atop(phys_avail[pa_indx]); 1549 1550 /* Trim off space for the message buffer. */ 1551 phys_avail[pa_indx] -= round_page(msgbufsize); 1552 1553 /* Map the message buffer. */ 1554 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1555} 1556 1557u_int64_t 1558hammer_time(u_int64_t modulep, u_int64_t physfree) 1559{ 1560 caddr_t kmdp; 1561 int gsel_tss, x; 1562 struct pcpu *pc; 1563 struct nmi_pcpu *np; 1564 u_int64_t msr; 1565 char *env; 1566 size_t kstack0_sz; 1567 1568 thread0.td_kstack = physfree + KERNBASE; 1569 thread0.td_kstack_pages = KSTACK_PAGES; 1570 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1571 bzero((void *)thread0.td_kstack, kstack0_sz); 1572 physfree += kstack0_sz; 1573 thread0.td_pcb = (struct pcb *)(thread0.td_kstack + kstack0_sz) - 1; 1574 1575 /* 1576 * This may be done better later if it gets more high level 1577 * components in it. If so just link td->td_proc here. 1578 */ 1579 proc_linkup0(&proc0, &thread0); 1580 1581 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1582 preload_bootstrap_relocate(KERNBASE); 1583 kmdp = preload_search_by_type("elf kernel"); 1584 if (kmdp == NULL) 1585 kmdp = preload_search_by_type("elf64 kernel"); 1586 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1587 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1588#ifdef DDB 1589 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1590 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1591#endif 1592 1593 /* Init basic tunables, hz etc */ 1594 init_param1(); 1595 1596 /* 1597 * make gdt memory segments 1598 */ 1599 for (x = 0; x < NGDT; x++) { 1600 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1601 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1602 ssdtosd(&gdt_segs[x], &gdt[x]); 1603 } 1604 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1605 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1606 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1607 1608 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1609 r_gdt.rd_base = (long) gdt; 1610 lgdt(&r_gdt); 1611 pc = &__pcpu[0]; 1612 1613 wrmsr(MSR_FSBASE, 0); /* User value */ 1614 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1615 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1616 1617 pcpu_init(pc, 0, sizeof(struct pcpu)); 1618 dpcpu_init((void *)(physfree + KERNBASE), 0); 1619 physfree += DPCPU_SIZE; 1620 PCPU_SET(prvspace, pc); 1621 PCPU_SET(curthread, &thread0); 1622 PCPU_SET(curpcb, thread0.td_pcb); 1623 PCPU_SET(tssp, &common_tss[0]); 1624 PCPU_SET(commontssp, &common_tss[0]); 1625 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1626 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1627 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1628 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1629 1630 /* 1631 * Initialize mutexes. 1632 * 1633 * icu_lock: in order to allow an interrupt to occur in a critical 1634 * section, to set pcpu->ipending (etc...) properly, we 1635 * must be able to get the icu lock, so it can't be 1636 * under witness. 1637 */ 1638 mutex_init(); 1639 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1640 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1641 1642 /* exceptions */ 1643 for (x = 0; x < NIDT; x++) 1644 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1645 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1646 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1647 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1648 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1649 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1650 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1651 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1652 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1653 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1654 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1655 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1656 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1657 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1658 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1659 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1660 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1661 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1662 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1663 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1664#ifdef KDTRACE_HOOKS 1665 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1666#endif 1667 1668 r_idt.rd_limit = sizeof(idt0) - 1; 1669 r_idt.rd_base = (long) idt; 1670 lidt(&r_idt); 1671 1672 /* 1673 * Initialize the i8254 before the console so that console 1674 * initialization can use DELAY(). 1675 */ 1676 i8254_init(); 1677 1678 /* 1679 * Initialize the console before we print anything out. 1680 */ 1681 cninit(); 1682 1683#ifdef DEV_ISA 1684#ifdef DEV_ATPIC 1685 elcr_probe(); 1686 atpic_startup(); 1687#else 1688 /* Reset and mask the atpics and leave them shut down. */ 1689 atpic_reset(); 1690 1691 /* 1692 * Point the ICU spurious interrupt vectors at the APIC spurious 1693 * interrupt handler. 1694 */ 1695 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1696 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1697#endif 1698#else 1699#error "have you forgotten the isa device?"; 1700#endif 1701 1702 kdb_init(); 1703 1704#ifdef KDB 1705 if (boothowto & RB_KDB) 1706 kdb_enter(KDB_WHY_BOOTFLAGS, 1707 "Boot flags requested debugger"); 1708#endif 1709 1710 identify_cpu(); /* Final stage of CPU initialization */ 1711 initializecpu(); /* Initialize CPU registers */ 1712 initializecpucache(); 1713 1714 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1715 common_tss[0].tss_rsp0 = thread0.td_kstack + 1716 kstack0_sz - sizeof(struct pcb); 1717 /* Ensure the stack is aligned to 16 bytes */ 1718 common_tss[0].tss_rsp0 &= ~0xFul; 1719 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1720 1721 /* doublefault stack space, runs on ist1 */ 1722 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1723 1724 /* 1725 * NMI stack, runs on ist2. The pcpu pointer is stored just 1726 * above the start of the ist2 stack. 1727 */ 1728 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1729 np->np_pcpu = (register_t) pc; 1730 common_tss[0].tss_ist2 = (long) np; 1731 1732 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1733 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1734 IOPAGES * PAGE_SIZE; 1735 1736 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1737 ltr(gsel_tss); 1738 1739 /* Set up the fast syscall stuff */ 1740 msr = rdmsr(MSR_EFER) | EFER_SCE; 1741 wrmsr(MSR_EFER, msr); 1742 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1743 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1744 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1745 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1746 wrmsr(MSR_STAR, msr); 1747 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1748 1749 getmemsize(kmdp, physfree); 1750 init_param2(physmem); 1751 1752 /* now running on new page tables, configured,and u/iom is accessible */ 1753 1754 msgbufinit(msgbufp, msgbufsize); 1755 fpuinit(); 1756 1757 /* transfer to user mode */ 1758 1759 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1760 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1761 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1762 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1763 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1764 1765 load_ds(_udatasel); 1766 load_es(_udatasel); 1767 load_fs(_ufssel); 1768 1769 /* setup proc 0's pcb */ 1770 thread0.td_pcb->pcb_flags = 0; 1771 thread0.td_pcb->pcb_cr3 = KPML4phys; 1772 thread0.td_frame = &proc0_tf; 1773 1774 env = getenv("kernelname"); 1775 if (env != NULL) 1776 strlcpy(kernelname, env, sizeof(kernelname)); 1777 1778#ifdef XENHVM 1779 if (inw(0x10) == 0x49d2) { 1780 if (bootverbose) 1781 printf("Xen detected: disabling emulated block and network devices\n"); 1782 outw(0x10, 3); 1783 } 1784#endif 1785 1786 cpu_probe_amdc1e(); 1787 1788 /* Location of kernel stack for locore */ 1789 return ((u_int64_t)thread0.td_pcb); 1790} 1791 1792void 1793cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1794{ 1795 1796 pcpu->pc_acpi_id = 0xffffffff; 1797} 1798 1799void 1800spinlock_enter(void) 1801{ 1802 struct thread *td; 1803 register_t flags; 1804 1805 td = curthread; 1806 if (td->td_md.md_spinlock_count == 0) { 1807 flags = intr_disable(); 1808 td->td_md.md_spinlock_count = 1; 1809 td->td_md.md_saved_flags = flags; 1810 } else 1811 td->td_md.md_spinlock_count++; 1812 critical_enter(); 1813} 1814 1815void 1816spinlock_exit(void) 1817{ 1818 struct thread *td; 1819 register_t flags; 1820 1821 td = curthread; 1822 critical_exit(); 1823 flags = td->td_md.md_saved_flags; 1824 td->td_md.md_spinlock_count--; 1825 if (td->td_md.md_spinlock_count == 0) 1826 intr_restore(flags); 1827} 1828 1829/* 1830 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1831 * we want to start a backtrace from the function that caused us to enter 1832 * the debugger. We have the context in the trapframe, but base the trace 1833 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1834 * enough for a backtrace. 1835 */ 1836void 1837makectx(struct trapframe *tf, struct pcb *pcb) 1838{ 1839 1840 pcb->pcb_r12 = tf->tf_r12; 1841 pcb->pcb_r13 = tf->tf_r13; 1842 pcb->pcb_r14 = tf->tf_r14; 1843 pcb->pcb_r15 = tf->tf_r15; 1844 pcb->pcb_rbp = tf->tf_rbp; 1845 pcb->pcb_rbx = tf->tf_rbx; 1846 pcb->pcb_rip = tf->tf_rip; 1847 pcb->pcb_rsp = tf->tf_rsp; 1848} 1849 1850int 1851ptrace_set_pc(struct thread *td, unsigned long addr) 1852{ 1853 td->td_frame->tf_rip = addr; 1854 return (0); 1855} 1856 1857int 1858ptrace_single_step(struct thread *td) 1859{ 1860 td->td_frame->tf_rflags |= PSL_T; 1861 return (0); 1862} 1863 1864int 1865ptrace_clear_single_step(struct thread *td) 1866{ 1867 td->td_frame->tf_rflags &= ~PSL_T; 1868 return (0); 1869} 1870 1871int 1872fill_regs(struct thread *td, struct reg *regs) 1873{ 1874 struct trapframe *tp; 1875 1876 tp = td->td_frame; 1877 return (fill_frame_regs(tp, regs)); 1878} 1879 1880int 1881fill_frame_regs(struct trapframe *tp, struct reg *regs) 1882{ 1883 regs->r_r15 = tp->tf_r15; 1884 regs->r_r14 = tp->tf_r14; 1885 regs->r_r13 = tp->tf_r13; 1886 regs->r_r12 = tp->tf_r12; 1887 regs->r_r11 = tp->tf_r11; 1888 regs->r_r10 = tp->tf_r10; 1889 regs->r_r9 = tp->tf_r9; 1890 regs->r_r8 = tp->tf_r8; 1891 regs->r_rdi = tp->tf_rdi; 1892 regs->r_rsi = tp->tf_rsi; 1893 regs->r_rbp = tp->tf_rbp; 1894 regs->r_rbx = tp->tf_rbx; 1895 regs->r_rdx = tp->tf_rdx; 1896 regs->r_rcx = tp->tf_rcx; 1897 regs->r_rax = tp->tf_rax; 1898 regs->r_rip = tp->tf_rip; 1899 regs->r_cs = tp->tf_cs; 1900 regs->r_rflags = tp->tf_rflags; 1901 regs->r_rsp = tp->tf_rsp; 1902 regs->r_ss = tp->tf_ss; 1903 if (tp->tf_flags & TF_HASSEGS) { 1904 regs->r_ds = tp->tf_ds; 1905 regs->r_es = tp->tf_es; 1906 regs->r_fs = tp->tf_fs; 1907 regs->r_gs = tp->tf_gs; 1908 } else { 1909 regs->r_ds = 0; 1910 regs->r_es = 0; 1911 regs->r_fs = 0; 1912 regs->r_gs = 0; 1913 } 1914 return (0); 1915} 1916 1917int 1918set_regs(struct thread *td, struct reg *regs) 1919{ 1920 struct trapframe *tp; 1921 register_t rflags; 1922 1923 tp = td->td_frame; 1924 rflags = regs->r_rflags & 0xffffffff; 1925 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1926 return (EINVAL); 1927 tp->tf_r15 = regs->r_r15; 1928 tp->tf_r14 = regs->r_r14; 1929 tp->tf_r13 = regs->r_r13; 1930 tp->tf_r12 = regs->r_r12; 1931 tp->tf_r11 = regs->r_r11; 1932 tp->tf_r10 = regs->r_r10; 1933 tp->tf_r9 = regs->r_r9; 1934 tp->tf_r8 = regs->r_r8; 1935 tp->tf_rdi = regs->r_rdi; 1936 tp->tf_rsi = regs->r_rsi; 1937 tp->tf_rbp = regs->r_rbp; 1938 tp->tf_rbx = regs->r_rbx; 1939 tp->tf_rdx = regs->r_rdx; 1940 tp->tf_rcx = regs->r_rcx; 1941 tp->tf_rax = regs->r_rax; 1942 tp->tf_rip = regs->r_rip; 1943 tp->tf_cs = regs->r_cs; 1944 tp->tf_rflags = rflags; 1945 tp->tf_rsp = regs->r_rsp; 1946 tp->tf_ss = regs->r_ss; 1947 if (0) { /* XXXKIB */ 1948 tp->tf_ds = regs->r_ds; 1949 tp->tf_es = regs->r_es; 1950 tp->tf_fs = regs->r_fs; 1951 tp->tf_gs = regs->r_gs; 1952 tp->tf_flags = TF_HASSEGS; 1953 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 1954 } 1955 return (0); 1956} 1957 1958/* XXX check all this stuff! */ 1959/* externalize from sv_xmm */ 1960static void 1961fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1962{ 1963 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1964 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1965 int i; 1966 1967 /* pcb -> fpregs */ 1968 bzero(fpregs, sizeof(*fpregs)); 1969 1970 /* FPU control/status */ 1971 penv_fpreg->en_cw = penv_xmm->en_cw; 1972 penv_fpreg->en_sw = penv_xmm->en_sw; 1973 penv_fpreg->en_tw = penv_xmm->en_tw; 1974 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1975 penv_fpreg->en_rip = penv_xmm->en_rip; 1976 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1977 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1978 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1979 1980 /* FPU registers */ 1981 for (i = 0; i < 8; ++i) 1982 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1983 1984 /* SSE registers */ 1985 for (i = 0; i < 16; ++i) 1986 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1987} 1988 1989/* internalize from fpregs into sv_xmm */ 1990static void 1991set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1992{ 1993 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1994 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1995 int i; 1996 1997 /* fpregs -> pcb */ 1998 /* FPU control/status */ 1999 penv_xmm->en_cw = penv_fpreg->en_cw; 2000 penv_xmm->en_sw = penv_fpreg->en_sw; 2001 penv_xmm->en_tw = penv_fpreg->en_tw; 2002 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2003 penv_xmm->en_rip = penv_fpreg->en_rip; 2004 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2005 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2006 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2007 2008 /* FPU registers */ 2009 for (i = 0; i < 8; ++i) 2010 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2011 2012 /* SSE registers */ 2013 for (i = 0; i < 16; ++i) 2014 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2015} 2016 2017/* externalize from td->pcb */ 2018int 2019fill_fpregs(struct thread *td, struct fpreg *fpregs) 2020{ 2021 2022 KASSERT(td == curthread || TD_IS_SUSPENDED(td), 2023 ("not suspended thread %p", td)); 2024 fpugetregs(td); 2025 fill_fpregs_xmm(&td->td_pcb->pcb_user_save, fpregs); 2026 return (0); 2027} 2028 2029/* internalize to td->pcb */ 2030int 2031set_fpregs(struct thread *td, struct fpreg *fpregs) 2032{ 2033 2034 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_user_save); 2035 fpuuserinited(td); 2036 return (0); 2037} 2038 2039/* 2040 * Get machine context. 2041 */ 2042int 2043get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2044{ 2045 struct pcb *pcb; 2046 struct trapframe *tp; 2047 2048 pcb = td->td_pcb; 2049 tp = td->td_frame; 2050 PROC_LOCK(curthread->td_proc); 2051 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2052 PROC_UNLOCK(curthread->td_proc); 2053 mcp->mc_r15 = tp->tf_r15; 2054 mcp->mc_r14 = tp->tf_r14; 2055 mcp->mc_r13 = tp->tf_r13; 2056 mcp->mc_r12 = tp->tf_r12; 2057 mcp->mc_r11 = tp->tf_r11; 2058 mcp->mc_r10 = tp->tf_r10; 2059 mcp->mc_r9 = tp->tf_r9; 2060 mcp->mc_r8 = tp->tf_r8; 2061 mcp->mc_rdi = tp->tf_rdi; 2062 mcp->mc_rsi = tp->tf_rsi; 2063 mcp->mc_rbp = tp->tf_rbp; 2064 mcp->mc_rbx = tp->tf_rbx; 2065 mcp->mc_rcx = tp->tf_rcx; 2066 mcp->mc_rflags = tp->tf_rflags; 2067 if (flags & GET_MC_CLEAR_RET) { 2068 mcp->mc_rax = 0; 2069 mcp->mc_rdx = 0; 2070 mcp->mc_rflags &= ~PSL_C; 2071 } else { 2072 mcp->mc_rax = tp->tf_rax; 2073 mcp->mc_rdx = tp->tf_rdx; 2074 } 2075 mcp->mc_rip = tp->tf_rip; 2076 mcp->mc_cs = tp->tf_cs; 2077 mcp->mc_rsp = tp->tf_rsp; 2078 mcp->mc_ss = tp->tf_ss; 2079 mcp->mc_ds = tp->tf_ds; 2080 mcp->mc_es = tp->tf_es; 2081 mcp->mc_fs = tp->tf_fs; 2082 mcp->mc_gs = tp->tf_gs; 2083 mcp->mc_flags = tp->tf_flags; 2084 mcp->mc_len = sizeof(*mcp); 2085 get_fpcontext(td, mcp); 2086 mcp->mc_fsbase = pcb->pcb_fsbase; 2087 mcp->mc_gsbase = pcb->pcb_gsbase; 2088 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2089 return (0); 2090} 2091 2092/* 2093 * Set machine context. 2094 * 2095 * However, we don't set any but the user modifiable flags, and we won't 2096 * touch the cs selector. 2097 */ 2098int 2099set_mcontext(struct thread *td, const mcontext_t *mcp) 2100{ 2101 struct pcb *pcb; 2102 struct trapframe *tp; 2103 long rflags; 2104 int ret; 2105 2106 pcb = td->td_pcb; 2107 tp = td->td_frame; 2108 if (mcp->mc_len != sizeof(*mcp) || 2109 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2110 return (EINVAL); 2111 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2112 (tp->tf_rflags & ~PSL_USERCHANGE); 2113 ret = set_fpcontext(td, mcp); 2114 if (ret != 0) 2115 return (ret); 2116 tp->tf_r15 = mcp->mc_r15; 2117 tp->tf_r14 = mcp->mc_r14; 2118 tp->tf_r13 = mcp->mc_r13; 2119 tp->tf_r12 = mcp->mc_r12; 2120 tp->tf_r11 = mcp->mc_r11; 2121 tp->tf_r10 = mcp->mc_r10; 2122 tp->tf_r9 = mcp->mc_r9; 2123 tp->tf_r8 = mcp->mc_r8; 2124 tp->tf_rdi = mcp->mc_rdi; 2125 tp->tf_rsi = mcp->mc_rsi; 2126 tp->tf_rbp = mcp->mc_rbp; 2127 tp->tf_rbx = mcp->mc_rbx; 2128 tp->tf_rdx = mcp->mc_rdx; 2129 tp->tf_rcx = mcp->mc_rcx; 2130 tp->tf_rax = mcp->mc_rax; 2131 tp->tf_rip = mcp->mc_rip; 2132 tp->tf_rflags = rflags; 2133 tp->tf_rsp = mcp->mc_rsp; 2134 tp->tf_ss = mcp->mc_ss; 2135 tp->tf_flags = mcp->mc_flags; 2136 if (tp->tf_flags & TF_HASSEGS) { 2137 tp->tf_ds = mcp->mc_ds; 2138 tp->tf_es = mcp->mc_es; 2139 tp->tf_fs = mcp->mc_fs; 2140 tp->tf_gs = mcp->mc_gs; 2141 } 2142 if (mcp->mc_flags & _MC_HASBASES) { 2143 pcb->pcb_fsbase = mcp->mc_fsbase; 2144 pcb->pcb_gsbase = mcp->mc_gsbase; 2145 } 2146 set_pcb_flags(pcb, PCB_FULL_IRET); 2147 return (0); 2148} 2149 2150static void 2151get_fpcontext(struct thread *td, mcontext_t *mcp) 2152{ 2153 2154 mcp->mc_ownedfp = fpugetregs(td); 2155 bcopy(&td->td_pcb->pcb_user_save, &mcp->mc_fpstate, 2156 sizeof(mcp->mc_fpstate)); 2157 mcp->mc_fpformat = fpuformat(); 2158} 2159 2160static int 2161set_fpcontext(struct thread *td, const mcontext_t *mcp) 2162{ 2163 struct savefpu *fpstate; 2164 2165 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2166 return (0); 2167 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2168 return (EINVAL); 2169 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2170 /* We don't care what state is left in the FPU or PCB. */ 2171 fpstate_drop(td); 2172 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2173 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2174 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2175 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2176 fpusetregs(td, fpstate); 2177 } else 2178 return (EINVAL); 2179 return (0); 2180} 2181 2182void 2183fpstate_drop(struct thread *td) 2184{ 2185 2186 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2187 critical_enter(); 2188 if (PCPU_GET(fpcurthread) == td) 2189 fpudrop(); 2190 /* 2191 * XXX force a full drop of the fpu. The above only drops it if we 2192 * owned it. 2193 * 2194 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2195 * drop. Dropping only to the pcb matches fnsave's behaviour. 2196 * We only need to drop to !PCB_INITDONE in sendsig(). But 2197 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2198 * have too many layers. 2199 */ 2200 clear_pcb_flags(curthread->td_pcb, 2201 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2202 critical_exit(); 2203} 2204 2205int 2206fill_dbregs(struct thread *td, struct dbreg *dbregs) 2207{ 2208 struct pcb *pcb; 2209 2210 if (td == NULL) { 2211 dbregs->dr[0] = rdr0(); 2212 dbregs->dr[1] = rdr1(); 2213 dbregs->dr[2] = rdr2(); 2214 dbregs->dr[3] = rdr3(); 2215 dbregs->dr[6] = rdr6(); 2216 dbregs->dr[7] = rdr7(); 2217 } else { 2218 pcb = td->td_pcb; 2219 dbregs->dr[0] = pcb->pcb_dr0; 2220 dbregs->dr[1] = pcb->pcb_dr1; 2221 dbregs->dr[2] = pcb->pcb_dr2; 2222 dbregs->dr[3] = pcb->pcb_dr3; 2223 dbregs->dr[6] = pcb->pcb_dr6; 2224 dbregs->dr[7] = pcb->pcb_dr7; 2225 } 2226 dbregs->dr[4] = 0; 2227 dbregs->dr[5] = 0; 2228 dbregs->dr[8] = 0; 2229 dbregs->dr[9] = 0; 2230 dbregs->dr[10] = 0; 2231 dbregs->dr[11] = 0; 2232 dbregs->dr[12] = 0; 2233 dbregs->dr[13] = 0; 2234 dbregs->dr[14] = 0; 2235 dbregs->dr[15] = 0; 2236 return (0); 2237} 2238 2239int 2240set_dbregs(struct thread *td, struct dbreg *dbregs) 2241{ 2242 struct pcb *pcb; 2243 int i; 2244 2245 if (td == NULL) { 2246 load_dr0(dbregs->dr[0]); 2247 load_dr1(dbregs->dr[1]); 2248 load_dr2(dbregs->dr[2]); 2249 load_dr3(dbregs->dr[3]); 2250 load_dr6(dbregs->dr[6]); 2251 load_dr7(dbregs->dr[7]); 2252 } else { 2253 /* 2254 * Don't let an illegal value for dr7 get set. Specifically, 2255 * check for undefined settings. Setting these bit patterns 2256 * result in undefined behaviour and can lead to an unexpected 2257 * TRCTRAP or a general protection fault right here. 2258 * Upper bits of dr6 and dr7 must not be set 2259 */ 2260 for (i = 0; i < 4; i++) { 2261 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2262 return (EINVAL); 2263 if (td->td_frame->tf_cs == _ucode32sel && 2264 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2265 return (EINVAL); 2266 } 2267 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2268 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2269 return (EINVAL); 2270 2271 pcb = td->td_pcb; 2272 2273 /* 2274 * Don't let a process set a breakpoint that is not within the 2275 * process's address space. If a process could do this, it 2276 * could halt the system by setting a breakpoint in the kernel 2277 * (if ddb was enabled). Thus, we need to check to make sure 2278 * that no breakpoints are being enabled for addresses outside 2279 * process's address space. 2280 * 2281 * XXX - what about when the watched area of the user's 2282 * address space is written into from within the kernel 2283 * ... wouldn't that still cause a breakpoint to be generated 2284 * from within kernel mode? 2285 */ 2286 2287 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2288 /* dr0 is enabled */ 2289 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2290 return (EINVAL); 2291 } 2292 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2293 /* dr1 is enabled */ 2294 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2295 return (EINVAL); 2296 } 2297 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2298 /* dr2 is enabled */ 2299 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2300 return (EINVAL); 2301 } 2302 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2303 /* dr3 is enabled */ 2304 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2305 return (EINVAL); 2306 } 2307 2308 pcb->pcb_dr0 = dbregs->dr[0]; 2309 pcb->pcb_dr1 = dbregs->dr[1]; 2310 pcb->pcb_dr2 = dbregs->dr[2]; 2311 pcb->pcb_dr3 = dbregs->dr[3]; 2312 pcb->pcb_dr6 = dbregs->dr[6]; 2313 pcb->pcb_dr7 = dbregs->dr[7]; 2314 2315 set_pcb_flags(pcb, PCB_DBREGS); 2316 } 2317 2318 return (0); 2319} 2320 2321void 2322reset_dbregs(void) 2323{ 2324 2325 load_dr7(0); /* Turn off the control bits first */ 2326 load_dr0(0); 2327 load_dr1(0); 2328 load_dr2(0); 2329 load_dr3(0); 2330 load_dr6(0); 2331} 2332 2333/* 2334 * Return > 0 if a hardware breakpoint has been hit, and the 2335 * breakpoint was in user space. Return 0, otherwise. 2336 */ 2337int 2338user_dbreg_trap(void) 2339{ 2340 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2341 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2342 int nbp; /* number of breakpoints that triggered */ 2343 caddr_t addr[4]; /* breakpoint addresses */ 2344 int i; 2345 2346 dr7 = rdr7(); 2347 if ((dr7 & 0x000000ff) == 0) { 2348 /* 2349 * all GE and LE bits in the dr7 register are zero, 2350 * thus the trap couldn't have been caused by the 2351 * hardware debug registers 2352 */ 2353 return 0; 2354 } 2355 2356 nbp = 0; 2357 dr6 = rdr6(); 2358 bp = dr6 & 0x0000000f; 2359 2360 if (!bp) { 2361 /* 2362 * None of the breakpoint bits are set meaning this 2363 * trap was not caused by any of the debug registers 2364 */ 2365 return 0; 2366 } 2367 2368 /* 2369 * at least one of the breakpoints were hit, check to see 2370 * which ones and if any of them are user space addresses 2371 */ 2372 2373 if (bp & 0x01) { 2374 addr[nbp++] = (caddr_t)rdr0(); 2375 } 2376 if (bp & 0x02) { 2377 addr[nbp++] = (caddr_t)rdr1(); 2378 } 2379 if (bp & 0x04) { 2380 addr[nbp++] = (caddr_t)rdr2(); 2381 } 2382 if (bp & 0x08) { 2383 addr[nbp++] = (caddr_t)rdr3(); 2384 } 2385 2386 for (i = 0; i < nbp; i++) { 2387 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2388 /* 2389 * addr[i] is in user space 2390 */ 2391 return nbp; 2392 } 2393 } 2394 2395 /* 2396 * None of the breakpoints are in user space. 2397 */ 2398 return 0; 2399} 2400 2401#ifdef KDB 2402 2403/* 2404 * Provide inb() and outb() as functions. They are normally only available as 2405 * inline functions, thus cannot be called from the debugger. 2406 */ 2407 2408/* silence compiler warnings */ 2409u_char inb_(u_short); 2410void outb_(u_short, u_char); 2411 2412u_char 2413inb_(u_short port) 2414{ 2415 return inb(port); 2416} 2417 2418void 2419outb_(u_short port, u_char data) 2420{ 2421 outb(port, data); 2422} 2423 2424#endif /* KDB */ 2425