machdep.c revision 213382
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 213382 2010-10-03 13:52:17Z kib $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_msgbuf.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57#include "opt_kdtrace.h" 58 59#include <sys/param.h> 60#include <sys/proc.h> 61#include <sys/systm.h> 62#include <sys/bio.h> 63#include <sys/buf.h> 64#include <sys/bus.h> 65#include <sys/callout.h> 66#include <sys/cons.h> 67#include <sys/cpu.h> 68#include <sys/eventhandler.h> 69#include <sys/exec.h> 70#include <sys/imgact.h> 71#include <sys/kdb.h> 72#include <sys/kernel.h> 73#include <sys/ktr.h> 74#include <sys/linker.h> 75#include <sys/lock.h> 76#include <sys/malloc.h> 77#include <sys/memrange.h> 78#include <sys/msgbuf.h> 79#include <sys/mutex.h> 80#include <sys/pcpu.h> 81#include <sys/ptrace.h> 82#include <sys/reboot.h> 83#include <sys/sched.h> 84#include <sys/signalvar.h> 85#include <sys/syscallsubr.h> 86#include <sys/sysctl.h> 87#include <sys/sysent.h> 88#include <sys/sysproto.h> 89#include <sys/ucontext.h> 90#include <sys/vmmeter.h> 91 92#include <vm/vm.h> 93#include <vm/vm_extern.h> 94#include <vm/vm_kern.h> 95#include <vm/vm_page.h> 96#include <vm/vm_map.h> 97#include <vm/vm_object.h> 98#include <vm/vm_pager.h> 99#include <vm/vm_param.h> 100 101#ifdef DDB 102#ifndef KDB 103#error KDB must be enabled in order for DDB to work! 104#endif 105#include <ddb/ddb.h> 106#include <ddb/db_sym.h> 107#endif 108 109#include <net/netisr.h> 110 111#include <machine/clock.h> 112#include <machine/cpu.h> 113#include <machine/cputypes.h> 114#include <machine/intr_machdep.h> 115#include <machine/mca.h> 116#include <machine/md_var.h> 117#include <machine/metadata.h> 118#include <machine/pc/bios.h> 119#include <machine/pcb.h> 120#include <machine/proc.h> 121#include <machine/reg.h> 122#include <machine/sigframe.h> 123#include <machine/specialreg.h> 124#ifdef PERFMON 125#include <machine/perfmon.h> 126#endif 127#include <machine/tss.h> 128#ifdef SMP 129#include <machine/smp.h> 130#endif 131 132#ifdef DEV_ATPIC 133#include <x86/isa/icu.h> 134#else 135#include <machine/apicvar.h> 136#endif 137 138#include <isa/isareg.h> 139#include <isa/rtc.h> 140 141/* Sanity check for __curthread() */ 142CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 143 144extern u_int64_t hammer_time(u_int64_t, u_int64_t); 145 146extern void printcpuinfo(void); /* XXX header file */ 147extern void identify_cpu(void); 148extern void panicifcpuunsupported(void); 149 150#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 151#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 152 153static void cpu_startup(void *); 154static void get_fpcontext(struct thread *td, mcontext_t *mcp); 155static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 156SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 157 158#ifdef DDB 159extern vm_offset_t ksym_start, ksym_end; 160#endif 161 162struct msgbuf *msgbufp; 163 164/* Intel ICH registers */ 165#define ICH_PMBASE 0x400 166#define ICH_SMI_EN ICH_PMBASE + 0x30 167 168int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 169 170int cold = 1; 171 172long Maxmem = 0; 173long realmem = 0; 174 175/* 176 * The number of PHYSMAP entries must be one less than the number of 177 * PHYSSEG entries because the PHYSMAP entry that spans the largest 178 * physical address that is accessible by ISA DMA is split into two 179 * PHYSSEG entries. 180 */ 181#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 182 183vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 184vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 185 186/* must be 2 less so 0 0 can signal end of chunks */ 187#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 188#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 189 190struct kva_md_info kmi; 191 192static struct trapframe proc0_tf; 193struct region_descriptor r_gdt, r_idt; 194 195struct pcpu __pcpu[MAXCPU]; 196 197struct mtx icu_lock; 198 199struct mem_range_softc mem_range_softc; 200 201struct mtx dt_lock; /* lock for GDT and LDT */ 202 203static void 204cpu_startup(dummy) 205 void *dummy; 206{ 207 uintmax_t memsize; 208 char *sysenv; 209 210 /* 211 * On MacBooks, we need to disallow the legacy USB circuit to 212 * generate an SMI# because this can cause several problems, 213 * namely: incorrect CPU frequency detection and failure to 214 * start the APs. 215 * We do this by disabling a bit in the SMI_EN (SMI Control and 216 * Enable register) of the Intel ICH LPC Interface Bridge. 217 */ 218 sysenv = getenv("smbios.system.product"); 219 if (sysenv != NULL) { 220 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 221 strncmp(sysenv, "MacBook3,1", 10) == 0 || 222 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 223 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 224 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 225 strncmp(sysenv, "Macmini1,1", 10) == 0) { 226 if (bootverbose) 227 printf("Disabling LEGACY_USB_EN bit on " 228 "Intel ICH.\n"); 229 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 230 } 231 freeenv(sysenv); 232 } 233 234 /* 235 * Good {morning,afternoon,evening,night}. 236 */ 237 startrtclock(); 238 printcpuinfo(); 239 panicifcpuunsupported(); 240#ifdef PERFMON 241 perfmon_init(); 242#endif 243 realmem = Maxmem; 244 245 /* 246 * Display physical memory if SMBIOS reports reasonable amount. 247 */ 248 memsize = 0; 249 sysenv = getenv("smbios.memory.enabled"); 250 if (sysenv != NULL) { 251 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 252 freeenv(sysenv); 253 } 254 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 255 memsize = ptoa((uintmax_t)Maxmem); 256 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 257 258 /* 259 * Display any holes after the first chunk of extended memory. 260 */ 261 if (bootverbose) { 262 int indx; 263 264 printf("Physical memory chunk(s):\n"); 265 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 266 vm_paddr_t size; 267 268 size = phys_avail[indx + 1] - phys_avail[indx]; 269 printf( 270 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 271 (uintmax_t)phys_avail[indx], 272 (uintmax_t)phys_avail[indx + 1] - 1, 273 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 274 } 275 } 276 277 vm_ksubmap_init(&kmi); 278 279 printf("avail memory = %ju (%ju MB)\n", 280 ptoa((uintmax_t)cnt.v_free_count), 281 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 282 283 /* 284 * Set up buffers, so they can be used to read disk labels. 285 */ 286 bufinit(); 287 vm_pager_bufferinit(); 288 289 cpu_setregs(); 290} 291 292/* 293 * Send an interrupt to process. 294 * 295 * Stack is set up to allow sigcode stored 296 * at top to call routine, followed by call 297 * to sigreturn routine below. After sigreturn 298 * resets the signal mask, the stack, and the 299 * frame pointer, it returns to the user 300 * specified pc, psl. 301 */ 302void 303sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 304{ 305 struct sigframe sf, *sfp; 306 struct proc *p; 307 struct thread *td; 308 struct sigacts *psp; 309 char *sp; 310 struct trapframe *regs; 311 int sig; 312 int oonstack; 313 314 td = curthread; 315 p = td->td_proc; 316 PROC_LOCK_ASSERT(p, MA_OWNED); 317 sig = ksi->ksi_signo; 318 psp = p->p_sigacts; 319 mtx_assert(&psp->ps_mtx, MA_OWNED); 320 regs = td->td_frame; 321 oonstack = sigonstack(regs->tf_rsp); 322 323 /* Save user context. */ 324 bzero(&sf, sizeof(sf)); 325 sf.sf_uc.uc_sigmask = *mask; 326 sf.sf_uc.uc_stack = td->td_sigstk; 327 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 328 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 329 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 330 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 331 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 332 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 333 fpstate_drop(td); 334 sf.sf_uc.uc_mcontext.mc_fsbase = td->td_pcb->pcb_fsbase; 335 sf.sf_uc.uc_mcontext.mc_gsbase = td->td_pcb->pcb_gsbase; 336 337 /* Allocate space for the signal handler context. */ 338 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 339 SIGISMEMBER(psp->ps_sigonstack, sig)) { 340 sp = td->td_sigstk.ss_sp + 341 td->td_sigstk.ss_size - sizeof(struct sigframe); 342#if defined(COMPAT_43) 343 td->td_sigstk.ss_flags |= SS_ONSTACK; 344#endif 345 } else 346 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 347 /* Align to 16 bytes. */ 348 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 349 350 /* Translate the signal if appropriate. */ 351 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 352 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 353 354 /* Build the argument list for the signal handler. */ 355 regs->tf_rdi = sig; /* arg 1 in %rdi */ 356 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 357 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 358 /* Signal handler installed with SA_SIGINFO. */ 359 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 360 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 361 362 /* Fill in POSIX parts */ 363 sf.sf_si = ksi->ksi_info; 364 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 365 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 366 } else { 367 /* Old FreeBSD-style arguments. */ 368 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 369 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 370 sf.sf_ahu.sf_handler = catcher; 371 } 372 mtx_unlock(&psp->ps_mtx); 373 PROC_UNLOCK(p); 374 375 /* 376 * Copy the sigframe out to the user's stack. 377 */ 378 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 379#ifdef DEBUG 380 printf("process %ld has trashed its stack\n", (long)p->p_pid); 381#endif 382 PROC_LOCK(p); 383 sigexit(td, SIGILL); 384 } 385 386 regs->tf_rsp = (long)sfp; 387 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 388 regs->tf_rflags &= ~(PSL_T | PSL_D); 389 regs->tf_cs = _ucodesel; 390 regs->tf_ds = _udatasel; 391 regs->tf_es = _udatasel; 392 regs->tf_fs = _ufssel; 393 regs->tf_gs = _ugssel; 394 regs->tf_flags = TF_HASSEGS; 395 td->td_pcb->pcb_full_iret = 1; 396 PROC_LOCK(p); 397 mtx_lock(&psp->ps_mtx); 398} 399 400/* 401 * System call to cleanup state after a signal 402 * has been taken. Reset signal mask and 403 * stack state from context left by sendsig (above). 404 * Return to previous pc and psl as specified by 405 * context left by sendsig. Check carefully to 406 * make sure that the user has not modified the 407 * state to gain improper privileges. 408 * 409 * MPSAFE 410 */ 411int 412sigreturn(td, uap) 413 struct thread *td; 414 struct sigreturn_args /* { 415 const struct __ucontext *sigcntxp; 416 } */ *uap; 417{ 418 ucontext_t uc; 419 struct proc *p = td->td_proc; 420 struct trapframe *regs; 421 ucontext_t *ucp; 422 long rflags; 423 int cs, error, ret; 424 ksiginfo_t ksi; 425 426 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 427 if (error != 0) { 428 uprintf("pid %d (%s): sigreturn copyin failed\n", 429 p->p_pid, td->td_name); 430 return (error); 431 } 432 ucp = &uc; 433 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 434 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 435 td->td_name, ucp->uc_mcontext.mc_flags); 436 return (EINVAL); 437 } 438 regs = td->td_frame; 439 rflags = ucp->uc_mcontext.mc_rflags; 440 /* 441 * Don't allow users to change privileged or reserved flags. 442 */ 443 /* 444 * XXX do allow users to change the privileged flag PSL_RF. 445 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 446 * should sometimes set it there too. tf_rflags is kept in 447 * the signal context during signal handling and there is no 448 * other place to remember it, so the PSL_RF bit may be 449 * corrupted by the signal handler without us knowing. 450 * Corruption of the PSL_RF bit at worst causes one more or 451 * one less debugger trap, so allowing it is fairly harmless. 452 */ 453 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 454 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 455 td->td_name, rflags); 456 return (EINVAL); 457 } 458 459 /* 460 * Don't allow users to load a valid privileged %cs. Let the 461 * hardware check for invalid selectors, excess privilege in 462 * other selectors, invalid %eip's and invalid %esp's. 463 */ 464 cs = ucp->uc_mcontext.mc_cs; 465 if (!CS_SECURE(cs)) { 466 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 467 td->td_name, cs); 468 ksiginfo_init_trap(&ksi); 469 ksi.ksi_signo = SIGBUS; 470 ksi.ksi_code = BUS_OBJERR; 471 ksi.ksi_trapno = T_PROTFLT; 472 ksi.ksi_addr = (void *)regs->tf_rip; 473 trapsignal(td, &ksi); 474 return (EINVAL); 475 } 476 477 ret = set_fpcontext(td, &ucp->uc_mcontext); 478 if (ret != 0) { 479 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 480 p->p_pid, td->td_name, ret); 481 return (ret); 482 } 483 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 484 td->td_pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 485 td->td_pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 486 487#if defined(COMPAT_43) 488 if (ucp->uc_mcontext.mc_onstack & 1) 489 td->td_sigstk.ss_flags |= SS_ONSTACK; 490 else 491 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 492#endif 493 494 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 495 td->td_pcb->pcb_flags |= PCB_FULLCTX; 496 td->td_pcb->pcb_full_iret = 1; 497 return (EJUSTRETURN); 498} 499 500#ifdef COMPAT_FREEBSD4 501int 502freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 503{ 504 505 return sigreturn(td, (struct sigreturn_args *)uap); 506} 507#endif 508 509 510/* 511 * Machine dependent boot() routine 512 * 513 * I haven't seen anything to put here yet 514 * Possibly some stuff might be grafted back here from boot() 515 */ 516void 517cpu_boot(int howto) 518{ 519} 520 521/* 522 * Flush the D-cache for non-DMA I/O so that the I-cache can 523 * be made coherent later. 524 */ 525void 526cpu_flush_dcache(void *ptr, size_t len) 527{ 528 /* Not applicable */ 529} 530 531/* Get current clock frequency for the given cpu id. */ 532int 533cpu_est_clockrate(int cpu_id, uint64_t *rate) 534{ 535 register_t reg; 536 uint64_t tsc1, tsc2; 537 538 if (pcpu_find(cpu_id) == NULL || rate == NULL) 539 return (EINVAL); 540 541 /* If we're booting, trust the rate calibrated moments ago. */ 542 if (cold) { 543 *rate = tsc_freq; 544 return (0); 545 } 546 547#ifdef SMP 548 /* Schedule ourselves on the indicated cpu. */ 549 thread_lock(curthread); 550 sched_bind(curthread, cpu_id); 551 thread_unlock(curthread); 552#endif 553 554 /* Calibrate by measuring a short delay. */ 555 reg = intr_disable(); 556 tsc1 = rdtsc(); 557 DELAY(1000); 558 tsc2 = rdtsc(); 559 intr_restore(reg); 560 561#ifdef SMP 562 thread_lock(curthread); 563 sched_unbind(curthread); 564 thread_unlock(curthread); 565#endif 566 567 /* 568 * Calculate the difference in readings, convert to Mhz, and 569 * subtract 0.5% of the total. Empirical testing has shown that 570 * overhead in DELAY() works out to approximately this value. 571 */ 572 tsc2 -= tsc1; 573 *rate = tsc2 * 1000 - tsc2 * 5; 574 return (0); 575} 576 577/* 578 * Shutdown the CPU as much as possible 579 */ 580void 581cpu_halt(void) 582{ 583 for (;;) 584 __asm__ ("hlt"); 585} 586 587void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 588static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 589static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 590TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 591SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 592 0, "Use MONITOR/MWAIT for short idle"); 593 594#define STATE_RUNNING 0x0 595#define STATE_MWAIT 0x1 596#define STATE_SLEEPING 0x2 597 598static void 599cpu_idle_acpi(int busy) 600{ 601 int *state; 602 603 state = (int *)PCPU_PTR(monitorbuf); 604 *state = STATE_SLEEPING; 605 disable_intr(); 606 if (sched_runnable()) 607 enable_intr(); 608 else if (cpu_idle_hook) 609 cpu_idle_hook(); 610 else 611 __asm __volatile("sti; hlt"); 612 *state = STATE_RUNNING; 613} 614 615static void 616cpu_idle_hlt(int busy) 617{ 618 int *state; 619 620 state = (int *)PCPU_PTR(monitorbuf); 621 *state = STATE_SLEEPING; 622 /* 623 * We must absolutely guarentee that hlt is the next instruction 624 * after sti or we introduce a timing window. 625 */ 626 disable_intr(); 627 if (sched_runnable()) 628 enable_intr(); 629 else 630 __asm __volatile("sti; hlt"); 631 *state = STATE_RUNNING; 632} 633 634/* 635 * MWAIT cpu power states. Lower 4 bits are sub-states. 636 */ 637#define MWAIT_C0 0xf0 638#define MWAIT_C1 0x00 639#define MWAIT_C2 0x10 640#define MWAIT_C3 0x20 641#define MWAIT_C4 0x30 642 643static void 644cpu_idle_mwait(int busy) 645{ 646 int *state; 647 648 state = (int *)PCPU_PTR(monitorbuf); 649 *state = STATE_MWAIT; 650 if (!sched_runnable()) { 651 cpu_monitor(state, 0, 0); 652 if (*state == STATE_MWAIT) 653 cpu_mwait(0, MWAIT_C1); 654 } 655 *state = STATE_RUNNING; 656} 657 658static void 659cpu_idle_spin(int busy) 660{ 661 int *state; 662 int i; 663 664 state = (int *)PCPU_PTR(monitorbuf); 665 *state = STATE_RUNNING; 666 for (i = 0; i < 1000; i++) { 667 if (sched_runnable()) 668 return; 669 cpu_spinwait(); 670 } 671} 672 673/* 674 * C1E renders the local APIC timer dead, so we disable it by 675 * reading the Interrupt Pending Message register and clearing 676 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 677 * 678 * Reference: 679 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 680 * #32559 revision 3.00+ 681 */ 682#define MSR_AMDK8_IPM 0xc0010055 683#define AMDK8_SMIONCMPHALT (1ULL << 27) 684#define AMDK8_C1EONCMPHALT (1ULL << 28) 685#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 686 687static void 688cpu_probe_amdc1e(void) 689{ 690 691 /* 692 * Detect the presence of C1E capability mostly on latest 693 * dual-cores (or future) k8 family. 694 */ 695 if (cpu_vendor_id == CPU_VENDOR_AMD && 696 (cpu_id & 0x00000f00) == 0x00000f00 && 697 (cpu_id & 0x0fff0000) >= 0x00040000) { 698 cpu_ident_amdc1e = 1; 699 } 700} 701 702void (*cpu_idle_fn)(int) = cpu_idle_acpi; 703 704void 705cpu_idle(int busy) 706{ 707 uint64_t msr; 708 709 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 710 busy, curcpu); 711#ifdef SMP 712 if (mp_grab_cpu_hlt()) 713 return; 714#endif 715 /* If we are busy - try to use fast methods. */ 716 if (busy) { 717 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 718 cpu_idle_mwait(busy); 719 goto out; 720 } 721 } 722 723 /* If we have time - switch timers into idle mode. */ 724 if (!busy) { 725 critical_enter(); 726 cpu_idleclock(); 727 } 728 729 /* Apply AMD APIC timer C1E workaround. */ 730 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 731 msr = rdmsr(MSR_AMDK8_IPM); 732 if (msr & AMDK8_CMPHALT) 733 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 734 } 735 736 /* Call main idle method. */ 737 cpu_idle_fn(busy); 738 739 /* Switch timers mack into active mode. */ 740 if (!busy) { 741 cpu_activeclock(); 742 critical_exit(); 743 } 744out: 745 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 746 busy, curcpu); 747} 748 749int 750cpu_idle_wakeup(int cpu) 751{ 752 struct pcpu *pcpu; 753 int *state; 754 755 pcpu = pcpu_find(cpu); 756 state = (int *)pcpu->pc_monitorbuf; 757 /* 758 * This doesn't need to be atomic since missing the race will 759 * simply result in unnecessary IPIs. 760 */ 761 if (*state == STATE_SLEEPING) 762 return (0); 763 if (*state == STATE_MWAIT) 764 *state = STATE_RUNNING; 765 return (1); 766} 767 768/* 769 * Ordered by speed/power consumption. 770 */ 771struct { 772 void *id_fn; 773 char *id_name; 774} idle_tbl[] = { 775 { cpu_idle_spin, "spin" }, 776 { cpu_idle_mwait, "mwait" }, 777 { cpu_idle_hlt, "hlt" }, 778 { cpu_idle_acpi, "acpi" }, 779 { NULL, NULL } 780}; 781 782static int 783idle_sysctl_available(SYSCTL_HANDLER_ARGS) 784{ 785 char *avail, *p; 786 int error; 787 int i; 788 789 avail = malloc(256, M_TEMP, M_WAITOK); 790 p = avail; 791 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 792 if (strstr(idle_tbl[i].id_name, "mwait") && 793 (cpu_feature2 & CPUID2_MON) == 0) 794 continue; 795 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 796 cpu_idle_hook == NULL) 797 continue; 798 p += sprintf(p, "%s, ", idle_tbl[i].id_name); 799 } 800 error = sysctl_handle_string(oidp, avail, 0, req); 801 free(avail, M_TEMP); 802 return (error); 803} 804 805SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 806 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 807 808static int 809idle_sysctl(SYSCTL_HANDLER_ARGS) 810{ 811 char buf[16]; 812 int error; 813 char *p; 814 int i; 815 816 p = "unknown"; 817 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 818 if (idle_tbl[i].id_fn == cpu_idle_fn) { 819 p = idle_tbl[i].id_name; 820 break; 821 } 822 } 823 strncpy(buf, p, sizeof(buf)); 824 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 825 if (error != 0 || req->newptr == NULL) 826 return (error); 827 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 828 if (strstr(idle_tbl[i].id_name, "mwait") && 829 (cpu_feature2 & CPUID2_MON) == 0) 830 continue; 831 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 832 cpu_idle_hook == NULL) 833 continue; 834 if (strcmp(idle_tbl[i].id_name, buf)) 835 continue; 836 cpu_idle_fn = idle_tbl[i].id_fn; 837 return (0); 838 } 839 return (EINVAL); 840} 841 842SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 843 idle_sysctl, "A", "currently selected idle function"); 844 845/* 846 * Reset registers to default values on exec. 847 */ 848void 849exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 850{ 851 struct trapframe *regs = td->td_frame; 852 struct pcb *pcb = td->td_pcb; 853 854 mtx_lock(&dt_lock); 855 if (td->td_proc->p_md.md_ldt != NULL) 856 user_ldt_free(td); 857 else 858 mtx_unlock(&dt_lock); 859 860 pcb->pcb_fsbase = 0; 861 pcb->pcb_gsbase = 0; 862 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 863 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 864 pcb->pcb_full_iret = 1; 865 866 bzero((char *)regs, sizeof(struct trapframe)); 867 regs->tf_rip = imgp->entry_addr; 868 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 869 regs->tf_rdi = stack; /* argv */ 870 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 871 regs->tf_ss = _udatasel; 872 regs->tf_cs = _ucodesel; 873 regs->tf_ds = _udatasel; 874 regs->tf_es = _udatasel; 875 regs->tf_fs = _ufssel; 876 regs->tf_gs = _ugssel; 877 regs->tf_flags = TF_HASSEGS; 878 879 /* 880 * Reset the hardware debug registers if they were in use. 881 * They won't have any meaning for the newly exec'd process. 882 */ 883 if (pcb->pcb_flags & PCB_DBREGS) { 884 pcb->pcb_dr0 = 0; 885 pcb->pcb_dr1 = 0; 886 pcb->pcb_dr2 = 0; 887 pcb->pcb_dr3 = 0; 888 pcb->pcb_dr6 = 0; 889 pcb->pcb_dr7 = 0; 890 if (pcb == PCPU_GET(curpcb)) { 891 /* 892 * Clear the debug registers on the running 893 * CPU, otherwise they will end up affecting 894 * the next process we switch to. 895 */ 896 reset_dbregs(); 897 } 898 pcb->pcb_flags &= ~PCB_DBREGS; 899 } 900 901 /* 902 * Drop the FP state if we hold it, so that the process gets a 903 * clean FP state if it uses the FPU again. 904 */ 905 fpstate_drop(td); 906} 907 908void 909cpu_setregs(void) 910{ 911 register_t cr0; 912 913 cr0 = rcr0(); 914 /* 915 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 916 * BSP. See the comments there about why we set them. 917 */ 918 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 919 load_cr0(cr0); 920} 921 922/* 923 * Initialize amd64 and configure to run kernel 924 */ 925 926/* 927 * Initialize segments & interrupt table 928 */ 929 930struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 931static struct gate_descriptor idt0[NIDT]; 932struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 933 934static char dblfault_stack[PAGE_SIZE] __aligned(16); 935 936static char nmi0_stack[PAGE_SIZE] __aligned(16); 937CTASSERT(sizeof(struct nmi_pcpu) == 16); 938 939struct amd64tss common_tss[MAXCPU]; 940 941/* 942 * Software prototypes -- in more palatable form. 943 * 944 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 945 * slots as corresponding segments for i386 kernel. 946 */ 947struct soft_segment_descriptor gdt_segs[] = { 948/* GNULL_SEL 0 Null Descriptor */ 949{ .ssd_base = 0x0, 950 .ssd_limit = 0x0, 951 .ssd_type = 0, 952 .ssd_dpl = 0, 953 .ssd_p = 0, 954 .ssd_long = 0, 955 .ssd_def32 = 0, 956 .ssd_gran = 0 }, 957/* GNULL2_SEL 1 Null Descriptor */ 958{ .ssd_base = 0x0, 959 .ssd_limit = 0x0, 960 .ssd_type = 0, 961 .ssd_dpl = 0, 962 .ssd_p = 0, 963 .ssd_long = 0, 964 .ssd_def32 = 0, 965 .ssd_gran = 0 }, 966/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 967{ .ssd_base = 0x0, 968 .ssd_limit = 0xfffff, 969 .ssd_type = SDT_MEMRWA, 970 .ssd_dpl = SEL_UPL, 971 .ssd_p = 1, 972 .ssd_long = 0, 973 .ssd_def32 = 1, 974 .ssd_gran = 1 }, 975/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 976{ .ssd_base = 0x0, 977 .ssd_limit = 0xfffff, 978 .ssd_type = SDT_MEMRWA, 979 .ssd_dpl = SEL_UPL, 980 .ssd_p = 1, 981 .ssd_long = 0, 982 .ssd_def32 = 1, 983 .ssd_gran = 1 }, 984/* GCODE_SEL 4 Code Descriptor for kernel */ 985{ .ssd_base = 0x0, 986 .ssd_limit = 0xfffff, 987 .ssd_type = SDT_MEMERA, 988 .ssd_dpl = SEL_KPL, 989 .ssd_p = 1, 990 .ssd_long = 1, 991 .ssd_def32 = 0, 992 .ssd_gran = 1 }, 993/* GDATA_SEL 5 Data Descriptor for kernel */ 994{ .ssd_base = 0x0, 995 .ssd_limit = 0xfffff, 996 .ssd_type = SDT_MEMRWA, 997 .ssd_dpl = SEL_KPL, 998 .ssd_p = 1, 999 .ssd_long = 1, 1000 .ssd_def32 = 0, 1001 .ssd_gran = 1 }, 1002/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1003{ .ssd_base = 0x0, 1004 .ssd_limit = 0xfffff, 1005 .ssd_type = SDT_MEMERA, 1006 .ssd_dpl = SEL_UPL, 1007 .ssd_p = 1, 1008 .ssd_long = 0, 1009 .ssd_def32 = 1, 1010 .ssd_gran = 1 }, 1011/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1012{ .ssd_base = 0x0, 1013 .ssd_limit = 0xfffff, 1014 .ssd_type = SDT_MEMRWA, 1015 .ssd_dpl = SEL_UPL, 1016 .ssd_p = 1, 1017 .ssd_long = 0, 1018 .ssd_def32 = 1, 1019 .ssd_gran = 1 }, 1020/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1021{ .ssd_base = 0x0, 1022 .ssd_limit = 0xfffff, 1023 .ssd_type = SDT_MEMERA, 1024 .ssd_dpl = SEL_UPL, 1025 .ssd_p = 1, 1026 .ssd_long = 1, 1027 .ssd_def32 = 0, 1028 .ssd_gran = 1 }, 1029/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1030{ .ssd_base = 0x0, 1031 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1032 .ssd_type = SDT_SYSTSS, 1033 .ssd_dpl = SEL_KPL, 1034 .ssd_p = 1, 1035 .ssd_long = 0, 1036 .ssd_def32 = 0, 1037 .ssd_gran = 0 }, 1038/* Actually, the TSS is a system descriptor which is double size */ 1039{ .ssd_base = 0x0, 1040 .ssd_limit = 0x0, 1041 .ssd_type = 0, 1042 .ssd_dpl = 0, 1043 .ssd_p = 0, 1044 .ssd_long = 0, 1045 .ssd_def32 = 0, 1046 .ssd_gran = 0 }, 1047/* GUSERLDT_SEL 11 LDT Descriptor */ 1048{ .ssd_base = 0x0, 1049 .ssd_limit = 0x0, 1050 .ssd_type = 0, 1051 .ssd_dpl = 0, 1052 .ssd_p = 0, 1053 .ssd_long = 0, 1054 .ssd_def32 = 0, 1055 .ssd_gran = 0 }, 1056/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1057{ .ssd_base = 0x0, 1058 .ssd_limit = 0x0, 1059 .ssd_type = 0, 1060 .ssd_dpl = 0, 1061 .ssd_p = 0, 1062 .ssd_long = 0, 1063 .ssd_def32 = 0, 1064 .ssd_gran = 0 }, 1065}; 1066 1067void 1068setidt(idx, func, typ, dpl, ist) 1069 int idx; 1070 inthand_t *func; 1071 int typ; 1072 int dpl; 1073 int ist; 1074{ 1075 struct gate_descriptor *ip; 1076 1077 ip = idt + idx; 1078 ip->gd_looffset = (uintptr_t)func; 1079 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1080 ip->gd_ist = ist; 1081 ip->gd_xx = 0; 1082 ip->gd_type = typ; 1083 ip->gd_dpl = dpl; 1084 ip->gd_p = 1; 1085 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1086} 1087 1088extern inthand_t 1089 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1090 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1091 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1092 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1093 IDTVEC(xmm), IDTVEC(dblfault), 1094#ifdef KDTRACE_HOOKS 1095 IDTVEC(dtrace_ret), 1096#endif 1097 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1098 1099#ifdef DDB 1100/* 1101 * Display the index and function name of any IDT entries that don't use 1102 * the default 'rsvd' entry point. 1103 */ 1104DB_SHOW_COMMAND(idt, db_show_idt) 1105{ 1106 struct gate_descriptor *ip; 1107 int idx; 1108 uintptr_t func; 1109 1110 ip = idt; 1111 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1112 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1113 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1114 db_printf("%3d\t", idx); 1115 db_printsym(func, DB_STGY_PROC); 1116 db_printf("\n"); 1117 } 1118 ip++; 1119 } 1120} 1121#endif 1122 1123void 1124sdtossd(sd, ssd) 1125 struct user_segment_descriptor *sd; 1126 struct soft_segment_descriptor *ssd; 1127{ 1128 1129 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1130 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1131 ssd->ssd_type = sd->sd_type; 1132 ssd->ssd_dpl = sd->sd_dpl; 1133 ssd->ssd_p = sd->sd_p; 1134 ssd->ssd_long = sd->sd_long; 1135 ssd->ssd_def32 = sd->sd_def32; 1136 ssd->ssd_gran = sd->sd_gran; 1137} 1138 1139void 1140ssdtosd(ssd, sd) 1141 struct soft_segment_descriptor *ssd; 1142 struct user_segment_descriptor *sd; 1143{ 1144 1145 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1146 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1147 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1148 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1149 sd->sd_type = ssd->ssd_type; 1150 sd->sd_dpl = ssd->ssd_dpl; 1151 sd->sd_p = ssd->ssd_p; 1152 sd->sd_long = ssd->ssd_long; 1153 sd->sd_def32 = ssd->ssd_def32; 1154 sd->sd_gran = ssd->ssd_gran; 1155} 1156 1157void 1158ssdtosyssd(ssd, sd) 1159 struct soft_segment_descriptor *ssd; 1160 struct system_segment_descriptor *sd; 1161{ 1162 1163 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1164 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1165 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1166 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1167 sd->sd_type = ssd->ssd_type; 1168 sd->sd_dpl = ssd->ssd_dpl; 1169 sd->sd_p = ssd->ssd_p; 1170 sd->sd_gran = ssd->ssd_gran; 1171} 1172 1173#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1174#include <isa/isavar.h> 1175#include <isa/isareg.h> 1176/* 1177 * Return a bitmap of the current interrupt requests. This is 8259-specific 1178 * and is only suitable for use at probe time. 1179 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1180 * It shouldn't be here. There should probably be an APIC centric 1181 * implementation in the apic driver code, if at all. 1182 */ 1183intrmask_t 1184isa_irq_pending(void) 1185{ 1186 u_char irr1; 1187 u_char irr2; 1188 1189 irr1 = inb(IO_ICU1); 1190 irr2 = inb(IO_ICU2); 1191 return ((irr2 << 8) | irr1); 1192} 1193#endif 1194 1195u_int basemem; 1196 1197static int 1198add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1199{ 1200 int i, insert_idx, physmap_idx; 1201 1202 physmap_idx = *physmap_idxp; 1203 1204 if (boothowto & RB_VERBOSE) 1205 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1206 smap->type, smap->base, smap->length); 1207 1208 if (smap->type != SMAP_TYPE_MEMORY) 1209 return (1); 1210 1211 if (smap->length == 0) 1212 return (0); 1213 1214 /* 1215 * Find insertion point while checking for overlap. Start off by 1216 * assuming the new entry will be added to the end. 1217 */ 1218 insert_idx = physmap_idx + 2; 1219 for (i = 0; i <= physmap_idx; i += 2) { 1220 if (smap->base < physmap[i + 1]) { 1221 if (smap->base + smap->length <= physmap[i]) { 1222 insert_idx = i; 1223 break; 1224 } 1225 if (boothowto & RB_VERBOSE) 1226 printf( 1227 "Overlapping memory regions, ignoring second region\n"); 1228 return (1); 1229 } 1230 } 1231 1232 /* See if we can prepend to the next entry. */ 1233 if (insert_idx <= physmap_idx && 1234 smap->base + smap->length == physmap[insert_idx]) { 1235 physmap[insert_idx] = smap->base; 1236 return (1); 1237 } 1238 1239 /* See if we can append to the previous entry. */ 1240 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1241 physmap[insert_idx - 1] += smap->length; 1242 return (1); 1243 } 1244 1245 physmap_idx += 2; 1246 *physmap_idxp = physmap_idx; 1247 if (physmap_idx == PHYSMAP_SIZE) { 1248 printf( 1249 "Too many segments in the physical address map, giving up\n"); 1250 return (0); 1251 } 1252 1253 /* 1254 * Move the last 'N' entries down to make room for the new 1255 * entry if needed. 1256 */ 1257 for (i = physmap_idx; i > insert_idx; i -= 2) { 1258 physmap[i] = physmap[i - 2]; 1259 physmap[i + 1] = physmap[i - 1]; 1260 } 1261 1262 /* Insert the new entry. */ 1263 physmap[insert_idx] = smap->base; 1264 physmap[insert_idx + 1] = smap->base + smap->length; 1265 return (1); 1266} 1267 1268/* 1269 * Populate the (physmap) array with base/bound pairs describing the 1270 * available physical memory in the system, then test this memory and 1271 * build the phys_avail array describing the actually-available memory. 1272 * 1273 * If we cannot accurately determine the physical memory map, then use 1274 * value from the 0xE801 call, and failing that, the RTC. 1275 * 1276 * Total memory size may be set by the kernel environment variable 1277 * hw.physmem or the compile-time define MAXMEM. 1278 * 1279 * XXX first should be vm_paddr_t. 1280 */ 1281static void 1282getmemsize(caddr_t kmdp, u_int64_t first) 1283{ 1284 int i, physmap_idx, pa_indx, da_indx; 1285 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1286 u_long physmem_tunable; 1287 pt_entry_t *pte; 1288 struct bios_smap *smapbase, *smap, *smapend; 1289 u_int32_t smapsize; 1290 quad_t dcons_addr, dcons_size; 1291 1292 bzero(physmap, sizeof(physmap)); 1293 basemem = 0; 1294 physmap_idx = 0; 1295 1296 /* 1297 * get memory map from INT 15:E820, kindly supplied by the loader. 1298 * 1299 * subr_module.c says: 1300 * "Consumer may safely assume that size value precedes data." 1301 * ie: an int32_t immediately precedes smap. 1302 */ 1303 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1304 MODINFO_METADATA | MODINFOMD_SMAP); 1305 if (smapbase == NULL) 1306 panic("No BIOS smap info from loader!"); 1307 1308 smapsize = *((u_int32_t *)smapbase - 1); 1309 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1310 1311 for (smap = smapbase; smap < smapend; smap++) 1312 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1313 break; 1314 1315 /* 1316 * Find the 'base memory' segment for SMP 1317 */ 1318 basemem = 0; 1319 for (i = 0; i <= physmap_idx; i += 2) { 1320 if (physmap[i] == 0x00000000) { 1321 basemem = physmap[i + 1] / 1024; 1322 break; 1323 } 1324 } 1325 if (basemem == 0) 1326 panic("BIOS smap did not include a basemem segment!"); 1327 1328#ifdef SMP 1329 /* make hole for AP bootstrap code */ 1330 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1331#endif 1332 1333 /* 1334 * Maxmem isn't the "maximum memory", it's one larger than the 1335 * highest page of the physical address space. It should be 1336 * called something like "Maxphyspage". We may adjust this 1337 * based on ``hw.physmem'' and the results of the memory test. 1338 */ 1339 Maxmem = atop(physmap[physmap_idx + 1]); 1340 1341#ifdef MAXMEM 1342 Maxmem = MAXMEM / 4; 1343#endif 1344 1345 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1346 Maxmem = atop(physmem_tunable); 1347 1348 /* 1349 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1350 * in the system. 1351 */ 1352 if (Maxmem > atop(physmap[physmap_idx + 1])) 1353 Maxmem = atop(physmap[physmap_idx + 1]); 1354 1355 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1356 (boothowto & RB_VERBOSE)) 1357 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1358 1359 /* call pmap initialization to make new kernel address space */ 1360 pmap_bootstrap(&first); 1361 1362 /* 1363 * Size up each available chunk of physical memory. 1364 */ 1365 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1366 pa_indx = 0; 1367 da_indx = 1; 1368 phys_avail[pa_indx++] = physmap[0]; 1369 phys_avail[pa_indx] = physmap[0]; 1370 dump_avail[da_indx] = physmap[0]; 1371 pte = CMAP1; 1372 1373 /* 1374 * Get dcons buffer address 1375 */ 1376 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1377 getenv_quad("dcons.size", &dcons_size) == 0) 1378 dcons_addr = 0; 1379 1380 /* 1381 * physmap is in bytes, so when converting to page boundaries, 1382 * round up the start address and round down the end address. 1383 */ 1384 for (i = 0; i <= physmap_idx; i += 2) { 1385 vm_paddr_t end; 1386 1387 end = ptoa((vm_paddr_t)Maxmem); 1388 if (physmap[i + 1] < end) 1389 end = trunc_page(physmap[i + 1]); 1390 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1391 int tmp, page_bad, full; 1392 int *ptr = (int *)CADDR1; 1393 1394 full = FALSE; 1395 /* 1396 * block out kernel memory as not available. 1397 */ 1398 if (pa >= 0x100000 && pa < first) 1399 goto do_dump_avail; 1400 1401 /* 1402 * block out dcons buffer 1403 */ 1404 if (dcons_addr > 0 1405 && pa >= trunc_page(dcons_addr) 1406 && pa < dcons_addr + dcons_size) 1407 goto do_dump_avail; 1408 1409 page_bad = FALSE; 1410 1411 /* 1412 * map page into kernel: valid, read/write,non-cacheable 1413 */ 1414 *pte = pa | PG_V | PG_RW | PG_N; 1415 invltlb(); 1416 1417 tmp = *(int *)ptr; 1418 /* 1419 * Test for alternating 1's and 0's 1420 */ 1421 *(volatile int *)ptr = 0xaaaaaaaa; 1422 if (*(volatile int *)ptr != 0xaaaaaaaa) 1423 page_bad = TRUE; 1424 /* 1425 * Test for alternating 0's and 1's 1426 */ 1427 *(volatile int *)ptr = 0x55555555; 1428 if (*(volatile int *)ptr != 0x55555555) 1429 page_bad = TRUE; 1430 /* 1431 * Test for all 1's 1432 */ 1433 *(volatile int *)ptr = 0xffffffff; 1434 if (*(volatile int *)ptr != 0xffffffff) 1435 page_bad = TRUE; 1436 /* 1437 * Test for all 0's 1438 */ 1439 *(volatile int *)ptr = 0x0; 1440 if (*(volatile int *)ptr != 0x0) 1441 page_bad = TRUE; 1442 /* 1443 * Restore original value. 1444 */ 1445 *(int *)ptr = tmp; 1446 1447 /* 1448 * Adjust array of valid/good pages. 1449 */ 1450 if (page_bad == TRUE) 1451 continue; 1452 /* 1453 * If this good page is a continuation of the 1454 * previous set of good pages, then just increase 1455 * the end pointer. Otherwise start a new chunk. 1456 * Note that "end" points one higher than end, 1457 * making the range >= start and < end. 1458 * If we're also doing a speculative memory 1459 * test and we at or past the end, bump up Maxmem 1460 * so that we keep going. The first bad page 1461 * will terminate the loop. 1462 */ 1463 if (phys_avail[pa_indx] == pa) { 1464 phys_avail[pa_indx] += PAGE_SIZE; 1465 } else { 1466 pa_indx++; 1467 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1468 printf( 1469 "Too many holes in the physical address space, giving up\n"); 1470 pa_indx--; 1471 full = TRUE; 1472 goto do_dump_avail; 1473 } 1474 phys_avail[pa_indx++] = pa; /* start */ 1475 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1476 } 1477 physmem++; 1478do_dump_avail: 1479 if (dump_avail[da_indx] == pa) { 1480 dump_avail[da_indx] += PAGE_SIZE; 1481 } else { 1482 da_indx++; 1483 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1484 da_indx--; 1485 goto do_next; 1486 } 1487 dump_avail[da_indx++] = pa; /* start */ 1488 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1489 } 1490do_next: 1491 if (full) 1492 break; 1493 } 1494 } 1495 *pte = 0; 1496 invltlb(); 1497 1498 /* 1499 * XXX 1500 * The last chunk must contain at least one page plus the message 1501 * buffer to avoid complicating other code (message buffer address 1502 * calculation, etc.). 1503 */ 1504 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1505 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1506 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1507 phys_avail[pa_indx--] = 0; 1508 phys_avail[pa_indx--] = 0; 1509 } 1510 1511 Maxmem = atop(phys_avail[pa_indx]); 1512 1513 /* Trim off space for the message buffer. */ 1514 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1515 1516 /* Map the message buffer. */ 1517 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1518} 1519 1520u_int64_t 1521hammer_time(u_int64_t modulep, u_int64_t physfree) 1522{ 1523 caddr_t kmdp; 1524 int gsel_tss, x; 1525 struct pcpu *pc; 1526 struct nmi_pcpu *np; 1527 u_int64_t msr; 1528 char *env; 1529 1530 thread0.td_kstack = physfree + KERNBASE; 1531 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1532 physfree += KSTACK_PAGES * PAGE_SIZE; 1533 thread0.td_pcb = (struct pcb *) 1534 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1535 1536 /* 1537 * This may be done better later if it gets more high level 1538 * components in it. If so just link td->td_proc here. 1539 */ 1540 proc_linkup0(&proc0, &thread0); 1541 1542 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1543 preload_bootstrap_relocate(KERNBASE); 1544 kmdp = preload_search_by_type("elf kernel"); 1545 if (kmdp == NULL) 1546 kmdp = preload_search_by_type("elf64 kernel"); 1547 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1548 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1549#ifdef DDB 1550 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1551 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1552#endif 1553 1554 /* Init basic tunables, hz etc */ 1555 init_param1(); 1556 1557 /* 1558 * make gdt memory segments 1559 */ 1560 for (x = 0; x < NGDT; x++) { 1561 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1562 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1563 ssdtosd(&gdt_segs[x], &gdt[x]); 1564 } 1565 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1566 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1567 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1568 1569 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1570 r_gdt.rd_base = (long) gdt; 1571 lgdt(&r_gdt); 1572 pc = &__pcpu[0]; 1573 1574 wrmsr(MSR_FSBASE, 0); /* User value */ 1575 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1576 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1577 1578 pcpu_init(pc, 0, sizeof(struct pcpu)); 1579 dpcpu_init((void *)(physfree + KERNBASE), 0); 1580 physfree += DPCPU_SIZE; 1581 PCPU_SET(prvspace, pc); 1582 PCPU_SET(curthread, &thread0); 1583 PCPU_SET(curpcb, thread0.td_pcb); 1584 PCPU_SET(tssp, &common_tss[0]); 1585 PCPU_SET(commontssp, &common_tss[0]); 1586 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1587 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1588 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1589 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1590 1591 /* 1592 * Initialize mutexes. 1593 * 1594 * icu_lock: in order to allow an interrupt to occur in a critical 1595 * section, to set pcpu->ipending (etc...) properly, we 1596 * must be able to get the icu lock, so it can't be 1597 * under witness. 1598 */ 1599 mutex_init(); 1600 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1601 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1602 1603 /* exceptions */ 1604 for (x = 0; x < NIDT; x++) 1605 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1606 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1607 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1608 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1609 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1610 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1611 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1612 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1613 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1614 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1615 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1616 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1617 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1618 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1619 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1620 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1621 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1622 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1623 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1624 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1625#ifdef KDTRACE_HOOKS 1626 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1627#endif 1628 1629 r_idt.rd_limit = sizeof(idt0) - 1; 1630 r_idt.rd_base = (long) idt; 1631 lidt(&r_idt); 1632 1633 /* 1634 * Initialize the i8254 before the console so that console 1635 * initialization can use DELAY(). 1636 */ 1637 i8254_init(); 1638 1639 /* 1640 * Initialize the console before we print anything out. 1641 */ 1642 cninit(); 1643 1644#ifdef DEV_ISA 1645#ifdef DEV_ATPIC 1646 elcr_probe(); 1647 atpic_startup(); 1648#else 1649 /* Reset and mask the atpics and leave them shut down. */ 1650 atpic_reset(); 1651 1652 /* 1653 * Point the ICU spurious interrupt vectors at the APIC spurious 1654 * interrupt handler. 1655 */ 1656 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1657 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1658#endif 1659#else 1660#error "have you forgotten the isa device?"; 1661#endif 1662 1663 kdb_init(); 1664 1665#ifdef KDB 1666 if (boothowto & RB_KDB) 1667 kdb_enter(KDB_WHY_BOOTFLAGS, 1668 "Boot flags requested debugger"); 1669#endif 1670 1671 identify_cpu(); /* Final stage of CPU initialization */ 1672 initializecpu(); /* Initialize CPU registers */ 1673 initializecpucache(); 1674 1675 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1676 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1677 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1678 /* Ensure the stack is aligned to 16 bytes */ 1679 common_tss[0].tss_rsp0 &= ~0xFul; 1680 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1681 1682 /* doublefault stack space, runs on ist1 */ 1683 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1684 1685 /* 1686 * NMI stack, runs on ist2. The pcpu pointer is stored just 1687 * above the start of the ist2 stack. 1688 */ 1689 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1690 np->np_pcpu = (register_t) pc; 1691 common_tss[0].tss_ist2 = (long) np; 1692 1693 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1694 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1695 IOPAGES * PAGE_SIZE; 1696 1697 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1698 ltr(gsel_tss); 1699 1700 /* Set up the fast syscall stuff */ 1701 msr = rdmsr(MSR_EFER) | EFER_SCE; 1702 wrmsr(MSR_EFER, msr); 1703 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1704 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1705 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1706 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1707 wrmsr(MSR_STAR, msr); 1708 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1709 1710 getmemsize(kmdp, physfree); 1711 init_param2(physmem); 1712 1713 /* now running on new page tables, configured,and u/iom is accessible */ 1714 1715 msgbufinit(msgbufp, MSGBUF_SIZE); 1716 fpuinit(); 1717 1718 /* transfer to user mode */ 1719 1720 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1721 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1722 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1723 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1724 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1725 1726 load_ds(_udatasel); 1727 load_es(_udatasel); 1728 load_fs(_ufssel); 1729 1730 /* setup proc 0's pcb */ 1731 thread0.td_pcb->pcb_flags = 0; 1732 thread0.td_pcb->pcb_cr3 = KPML4phys; 1733 thread0.td_frame = &proc0_tf; 1734 1735 env = getenv("kernelname"); 1736 if (env != NULL) 1737 strlcpy(kernelname, env, sizeof(kernelname)); 1738 1739#ifdef XENHVM 1740 if (inw(0x10) == 0x49d2) { 1741 if (bootverbose) 1742 printf("Xen detected: disabling emulated block and network devices\n"); 1743 outw(0x10, 3); 1744 } 1745#endif 1746 1747 cpu_probe_amdc1e(); 1748 1749 /* Location of kernel stack for locore */ 1750 return ((u_int64_t)thread0.td_pcb); 1751} 1752 1753void 1754cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1755{ 1756 1757 pcpu->pc_acpi_id = 0xffffffff; 1758} 1759 1760void 1761spinlock_enter(void) 1762{ 1763 struct thread *td; 1764 1765 td = curthread; 1766 if (td->td_md.md_spinlock_count == 0) 1767 td->td_md.md_saved_flags = intr_disable(); 1768 td->td_md.md_spinlock_count++; 1769 critical_enter(); 1770} 1771 1772void 1773spinlock_exit(void) 1774{ 1775 struct thread *td; 1776 1777 td = curthread; 1778 critical_exit(); 1779 td->td_md.md_spinlock_count--; 1780 if (td->td_md.md_spinlock_count == 0) 1781 intr_restore(td->td_md.md_saved_flags); 1782} 1783 1784/* 1785 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1786 * we want to start a backtrace from the function that caused us to enter 1787 * the debugger. We have the context in the trapframe, but base the trace 1788 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1789 * enough for a backtrace. 1790 */ 1791void 1792makectx(struct trapframe *tf, struct pcb *pcb) 1793{ 1794 1795 pcb->pcb_r12 = tf->tf_r12; 1796 pcb->pcb_r13 = tf->tf_r13; 1797 pcb->pcb_r14 = tf->tf_r14; 1798 pcb->pcb_r15 = tf->tf_r15; 1799 pcb->pcb_rbp = tf->tf_rbp; 1800 pcb->pcb_rbx = tf->tf_rbx; 1801 pcb->pcb_rip = tf->tf_rip; 1802 pcb->pcb_rsp = tf->tf_rsp; 1803} 1804 1805int 1806ptrace_set_pc(struct thread *td, unsigned long addr) 1807{ 1808 td->td_frame->tf_rip = addr; 1809 return (0); 1810} 1811 1812int 1813ptrace_single_step(struct thread *td) 1814{ 1815 td->td_frame->tf_rflags |= PSL_T; 1816 return (0); 1817} 1818 1819int 1820ptrace_clear_single_step(struct thread *td) 1821{ 1822 td->td_frame->tf_rflags &= ~PSL_T; 1823 return (0); 1824} 1825 1826int 1827fill_regs(struct thread *td, struct reg *regs) 1828{ 1829 struct trapframe *tp; 1830 1831 tp = td->td_frame; 1832 regs->r_r15 = tp->tf_r15; 1833 regs->r_r14 = tp->tf_r14; 1834 regs->r_r13 = tp->tf_r13; 1835 regs->r_r12 = tp->tf_r12; 1836 regs->r_r11 = tp->tf_r11; 1837 regs->r_r10 = tp->tf_r10; 1838 regs->r_r9 = tp->tf_r9; 1839 regs->r_r8 = tp->tf_r8; 1840 regs->r_rdi = tp->tf_rdi; 1841 regs->r_rsi = tp->tf_rsi; 1842 regs->r_rbp = tp->tf_rbp; 1843 regs->r_rbx = tp->tf_rbx; 1844 regs->r_rdx = tp->tf_rdx; 1845 regs->r_rcx = tp->tf_rcx; 1846 regs->r_rax = tp->tf_rax; 1847 regs->r_rip = tp->tf_rip; 1848 regs->r_cs = tp->tf_cs; 1849 regs->r_rflags = tp->tf_rflags; 1850 regs->r_rsp = tp->tf_rsp; 1851 regs->r_ss = tp->tf_ss; 1852 if (tp->tf_flags & TF_HASSEGS) { 1853 regs->r_ds = tp->tf_ds; 1854 regs->r_es = tp->tf_es; 1855 regs->r_fs = tp->tf_fs; 1856 regs->r_gs = tp->tf_gs; 1857 } else { 1858 regs->r_ds = 0; 1859 regs->r_es = 0; 1860 regs->r_fs = 0; 1861 regs->r_gs = 0; 1862 } 1863 return (0); 1864} 1865 1866int 1867set_regs(struct thread *td, struct reg *regs) 1868{ 1869 struct trapframe *tp; 1870 register_t rflags; 1871 1872 tp = td->td_frame; 1873 rflags = regs->r_rflags & 0xffffffff; 1874 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1875 return (EINVAL); 1876 tp->tf_r15 = regs->r_r15; 1877 tp->tf_r14 = regs->r_r14; 1878 tp->tf_r13 = regs->r_r13; 1879 tp->tf_r12 = regs->r_r12; 1880 tp->tf_r11 = regs->r_r11; 1881 tp->tf_r10 = regs->r_r10; 1882 tp->tf_r9 = regs->r_r9; 1883 tp->tf_r8 = regs->r_r8; 1884 tp->tf_rdi = regs->r_rdi; 1885 tp->tf_rsi = regs->r_rsi; 1886 tp->tf_rbp = regs->r_rbp; 1887 tp->tf_rbx = regs->r_rbx; 1888 tp->tf_rdx = regs->r_rdx; 1889 tp->tf_rcx = regs->r_rcx; 1890 tp->tf_rax = regs->r_rax; 1891 tp->tf_rip = regs->r_rip; 1892 tp->tf_cs = regs->r_cs; 1893 tp->tf_rflags = rflags; 1894 tp->tf_rsp = regs->r_rsp; 1895 tp->tf_ss = regs->r_ss; 1896 if (0) { /* XXXKIB */ 1897 tp->tf_ds = regs->r_ds; 1898 tp->tf_es = regs->r_es; 1899 tp->tf_fs = regs->r_fs; 1900 tp->tf_gs = regs->r_gs; 1901 tp->tf_flags = TF_HASSEGS; 1902 } 1903 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1904 return (0); 1905} 1906 1907/* XXX check all this stuff! */ 1908/* externalize from sv_xmm */ 1909static void 1910fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1911{ 1912 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1913 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1914 int i; 1915 1916 /* pcb -> fpregs */ 1917 bzero(fpregs, sizeof(*fpregs)); 1918 1919 /* FPU control/status */ 1920 penv_fpreg->en_cw = penv_xmm->en_cw; 1921 penv_fpreg->en_sw = penv_xmm->en_sw; 1922 penv_fpreg->en_tw = penv_xmm->en_tw; 1923 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1924 penv_fpreg->en_rip = penv_xmm->en_rip; 1925 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1926 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1927 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1928 1929 /* FPU registers */ 1930 for (i = 0; i < 8; ++i) 1931 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1932 1933 /* SSE registers */ 1934 for (i = 0; i < 16; ++i) 1935 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1936} 1937 1938/* internalize from fpregs into sv_xmm */ 1939static void 1940set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1941{ 1942 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1943 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1944 int i; 1945 1946 /* fpregs -> pcb */ 1947 /* FPU control/status */ 1948 penv_xmm->en_cw = penv_fpreg->en_cw; 1949 penv_xmm->en_sw = penv_fpreg->en_sw; 1950 penv_xmm->en_tw = penv_fpreg->en_tw; 1951 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1952 penv_xmm->en_rip = penv_fpreg->en_rip; 1953 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1954 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1955 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1956 1957 /* FPU registers */ 1958 for (i = 0; i < 8; ++i) 1959 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1960 1961 /* SSE registers */ 1962 for (i = 0; i < 16; ++i) 1963 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1964} 1965 1966/* externalize from td->pcb */ 1967int 1968fill_fpregs(struct thread *td, struct fpreg *fpregs) 1969{ 1970 1971 fill_fpregs_xmm(&td->td_pcb->pcb_user_save, fpregs); 1972 return (0); 1973} 1974 1975/* internalize to td->pcb */ 1976int 1977set_fpregs(struct thread *td, struct fpreg *fpregs) 1978{ 1979 1980 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_user_save); 1981 return (0); 1982} 1983 1984/* 1985 * Get machine context. 1986 */ 1987int 1988get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1989{ 1990 struct trapframe *tp; 1991 1992 tp = td->td_frame; 1993 PROC_LOCK(curthread->td_proc); 1994 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1995 PROC_UNLOCK(curthread->td_proc); 1996 mcp->mc_r15 = tp->tf_r15; 1997 mcp->mc_r14 = tp->tf_r14; 1998 mcp->mc_r13 = tp->tf_r13; 1999 mcp->mc_r12 = tp->tf_r12; 2000 mcp->mc_r11 = tp->tf_r11; 2001 mcp->mc_r10 = tp->tf_r10; 2002 mcp->mc_r9 = tp->tf_r9; 2003 mcp->mc_r8 = tp->tf_r8; 2004 mcp->mc_rdi = tp->tf_rdi; 2005 mcp->mc_rsi = tp->tf_rsi; 2006 mcp->mc_rbp = tp->tf_rbp; 2007 mcp->mc_rbx = tp->tf_rbx; 2008 mcp->mc_rcx = tp->tf_rcx; 2009 mcp->mc_rflags = tp->tf_rflags; 2010 if (flags & GET_MC_CLEAR_RET) { 2011 mcp->mc_rax = 0; 2012 mcp->mc_rdx = 0; 2013 mcp->mc_rflags &= ~PSL_C; 2014 } else { 2015 mcp->mc_rax = tp->tf_rax; 2016 mcp->mc_rdx = tp->tf_rdx; 2017 } 2018 mcp->mc_rip = tp->tf_rip; 2019 mcp->mc_cs = tp->tf_cs; 2020 mcp->mc_rsp = tp->tf_rsp; 2021 mcp->mc_ss = tp->tf_ss; 2022 mcp->mc_ds = tp->tf_ds; 2023 mcp->mc_es = tp->tf_es; 2024 mcp->mc_fs = tp->tf_fs; 2025 mcp->mc_gs = tp->tf_gs; 2026 mcp->mc_flags = tp->tf_flags; 2027 mcp->mc_len = sizeof(*mcp); 2028 get_fpcontext(td, mcp); 2029 mcp->mc_fsbase = td->td_pcb->pcb_fsbase; 2030 mcp->mc_gsbase = td->td_pcb->pcb_gsbase; 2031 return (0); 2032} 2033 2034/* 2035 * Set machine context. 2036 * 2037 * However, we don't set any but the user modifiable flags, and we won't 2038 * touch the cs selector. 2039 */ 2040int 2041set_mcontext(struct thread *td, const mcontext_t *mcp) 2042{ 2043 struct trapframe *tp; 2044 long rflags; 2045 int ret; 2046 2047 tp = td->td_frame; 2048 if (mcp->mc_len != sizeof(*mcp) || 2049 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2050 return (EINVAL); 2051 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2052 (tp->tf_rflags & ~PSL_USERCHANGE); 2053 ret = set_fpcontext(td, mcp); 2054 if (ret != 0) 2055 return (ret); 2056 tp->tf_r15 = mcp->mc_r15; 2057 tp->tf_r14 = mcp->mc_r14; 2058 tp->tf_r13 = mcp->mc_r13; 2059 tp->tf_r12 = mcp->mc_r12; 2060 tp->tf_r11 = mcp->mc_r11; 2061 tp->tf_r10 = mcp->mc_r10; 2062 tp->tf_r9 = mcp->mc_r9; 2063 tp->tf_r8 = mcp->mc_r8; 2064 tp->tf_rdi = mcp->mc_rdi; 2065 tp->tf_rsi = mcp->mc_rsi; 2066 tp->tf_rbp = mcp->mc_rbp; 2067 tp->tf_rbx = mcp->mc_rbx; 2068 tp->tf_rdx = mcp->mc_rdx; 2069 tp->tf_rcx = mcp->mc_rcx; 2070 tp->tf_rax = mcp->mc_rax; 2071 tp->tf_rip = mcp->mc_rip; 2072 tp->tf_rflags = rflags; 2073 tp->tf_rsp = mcp->mc_rsp; 2074 tp->tf_ss = mcp->mc_ss; 2075 tp->tf_flags = mcp->mc_flags; 2076 if (tp->tf_flags & TF_HASSEGS) { 2077 tp->tf_ds = mcp->mc_ds; 2078 tp->tf_es = mcp->mc_es; 2079 tp->tf_fs = mcp->mc_fs; 2080 tp->tf_gs = mcp->mc_gs; 2081 } 2082 if (mcp->mc_flags & _MC_HASBASES) { 2083 td->td_pcb->pcb_fsbase = mcp->mc_fsbase; 2084 td->td_pcb->pcb_gsbase = mcp->mc_gsbase; 2085 } 2086 td->td_pcb->pcb_flags |= PCB_FULLCTX; 2087 td->td_pcb->pcb_full_iret = 1; 2088 return (0); 2089} 2090 2091static void 2092get_fpcontext(struct thread *td, mcontext_t *mcp) 2093{ 2094 2095 mcp->mc_ownedfp = fpugetuserregs(td, 2096 (struct savefpu *)&mcp->mc_fpstate); 2097 mcp->mc_fpformat = fpuformat(); 2098} 2099 2100static int 2101set_fpcontext(struct thread *td, const mcontext_t *mcp) 2102{ 2103 struct savefpu *fpstate; 2104 2105 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2106 return (0); 2107 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2108 return (EINVAL); 2109 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2110 /* We don't care what state is left in the FPU or PCB. */ 2111 fpstate_drop(td); 2112 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2113 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2114 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2115 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2116 fpusetuserregs(td, fpstate); 2117 } else 2118 return (EINVAL); 2119 return (0); 2120} 2121 2122void 2123fpstate_drop(struct thread *td) 2124{ 2125 2126 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2127 critical_enter(); 2128 if (PCPU_GET(fpcurthread) == td) 2129 fpudrop(); 2130 /* 2131 * XXX force a full drop of the fpu. The above only drops it if we 2132 * owned it. 2133 * 2134 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2135 * drop. Dropping only to the pcb matches fnsave's behaviour. 2136 * We only need to drop to !PCB_INITDONE in sendsig(). But 2137 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2138 * have too many layers. 2139 */ 2140 curthread->td_pcb->pcb_flags &= ~(PCB_FPUINITDONE | 2141 PCB_USERFPUINITDONE); 2142 critical_exit(); 2143} 2144 2145int 2146fill_dbregs(struct thread *td, struct dbreg *dbregs) 2147{ 2148 struct pcb *pcb; 2149 2150 if (td == NULL) { 2151 dbregs->dr[0] = rdr0(); 2152 dbregs->dr[1] = rdr1(); 2153 dbregs->dr[2] = rdr2(); 2154 dbregs->dr[3] = rdr3(); 2155 dbregs->dr[6] = rdr6(); 2156 dbregs->dr[7] = rdr7(); 2157 } else { 2158 pcb = td->td_pcb; 2159 dbregs->dr[0] = pcb->pcb_dr0; 2160 dbregs->dr[1] = pcb->pcb_dr1; 2161 dbregs->dr[2] = pcb->pcb_dr2; 2162 dbregs->dr[3] = pcb->pcb_dr3; 2163 dbregs->dr[6] = pcb->pcb_dr6; 2164 dbregs->dr[7] = pcb->pcb_dr7; 2165 } 2166 dbregs->dr[4] = 0; 2167 dbregs->dr[5] = 0; 2168 dbregs->dr[8] = 0; 2169 dbregs->dr[9] = 0; 2170 dbregs->dr[10] = 0; 2171 dbregs->dr[11] = 0; 2172 dbregs->dr[12] = 0; 2173 dbregs->dr[13] = 0; 2174 dbregs->dr[14] = 0; 2175 dbregs->dr[15] = 0; 2176 return (0); 2177} 2178 2179int 2180set_dbregs(struct thread *td, struct dbreg *dbregs) 2181{ 2182 struct pcb *pcb; 2183 int i; 2184 2185 if (td == NULL) { 2186 load_dr0(dbregs->dr[0]); 2187 load_dr1(dbregs->dr[1]); 2188 load_dr2(dbregs->dr[2]); 2189 load_dr3(dbregs->dr[3]); 2190 load_dr6(dbregs->dr[6]); 2191 load_dr7(dbregs->dr[7]); 2192 } else { 2193 /* 2194 * Don't let an illegal value for dr7 get set. Specifically, 2195 * check for undefined settings. Setting these bit patterns 2196 * result in undefined behaviour and can lead to an unexpected 2197 * TRCTRAP or a general protection fault right here. 2198 * Upper bits of dr6 and dr7 must not be set 2199 */ 2200 for (i = 0; i < 4; i++) { 2201 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2202 return (EINVAL); 2203 if (td->td_frame->tf_cs == _ucode32sel && 2204 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2205 return (EINVAL); 2206 } 2207 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2208 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2209 return (EINVAL); 2210 2211 pcb = td->td_pcb; 2212 2213 /* 2214 * Don't let a process set a breakpoint that is not within the 2215 * process's address space. If a process could do this, it 2216 * could halt the system by setting a breakpoint in the kernel 2217 * (if ddb was enabled). Thus, we need to check to make sure 2218 * that no breakpoints are being enabled for addresses outside 2219 * process's address space. 2220 * 2221 * XXX - what about when the watched area of the user's 2222 * address space is written into from within the kernel 2223 * ... wouldn't that still cause a breakpoint to be generated 2224 * from within kernel mode? 2225 */ 2226 2227 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2228 /* dr0 is enabled */ 2229 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2230 return (EINVAL); 2231 } 2232 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2233 /* dr1 is enabled */ 2234 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2235 return (EINVAL); 2236 } 2237 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2238 /* dr2 is enabled */ 2239 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2240 return (EINVAL); 2241 } 2242 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2243 /* dr3 is enabled */ 2244 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2245 return (EINVAL); 2246 } 2247 2248 pcb->pcb_dr0 = dbregs->dr[0]; 2249 pcb->pcb_dr1 = dbregs->dr[1]; 2250 pcb->pcb_dr2 = dbregs->dr[2]; 2251 pcb->pcb_dr3 = dbregs->dr[3]; 2252 pcb->pcb_dr6 = dbregs->dr[6]; 2253 pcb->pcb_dr7 = dbregs->dr[7]; 2254 2255 pcb->pcb_flags |= PCB_DBREGS; 2256 } 2257 2258 return (0); 2259} 2260 2261void 2262reset_dbregs(void) 2263{ 2264 2265 load_dr7(0); /* Turn off the control bits first */ 2266 load_dr0(0); 2267 load_dr1(0); 2268 load_dr2(0); 2269 load_dr3(0); 2270 load_dr6(0); 2271} 2272 2273/* 2274 * Return > 0 if a hardware breakpoint has been hit, and the 2275 * breakpoint was in user space. Return 0, otherwise. 2276 */ 2277int 2278user_dbreg_trap(void) 2279{ 2280 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2281 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2282 int nbp; /* number of breakpoints that triggered */ 2283 caddr_t addr[4]; /* breakpoint addresses */ 2284 int i; 2285 2286 dr7 = rdr7(); 2287 if ((dr7 & 0x000000ff) == 0) { 2288 /* 2289 * all GE and LE bits in the dr7 register are zero, 2290 * thus the trap couldn't have been caused by the 2291 * hardware debug registers 2292 */ 2293 return 0; 2294 } 2295 2296 nbp = 0; 2297 dr6 = rdr6(); 2298 bp = dr6 & 0x0000000f; 2299 2300 if (!bp) { 2301 /* 2302 * None of the breakpoint bits are set meaning this 2303 * trap was not caused by any of the debug registers 2304 */ 2305 return 0; 2306 } 2307 2308 /* 2309 * at least one of the breakpoints were hit, check to see 2310 * which ones and if any of them are user space addresses 2311 */ 2312 2313 if (bp & 0x01) { 2314 addr[nbp++] = (caddr_t)rdr0(); 2315 } 2316 if (bp & 0x02) { 2317 addr[nbp++] = (caddr_t)rdr1(); 2318 } 2319 if (bp & 0x04) { 2320 addr[nbp++] = (caddr_t)rdr2(); 2321 } 2322 if (bp & 0x08) { 2323 addr[nbp++] = (caddr_t)rdr3(); 2324 } 2325 2326 for (i = 0; i < nbp; i++) { 2327 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2328 /* 2329 * addr[i] is in user space 2330 */ 2331 return nbp; 2332 } 2333 } 2334 2335 /* 2336 * None of the breakpoints are in user space. 2337 */ 2338 return 0; 2339} 2340 2341#ifdef KDB 2342 2343/* 2344 * Provide inb() and outb() as functions. They are normally only available as 2345 * inline functions, thus cannot be called from the debugger. 2346 */ 2347 2348/* silence compiler warnings */ 2349u_char inb_(u_short); 2350void outb_(u_short, u_char); 2351 2352u_char 2353inb_(u_short port) 2354{ 2355 return inb(port); 2356} 2357 2358void 2359outb_(u_short port, u_char data) 2360{ 2361 outb(port, data); 2362} 2363 2364#endif /* KDB */ 2365