machdep.c revision 196033
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 196033 2009-08-02 11:26:23Z ed $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_msgbuf.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57 58#include <sys/param.h> 59#include <sys/proc.h> 60#include <sys/systm.h> 61#include <sys/bio.h> 62#include <sys/buf.h> 63#include <sys/bus.h> 64#include <sys/callout.h> 65#include <sys/cons.h> 66#include <sys/cpu.h> 67#include <sys/eventhandler.h> 68#include <sys/exec.h> 69#include <sys/imgact.h> 70#include <sys/kdb.h> 71#include <sys/kernel.h> 72#include <sys/ktr.h> 73#include <sys/linker.h> 74#include <sys/lock.h> 75#include <sys/malloc.h> 76#include <sys/memrange.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/sched.h> 83#include <sys/signalvar.h> 84#include <sys/sysctl.h> 85#include <sys/sysent.h> 86#include <sys/sysproto.h> 87#include <sys/ucontext.h> 88#include <sys/vmmeter.h> 89 90#include <vm/vm.h> 91#include <vm/vm_extern.h> 92#include <vm/vm_kern.h> 93#include <vm/vm_page.h> 94#include <vm/vm_map.h> 95#include <vm/vm_object.h> 96#include <vm/vm_pager.h> 97#include <vm/vm_param.h> 98 99#ifdef DDB 100#ifndef KDB 101#error KDB must be enabled in order for DDB to work! 102#endif 103#include <ddb/ddb.h> 104#include <ddb/db_sym.h> 105#endif 106 107#include <net/netisr.h> 108 109#include <machine/clock.h> 110#include <machine/cpu.h> 111#include <machine/cputypes.h> 112#include <machine/intr_machdep.h> 113#include <machine/mca.h> 114#include <machine/md_var.h> 115#include <machine/metadata.h> 116#include <machine/pc/bios.h> 117#include <machine/pcb.h> 118#include <machine/proc.h> 119#include <machine/reg.h> 120#include <machine/sigframe.h> 121#include <machine/specialreg.h> 122#ifdef PERFMON 123#include <machine/perfmon.h> 124#endif 125#include <machine/tss.h> 126#ifdef SMP 127#include <machine/smp.h> 128#endif 129 130#ifdef DEV_ATPIC 131#include <amd64/isa/icu.h> 132#else 133#include <machine/apicvar.h> 134#endif 135 136#include <isa/isareg.h> 137#include <isa/rtc.h> 138 139/* Sanity check for __curthread() */ 140CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 141 142extern u_int64_t hammer_time(u_int64_t, u_int64_t); 143 144extern void printcpuinfo(void); /* XXX header file */ 145extern void identify_cpu(void); 146extern void panicifcpuunsupported(void); 147 148#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 149#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 150 151static void cpu_startup(void *); 152static void get_fpcontext(struct thread *td, mcontext_t *mcp); 153static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 154SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 155 156#ifdef DDB 157extern vm_offset_t ksym_start, ksym_end; 158#endif 159 160/* Intel ICH registers */ 161#define ICH_PMBASE 0x400 162#define ICH_SMI_EN ICH_PMBASE + 0x30 163 164int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 165 166int cold = 1; 167 168long Maxmem = 0; 169long realmem = 0; 170 171/* 172 * The number of PHYSMAP entries must be one less than the number of 173 * PHYSSEG entries because the PHYSMAP entry that spans the largest 174 * physical address that is accessible by ISA DMA is split into two 175 * PHYSSEG entries. 176 */ 177#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 178 179vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 180vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 181 182/* must be 2 less so 0 0 can signal end of chunks */ 183#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 184#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 185 186struct kva_md_info kmi; 187 188static struct trapframe proc0_tf; 189struct region_descriptor r_gdt, r_idt; 190 191struct pcpu __pcpu[MAXCPU]; 192 193struct mtx icu_lock; 194 195struct mem_range_softc mem_range_softc; 196 197struct mtx dt_lock; /* lock for GDT and LDT */ 198 199static void 200cpu_startup(dummy) 201 void *dummy; 202{ 203 uintmax_t memsize; 204 char *sysenv; 205 206 /* 207 * On MacBooks, we need to disallow the legacy USB circuit to 208 * generate an SMI# because this can cause several problems, 209 * namely: incorrect CPU frequency detection and failure to 210 * start the APs. 211 * We do this by disabling a bit in the SMI_EN (SMI Control and 212 * Enable register) of the Intel ICH LPC Interface Bridge. 213 */ 214 sysenv = getenv("smbios.system.product"); 215 if (sysenv != NULL) { 216 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 217 strncmp(sysenv, "MacBook3,1", 10) == 0 || 218 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 219 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 220 strncmp(sysenv, "Macmini1,1", 10) == 0) { 221 if (bootverbose) 222 printf("Disabling LEGACY_USB_EN bit on " 223 "Intel ICH.\n"); 224 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 225 } 226 freeenv(sysenv); 227 } 228 229 /* 230 * Good {morning,afternoon,evening,night}. 231 */ 232 startrtclock(); 233 printcpuinfo(); 234 panicifcpuunsupported(); 235#ifdef PERFMON 236 perfmon_init(); 237#endif 238 sysenv = getenv("smbios.memory.enabled"); 239 if (sysenv != NULL) { 240 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10); 241 freeenv(sysenv); 242 } else 243 memsize = 0; 244 if (memsize > 0) 245 printf("real memory = %ju (%ju MB)\n", memsize << 10, 246 memsize >> 10); 247 else 248 printf("real memory = %ju (%ju MB)\n", ptoa((uintmax_t)Maxmem), 249 ptoa((uintmax_t)Maxmem) / 1048576); 250 realmem = Maxmem; 251 /* 252 * Display any holes after the first chunk of extended memory. 253 */ 254 if (bootverbose) { 255 int indx; 256 257 printf("Physical memory chunk(s):\n"); 258 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 259 vm_paddr_t size; 260 261 size = phys_avail[indx + 1] - phys_avail[indx]; 262 printf( 263 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 264 (uintmax_t)phys_avail[indx], 265 (uintmax_t)phys_avail[indx + 1] - 1, 266 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 267 } 268 } 269 270 vm_ksubmap_init(&kmi); 271 272 printf("avail memory = %ju (%ju MB)\n", 273 ptoa((uintmax_t)cnt.v_free_count), 274 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 275 276 /* 277 * Set up buffers, so they can be used to read disk labels. 278 */ 279 bufinit(); 280 vm_pager_bufferinit(); 281 282 cpu_setregs(); 283 mca_init(); 284} 285 286/* 287 * Send an interrupt to process. 288 * 289 * Stack is set up to allow sigcode stored 290 * at top to call routine, followed by call 291 * to sigreturn routine below. After sigreturn 292 * resets the signal mask, the stack, and the 293 * frame pointer, it returns to the user 294 * specified pc, psl. 295 */ 296void 297sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 298{ 299 struct sigframe sf, *sfp; 300 struct proc *p; 301 struct thread *td; 302 struct sigacts *psp; 303 char *sp; 304 struct trapframe *regs; 305 int sig; 306 int oonstack; 307 308 td = curthread; 309 p = td->td_proc; 310 PROC_LOCK_ASSERT(p, MA_OWNED); 311 sig = ksi->ksi_signo; 312 psp = p->p_sigacts; 313 mtx_assert(&psp->ps_mtx, MA_OWNED); 314 regs = td->td_frame; 315 oonstack = sigonstack(regs->tf_rsp); 316 317 /* Save user context. */ 318 bzero(&sf, sizeof(sf)); 319 sf.sf_uc.uc_sigmask = *mask; 320 sf.sf_uc.uc_stack = td->td_sigstk; 321 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 322 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 323 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 324 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 325 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 326 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 327 fpstate_drop(td); 328 sf.sf_uc.uc_mcontext.mc_fsbase = td->td_pcb->pcb_fsbase; 329 sf.sf_uc.uc_mcontext.mc_gsbase = td->td_pcb->pcb_gsbase; 330 331 /* Allocate space for the signal handler context. */ 332 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 333 SIGISMEMBER(psp->ps_sigonstack, sig)) { 334 sp = td->td_sigstk.ss_sp + 335 td->td_sigstk.ss_size - sizeof(struct sigframe); 336#if defined(COMPAT_43) 337 td->td_sigstk.ss_flags |= SS_ONSTACK; 338#endif 339 } else 340 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 341 /* Align to 16 bytes. */ 342 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 343 344 /* Translate the signal if appropriate. */ 345 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 346 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 347 348 /* Build the argument list for the signal handler. */ 349 regs->tf_rdi = sig; /* arg 1 in %rdi */ 350 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 351 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 352 /* Signal handler installed with SA_SIGINFO. */ 353 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 354 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 355 356 /* Fill in POSIX parts */ 357 sf.sf_si = ksi->ksi_info; 358 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 359 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 360 } else { 361 /* Old FreeBSD-style arguments. */ 362 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 363 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 364 sf.sf_ahu.sf_handler = catcher; 365 } 366 mtx_unlock(&psp->ps_mtx); 367 PROC_UNLOCK(p); 368 369 /* 370 * Copy the sigframe out to the user's stack. 371 */ 372 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 373#ifdef DEBUG 374 printf("process %ld has trashed its stack\n", (long)p->p_pid); 375#endif 376 PROC_LOCK(p); 377 sigexit(td, SIGILL); 378 } 379 380 regs->tf_rsp = (long)sfp; 381 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 382 regs->tf_rflags &= ~(PSL_T | PSL_D); 383 regs->tf_cs = _ucodesel; 384 regs->tf_ds = _udatasel; 385 regs->tf_es = _udatasel; 386 regs->tf_fs = _ufssel; 387 regs->tf_gs = _ugssel; 388 regs->tf_flags = TF_HASSEGS; 389 td->td_pcb->pcb_full_iret = 1; 390 PROC_LOCK(p); 391 mtx_lock(&psp->ps_mtx); 392} 393 394/* 395 * System call to cleanup state after a signal 396 * has been taken. Reset signal mask and 397 * stack state from context left by sendsig (above). 398 * Return to previous pc and psl as specified by 399 * context left by sendsig. Check carefully to 400 * make sure that the user has not modified the 401 * state to gain improper privileges. 402 * 403 * MPSAFE 404 */ 405int 406sigreturn(td, uap) 407 struct thread *td; 408 struct sigreturn_args /* { 409 const struct __ucontext *sigcntxp; 410 } */ *uap; 411{ 412 ucontext_t uc; 413 struct proc *p = td->td_proc; 414 struct trapframe *regs; 415 const ucontext_t *ucp; 416 long rflags; 417 int cs, error, ret; 418 ksiginfo_t ksi; 419 420 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 421 if (error != 0) { 422 printf("sigreturn (pid %d): copyin failed\n", p->p_pid); 423 return (error); 424 } 425 ucp = &uc; 426 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 427 printf("sigreturn (pid %d): mc_flags %x\n", p->p_pid, 428 ucp->uc_mcontext.mc_flags); 429 return (EINVAL); 430 } 431 regs = td->td_frame; 432 rflags = ucp->uc_mcontext.mc_rflags; 433 /* 434 * Don't allow users to change privileged or reserved flags. 435 */ 436 /* 437 * XXX do allow users to change the privileged flag PSL_RF. 438 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 439 * should sometimes set it there too. tf_rflags is kept in 440 * the signal context during signal handling and there is no 441 * other place to remember it, so the PSL_RF bit may be 442 * corrupted by the signal handler without us knowing. 443 * Corruption of the PSL_RF bit at worst causes one more or 444 * one less debugger trap, so allowing it is fairly harmless. 445 */ 446 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 447 printf("sigreturn (pid %d): rflags = 0x%lx\n", p->p_pid, 448 rflags); 449 return (EINVAL); 450 } 451 452 /* 453 * Don't allow users to load a valid privileged %cs. Let the 454 * hardware check for invalid selectors, excess privilege in 455 * other selectors, invalid %eip's and invalid %esp's. 456 */ 457 cs = ucp->uc_mcontext.mc_cs; 458 if (!CS_SECURE(cs)) { 459 printf("sigreturn (pid %d): cs = 0x%x\n", p->p_pid, cs); 460 ksiginfo_init_trap(&ksi); 461 ksi.ksi_signo = SIGBUS; 462 ksi.ksi_code = BUS_OBJERR; 463 ksi.ksi_trapno = T_PROTFLT; 464 ksi.ksi_addr = (void *)regs->tf_rip; 465 trapsignal(td, &ksi); 466 return (EINVAL); 467 } 468 469 ret = set_fpcontext(td, &ucp->uc_mcontext); 470 if (ret != 0) { 471 printf("sigreturn (pid %d): set_fpcontext\n", p->p_pid); 472 return (ret); 473 } 474 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 475 td->td_pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 476 td->td_pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 477 478 PROC_LOCK(p); 479#if defined(COMPAT_43) 480 if (ucp->uc_mcontext.mc_onstack & 1) 481 td->td_sigstk.ss_flags |= SS_ONSTACK; 482 else 483 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 484#endif 485 486 td->td_sigmask = ucp->uc_sigmask; 487 SIG_CANTMASK(td->td_sigmask); 488 signotify(td); 489 PROC_UNLOCK(p); 490 td->td_pcb->pcb_flags |= PCB_FULLCTX; 491 td->td_pcb->pcb_full_iret = 1; 492 return (EJUSTRETURN); 493} 494 495#ifdef COMPAT_FREEBSD4 496int 497freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 498{ 499 500 return sigreturn(td, (struct sigreturn_args *)uap); 501} 502#endif 503 504 505/* 506 * Machine dependent boot() routine 507 * 508 * I haven't seen anything to put here yet 509 * Possibly some stuff might be grafted back here from boot() 510 */ 511void 512cpu_boot(int howto) 513{ 514} 515 516/* 517 * Flush the D-cache for non-DMA I/O so that the I-cache can 518 * be made coherent later. 519 */ 520void 521cpu_flush_dcache(void *ptr, size_t len) 522{ 523 /* Not applicable */ 524} 525 526/* Get current clock frequency for the given cpu id. */ 527int 528cpu_est_clockrate(int cpu_id, uint64_t *rate) 529{ 530 register_t reg; 531 uint64_t tsc1, tsc2; 532 533 if (pcpu_find(cpu_id) == NULL || rate == NULL) 534 return (EINVAL); 535 536 /* If we're booting, trust the rate calibrated moments ago. */ 537 if (cold) { 538 *rate = tsc_freq; 539 return (0); 540 } 541 542#ifdef SMP 543 /* Schedule ourselves on the indicated cpu. */ 544 thread_lock(curthread); 545 sched_bind(curthread, cpu_id); 546 thread_unlock(curthread); 547#endif 548 549 /* Calibrate by measuring a short delay. */ 550 reg = intr_disable(); 551 tsc1 = rdtsc(); 552 DELAY(1000); 553 tsc2 = rdtsc(); 554 intr_restore(reg); 555 556#ifdef SMP 557 thread_lock(curthread); 558 sched_unbind(curthread); 559 thread_unlock(curthread); 560#endif 561 562 /* 563 * Calculate the difference in readings, convert to Mhz, and 564 * subtract 0.5% of the total. Empirical testing has shown that 565 * overhead in DELAY() works out to approximately this value. 566 */ 567 tsc2 -= tsc1; 568 *rate = tsc2 * 1000 - tsc2 * 5; 569 return (0); 570} 571 572/* 573 * Shutdown the CPU as much as possible 574 */ 575void 576cpu_halt(void) 577{ 578 for (;;) 579 __asm__ ("hlt"); 580} 581 582void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 583 584static void 585cpu_idle_hlt(int busy) 586{ 587 /* 588 * we must absolutely guarentee that hlt is the next instruction 589 * after sti or we introduce a timing window. 590 */ 591 disable_intr(); 592 if (sched_runnable()) 593 enable_intr(); 594 else 595 __asm __volatile("sti; hlt"); 596} 597 598static void 599cpu_idle_acpi(int busy) 600{ 601 disable_intr(); 602 if (sched_runnable()) 603 enable_intr(); 604 else if (cpu_idle_hook) 605 cpu_idle_hook(); 606 else 607 __asm __volatile("sti; hlt"); 608} 609 610static int cpu_ident_amdc1e = 0; 611 612static int 613cpu_probe_amdc1e(void) 614{ 615 int i; 616 617 /* 618 * Forget it, if we're not using local APIC timer. 619 */ 620 if (resource_disabled("apic", 0) || 621 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) 622 return (0); 623 624 /* 625 * Detect the presence of C1E capability mostly on latest 626 * dual-cores (or future) k8 family. 627 */ 628 if (cpu_vendor_id == CPU_VENDOR_AMD && 629 (cpu_id & 0x00000f00) == 0x00000f00 && 630 (cpu_id & 0x0fff0000) >= 0x00040000) { 631 cpu_ident_amdc1e = 1; 632 return (1); 633 } 634 635 return (0); 636} 637 638/* 639 * C1E renders the local APIC timer dead, so we disable it by 640 * reading the Interrupt Pending Message register and clearing 641 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 642 * 643 * Reference: 644 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 645 * #32559 revision 3.00+ 646 */ 647#define MSR_AMDK8_IPM 0xc0010055 648#define AMDK8_SMIONCMPHALT (1ULL << 27) 649#define AMDK8_C1EONCMPHALT (1ULL << 28) 650#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 651 652static void 653cpu_idle_amdc1e(int busy) 654{ 655 656 disable_intr(); 657 if (sched_runnable()) 658 enable_intr(); 659 else { 660 uint64_t msr; 661 662 msr = rdmsr(MSR_AMDK8_IPM); 663 if (msr & AMDK8_CMPHALT) 664 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 665 666 if (cpu_idle_hook) 667 cpu_idle_hook(); 668 else 669 __asm __volatile("sti; hlt"); 670 } 671} 672 673static void 674cpu_idle_spin(int busy) 675{ 676 return; 677} 678 679void (*cpu_idle_fn)(int) = cpu_idle_acpi; 680 681void 682cpu_idle(int busy) 683{ 684#ifdef SMP 685 if (mp_grab_cpu_hlt()) 686 return; 687#endif 688 cpu_idle_fn(busy); 689} 690 691/* 692 * mwait cpu power states. Lower 4 bits are sub-states. 693 */ 694#define MWAIT_C0 0xf0 695#define MWAIT_C1 0x00 696#define MWAIT_C2 0x10 697#define MWAIT_C3 0x20 698#define MWAIT_C4 0x30 699 700#define MWAIT_DISABLED 0x0 701#define MWAIT_WOKEN 0x1 702#define MWAIT_WAITING 0x2 703 704static void 705cpu_idle_mwait(int busy) 706{ 707 int *mwait; 708 709 mwait = (int *)PCPU_PTR(monitorbuf); 710 *mwait = MWAIT_WAITING; 711 if (sched_runnable()) 712 return; 713 cpu_monitor(mwait, 0, 0); 714 if (*mwait == MWAIT_WAITING) 715 cpu_mwait(0, MWAIT_C1); 716} 717 718static void 719cpu_idle_mwait_hlt(int busy) 720{ 721 int *mwait; 722 723 mwait = (int *)PCPU_PTR(monitorbuf); 724 if (busy == 0) { 725 *mwait = MWAIT_DISABLED; 726 cpu_idle_hlt(busy); 727 return; 728 } 729 *mwait = MWAIT_WAITING; 730 if (sched_runnable()) 731 return; 732 cpu_monitor(mwait, 0, 0); 733 if (*mwait == MWAIT_WAITING) 734 cpu_mwait(0, MWAIT_C1); 735} 736 737int 738cpu_idle_wakeup(int cpu) 739{ 740 struct pcpu *pcpu; 741 int *mwait; 742 743 if (cpu_idle_fn == cpu_idle_spin) 744 return (1); 745 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt) 746 return (0); 747 pcpu = pcpu_find(cpu); 748 mwait = (int *)pcpu->pc_monitorbuf; 749 /* 750 * This doesn't need to be atomic since missing the race will 751 * simply result in unnecessary IPIs. 752 */ 753 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED) 754 return (0); 755 *mwait = MWAIT_WOKEN; 756 757 return (1); 758} 759 760/* 761 * Ordered by speed/power consumption. 762 */ 763struct { 764 void *id_fn; 765 char *id_name; 766} idle_tbl[] = { 767 { cpu_idle_spin, "spin" }, 768 { cpu_idle_mwait, "mwait" }, 769 { cpu_idle_mwait_hlt, "mwait_hlt" }, 770 { cpu_idle_amdc1e, "amdc1e" }, 771 { cpu_idle_hlt, "hlt" }, 772 { cpu_idle_acpi, "acpi" }, 773 { NULL, NULL } 774}; 775 776static int 777idle_sysctl_available(SYSCTL_HANDLER_ARGS) 778{ 779 char *avail, *p; 780 int error; 781 int i; 782 783 avail = malloc(256, M_TEMP, M_WAITOK); 784 p = avail; 785 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 786 if (strstr(idle_tbl[i].id_name, "mwait") && 787 (cpu_feature2 & CPUID2_MON) == 0) 788 continue; 789 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 790 cpu_ident_amdc1e == 0) 791 continue; 792 p += sprintf(p, "%s, ", idle_tbl[i].id_name); 793 } 794 error = sysctl_handle_string(oidp, avail, 0, req); 795 free(avail, M_TEMP); 796 return (error); 797} 798 799static int 800idle_sysctl(SYSCTL_HANDLER_ARGS) 801{ 802 char buf[16]; 803 int error; 804 char *p; 805 int i; 806 807 p = "unknown"; 808 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 809 if (idle_tbl[i].id_fn == cpu_idle_fn) { 810 p = idle_tbl[i].id_name; 811 break; 812 } 813 } 814 strncpy(buf, p, sizeof(buf)); 815 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 816 if (error != 0 || req->newptr == NULL) 817 return (error); 818 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 819 if (strstr(idle_tbl[i].id_name, "mwait") && 820 (cpu_feature2 & CPUID2_MON) == 0) 821 continue; 822 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 823 cpu_ident_amdc1e == 0) 824 continue; 825 if (strcmp(idle_tbl[i].id_name, buf)) 826 continue; 827 cpu_idle_fn = idle_tbl[i].id_fn; 828 return (0); 829 } 830 return (EINVAL); 831} 832 833SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 834 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 835 836SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 837 idle_sysctl, "A", "currently selected idle function"); 838 839/* 840 * Reset registers to default values on exec. 841 */ 842void 843exec_setregs(td, entry, stack, ps_strings) 844 struct thread *td; 845 u_long entry; 846 u_long stack; 847 u_long ps_strings; 848{ 849 struct trapframe *regs = td->td_frame; 850 struct pcb *pcb = td->td_pcb; 851 852 mtx_lock(&dt_lock); 853 if (td->td_proc->p_md.md_ldt != NULL) 854 user_ldt_free(td); 855 else 856 mtx_unlock(&dt_lock); 857 858 pcb->pcb_fsbase = 0; 859 pcb->pcb_gsbase = 0; 860 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 861 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 862 pcb->pcb_full_iret = 1; 863 864 bzero((char *)regs, sizeof(struct trapframe)); 865 regs->tf_rip = entry; 866 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 867 regs->tf_rdi = stack; /* argv */ 868 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 869 regs->tf_ss = _udatasel; 870 regs->tf_cs = _ucodesel; 871 regs->tf_ds = _udatasel; 872 regs->tf_es = _udatasel; 873 regs->tf_fs = _ufssel; 874 regs->tf_gs = _ugssel; 875 regs->tf_flags = TF_HASSEGS; 876 877 /* 878 * Reset the hardware debug registers if they were in use. 879 * They won't have any meaning for the newly exec'd process. 880 */ 881 if (pcb->pcb_flags & PCB_DBREGS) { 882 pcb->pcb_dr0 = 0; 883 pcb->pcb_dr1 = 0; 884 pcb->pcb_dr2 = 0; 885 pcb->pcb_dr3 = 0; 886 pcb->pcb_dr6 = 0; 887 pcb->pcb_dr7 = 0; 888 if (pcb == PCPU_GET(curpcb)) { 889 /* 890 * Clear the debug registers on the running 891 * CPU, otherwise they will end up affecting 892 * the next process we switch to. 893 */ 894 reset_dbregs(); 895 } 896 pcb->pcb_flags &= ~PCB_DBREGS; 897 } 898 899 /* 900 * Drop the FP state if we hold it, so that the process gets a 901 * clean FP state if it uses the FPU again. 902 */ 903 fpstate_drop(td); 904} 905 906void 907cpu_setregs(void) 908{ 909 register_t cr0; 910 911 cr0 = rcr0(); 912 /* 913 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 914 * BSP. See the comments there about why we set them. 915 */ 916 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 917 load_cr0(cr0); 918} 919 920/* 921 * Initialize amd64 and configure to run kernel 922 */ 923 924/* 925 * Initialize segments & interrupt table 926 */ 927 928struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 929static struct gate_descriptor idt0[NIDT]; 930struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 931 932static char dblfault_stack[PAGE_SIZE] __aligned(16); 933 934static char nmi0_stack[PAGE_SIZE] __aligned(16); 935CTASSERT(sizeof(struct nmi_pcpu) == 16); 936 937struct amd64tss common_tss[MAXCPU]; 938 939/* 940 * Software prototypes -- in more palatable form. 941 * 942 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 943 * slots as corresponding segments for i386 kernel. 944 */ 945struct soft_segment_descriptor gdt_segs[] = { 946/* GNULL_SEL 0 Null Descriptor */ 947{ .ssd_base = 0x0, 948 .ssd_limit = 0x0, 949 .ssd_type = 0, 950 .ssd_dpl = 0, 951 .ssd_p = 0, 952 .ssd_long = 0, 953 .ssd_def32 = 0, 954 .ssd_gran = 0 }, 955/* GNULL2_SEL 1 Null Descriptor */ 956{ .ssd_base = 0x0, 957 .ssd_limit = 0x0, 958 .ssd_type = 0, 959 .ssd_dpl = 0, 960 .ssd_p = 0, 961 .ssd_long = 0, 962 .ssd_def32 = 0, 963 .ssd_gran = 0 }, 964/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 965{ .ssd_base = 0x0, 966 .ssd_limit = 0xfffff, 967 .ssd_type = SDT_MEMRWA, 968 .ssd_dpl = SEL_UPL, 969 .ssd_p = 1, 970 .ssd_long = 0, 971 .ssd_def32 = 1, 972 .ssd_gran = 1 }, 973/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 974{ .ssd_base = 0x0, 975 .ssd_limit = 0xfffff, 976 .ssd_type = SDT_MEMRWA, 977 .ssd_dpl = SEL_UPL, 978 .ssd_p = 1, 979 .ssd_long = 0, 980 .ssd_def32 = 1, 981 .ssd_gran = 1 }, 982/* GCODE_SEL 4 Code Descriptor for kernel */ 983{ .ssd_base = 0x0, 984 .ssd_limit = 0xfffff, 985 .ssd_type = SDT_MEMERA, 986 .ssd_dpl = SEL_KPL, 987 .ssd_p = 1, 988 .ssd_long = 1, 989 .ssd_def32 = 0, 990 .ssd_gran = 1 }, 991/* GDATA_SEL 5 Data Descriptor for kernel */ 992{ .ssd_base = 0x0, 993 .ssd_limit = 0xfffff, 994 .ssd_type = SDT_MEMRWA, 995 .ssd_dpl = SEL_KPL, 996 .ssd_p = 1, 997 .ssd_long = 1, 998 .ssd_def32 = 0, 999 .ssd_gran = 1 }, 1000/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1001{ .ssd_base = 0x0, 1002 .ssd_limit = 0xfffff, 1003 .ssd_type = SDT_MEMERA, 1004 .ssd_dpl = SEL_UPL, 1005 .ssd_p = 1, 1006 .ssd_long = 0, 1007 .ssd_def32 = 1, 1008 .ssd_gran = 1 }, 1009/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1010{ .ssd_base = 0x0, 1011 .ssd_limit = 0xfffff, 1012 .ssd_type = SDT_MEMRWA, 1013 .ssd_dpl = SEL_UPL, 1014 .ssd_p = 1, 1015 .ssd_long = 0, 1016 .ssd_def32 = 1, 1017 .ssd_gran = 1 }, 1018/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1019{ .ssd_base = 0x0, 1020 .ssd_limit = 0xfffff, 1021 .ssd_type = SDT_MEMERA, 1022 .ssd_dpl = SEL_UPL, 1023 .ssd_p = 1, 1024 .ssd_long = 1, 1025 .ssd_def32 = 0, 1026 .ssd_gran = 1 }, 1027/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1028{ .ssd_base = 0x0, 1029 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1030 .ssd_type = SDT_SYSTSS, 1031 .ssd_dpl = SEL_KPL, 1032 .ssd_p = 1, 1033 .ssd_long = 0, 1034 .ssd_def32 = 0, 1035 .ssd_gran = 0 }, 1036/* Actually, the TSS is a system descriptor which is double size */ 1037{ .ssd_base = 0x0, 1038 .ssd_limit = 0x0, 1039 .ssd_type = 0, 1040 .ssd_dpl = 0, 1041 .ssd_p = 0, 1042 .ssd_long = 0, 1043 .ssd_def32 = 0, 1044 .ssd_gran = 0 }, 1045/* GUSERLDT_SEL 11 LDT Descriptor */ 1046{ .ssd_base = 0x0, 1047 .ssd_limit = 0x0, 1048 .ssd_type = 0, 1049 .ssd_dpl = 0, 1050 .ssd_p = 0, 1051 .ssd_long = 0, 1052 .ssd_def32 = 0, 1053 .ssd_gran = 0 }, 1054/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1055{ .ssd_base = 0x0, 1056 .ssd_limit = 0x0, 1057 .ssd_type = 0, 1058 .ssd_dpl = 0, 1059 .ssd_p = 0, 1060 .ssd_long = 0, 1061 .ssd_def32 = 0, 1062 .ssd_gran = 0 }, 1063}; 1064 1065void 1066setidt(idx, func, typ, dpl, ist) 1067 int idx; 1068 inthand_t *func; 1069 int typ; 1070 int dpl; 1071 int ist; 1072{ 1073 struct gate_descriptor *ip; 1074 1075 ip = idt + idx; 1076 ip->gd_looffset = (uintptr_t)func; 1077 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1078 ip->gd_ist = ist; 1079 ip->gd_xx = 0; 1080 ip->gd_type = typ; 1081 ip->gd_dpl = dpl; 1082 ip->gd_p = 1; 1083 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1084} 1085 1086extern inthand_t 1087 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1088 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1089 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1090 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1091 IDTVEC(xmm), IDTVEC(dblfault), 1092 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1093 1094#ifdef DDB 1095/* 1096 * Display the index and function name of any IDT entries that don't use 1097 * the default 'rsvd' entry point. 1098 */ 1099DB_SHOW_COMMAND(idt, db_show_idt) 1100{ 1101 struct gate_descriptor *ip; 1102 int idx; 1103 uintptr_t func; 1104 1105 ip = idt; 1106 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1107 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1108 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1109 db_printf("%3d\t", idx); 1110 db_printsym(func, DB_STGY_PROC); 1111 db_printf("\n"); 1112 } 1113 ip++; 1114 } 1115} 1116#endif 1117 1118void 1119sdtossd(sd, ssd) 1120 struct user_segment_descriptor *sd; 1121 struct soft_segment_descriptor *ssd; 1122{ 1123 1124 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1125 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1126 ssd->ssd_type = sd->sd_type; 1127 ssd->ssd_dpl = sd->sd_dpl; 1128 ssd->ssd_p = sd->sd_p; 1129 ssd->ssd_long = sd->sd_long; 1130 ssd->ssd_def32 = sd->sd_def32; 1131 ssd->ssd_gran = sd->sd_gran; 1132} 1133 1134void 1135ssdtosd(ssd, sd) 1136 struct soft_segment_descriptor *ssd; 1137 struct user_segment_descriptor *sd; 1138{ 1139 1140 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1141 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1142 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1143 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1144 sd->sd_type = ssd->ssd_type; 1145 sd->sd_dpl = ssd->ssd_dpl; 1146 sd->sd_p = ssd->ssd_p; 1147 sd->sd_long = ssd->ssd_long; 1148 sd->sd_def32 = ssd->ssd_def32; 1149 sd->sd_gran = ssd->ssd_gran; 1150} 1151 1152void 1153ssdtosyssd(ssd, sd) 1154 struct soft_segment_descriptor *ssd; 1155 struct system_segment_descriptor *sd; 1156{ 1157 1158 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1159 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1160 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1161 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1162 sd->sd_type = ssd->ssd_type; 1163 sd->sd_dpl = ssd->ssd_dpl; 1164 sd->sd_p = ssd->ssd_p; 1165 sd->sd_gran = ssd->ssd_gran; 1166} 1167 1168#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1169#include <isa/isavar.h> 1170#include <isa/isareg.h> 1171/* 1172 * Return a bitmap of the current interrupt requests. This is 8259-specific 1173 * and is only suitable for use at probe time. 1174 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1175 * It shouldn't be here. There should probably be an APIC centric 1176 * implementation in the apic driver code, if at all. 1177 */ 1178intrmask_t 1179isa_irq_pending(void) 1180{ 1181 u_char irr1; 1182 u_char irr2; 1183 1184 irr1 = inb(IO_ICU1); 1185 irr2 = inb(IO_ICU2); 1186 return ((irr2 << 8) | irr1); 1187} 1188#endif 1189 1190u_int basemem; 1191 1192/* 1193 * Populate the (physmap) array with base/bound pairs describing the 1194 * available physical memory in the system, then test this memory and 1195 * build the phys_avail array describing the actually-available memory. 1196 * 1197 * If we cannot accurately determine the physical memory map, then use 1198 * value from the 0xE801 call, and failing that, the RTC. 1199 * 1200 * Total memory size may be set by the kernel environment variable 1201 * hw.physmem or the compile-time define MAXMEM. 1202 * 1203 * XXX first should be vm_paddr_t. 1204 */ 1205static void 1206getmemsize(caddr_t kmdp, u_int64_t first) 1207{ 1208 int i, off, physmap_idx, pa_indx, da_indx; 1209 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1210 u_long physmem_tunable; 1211 pt_entry_t *pte; 1212 struct bios_smap *smapbase, *smap, *smapend; 1213 u_int32_t smapsize; 1214 quad_t dcons_addr, dcons_size; 1215 1216 bzero(physmap, sizeof(physmap)); 1217 basemem = 0; 1218 physmap_idx = 0; 1219 1220 /* 1221 * get memory map from INT 15:E820, kindly supplied by the loader. 1222 * 1223 * subr_module.c says: 1224 * "Consumer may safely assume that size value precedes data." 1225 * ie: an int32_t immediately precedes smap. 1226 */ 1227 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1228 MODINFO_METADATA | MODINFOMD_SMAP); 1229 if (smapbase == NULL) 1230 panic("No BIOS smap info from loader!"); 1231 1232 smapsize = *((u_int32_t *)smapbase - 1); 1233 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1234 1235 for (smap = smapbase; smap < smapend; smap++) { 1236 if (boothowto & RB_VERBOSE) 1237 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1238 smap->type, smap->base, smap->length); 1239 1240 if (smap->type != SMAP_TYPE_MEMORY) 1241 continue; 1242 1243 if (smap->length == 0) 1244 continue; 1245 1246 for (i = 0; i <= physmap_idx; i += 2) { 1247 if (smap->base < physmap[i + 1]) { 1248 if (boothowto & RB_VERBOSE) 1249 printf( 1250 "Overlapping or non-monotonic memory region, ignoring second region\n"); 1251 continue; 1252 } 1253 } 1254 1255 if (smap->base == physmap[physmap_idx + 1]) { 1256 physmap[physmap_idx + 1] += smap->length; 1257 continue; 1258 } 1259 1260 physmap_idx += 2; 1261 if (physmap_idx == PHYSMAP_SIZE) { 1262 printf( 1263 "Too many segments in the physical address map, giving up\n"); 1264 break; 1265 } 1266 physmap[physmap_idx] = smap->base; 1267 physmap[physmap_idx + 1] = smap->base + smap->length; 1268 } 1269 1270 /* 1271 * Find the 'base memory' segment for SMP 1272 */ 1273 basemem = 0; 1274 for (i = 0; i <= physmap_idx; i += 2) { 1275 if (physmap[i] == 0x00000000) { 1276 basemem = physmap[i + 1] / 1024; 1277 break; 1278 } 1279 } 1280 if (basemem == 0) 1281 panic("BIOS smap did not include a basemem segment!"); 1282 1283#ifdef SMP 1284 /* make hole for AP bootstrap code */ 1285 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1286#endif 1287 1288 /* 1289 * Maxmem isn't the "maximum memory", it's one larger than the 1290 * highest page of the physical address space. It should be 1291 * called something like "Maxphyspage". We may adjust this 1292 * based on ``hw.physmem'' and the results of the memory test. 1293 */ 1294 Maxmem = atop(physmap[physmap_idx + 1]); 1295 1296#ifdef MAXMEM 1297 Maxmem = MAXMEM / 4; 1298#endif 1299 1300 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1301 Maxmem = atop(physmem_tunable); 1302 1303 /* 1304 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1305 * in the system. 1306 */ 1307 if (Maxmem > atop(physmap[physmap_idx + 1])) 1308 Maxmem = atop(physmap[physmap_idx + 1]); 1309 1310 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1311 (boothowto & RB_VERBOSE)) 1312 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1313 1314 /* call pmap initialization to make new kernel address space */ 1315 pmap_bootstrap(&first); 1316 1317 /* 1318 * Size up each available chunk of physical memory. 1319 */ 1320 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1321 pa_indx = 0; 1322 da_indx = 1; 1323 phys_avail[pa_indx++] = physmap[0]; 1324 phys_avail[pa_indx] = physmap[0]; 1325 dump_avail[da_indx] = physmap[0]; 1326 pte = CMAP1; 1327 1328 /* 1329 * Get dcons buffer address 1330 */ 1331 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1332 getenv_quad("dcons.size", &dcons_size) == 0) 1333 dcons_addr = 0; 1334 1335 /* 1336 * physmap is in bytes, so when converting to page boundaries, 1337 * round up the start address and round down the end address. 1338 */ 1339 for (i = 0; i <= physmap_idx; i += 2) { 1340 vm_paddr_t end; 1341 1342 end = ptoa((vm_paddr_t)Maxmem); 1343 if (physmap[i + 1] < end) 1344 end = trunc_page(physmap[i + 1]); 1345 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1346 int tmp, page_bad, full; 1347 int *ptr = (int *)CADDR1; 1348 1349 full = FALSE; 1350 /* 1351 * block out kernel memory as not available. 1352 */ 1353 if (pa >= 0x100000 && pa < first) 1354 goto do_dump_avail; 1355 1356 /* 1357 * block out dcons buffer 1358 */ 1359 if (dcons_addr > 0 1360 && pa >= trunc_page(dcons_addr) 1361 && pa < dcons_addr + dcons_size) 1362 goto do_dump_avail; 1363 1364 page_bad = FALSE; 1365 1366 /* 1367 * map page into kernel: valid, read/write,non-cacheable 1368 */ 1369 *pte = pa | PG_V | PG_RW | PG_N; 1370 invltlb(); 1371 1372 tmp = *(int *)ptr; 1373 /* 1374 * Test for alternating 1's and 0's 1375 */ 1376 *(volatile int *)ptr = 0xaaaaaaaa; 1377 if (*(volatile int *)ptr != 0xaaaaaaaa) 1378 page_bad = TRUE; 1379 /* 1380 * Test for alternating 0's and 1's 1381 */ 1382 *(volatile int *)ptr = 0x55555555; 1383 if (*(volatile int *)ptr != 0x55555555) 1384 page_bad = TRUE; 1385 /* 1386 * Test for all 1's 1387 */ 1388 *(volatile int *)ptr = 0xffffffff; 1389 if (*(volatile int *)ptr != 0xffffffff) 1390 page_bad = TRUE; 1391 /* 1392 * Test for all 0's 1393 */ 1394 *(volatile int *)ptr = 0x0; 1395 if (*(volatile int *)ptr != 0x0) 1396 page_bad = TRUE; 1397 /* 1398 * Restore original value. 1399 */ 1400 *(int *)ptr = tmp; 1401 1402 /* 1403 * Adjust array of valid/good pages. 1404 */ 1405 if (page_bad == TRUE) 1406 continue; 1407 /* 1408 * If this good page is a continuation of the 1409 * previous set of good pages, then just increase 1410 * the end pointer. Otherwise start a new chunk. 1411 * Note that "end" points one higher than end, 1412 * making the range >= start and < end. 1413 * If we're also doing a speculative memory 1414 * test and we at or past the end, bump up Maxmem 1415 * so that we keep going. The first bad page 1416 * will terminate the loop. 1417 */ 1418 if (phys_avail[pa_indx] == pa) { 1419 phys_avail[pa_indx] += PAGE_SIZE; 1420 } else { 1421 pa_indx++; 1422 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1423 printf( 1424 "Too many holes in the physical address space, giving up\n"); 1425 pa_indx--; 1426 full = TRUE; 1427 goto do_dump_avail; 1428 } 1429 phys_avail[pa_indx++] = pa; /* start */ 1430 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1431 } 1432 physmem++; 1433do_dump_avail: 1434 if (dump_avail[da_indx] == pa) { 1435 dump_avail[da_indx] += PAGE_SIZE; 1436 } else { 1437 da_indx++; 1438 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1439 da_indx--; 1440 goto do_next; 1441 } 1442 dump_avail[da_indx++] = pa; /* start */ 1443 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1444 } 1445do_next: 1446 if (full) 1447 break; 1448 } 1449 } 1450 *pte = 0; 1451 invltlb(); 1452 1453 /* 1454 * XXX 1455 * The last chunk must contain at least one page plus the message 1456 * buffer to avoid complicating other code (message buffer address 1457 * calculation, etc.). 1458 */ 1459 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1460 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1461 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1462 phys_avail[pa_indx--] = 0; 1463 phys_avail[pa_indx--] = 0; 1464 } 1465 1466 Maxmem = atop(phys_avail[pa_indx]); 1467 1468 /* Trim off space for the message buffer. */ 1469 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1470 1471 /* Map the message buffer. */ 1472 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1473 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] + 1474 off); 1475} 1476 1477u_int64_t 1478hammer_time(u_int64_t modulep, u_int64_t physfree) 1479{ 1480 caddr_t kmdp; 1481 int gsel_tss, x; 1482 struct pcpu *pc; 1483 struct nmi_pcpu *np; 1484 u_int64_t msr; 1485 char *env; 1486 1487 thread0.td_kstack = physfree + KERNBASE; 1488 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1489 physfree += KSTACK_PAGES * PAGE_SIZE; 1490 thread0.td_pcb = (struct pcb *) 1491 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1492 1493 /* 1494 * This may be done better later if it gets more high level 1495 * components in it. If so just link td->td_proc here. 1496 */ 1497 proc_linkup0(&proc0, &thread0); 1498 1499 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1500 preload_bootstrap_relocate(KERNBASE); 1501 kmdp = preload_search_by_type("elf kernel"); 1502 if (kmdp == NULL) 1503 kmdp = preload_search_by_type("elf64 kernel"); 1504 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1505 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1506#ifdef DDB 1507 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1508 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1509#endif 1510 1511 /* Init basic tunables, hz etc */ 1512 init_param1(); 1513 1514 /* 1515 * make gdt memory segments 1516 */ 1517 for (x = 0; x < NGDT; x++) { 1518 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1519 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1520 ssdtosd(&gdt_segs[x], &gdt[x]); 1521 } 1522 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1523 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1524 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1525 1526 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1527 r_gdt.rd_base = (long) gdt; 1528 lgdt(&r_gdt); 1529 pc = &__pcpu[0]; 1530 1531 wrmsr(MSR_FSBASE, 0); /* User value */ 1532 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1533 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1534 1535 pcpu_init(pc, 0, sizeof(struct pcpu)); 1536 dpcpu_init((void *)(physfree + KERNBASE), 0); 1537 physfree += DPCPU_SIZE; 1538 PCPU_SET(prvspace, pc); 1539 PCPU_SET(curthread, &thread0); 1540 PCPU_SET(curpcb, thread0.td_pcb); 1541 PCPU_SET(tssp, &common_tss[0]); 1542 PCPU_SET(commontssp, &common_tss[0]); 1543 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1544 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1545 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1546 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1547 1548 /* 1549 * Initialize mutexes. 1550 * 1551 * icu_lock: in order to allow an interrupt to occur in a critical 1552 * section, to set pcpu->ipending (etc...) properly, we 1553 * must be able to get the icu lock, so it can't be 1554 * under witness. 1555 */ 1556 mutex_init(); 1557 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1558 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1559 1560 /* exceptions */ 1561 for (x = 0; x < NIDT; x++) 1562 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1563 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1564 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1565 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1566 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1567 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1568 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1569 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1570 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1571 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1572 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1573 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1574 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1575 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1576 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1577 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1578 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1579 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1580 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1581 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1582 1583 r_idt.rd_limit = sizeof(idt0) - 1; 1584 r_idt.rd_base = (long) idt; 1585 lidt(&r_idt); 1586 1587 /* 1588 * Initialize the i8254 before the console so that console 1589 * initialization can use DELAY(). 1590 */ 1591 i8254_init(); 1592 1593 /* 1594 * Initialize the console before we print anything out. 1595 */ 1596 cninit(); 1597 1598#ifdef DEV_ISA 1599#ifdef DEV_ATPIC 1600 elcr_probe(); 1601 atpic_startup(); 1602#else 1603 /* Reset and mask the atpics and leave them shut down. */ 1604 atpic_reset(); 1605 1606 /* 1607 * Point the ICU spurious interrupt vectors at the APIC spurious 1608 * interrupt handler. 1609 */ 1610 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1611 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1612#endif 1613#else 1614#error "have you forgotten the isa device?"; 1615#endif 1616 1617 kdb_init(); 1618 1619#ifdef KDB 1620 if (boothowto & RB_KDB) 1621 kdb_enter(KDB_WHY_BOOTFLAGS, 1622 "Boot flags requested debugger"); 1623#endif 1624 1625 identify_cpu(); /* Final stage of CPU initialization */ 1626 initializecpu(); /* Initialize CPU registers */ 1627 1628 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1629 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1630 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1631 /* Ensure the stack is aligned to 16 bytes */ 1632 common_tss[0].tss_rsp0 &= ~0xFul; 1633 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1634 1635 /* doublefault stack space, runs on ist1 */ 1636 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1637 1638 /* 1639 * NMI stack, runs on ist2. The pcpu pointer is stored just 1640 * above the start of the ist2 stack. 1641 */ 1642 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1643 np->np_pcpu = (register_t) pc; 1644 common_tss[0].tss_ist2 = (long) np; 1645 1646 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1647 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1648 IOPAGES * PAGE_SIZE; 1649 1650 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1651 ltr(gsel_tss); 1652 1653 /* Set up the fast syscall stuff */ 1654 msr = rdmsr(MSR_EFER) | EFER_SCE; 1655 wrmsr(MSR_EFER, msr); 1656 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1657 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1658 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1659 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1660 wrmsr(MSR_STAR, msr); 1661 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1662 1663 getmemsize(kmdp, physfree); 1664 init_param2(physmem); 1665 1666 /* now running on new page tables, configured,and u/iom is accessible */ 1667 1668 msgbufinit(msgbufp, MSGBUF_SIZE); 1669 fpuinit(); 1670 1671 /* transfer to user mode */ 1672 1673 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1674 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1675 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1676 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1677 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1678 1679 load_ds(_udatasel); 1680 load_es(_udatasel); 1681 load_fs(_ufssel); 1682 1683 /* setup proc 0's pcb */ 1684 thread0.td_pcb->pcb_flags = 0; 1685 thread0.td_pcb->pcb_cr3 = KPML4phys; 1686 thread0.td_frame = &proc0_tf; 1687 1688 env = getenv("kernelname"); 1689 if (env != NULL) 1690 strlcpy(kernelname, env, sizeof(kernelname)); 1691 1692#ifdef XENHVM 1693 if (inw(0x10) == 0x49d2) { 1694 if (bootverbose) 1695 printf("Xen detected: disabling emulated block and network devices\n"); 1696 outw(0x10, 3); 1697 } 1698#endif 1699 1700 if (cpu_probe_amdc1e()) 1701 cpu_idle_fn = cpu_idle_amdc1e; 1702 1703 /* Location of kernel stack for locore */ 1704 return ((u_int64_t)thread0.td_pcb); 1705} 1706 1707void 1708cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1709{ 1710 1711 pcpu->pc_acpi_id = 0xffffffff; 1712} 1713 1714void 1715spinlock_enter(void) 1716{ 1717 struct thread *td; 1718 1719 td = curthread; 1720 if (td->td_md.md_spinlock_count == 0) 1721 td->td_md.md_saved_flags = intr_disable(); 1722 td->td_md.md_spinlock_count++; 1723 critical_enter(); 1724} 1725 1726void 1727spinlock_exit(void) 1728{ 1729 struct thread *td; 1730 1731 td = curthread; 1732 critical_exit(); 1733 td->td_md.md_spinlock_count--; 1734 if (td->td_md.md_spinlock_count == 0) 1735 intr_restore(td->td_md.md_saved_flags); 1736} 1737 1738/* 1739 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1740 * we want to start a backtrace from the function that caused us to enter 1741 * the debugger. We have the context in the trapframe, but base the trace 1742 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1743 * enough for a backtrace. 1744 */ 1745void 1746makectx(struct trapframe *tf, struct pcb *pcb) 1747{ 1748 1749 pcb->pcb_r12 = tf->tf_r12; 1750 pcb->pcb_r13 = tf->tf_r13; 1751 pcb->pcb_r14 = tf->tf_r14; 1752 pcb->pcb_r15 = tf->tf_r15; 1753 pcb->pcb_rbp = tf->tf_rbp; 1754 pcb->pcb_rbx = tf->tf_rbx; 1755 pcb->pcb_rip = tf->tf_rip; 1756 pcb->pcb_rsp = (ISPL(tf->tf_cs)) ? tf->tf_rsp : (long)(tf + 1) - 8; 1757} 1758 1759int 1760ptrace_set_pc(struct thread *td, unsigned long addr) 1761{ 1762 td->td_frame->tf_rip = addr; 1763 return (0); 1764} 1765 1766int 1767ptrace_single_step(struct thread *td) 1768{ 1769 td->td_frame->tf_rflags |= PSL_T; 1770 return (0); 1771} 1772 1773int 1774ptrace_clear_single_step(struct thread *td) 1775{ 1776 td->td_frame->tf_rflags &= ~PSL_T; 1777 return (0); 1778} 1779 1780int 1781fill_regs(struct thread *td, struct reg *regs) 1782{ 1783 struct trapframe *tp; 1784 1785 tp = td->td_frame; 1786 regs->r_r15 = tp->tf_r15; 1787 regs->r_r14 = tp->tf_r14; 1788 regs->r_r13 = tp->tf_r13; 1789 regs->r_r12 = tp->tf_r12; 1790 regs->r_r11 = tp->tf_r11; 1791 regs->r_r10 = tp->tf_r10; 1792 regs->r_r9 = tp->tf_r9; 1793 regs->r_r8 = tp->tf_r8; 1794 regs->r_rdi = tp->tf_rdi; 1795 regs->r_rsi = tp->tf_rsi; 1796 regs->r_rbp = tp->tf_rbp; 1797 regs->r_rbx = tp->tf_rbx; 1798 regs->r_rdx = tp->tf_rdx; 1799 regs->r_rcx = tp->tf_rcx; 1800 regs->r_rax = tp->tf_rax; 1801 regs->r_rip = tp->tf_rip; 1802 regs->r_cs = tp->tf_cs; 1803 regs->r_rflags = tp->tf_rflags; 1804 regs->r_rsp = tp->tf_rsp; 1805 regs->r_ss = tp->tf_ss; 1806 if (tp->tf_flags & TF_HASSEGS) { 1807 regs->r_ds = tp->tf_ds; 1808 regs->r_es = tp->tf_es; 1809 regs->r_fs = tp->tf_fs; 1810 regs->r_gs = tp->tf_gs; 1811 } else { 1812 regs->r_ds = 0; 1813 regs->r_es = 0; 1814 regs->r_fs = 0; 1815 regs->r_gs = 0; 1816 } 1817 return (0); 1818} 1819 1820int 1821set_regs(struct thread *td, struct reg *regs) 1822{ 1823 struct trapframe *tp; 1824 register_t rflags; 1825 1826 tp = td->td_frame; 1827 rflags = regs->r_rflags & 0xffffffff; 1828 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1829 return (EINVAL); 1830 tp->tf_r15 = regs->r_r15; 1831 tp->tf_r14 = regs->r_r14; 1832 tp->tf_r13 = regs->r_r13; 1833 tp->tf_r12 = regs->r_r12; 1834 tp->tf_r11 = regs->r_r11; 1835 tp->tf_r10 = regs->r_r10; 1836 tp->tf_r9 = regs->r_r9; 1837 tp->tf_r8 = regs->r_r8; 1838 tp->tf_rdi = regs->r_rdi; 1839 tp->tf_rsi = regs->r_rsi; 1840 tp->tf_rbp = regs->r_rbp; 1841 tp->tf_rbx = regs->r_rbx; 1842 tp->tf_rdx = regs->r_rdx; 1843 tp->tf_rcx = regs->r_rcx; 1844 tp->tf_rax = regs->r_rax; 1845 tp->tf_rip = regs->r_rip; 1846 tp->tf_cs = regs->r_cs; 1847 tp->tf_rflags = rflags; 1848 tp->tf_rsp = regs->r_rsp; 1849 tp->tf_ss = regs->r_ss; 1850 if (0) { /* XXXKIB */ 1851 tp->tf_ds = regs->r_ds; 1852 tp->tf_es = regs->r_es; 1853 tp->tf_fs = regs->r_fs; 1854 tp->tf_gs = regs->r_gs; 1855 tp->tf_flags = TF_HASSEGS; 1856 } 1857 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1858 return (0); 1859} 1860 1861/* XXX check all this stuff! */ 1862/* externalize from sv_xmm */ 1863static void 1864fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1865{ 1866 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1867 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1868 int i; 1869 1870 /* pcb -> fpregs */ 1871 bzero(fpregs, sizeof(*fpregs)); 1872 1873 /* FPU control/status */ 1874 penv_fpreg->en_cw = penv_xmm->en_cw; 1875 penv_fpreg->en_sw = penv_xmm->en_sw; 1876 penv_fpreg->en_tw = penv_xmm->en_tw; 1877 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1878 penv_fpreg->en_rip = penv_xmm->en_rip; 1879 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1880 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1881 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1882 1883 /* FPU registers */ 1884 for (i = 0; i < 8; ++i) 1885 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1886 1887 /* SSE registers */ 1888 for (i = 0; i < 16; ++i) 1889 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1890} 1891 1892/* internalize from fpregs into sv_xmm */ 1893static void 1894set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1895{ 1896 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1897 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1898 int i; 1899 1900 /* fpregs -> pcb */ 1901 /* FPU control/status */ 1902 penv_xmm->en_cw = penv_fpreg->en_cw; 1903 penv_xmm->en_sw = penv_fpreg->en_sw; 1904 penv_xmm->en_tw = penv_fpreg->en_tw; 1905 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1906 penv_xmm->en_rip = penv_fpreg->en_rip; 1907 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1908 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1909 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1910 1911 /* FPU registers */ 1912 for (i = 0; i < 8; ++i) 1913 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1914 1915 /* SSE registers */ 1916 for (i = 0; i < 16; ++i) 1917 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1918} 1919 1920/* externalize from td->pcb */ 1921int 1922fill_fpregs(struct thread *td, struct fpreg *fpregs) 1923{ 1924 1925 fill_fpregs_xmm(&td->td_pcb->pcb_save, fpregs); 1926 return (0); 1927} 1928 1929/* internalize to td->pcb */ 1930int 1931set_fpregs(struct thread *td, struct fpreg *fpregs) 1932{ 1933 1934 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_save); 1935 return (0); 1936} 1937 1938/* 1939 * Get machine context. 1940 */ 1941int 1942get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1943{ 1944 struct trapframe *tp; 1945 1946 tp = td->td_frame; 1947 PROC_LOCK(curthread->td_proc); 1948 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1949 PROC_UNLOCK(curthread->td_proc); 1950 mcp->mc_r15 = tp->tf_r15; 1951 mcp->mc_r14 = tp->tf_r14; 1952 mcp->mc_r13 = tp->tf_r13; 1953 mcp->mc_r12 = tp->tf_r12; 1954 mcp->mc_r11 = tp->tf_r11; 1955 mcp->mc_r10 = tp->tf_r10; 1956 mcp->mc_r9 = tp->tf_r9; 1957 mcp->mc_r8 = tp->tf_r8; 1958 mcp->mc_rdi = tp->tf_rdi; 1959 mcp->mc_rsi = tp->tf_rsi; 1960 mcp->mc_rbp = tp->tf_rbp; 1961 mcp->mc_rbx = tp->tf_rbx; 1962 mcp->mc_rcx = tp->tf_rcx; 1963 mcp->mc_rflags = tp->tf_rflags; 1964 if (flags & GET_MC_CLEAR_RET) { 1965 mcp->mc_rax = 0; 1966 mcp->mc_rdx = 0; 1967 mcp->mc_rflags &= ~PSL_C; 1968 } else { 1969 mcp->mc_rax = tp->tf_rax; 1970 mcp->mc_rdx = tp->tf_rdx; 1971 } 1972 mcp->mc_rip = tp->tf_rip; 1973 mcp->mc_cs = tp->tf_cs; 1974 mcp->mc_rsp = tp->tf_rsp; 1975 mcp->mc_ss = tp->tf_ss; 1976 mcp->mc_ds = tp->tf_ds; 1977 mcp->mc_es = tp->tf_es; 1978 mcp->mc_fs = tp->tf_fs; 1979 mcp->mc_gs = tp->tf_gs; 1980 mcp->mc_flags = tp->tf_flags; 1981 mcp->mc_len = sizeof(*mcp); 1982 get_fpcontext(td, mcp); 1983 mcp->mc_fsbase = td->td_pcb->pcb_fsbase; 1984 mcp->mc_gsbase = td->td_pcb->pcb_gsbase; 1985 return (0); 1986} 1987 1988/* 1989 * Set machine context. 1990 * 1991 * However, we don't set any but the user modifiable flags, and we won't 1992 * touch the cs selector. 1993 */ 1994int 1995set_mcontext(struct thread *td, const mcontext_t *mcp) 1996{ 1997 struct trapframe *tp; 1998 long rflags; 1999 int ret; 2000 2001 tp = td->td_frame; 2002 if (mcp->mc_len != sizeof(*mcp) || 2003 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2004 return (EINVAL); 2005 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2006 (tp->tf_rflags & ~PSL_USERCHANGE); 2007 ret = set_fpcontext(td, mcp); 2008 if (ret != 0) 2009 return (ret); 2010 tp->tf_r15 = mcp->mc_r15; 2011 tp->tf_r14 = mcp->mc_r14; 2012 tp->tf_r13 = mcp->mc_r13; 2013 tp->tf_r12 = mcp->mc_r12; 2014 tp->tf_r11 = mcp->mc_r11; 2015 tp->tf_r10 = mcp->mc_r10; 2016 tp->tf_r9 = mcp->mc_r9; 2017 tp->tf_r8 = mcp->mc_r8; 2018 tp->tf_rdi = mcp->mc_rdi; 2019 tp->tf_rsi = mcp->mc_rsi; 2020 tp->tf_rbp = mcp->mc_rbp; 2021 tp->tf_rbx = mcp->mc_rbx; 2022 tp->tf_rdx = mcp->mc_rdx; 2023 tp->tf_rcx = mcp->mc_rcx; 2024 tp->tf_rax = mcp->mc_rax; 2025 tp->tf_rip = mcp->mc_rip; 2026 tp->tf_rflags = rflags; 2027 tp->tf_rsp = mcp->mc_rsp; 2028 tp->tf_ss = mcp->mc_ss; 2029 tp->tf_flags = mcp->mc_flags; 2030 if (tp->tf_flags & TF_HASSEGS) { 2031 tp->tf_ds = mcp->mc_ds; 2032 tp->tf_es = mcp->mc_es; 2033 tp->tf_fs = mcp->mc_fs; 2034 tp->tf_gs = mcp->mc_gs; 2035 } 2036 if (mcp->mc_flags & _MC_HASBASES) { 2037 td->td_pcb->pcb_fsbase = mcp->mc_fsbase; 2038 td->td_pcb->pcb_gsbase = mcp->mc_gsbase; 2039 } 2040 td->td_pcb->pcb_flags |= PCB_FULLCTX; 2041 td->td_pcb->pcb_full_iret = 1; 2042 return (0); 2043} 2044 2045static void 2046get_fpcontext(struct thread *td, mcontext_t *mcp) 2047{ 2048 2049 mcp->mc_ownedfp = fpugetregs(td, (struct savefpu *)&mcp->mc_fpstate); 2050 mcp->mc_fpformat = fpuformat(); 2051} 2052 2053static int 2054set_fpcontext(struct thread *td, const mcontext_t *mcp) 2055{ 2056 struct savefpu *fpstate; 2057 2058 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2059 return (0); 2060 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2061 return (EINVAL); 2062 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2063 /* We don't care what state is left in the FPU or PCB. */ 2064 fpstate_drop(td); 2065 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2066 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2067 /* 2068 * XXX we violate the dubious requirement that fpusetregs() 2069 * be called with interrupts disabled. 2070 * XXX obsolete on trap-16 systems? 2071 */ 2072 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2073 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2074 fpusetregs(td, fpstate); 2075 } else 2076 return (EINVAL); 2077 return (0); 2078} 2079 2080void 2081fpstate_drop(struct thread *td) 2082{ 2083 register_t s; 2084 2085 s = intr_disable(); 2086 if (PCPU_GET(fpcurthread) == td) 2087 fpudrop(); 2088 /* 2089 * XXX force a full drop of the fpu. The above only drops it if we 2090 * owned it. 2091 * 2092 * XXX I don't much like fpugetregs()'s semantics of doing a full 2093 * drop. Dropping only to the pcb matches fnsave's behaviour. 2094 * We only need to drop to !PCB_INITDONE in sendsig(). But 2095 * sendsig() is the only caller of fpugetregs()... perhaps we just 2096 * have too many layers. 2097 */ 2098 curthread->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 2099 intr_restore(s); 2100} 2101 2102int 2103fill_dbregs(struct thread *td, struct dbreg *dbregs) 2104{ 2105 struct pcb *pcb; 2106 2107 if (td == NULL) { 2108 dbregs->dr[0] = rdr0(); 2109 dbregs->dr[1] = rdr1(); 2110 dbregs->dr[2] = rdr2(); 2111 dbregs->dr[3] = rdr3(); 2112 dbregs->dr[6] = rdr6(); 2113 dbregs->dr[7] = rdr7(); 2114 } else { 2115 pcb = td->td_pcb; 2116 dbregs->dr[0] = pcb->pcb_dr0; 2117 dbregs->dr[1] = pcb->pcb_dr1; 2118 dbregs->dr[2] = pcb->pcb_dr2; 2119 dbregs->dr[3] = pcb->pcb_dr3; 2120 dbregs->dr[6] = pcb->pcb_dr6; 2121 dbregs->dr[7] = pcb->pcb_dr7; 2122 } 2123 dbregs->dr[4] = 0; 2124 dbregs->dr[5] = 0; 2125 dbregs->dr[8] = 0; 2126 dbregs->dr[9] = 0; 2127 dbregs->dr[10] = 0; 2128 dbregs->dr[11] = 0; 2129 dbregs->dr[12] = 0; 2130 dbregs->dr[13] = 0; 2131 dbregs->dr[14] = 0; 2132 dbregs->dr[15] = 0; 2133 return (0); 2134} 2135 2136int 2137set_dbregs(struct thread *td, struct dbreg *dbregs) 2138{ 2139 struct pcb *pcb; 2140 int i; 2141 2142 if (td == NULL) { 2143 load_dr0(dbregs->dr[0]); 2144 load_dr1(dbregs->dr[1]); 2145 load_dr2(dbregs->dr[2]); 2146 load_dr3(dbregs->dr[3]); 2147 load_dr6(dbregs->dr[6]); 2148 load_dr7(dbregs->dr[7]); 2149 } else { 2150 /* 2151 * Don't let an illegal value for dr7 get set. Specifically, 2152 * check for undefined settings. Setting these bit patterns 2153 * result in undefined behaviour and can lead to an unexpected 2154 * TRCTRAP or a general protection fault right here. 2155 * Upper bits of dr6 and dr7 must not be set 2156 */ 2157 for (i = 0; i < 4; i++) { 2158 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2159 return (EINVAL); 2160 if (td->td_frame->tf_cs == _ucode32sel && 2161 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2162 return (EINVAL); 2163 } 2164 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2165 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2166 return (EINVAL); 2167 2168 pcb = td->td_pcb; 2169 2170 /* 2171 * Don't let a process set a breakpoint that is not within the 2172 * process's address space. If a process could do this, it 2173 * could halt the system by setting a breakpoint in the kernel 2174 * (if ddb was enabled). Thus, we need to check to make sure 2175 * that no breakpoints are being enabled for addresses outside 2176 * process's address space. 2177 * 2178 * XXX - what about when the watched area of the user's 2179 * address space is written into from within the kernel 2180 * ... wouldn't that still cause a breakpoint to be generated 2181 * from within kernel mode? 2182 */ 2183 2184 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2185 /* dr0 is enabled */ 2186 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2187 return (EINVAL); 2188 } 2189 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2190 /* dr1 is enabled */ 2191 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2192 return (EINVAL); 2193 } 2194 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2195 /* dr2 is enabled */ 2196 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2197 return (EINVAL); 2198 } 2199 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2200 /* dr3 is enabled */ 2201 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2202 return (EINVAL); 2203 } 2204 2205 pcb->pcb_dr0 = dbregs->dr[0]; 2206 pcb->pcb_dr1 = dbregs->dr[1]; 2207 pcb->pcb_dr2 = dbregs->dr[2]; 2208 pcb->pcb_dr3 = dbregs->dr[3]; 2209 pcb->pcb_dr6 = dbregs->dr[6]; 2210 pcb->pcb_dr7 = dbregs->dr[7]; 2211 2212 pcb->pcb_flags |= PCB_DBREGS; 2213 } 2214 2215 return (0); 2216} 2217 2218void 2219reset_dbregs(void) 2220{ 2221 2222 load_dr7(0); /* Turn off the control bits first */ 2223 load_dr0(0); 2224 load_dr1(0); 2225 load_dr2(0); 2226 load_dr3(0); 2227 load_dr6(0); 2228} 2229 2230/* 2231 * Return > 0 if a hardware breakpoint has been hit, and the 2232 * breakpoint was in user space. Return 0, otherwise. 2233 */ 2234int 2235user_dbreg_trap(void) 2236{ 2237 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2238 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2239 int nbp; /* number of breakpoints that triggered */ 2240 caddr_t addr[4]; /* breakpoint addresses */ 2241 int i; 2242 2243 dr7 = rdr7(); 2244 if ((dr7 & 0x000000ff) == 0) { 2245 /* 2246 * all GE and LE bits in the dr7 register are zero, 2247 * thus the trap couldn't have been caused by the 2248 * hardware debug registers 2249 */ 2250 return 0; 2251 } 2252 2253 nbp = 0; 2254 dr6 = rdr6(); 2255 bp = dr6 & 0x0000000f; 2256 2257 if (!bp) { 2258 /* 2259 * None of the breakpoint bits are set meaning this 2260 * trap was not caused by any of the debug registers 2261 */ 2262 return 0; 2263 } 2264 2265 /* 2266 * at least one of the breakpoints were hit, check to see 2267 * which ones and if any of them are user space addresses 2268 */ 2269 2270 if (bp & 0x01) { 2271 addr[nbp++] = (caddr_t)rdr0(); 2272 } 2273 if (bp & 0x02) { 2274 addr[nbp++] = (caddr_t)rdr1(); 2275 } 2276 if (bp & 0x04) { 2277 addr[nbp++] = (caddr_t)rdr2(); 2278 } 2279 if (bp & 0x08) { 2280 addr[nbp++] = (caddr_t)rdr3(); 2281 } 2282 2283 for (i = 0; i < nbp; i++) { 2284 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2285 /* 2286 * addr[i] is in user space 2287 */ 2288 return nbp; 2289 } 2290 } 2291 2292 /* 2293 * None of the breakpoints are in user space. 2294 */ 2295 return 0; 2296} 2297 2298#ifdef KDB 2299 2300/* 2301 * Provide inb() and outb() as functions. They are normally only available as 2302 * inline functions, thus cannot be called from the debugger. 2303 */ 2304 2305/* silence compiler warnings */ 2306u_char inb_(u_short); 2307void outb_(u_short, u_char); 2308 2309u_char 2310inb_(u_short port) 2311{ 2312 return inb(port); 2313} 2314 2315void 2316outb_(u_short port, u_char data) 2317{ 2318 outb(port, data); 2319} 2320 2321#endif /* KDB */ 2322