machdep.c revision 195907
1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/amd64/amd64/machdep.c 195907 2009-07-27 13:51:55Z rpaulo $"); 43 44#include "opt_atalk.h" 45#include "opt_atpic.h" 46#include "opt_compat.h" 47#include "opt_cpu.h" 48#include "opt_ddb.h" 49#include "opt_inet.h" 50#include "opt_ipx.h" 51#include "opt_isa.h" 52#include "opt_kstack_pages.h" 53#include "opt_maxmem.h" 54#include "opt_msgbuf.h" 55#include "opt_perfmon.h" 56#include "opt_sched.h" 57 58#include <sys/param.h> 59#include <sys/proc.h> 60#include <sys/systm.h> 61#include <sys/bio.h> 62#include <sys/buf.h> 63#include <sys/bus.h> 64#include <sys/callout.h> 65#include <sys/cons.h> 66#include <sys/cpu.h> 67#include <sys/eventhandler.h> 68#include <sys/exec.h> 69#include <sys/imgact.h> 70#include <sys/kdb.h> 71#include <sys/kernel.h> 72#include <sys/ktr.h> 73#include <sys/linker.h> 74#include <sys/lock.h> 75#include <sys/malloc.h> 76#include <sys/memrange.h> 77#include <sys/msgbuf.h> 78#include <sys/mutex.h> 79#include <sys/pcpu.h> 80#include <sys/ptrace.h> 81#include <sys/reboot.h> 82#include <sys/sched.h> 83#include <sys/signalvar.h> 84#include <sys/sysctl.h> 85#include <sys/sysent.h> 86#include <sys/sysproto.h> 87#include <sys/ucontext.h> 88#include <sys/vmmeter.h> 89 90#include <vm/vm.h> 91#include <vm/vm_extern.h> 92#include <vm/vm_kern.h> 93#include <vm/vm_page.h> 94#include <vm/vm_map.h> 95#include <vm/vm_object.h> 96#include <vm/vm_pager.h> 97#include <vm/vm_param.h> 98 99#ifdef DDB 100#ifndef KDB 101#error KDB must be enabled in order for DDB to work! 102#endif 103#include <ddb/ddb.h> 104#include <ddb/db_sym.h> 105#endif 106 107#include <net/netisr.h> 108 109#include <machine/clock.h> 110#include <machine/cpu.h> 111#include <machine/cputypes.h> 112#include <machine/intr_machdep.h> 113#include <machine/mca.h> 114#include <machine/md_var.h> 115#include <machine/metadata.h> 116#include <machine/pc/bios.h> 117#include <machine/pcb.h> 118#include <machine/proc.h> 119#include <machine/reg.h> 120#include <machine/sigframe.h> 121#include <machine/specialreg.h> 122#ifdef PERFMON 123#include <machine/perfmon.h> 124#endif 125#include <machine/tss.h> 126#ifdef SMP 127#include <machine/smp.h> 128#endif 129 130#ifdef DEV_ATPIC 131#include <amd64/isa/icu.h> 132#else 133#include <machine/apicvar.h> 134#endif 135 136#include <isa/isareg.h> 137#include <isa/rtc.h> 138 139/* Sanity check for __curthread() */ 140CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 141 142extern u_int64_t hammer_time(u_int64_t, u_int64_t); 143 144extern void printcpuinfo(void); /* XXX header file */ 145extern void identify_cpu(void); 146extern void panicifcpuunsupported(void); 147 148#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 149#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 150 151static void cpu_startup(void *); 152static void get_fpcontext(struct thread *td, mcontext_t *mcp); 153static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 154SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 155 156#ifdef DDB 157extern vm_offset_t ksym_start, ksym_end; 158#endif 159 160/* Intel ICH registers */ 161#define ICH_PMBASE 0x400 162#define ICH_SMI_EN ICH_PMBASE + 0x30 163 164int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 165 166int cold = 1; 167 168long Maxmem = 0; 169long realmem = 0; 170 171/* 172 * The number of PHYSMAP entries must be one less than the number of 173 * PHYSSEG entries because the PHYSMAP entry that spans the largest 174 * physical address that is accessible by ISA DMA is split into two 175 * PHYSSEG entries. 176 */ 177#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 178 179vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 180vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 181 182/* must be 2 less so 0 0 can signal end of chunks */ 183#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 184#define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 185 186struct kva_md_info kmi; 187 188static struct trapframe proc0_tf; 189struct region_descriptor r_gdt, r_idt; 190 191struct pcpu __pcpu[MAXCPU]; 192 193struct mtx icu_lock; 194 195struct mem_range_softc mem_range_softc; 196 197struct mtx dt_lock; /* lock for GDT and LDT */ 198 199static void 200cpu_startup(dummy) 201 void *dummy; 202{ 203 uintmax_t memsize; 204 char *sysenv; 205 206 /* 207 * On MacBooks, we need to disallow the legacy USB circuit to 208 * generate an SMI# because this can cause several problems, 209 * namely: incorrect CPU frequency detection and failure to 210 * start the APs. 211 * We do this by disabling a bit in the SMI_EN (SMI Control and 212 * Enable register) of the Intel ICH LPC Interface Bridge. 213 */ 214 sysenv = getenv("smbios.system.product"); 215 if (sysenv != NULL) { 216 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 217 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 218 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 219 strncmp(sysenv, "Macmini1,1", 10) == 0) { 220 if (bootverbose) 221 printf("Disabling LEGACY_USB_EN bit on " 222 "Intel ICH.\n"); 223 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 224 } 225 freeenv(sysenv); 226 } 227 228 /* 229 * Good {morning,afternoon,evening,night}. 230 */ 231 startrtclock(); 232 printcpuinfo(); 233 panicifcpuunsupported(); 234#ifdef PERFMON 235 perfmon_init(); 236#endif 237 sysenv = getenv("smbios.memory.enabled"); 238 if (sysenv != NULL) { 239 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10); 240 freeenv(sysenv); 241 } else 242 memsize = 0; 243 if (memsize > 0) 244 printf("real memory = %ju (%ju MB)\n", memsize << 10, 245 memsize >> 10); 246 else 247 printf("real memory = %ju (%ju MB)\n", ptoa((uintmax_t)Maxmem), 248 ptoa((uintmax_t)Maxmem) / 1048576); 249 realmem = Maxmem; 250 /* 251 * Display any holes after the first chunk of extended memory. 252 */ 253 if (bootverbose) { 254 int indx; 255 256 printf("Physical memory chunk(s):\n"); 257 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 258 vm_paddr_t size; 259 260 size = phys_avail[indx + 1] - phys_avail[indx]; 261 printf( 262 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 263 (uintmax_t)phys_avail[indx], 264 (uintmax_t)phys_avail[indx + 1] - 1, 265 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 266 } 267 } 268 269 vm_ksubmap_init(&kmi); 270 271 printf("avail memory = %ju (%ju MB)\n", 272 ptoa((uintmax_t)cnt.v_free_count), 273 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 274 275 /* 276 * Set up buffers, so they can be used to read disk labels. 277 */ 278 bufinit(); 279 vm_pager_bufferinit(); 280 281 cpu_setregs(); 282 mca_init(); 283} 284 285/* 286 * Send an interrupt to process. 287 * 288 * Stack is set up to allow sigcode stored 289 * at top to call routine, followed by call 290 * to sigreturn routine below. After sigreturn 291 * resets the signal mask, the stack, and the 292 * frame pointer, it returns to the user 293 * specified pc, psl. 294 */ 295void 296sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 297{ 298 struct sigframe sf, *sfp; 299 struct proc *p; 300 struct thread *td; 301 struct sigacts *psp; 302 char *sp; 303 struct trapframe *regs; 304 int sig; 305 int oonstack; 306 307 td = curthread; 308 p = td->td_proc; 309 PROC_LOCK_ASSERT(p, MA_OWNED); 310 sig = ksi->ksi_signo; 311 psp = p->p_sigacts; 312 mtx_assert(&psp->ps_mtx, MA_OWNED); 313 regs = td->td_frame; 314 oonstack = sigonstack(regs->tf_rsp); 315 316 /* Save user context. */ 317 bzero(&sf, sizeof(sf)); 318 sf.sf_uc.uc_sigmask = *mask; 319 sf.sf_uc.uc_stack = td->td_sigstk; 320 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 321 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 322 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 323 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 324 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 325 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 326 fpstate_drop(td); 327 sf.sf_uc.uc_mcontext.mc_fsbase = td->td_pcb->pcb_fsbase; 328 sf.sf_uc.uc_mcontext.mc_gsbase = td->td_pcb->pcb_gsbase; 329 330 /* Allocate space for the signal handler context. */ 331 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 332 SIGISMEMBER(psp->ps_sigonstack, sig)) { 333 sp = td->td_sigstk.ss_sp + 334 td->td_sigstk.ss_size - sizeof(struct sigframe); 335#if defined(COMPAT_43) 336 td->td_sigstk.ss_flags |= SS_ONSTACK; 337#endif 338 } else 339 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 340 /* Align to 16 bytes. */ 341 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 342 343 /* Translate the signal if appropriate. */ 344 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 345 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 346 347 /* Build the argument list for the signal handler. */ 348 regs->tf_rdi = sig; /* arg 1 in %rdi */ 349 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 350 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 351 /* Signal handler installed with SA_SIGINFO. */ 352 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 353 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 354 355 /* Fill in POSIX parts */ 356 sf.sf_si = ksi->ksi_info; 357 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 358 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 359 } else { 360 /* Old FreeBSD-style arguments. */ 361 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 362 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 363 sf.sf_ahu.sf_handler = catcher; 364 } 365 mtx_unlock(&psp->ps_mtx); 366 PROC_UNLOCK(p); 367 368 /* 369 * Copy the sigframe out to the user's stack. 370 */ 371 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 372#ifdef DEBUG 373 printf("process %ld has trashed its stack\n", (long)p->p_pid); 374#endif 375 PROC_LOCK(p); 376 sigexit(td, SIGILL); 377 } 378 379 regs->tf_rsp = (long)sfp; 380 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 381 regs->tf_rflags &= ~(PSL_T | PSL_D); 382 regs->tf_cs = _ucodesel; 383 regs->tf_ds = _udatasel; 384 regs->tf_es = _udatasel; 385 regs->tf_fs = _ufssel; 386 regs->tf_gs = _ugssel; 387 regs->tf_flags = TF_HASSEGS; 388 td->td_pcb->pcb_full_iret = 1; 389 PROC_LOCK(p); 390 mtx_lock(&psp->ps_mtx); 391} 392 393/* 394 * System call to cleanup state after a signal 395 * has been taken. Reset signal mask and 396 * stack state from context left by sendsig (above). 397 * Return to previous pc and psl as specified by 398 * context left by sendsig. Check carefully to 399 * make sure that the user has not modified the 400 * state to gain improper privileges. 401 * 402 * MPSAFE 403 */ 404int 405sigreturn(td, uap) 406 struct thread *td; 407 struct sigreturn_args /* { 408 const struct __ucontext *sigcntxp; 409 } */ *uap; 410{ 411 ucontext_t uc; 412 struct proc *p = td->td_proc; 413 struct trapframe *regs; 414 const ucontext_t *ucp; 415 long rflags; 416 int cs, error, ret; 417 ksiginfo_t ksi; 418 419 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 420 if (error != 0) { 421 printf("sigreturn (pid %d): copyin failed\n", p->p_pid); 422 return (error); 423 } 424 ucp = &uc; 425 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 426 printf("sigreturn (pid %d): mc_flags %x\n", p->p_pid, 427 ucp->uc_mcontext.mc_flags); 428 return (EINVAL); 429 } 430 regs = td->td_frame; 431 rflags = ucp->uc_mcontext.mc_rflags; 432 /* 433 * Don't allow users to change privileged or reserved flags. 434 */ 435 /* 436 * XXX do allow users to change the privileged flag PSL_RF. 437 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 438 * should sometimes set it there too. tf_rflags is kept in 439 * the signal context during signal handling and there is no 440 * other place to remember it, so the PSL_RF bit may be 441 * corrupted by the signal handler without us knowing. 442 * Corruption of the PSL_RF bit at worst causes one more or 443 * one less debugger trap, so allowing it is fairly harmless. 444 */ 445 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 446 printf("sigreturn (pid %d): rflags = 0x%lx\n", p->p_pid, 447 rflags); 448 return (EINVAL); 449 } 450 451 /* 452 * Don't allow users to load a valid privileged %cs. Let the 453 * hardware check for invalid selectors, excess privilege in 454 * other selectors, invalid %eip's and invalid %esp's. 455 */ 456 cs = ucp->uc_mcontext.mc_cs; 457 if (!CS_SECURE(cs)) { 458 printf("sigreturn (pid %d): cs = 0x%x\n", p->p_pid, cs); 459 ksiginfo_init_trap(&ksi); 460 ksi.ksi_signo = SIGBUS; 461 ksi.ksi_code = BUS_OBJERR; 462 ksi.ksi_trapno = T_PROTFLT; 463 ksi.ksi_addr = (void *)regs->tf_rip; 464 trapsignal(td, &ksi); 465 return (EINVAL); 466 } 467 468 ret = set_fpcontext(td, &ucp->uc_mcontext); 469 if (ret != 0) { 470 printf("sigreturn (pid %d): set_fpcontext\n", p->p_pid); 471 return (ret); 472 } 473 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 474 td->td_pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 475 td->td_pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 476 477 PROC_LOCK(p); 478#if defined(COMPAT_43) 479 if (ucp->uc_mcontext.mc_onstack & 1) 480 td->td_sigstk.ss_flags |= SS_ONSTACK; 481 else 482 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 483#endif 484 485 td->td_sigmask = ucp->uc_sigmask; 486 SIG_CANTMASK(td->td_sigmask); 487 signotify(td); 488 PROC_UNLOCK(p); 489 td->td_pcb->pcb_flags |= PCB_FULLCTX; 490 td->td_pcb->pcb_full_iret = 1; 491 return (EJUSTRETURN); 492} 493 494#ifdef COMPAT_FREEBSD4 495int 496freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 497{ 498 499 return sigreturn(td, (struct sigreturn_args *)uap); 500} 501#endif 502 503 504/* 505 * Machine dependent boot() routine 506 * 507 * I haven't seen anything to put here yet 508 * Possibly some stuff might be grafted back here from boot() 509 */ 510void 511cpu_boot(int howto) 512{ 513} 514 515/* 516 * Flush the D-cache for non-DMA I/O so that the I-cache can 517 * be made coherent later. 518 */ 519void 520cpu_flush_dcache(void *ptr, size_t len) 521{ 522 /* Not applicable */ 523} 524 525/* Get current clock frequency for the given cpu id. */ 526int 527cpu_est_clockrate(int cpu_id, uint64_t *rate) 528{ 529 register_t reg; 530 uint64_t tsc1, tsc2; 531 532 if (pcpu_find(cpu_id) == NULL || rate == NULL) 533 return (EINVAL); 534 535 /* If we're booting, trust the rate calibrated moments ago. */ 536 if (cold) { 537 *rate = tsc_freq; 538 return (0); 539 } 540 541#ifdef SMP 542 /* Schedule ourselves on the indicated cpu. */ 543 thread_lock(curthread); 544 sched_bind(curthread, cpu_id); 545 thread_unlock(curthread); 546#endif 547 548 /* Calibrate by measuring a short delay. */ 549 reg = intr_disable(); 550 tsc1 = rdtsc(); 551 DELAY(1000); 552 tsc2 = rdtsc(); 553 intr_restore(reg); 554 555#ifdef SMP 556 thread_lock(curthread); 557 sched_unbind(curthread); 558 thread_unlock(curthread); 559#endif 560 561 /* 562 * Calculate the difference in readings, convert to Mhz, and 563 * subtract 0.5% of the total. Empirical testing has shown that 564 * overhead in DELAY() works out to approximately this value. 565 */ 566 tsc2 -= tsc1; 567 *rate = tsc2 * 1000 - tsc2 * 5; 568 return (0); 569} 570 571/* 572 * Shutdown the CPU as much as possible 573 */ 574void 575cpu_halt(void) 576{ 577 for (;;) 578 __asm__ ("hlt"); 579} 580 581void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 582 583static void 584cpu_idle_hlt(int busy) 585{ 586 /* 587 * we must absolutely guarentee that hlt is the next instruction 588 * after sti or we introduce a timing window. 589 */ 590 disable_intr(); 591 if (sched_runnable()) 592 enable_intr(); 593 else 594 __asm __volatile("sti; hlt"); 595} 596 597static void 598cpu_idle_acpi(int busy) 599{ 600 disable_intr(); 601 if (sched_runnable()) 602 enable_intr(); 603 else if (cpu_idle_hook) 604 cpu_idle_hook(); 605 else 606 __asm __volatile("sti; hlt"); 607} 608 609static int cpu_ident_amdc1e = 0; 610 611static int 612cpu_probe_amdc1e(void) 613{ 614 int i; 615 616 /* 617 * Forget it, if we're not using local APIC timer. 618 */ 619 if (resource_disabled("apic", 0) || 620 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) 621 return (0); 622 623 /* 624 * Detect the presence of C1E capability mostly on latest 625 * dual-cores (or future) k8 family. 626 */ 627 if (cpu_vendor_id == CPU_VENDOR_AMD && 628 (cpu_id & 0x00000f00) == 0x00000f00 && 629 (cpu_id & 0x0fff0000) >= 0x00040000) { 630 cpu_ident_amdc1e = 1; 631 return (1); 632 } 633 634 return (0); 635} 636 637/* 638 * C1E renders the local APIC timer dead, so we disable it by 639 * reading the Interrupt Pending Message register and clearing 640 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 641 * 642 * Reference: 643 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 644 * #32559 revision 3.00+ 645 */ 646#define MSR_AMDK8_IPM 0xc0010055 647#define AMDK8_SMIONCMPHALT (1ULL << 27) 648#define AMDK8_C1EONCMPHALT (1ULL << 28) 649#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 650 651static void 652cpu_idle_amdc1e(int busy) 653{ 654 655 disable_intr(); 656 if (sched_runnable()) 657 enable_intr(); 658 else { 659 uint64_t msr; 660 661 msr = rdmsr(MSR_AMDK8_IPM); 662 if (msr & AMDK8_CMPHALT) 663 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 664 665 if (cpu_idle_hook) 666 cpu_idle_hook(); 667 else 668 __asm __volatile("sti; hlt"); 669 } 670} 671 672static void 673cpu_idle_spin(int busy) 674{ 675 return; 676} 677 678void (*cpu_idle_fn)(int) = cpu_idle_acpi; 679 680void 681cpu_idle(int busy) 682{ 683#ifdef SMP 684 if (mp_grab_cpu_hlt()) 685 return; 686#endif 687 cpu_idle_fn(busy); 688} 689 690/* 691 * mwait cpu power states. Lower 4 bits are sub-states. 692 */ 693#define MWAIT_C0 0xf0 694#define MWAIT_C1 0x00 695#define MWAIT_C2 0x10 696#define MWAIT_C3 0x20 697#define MWAIT_C4 0x30 698 699#define MWAIT_DISABLED 0x0 700#define MWAIT_WOKEN 0x1 701#define MWAIT_WAITING 0x2 702 703static void 704cpu_idle_mwait(int busy) 705{ 706 int *mwait; 707 708 mwait = (int *)PCPU_PTR(monitorbuf); 709 *mwait = MWAIT_WAITING; 710 if (sched_runnable()) 711 return; 712 cpu_monitor(mwait, 0, 0); 713 if (*mwait == MWAIT_WAITING) 714 cpu_mwait(0, MWAIT_C1); 715} 716 717static void 718cpu_idle_mwait_hlt(int busy) 719{ 720 int *mwait; 721 722 mwait = (int *)PCPU_PTR(monitorbuf); 723 if (busy == 0) { 724 *mwait = MWAIT_DISABLED; 725 cpu_idle_hlt(busy); 726 return; 727 } 728 *mwait = MWAIT_WAITING; 729 if (sched_runnable()) 730 return; 731 cpu_monitor(mwait, 0, 0); 732 if (*mwait == MWAIT_WAITING) 733 cpu_mwait(0, MWAIT_C1); 734} 735 736int 737cpu_idle_wakeup(int cpu) 738{ 739 struct pcpu *pcpu; 740 int *mwait; 741 742 if (cpu_idle_fn == cpu_idle_spin) 743 return (1); 744 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt) 745 return (0); 746 pcpu = pcpu_find(cpu); 747 mwait = (int *)pcpu->pc_monitorbuf; 748 /* 749 * This doesn't need to be atomic since missing the race will 750 * simply result in unnecessary IPIs. 751 */ 752 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED) 753 return (0); 754 *mwait = MWAIT_WOKEN; 755 756 return (1); 757} 758 759/* 760 * Ordered by speed/power consumption. 761 */ 762struct { 763 void *id_fn; 764 char *id_name; 765} idle_tbl[] = { 766 { cpu_idle_spin, "spin" }, 767 { cpu_idle_mwait, "mwait" }, 768 { cpu_idle_mwait_hlt, "mwait_hlt" }, 769 { cpu_idle_amdc1e, "amdc1e" }, 770 { cpu_idle_hlt, "hlt" }, 771 { cpu_idle_acpi, "acpi" }, 772 { NULL, NULL } 773}; 774 775static int 776idle_sysctl_available(SYSCTL_HANDLER_ARGS) 777{ 778 char *avail, *p; 779 int error; 780 int i; 781 782 avail = malloc(256, M_TEMP, M_WAITOK); 783 p = avail; 784 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 785 if (strstr(idle_tbl[i].id_name, "mwait") && 786 (cpu_feature2 & CPUID2_MON) == 0) 787 continue; 788 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 789 cpu_ident_amdc1e == 0) 790 continue; 791 p += sprintf(p, "%s, ", idle_tbl[i].id_name); 792 } 793 error = sysctl_handle_string(oidp, avail, 0, req); 794 free(avail, M_TEMP); 795 return (error); 796} 797 798static int 799idle_sysctl(SYSCTL_HANDLER_ARGS) 800{ 801 char buf[16]; 802 int error; 803 char *p; 804 int i; 805 806 p = "unknown"; 807 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 808 if (idle_tbl[i].id_fn == cpu_idle_fn) { 809 p = idle_tbl[i].id_name; 810 break; 811 } 812 } 813 strncpy(buf, p, sizeof(buf)); 814 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 815 if (error != 0 || req->newptr == NULL) 816 return (error); 817 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 818 if (strstr(idle_tbl[i].id_name, "mwait") && 819 (cpu_feature2 & CPUID2_MON) == 0) 820 continue; 821 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 822 cpu_ident_amdc1e == 0) 823 continue; 824 if (strcmp(idle_tbl[i].id_name, buf)) 825 continue; 826 cpu_idle_fn = idle_tbl[i].id_fn; 827 return (0); 828 } 829 return (EINVAL); 830} 831 832SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 833 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 834 835SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 836 idle_sysctl, "A", "currently selected idle function"); 837 838/* 839 * Reset registers to default values on exec. 840 */ 841void 842exec_setregs(td, entry, stack, ps_strings) 843 struct thread *td; 844 u_long entry; 845 u_long stack; 846 u_long ps_strings; 847{ 848 struct trapframe *regs = td->td_frame; 849 struct pcb *pcb = td->td_pcb; 850 851 mtx_lock(&dt_lock); 852 if (td->td_proc->p_md.md_ldt != NULL) 853 user_ldt_free(td); 854 else 855 mtx_unlock(&dt_lock); 856 857 pcb->pcb_fsbase = 0; 858 pcb->pcb_gsbase = 0; 859 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 860 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 861 pcb->pcb_full_iret = 1; 862 863 bzero((char *)regs, sizeof(struct trapframe)); 864 regs->tf_rip = entry; 865 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 866 regs->tf_rdi = stack; /* argv */ 867 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 868 regs->tf_ss = _udatasel; 869 regs->tf_cs = _ucodesel; 870 regs->tf_ds = _udatasel; 871 regs->tf_es = _udatasel; 872 regs->tf_fs = _ufssel; 873 regs->tf_gs = _ugssel; 874 regs->tf_flags = TF_HASSEGS; 875 876 /* 877 * Reset the hardware debug registers if they were in use. 878 * They won't have any meaning for the newly exec'd process. 879 */ 880 if (pcb->pcb_flags & PCB_DBREGS) { 881 pcb->pcb_dr0 = 0; 882 pcb->pcb_dr1 = 0; 883 pcb->pcb_dr2 = 0; 884 pcb->pcb_dr3 = 0; 885 pcb->pcb_dr6 = 0; 886 pcb->pcb_dr7 = 0; 887 if (pcb == PCPU_GET(curpcb)) { 888 /* 889 * Clear the debug registers on the running 890 * CPU, otherwise they will end up affecting 891 * the next process we switch to. 892 */ 893 reset_dbregs(); 894 } 895 pcb->pcb_flags &= ~PCB_DBREGS; 896 } 897 898 /* 899 * Drop the FP state if we hold it, so that the process gets a 900 * clean FP state if it uses the FPU again. 901 */ 902 fpstate_drop(td); 903} 904 905void 906cpu_setregs(void) 907{ 908 register_t cr0; 909 910 cr0 = rcr0(); 911 /* 912 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 913 * BSP. See the comments there about why we set them. 914 */ 915 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 916 load_cr0(cr0); 917} 918 919/* 920 * Initialize amd64 and configure to run kernel 921 */ 922 923/* 924 * Initialize segments & interrupt table 925 */ 926 927struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 928static struct gate_descriptor idt0[NIDT]; 929struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 930 931static char dblfault_stack[PAGE_SIZE] __aligned(16); 932 933static char nmi0_stack[PAGE_SIZE] __aligned(16); 934CTASSERT(sizeof(struct nmi_pcpu) == 16); 935 936struct amd64tss common_tss[MAXCPU]; 937 938/* 939 * Software prototypes -- in more palatable form. 940 * 941 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 942 * slots as corresponding segments for i386 kernel. 943 */ 944struct soft_segment_descriptor gdt_segs[] = { 945/* GNULL_SEL 0 Null Descriptor */ 946{ .ssd_base = 0x0, 947 .ssd_limit = 0x0, 948 .ssd_type = 0, 949 .ssd_dpl = 0, 950 .ssd_p = 0, 951 .ssd_long = 0, 952 .ssd_def32 = 0, 953 .ssd_gran = 0 }, 954/* GNULL2_SEL 1 Null Descriptor */ 955{ .ssd_base = 0x0, 956 .ssd_limit = 0x0, 957 .ssd_type = 0, 958 .ssd_dpl = 0, 959 .ssd_p = 0, 960 .ssd_long = 0, 961 .ssd_def32 = 0, 962 .ssd_gran = 0 }, 963/* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 964{ .ssd_base = 0x0, 965 .ssd_limit = 0xfffff, 966 .ssd_type = SDT_MEMRWA, 967 .ssd_dpl = SEL_UPL, 968 .ssd_p = 1, 969 .ssd_long = 0, 970 .ssd_def32 = 1, 971 .ssd_gran = 1 }, 972/* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 973{ .ssd_base = 0x0, 974 .ssd_limit = 0xfffff, 975 .ssd_type = SDT_MEMRWA, 976 .ssd_dpl = SEL_UPL, 977 .ssd_p = 1, 978 .ssd_long = 0, 979 .ssd_def32 = 1, 980 .ssd_gran = 1 }, 981/* GCODE_SEL 4 Code Descriptor for kernel */ 982{ .ssd_base = 0x0, 983 .ssd_limit = 0xfffff, 984 .ssd_type = SDT_MEMERA, 985 .ssd_dpl = SEL_KPL, 986 .ssd_p = 1, 987 .ssd_long = 1, 988 .ssd_def32 = 0, 989 .ssd_gran = 1 }, 990/* GDATA_SEL 5 Data Descriptor for kernel */ 991{ .ssd_base = 0x0, 992 .ssd_limit = 0xfffff, 993 .ssd_type = SDT_MEMRWA, 994 .ssd_dpl = SEL_KPL, 995 .ssd_p = 1, 996 .ssd_long = 1, 997 .ssd_def32 = 0, 998 .ssd_gran = 1 }, 999/* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1000{ .ssd_base = 0x0, 1001 .ssd_limit = 0xfffff, 1002 .ssd_type = SDT_MEMERA, 1003 .ssd_dpl = SEL_UPL, 1004 .ssd_p = 1, 1005 .ssd_long = 0, 1006 .ssd_def32 = 1, 1007 .ssd_gran = 1 }, 1008/* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1009{ .ssd_base = 0x0, 1010 .ssd_limit = 0xfffff, 1011 .ssd_type = SDT_MEMRWA, 1012 .ssd_dpl = SEL_UPL, 1013 .ssd_p = 1, 1014 .ssd_long = 0, 1015 .ssd_def32 = 1, 1016 .ssd_gran = 1 }, 1017/* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1018{ .ssd_base = 0x0, 1019 .ssd_limit = 0xfffff, 1020 .ssd_type = SDT_MEMERA, 1021 .ssd_dpl = SEL_UPL, 1022 .ssd_p = 1, 1023 .ssd_long = 1, 1024 .ssd_def32 = 0, 1025 .ssd_gran = 1 }, 1026/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1027{ .ssd_base = 0x0, 1028 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1029 .ssd_type = SDT_SYSTSS, 1030 .ssd_dpl = SEL_KPL, 1031 .ssd_p = 1, 1032 .ssd_long = 0, 1033 .ssd_def32 = 0, 1034 .ssd_gran = 0 }, 1035/* Actually, the TSS is a system descriptor which is double size */ 1036{ .ssd_base = 0x0, 1037 .ssd_limit = 0x0, 1038 .ssd_type = 0, 1039 .ssd_dpl = 0, 1040 .ssd_p = 0, 1041 .ssd_long = 0, 1042 .ssd_def32 = 0, 1043 .ssd_gran = 0 }, 1044/* GUSERLDT_SEL 11 LDT Descriptor */ 1045{ .ssd_base = 0x0, 1046 .ssd_limit = 0x0, 1047 .ssd_type = 0, 1048 .ssd_dpl = 0, 1049 .ssd_p = 0, 1050 .ssd_long = 0, 1051 .ssd_def32 = 0, 1052 .ssd_gran = 0 }, 1053/* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1054{ .ssd_base = 0x0, 1055 .ssd_limit = 0x0, 1056 .ssd_type = 0, 1057 .ssd_dpl = 0, 1058 .ssd_p = 0, 1059 .ssd_long = 0, 1060 .ssd_def32 = 0, 1061 .ssd_gran = 0 }, 1062}; 1063 1064void 1065setidt(idx, func, typ, dpl, ist) 1066 int idx; 1067 inthand_t *func; 1068 int typ; 1069 int dpl; 1070 int ist; 1071{ 1072 struct gate_descriptor *ip; 1073 1074 ip = idt + idx; 1075 ip->gd_looffset = (uintptr_t)func; 1076 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1077 ip->gd_ist = ist; 1078 ip->gd_xx = 0; 1079 ip->gd_type = typ; 1080 ip->gd_dpl = dpl; 1081 ip->gd_p = 1; 1082 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1083} 1084 1085extern inthand_t 1086 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1087 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1088 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1089 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1090 IDTVEC(xmm), IDTVEC(dblfault), 1091 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1092 1093#ifdef DDB 1094/* 1095 * Display the index and function name of any IDT entries that don't use 1096 * the default 'rsvd' entry point. 1097 */ 1098DB_SHOW_COMMAND(idt, db_show_idt) 1099{ 1100 struct gate_descriptor *ip; 1101 int idx; 1102 uintptr_t func; 1103 1104 ip = idt; 1105 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1106 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1107 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1108 db_printf("%3d\t", idx); 1109 db_printsym(func, DB_STGY_PROC); 1110 db_printf("\n"); 1111 } 1112 ip++; 1113 } 1114} 1115#endif 1116 1117void 1118sdtossd(sd, ssd) 1119 struct user_segment_descriptor *sd; 1120 struct soft_segment_descriptor *ssd; 1121{ 1122 1123 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1124 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1125 ssd->ssd_type = sd->sd_type; 1126 ssd->ssd_dpl = sd->sd_dpl; 1127 ssd->ssd_p = sd->sd_p; 1128 ssd->ssd_long = sd->sd_long; 1129 ssd->ssd_def32 = sd->sd_def32; 1130 ssd->ssd_gran = sd->sd_gran; 1131} 1132 1133void 1134ssdtosd(ssd, sd) 1135 struct soft_segment_descriptor *ssd; 1136 struct user_segment_descriptor *sd; 1137{ 1138 1139 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1140 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1141 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1142 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1143 sd->sd_type = ssd->ssd_type; 1144 sd->sd_dpl = ssd->ssd_dpl; 1145 sd->sd_p = ssd->ssd_p; 1146 sd->sd_long = ssd->ssd_long; 1147 sd->sd_def32 = ssd->ssd_def32; 1148 sd->sd_gran = ssd->ssd_gran; 1149} 1150 1151void 1152ssdtosyssd(ssd, sd) 1153 struct soft_segment_descriptor *ssd; 1154 struct system_segment_descriptor *sd; 1155{ 1156 1157 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1158 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1159 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1160 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1161 sd->sd_type = ssd->ssd_type; 1162 sd->sd_dpl = ssd->ssd_dpl; 1163 sd->sd_p = ssd->ssd_p; 1164 sd->sd_gran = ssd->ssd_gran; 1165} 1166 1167#if !defined(DEV_ATPIC) && defined(DEV_ISA) 1168#include <isa/isavar.h> 1169#include <isa/isareg.h> 1170/* 1171 * Return a bitmap of the current interrupt requests. This is 8259-specific 1172 * and is only suitable for use at probe time. 1173 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1174 * It shouldn't be here. There should probably be an APIC centric 1175 * implementation in the apic driver code, if at all. 1176 */ 1177intrmask_t 1178isa_irq_pending(void) 1179{ 1180 u_char irr1; 1181 u_char irr2; 1182 1183 irr1 = inb(IO_ICU1); 1184 irr2 = inb(IO_ICU2); 1185 return ((irr2 << 8) | irr1); 1186} 1187#endif 1188 1189u_int basemem; 1190 1191/* 1192 * Populate the (physmap) array with base/bound pairs describing the 1193 * available physical memory in the system, then test this memory and 1194 * build the phys_avail array describing the actually-available memory. 1195 * 1196 * If we cannot accurately determine the physical memory map, then use 1197 * value from the 0xE801 call, and failing that, the RTC. 1198 * 1199 * Total memory size may be set by the kernel environment variable 1200 * hw.physmem or the compile-time define MAXMEM. 1201 * 1202 * XXX first should be vm_paddr_t. 1203 */ 1204static void 1205getmemsize(caddr_t kmdp, u_int64_t first) 1206{ 1207 int i, off, physmap_idx, pa_indx, da_indx; 1208 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1209 u_long physmem_tunable; 1210 pt_entry_t *pte; 1211 struct bios_smap *smapbase, *smap, *smapend; 1212 u_int32_t smapsize; 1213 quad_t dcons_addr, dcons_size; 1214 1215 bzero(physmap, sizeof(physmap)); 1216 basemem = 0; 1217 physmap_idx = 0; 1218 1219 /* 1220 * get memory map from INT 15:E820, kindly supplied by the loader. 1221 * 1222 * subr_module.c says: 1223 * "Consumer may safely assume that size value precedes data." 1224 * ie: an int32_t immediately precedes smap. 1225 */ 1226 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1227 MODINFO_METADATA | MODINFOMD_SMAP); 1228 if (smapbase == NULL) 1229 panic("No BIOS smap info from loader!"); 1230 1231 smapsize = *((u_int32_t *)smapbase - 1); 1232 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1233 1234 for (smap = smapbase; smap < smapend; smap++) { 1235 if (boothowto & RB_VERBOSE) 1236 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1237 smap->type, smap->base, smap->length); 1238 1239 if (smap->type != SMAP_TYPE_MEMORY) 1240 continue; 1241 1242 if (smap->length == 0) 1243 continue; 1244 1245 for (i = 0; i <= physmap_idx; i += 2) { 1246 if (smap->base < physmap[i + 1]) { 1247 if (boothowto & RB_VERBOSE) 1248 printf( 1249 "Overlapping or non-monotonic memory region, ignoring second region\n"); 1250 continue; 1251 } 1252 } 1253 1254 if (smap->base == physmap[physmap_idx + 1]) { 1255 physmap[physmap_idx + 1] += smap->length; 1256 continue; 1257 } 1258 1259 physmap_idx += 2; 1260 if (physmap_idx == PHYSMAP_SIZE) { 1261 printf( 1262 "Too many segments in the physical address map, giving up\n"); 1263 break; 1264 } 1265 physmap[physmap_idx] = smap->base; 1266 physmap[physmap_idx + 1] = smap->base + smap->length; 1267 } 1268 1269 /* 1270 * Find the 'base memory' segment for SMP 1271 */ 1272 basemem = 0; 1273 for (i = 0; i <= physmap_idx; i += 2) { 1274 if (physmap[i] == 0x00000000) { 1275 basemem = physmap[i + 1] / 1024; 1276 break; 1277 } 1278 } 1279 if (basemem == 0) 1280 panic("BIOS smap did not include a basemem segment!"); 1281 1282#ifdef SMP 1283 /* make hole for AP bootstrap code */ 1284 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1285#endif 1286 1287 /* 1288 * Maxmem isn't the "maximum memory", it's one larger than the 1289 * highest page of the physical address space. It should be 1290 * called something like "Maxphyspage". We may adjust this 1291 * based on ``hw.physmem'' and the results of the memory test. 1292 */ 1293 Maxmem = atop(physmap[physmap_idx + 1]); 1294 1295#ifdef MAXMEM 1296 Maxmem = MAXMEM / 4; 1297#endif 1298 1299 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1300 Maxmem = atop(physmem_tunable); 1301 1302 /* 1303 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1304 * in the system. 1305 */ 1306 if (Maxmem > atop(physmap[physmap_idx + 1])) 1307 Maxmem = atop(physmap[physmap_idx + 1]); 1308 1309 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1310 (boothowto & RB_VERBOSE)) 1311 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1312 1313 /* call pmap initialization to make new kernel address space */ 1314 pmap_bootstrap(&first); 1315 1316 /* 1317 * Size up each available chunk of physical memory. 1318 */ 1319 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1320 pa_indx = 0; 1321 da_indx = 1; 1322 phys_avail[pa_indx++] = physmap[0]; 1323 phys_avail[pa_indx] = physmap[0]; 1324 dump_avail[da_indx] = physmap[0]; 1325 pte = CMAP1; 1326 1327 /* 1328 * Get dcons buffer address 1329 */ 1330 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1331 getenv_quad("dcons.size", &dcons_size) == 0) 1332 dcons_addr = 0; 1333 1334 /* 1335 * physmap is in bytes, so when converting to page boundaries, 1336 * round up the start address and round down the end address. 1337 */ 1338 for (i = 0; i <= physmap_idx; i += 2) { 1339 vm_paddr_t end; 1340 1341 end = ptoa((vm_paddr_t)Maxmem); 1342 if (physmap[i + 1] < end) 1343 end = trunc_page(physmap[i + 1]); 1344 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1345 int tmp, page_bad, full; 1346 int *ptr = (int *)CADDR1; 1347 1348 full = FALSE; 1349 /* 1350 * block out kernel memory as not available. 1351 */ 1352 if (pa >= 0x100000 && pa < first) 1353 goto do_dump_avail; 1354 1355 /* 1356 * block out dcons buffer 1357 */ 1358 if (dcons_addr > 0 1359 && pa >= trunc_page(dcons_addr) 1360 && pa < dcons_addr + dcons_size) 1361 goto do_dump_avail; 1362 1363 page_bad = FALSE; 1364 1365 /* 1366 * map page into kernel: valid, read/write,non-cacheable 1367 */ 1368 *pte = pa | PG_V | PG_RW | PG_N; 1369 invltlb(); 1370 1371 tmp = *(int *)ptr; 1372 /* 1373 * Test for alternating 1's and 0's 1374 */ 1375 *(volatile int *)ptr = 0xaaaaaaaa; 1376 if (*(volatile int *)ptr != 0xaaaaaaaa) 1377 page_bad = TRUE; 1378 /* 1379 * Test for alternating 0's and 1's 1380 */ 1381 *(volatile int *)ptr = 0x55555555; 1382 if (*(volatile int *)ptr != 0x55555555) 1383 page_bad = TRUE; 1384 /* 1385 * Test for all 1's 1386 */ 1387 *(volatile int *)ptr = 0xffffffff; 1388 if (*(volatile int *)ptr != 0xffffffff) 1389 page_bad = TRUE; 1390 /* 1391 * Test for all 0's 1392 */ 1393 *(volatile int *)ptr = 0x0; 1394 if (*(volatile int *)ptr != 0x0) 1395 page_bad = TRUE; 1396 /* 1397 * Restore original value. 1398 */ 1399 *(int *)ptr = tmp; 1400 1401 /* 1402 * Adjust array of valid/good pages. 1403 */ 1404 if (page_bad == TRUE) 1405 continue; 1406 /* 1407 * If this good page is a continuation of the 1408 * previous set of good pages, then just increase 1409 * the end pointer. Otherwise start a new chunk. 1410 * Note that "end" points one higher than end, 1411 * making the range >= start and < end. 1412 * If we're also doing a speculative memory 1413 * test and we at or past the end, bump up Maxmem 1414 * so that we keep going. The first bad page 1415 * will terminate the loop. 1416 */ 1417 if (phys_avail[pa_indx] == pa) { 1418 phys_avail[pa_indx] += PAGE_SIZE; 1419 } else { 1420 pa_indx++; 1421 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1422 printf( 1423 "Too many holes in the physical address space, giving up\n"); 1424 pa_indx--; 1425 full = TRUE; 1426 goto do_dump_avail; 1427 } 1428 phys_avail[pa_indx++] = pa; /* start */ 1429 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1430 } 1431 physmem++; 1432do_dump_avail: 1433 if (dump_avail[da_indx] == pa) { 1434 dump_avail[da_indx] += PAGE_SIZE; 1435 } else { 1436 da_indx++; 1437 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1438 da_indx--; 1439 goto do_next; 1440 } 1441 dump_avail[da_indx++] = pa; /* start */ 1442 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1443 } 1444do_next: 1445 if (full) 1446 break; 1447 } 1448 } 1449 *pte = 0; 1450 invltlb(); 1451 1452 /* 1453 * XXX 1454 * The last chunk must contain at least one page plus the message 1455 * buffer to avoid complicating other code (message buffer address 1456 * calculation, etc.). 1457 */ 1458 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1459 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1460 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1461 phys_avail[pa_indx--] = 0; 1462 phys_avail[pa_indx--] = 0; 1463 } 1464 1465 Maxmem = atop(phys_avail[pa_indx]); 1466 1467 /* Trim off space for the message buffer. */ 1468 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1469 1470 /* Map the message buffer. */ 1471 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1472 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] + 1473 off); 1474} 1475 1476u_int64_t 1477hammer_time(u_int64_t modulep, u_int64_t physfree) 1478{ 1479 caddr_t kmdp; 1480 int gsel_tss, x; 1481 struct pcpu *pc; 1482 struct nmi_pcpu *np; 1483 u_int64_t msr; 1484 char *env; 1485 1486 thread0.td_kstack = physfree + KERNBASE; 1487 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1488 physfree += KSTACK_PAGES * PAGE_SIZE; 1489 thread0.td_pcb = (struct pcb *) 1490 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1491 1492 /* 1493 * This may be done better later if it gets more high level 1494 * components in it. If so just link td->td_proc here. 1495 */ 1496 proc_linkup0(&proc0, &thread0); 1497 1498 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1499 preload_bootstrap_relocate(KERNBASE); 1500 kmdp = preload_search_by_type("elf kernel"); 1501 if (kmdp == NULL) 1502 kmdp = preload_search_by_type("elf64 kernel"); 1503 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1504 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1505#ifdef DDB 1506 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1507 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1508#endif 1509 1510 /* Init basic tunables, hz etc */ 1511 init_param1(); 1512 1513 /* 1514 * make gdt memory segments 1515 */ 1516 for (x = 0; x < NGDT; x++) { 1517 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1518 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1519 ssdtosd(&gdt_segs[x], &gdt[x]); 1520 } 1521 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1522 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1523 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1524 1525 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1526 r_gdt.rd_base = (long) gdt; 1527 lgdt(&r_gdt); 1528 pc = &__pcpu[0]; 1529 1530 wrmsr(MSR_FSBASE, 0); /* User value */ 1531 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1532 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1533 1534 pcpu_init(pc, 0, sizeof(struct pcpu)); 1535 dpcpu_init((void *)(physfree + KERNBASE), 0); 1536 physfree += DPCPU_SIZE; 1537 PCPU_SET(prvspace, pc); 1538 PCPU_SET(curthread, &thread0); 1539 PCPU_SET(curpcb, thread0.td_pcb); 1540 PCPU_SET(tssp, &common_tss[0]); 1541 PCPU_SET(commontssp, &common_tss[0]); 1542 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1543 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1544 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1545 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1546 1547 /* 1548 * Initialize mutexes. 1549 * 1550 * icu_lock: in order to allow an interrupt to occur in a critical 1551 * section, to set pcpu->ipending (etc...) properly, we 1552 * must be able to get the icu lock, so it can't be 1553 * under witness. 1554 */ 1555 mutex_init(); 1556 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1557 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1558 1559 /* exceptions */ 1560 for (x = 0; x < NIDT; x++) 1561 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1562 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1563 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1564 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1565 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1566 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1567 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1568 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1569 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1570 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1571 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1572 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1573 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1574 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1575 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1576 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1577 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1578 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1579 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1580 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1581 1582 r_idt.rd_limit = sizeof(idt0) - 1; 1583 r_idt.rd_base = (long) idt; 1584 lidt(&r_idt); 1585 1586 /* 1587 * Initialize the i8254 before the console so that console 1588 * initialization can use DELAY(). 1589 */ 1590 i8254_init(); 1591 1592 /* 1593 * Initialize the console before we print anything out. 1594 */ 1595 cninit(); 1596 1597#ifdef DEV_ISA 1598#ifdef DEV_ATPIC 1599 elcr_probe(); 1600 atpic_startup(); 1601#else 1602 /* Reset and mask the atpics and leave them shut down. */ 1603 atpic_reset(); 1604 1605 /* 1606 * Point the ICU spurious interrupt vectors at the APIC spurious 1607 * interrupt handler. 1608 */ 1609 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1610 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1611#endif 1612#else 1613#error "have you forgotten the isa device?"; 1614#endif 1615 1616 kdb_init(); 1617 1618#ifdef KDB 1619 if (boothowto & RB_KDB) 1620 kdb_enter(KDB_WHY_BOOTFLAGS, 1621 "Boot flags requested debugger"); 1622#endif 1623 1624 identify_cpu(); /* Final stage of CPU initialization */ 1625 initializecpu(); /* Initialize CPU registers */ 1626 1627 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1628 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1629 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1630 /* Ensure the stack is aligned to 16 bytes */ 1631 common_tss[0].tss_rsp0 &= ~0xFul; 1632 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1633 1634 /* doublefault stack space, runs on ist1 */ 1635 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1636 1637 /* 1638 * NMI stack, runs on ist2. The pcpu pointer is stored just 1639 * above the start of the ist2 stack. 1640 */ 1641 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1642 np->np_pcpu = (register_t) pc; 1643 common_tss[0].tss_ist2 = (long) np; 1644 1645 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1646 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1647 IOPAGES * PAGE_SIZE; 1648 1649 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1650 ltr(gsel_tss); 1651 1652 /* Set up the fast syscall stuff */ 1653 msr = rdmsr(MSR_EFER) | EFER_SCE; 1654 wrmsr(MSR_EFER, msr); 1655 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1656 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1657 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1658 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1659 wrmsr(MSR_STAR, msr); 1660 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1661 1662 getmemsize(kmdp, physfree); 1663 init_param2(physmem); 1664 1665 /* now running on new page tables, configured,and u/iom is accessible */ 1666 1667 msgbufinit(msgbufp, MSGBUF_SIZE); 1668 fpuinit(); 1669 1670 /* transfer to user mode */ 1671 1672 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1673 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1674 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1675 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1676 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1677 1678 load_ds(_udatasel); 1679 load_es(_udatasel); 1680 load_fs(_ufssel); 1681 1682 /* setup proc 0's pcb */ 1683 thread0.td_pcb->pcb_flags = 0; 1684 thread0.td_pcb->pcb_cr3 = KPML4phys; 1685 thread0.td_frame = &proc0_tf; 1686 1687 env = getenv("kernelname"); 1688 if (env != NULL) 1689 strlcpy(kernelname, env, sizeof(kernelname)); 1690 1691#ifdef XENHVM 1692 if (inw(0x10) == 0x49d2) { 1693 if (bootverbose) 1694 printf("Xen detected: disabling emulated block and network devices\n"); 1695 outw(0x10, 3); 1696 } 1697#endif 1698 1699 if (cpu_probe_amdc1e()) 1700 cpu_idle_fn = cpu_idle_amdc1e; 1701 1702 /* Location of kernel stack for locore */ 1703 return ((u_int64_t)thread0.td_pcb); 1704} 1705 1706void 1707cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1708{ 1709 1710 pcpu->pc_acpi_id = 0xffffffff; 1711} 1712 1713void 1714spinlock_enter(void) 1715{ 1716 struct thread *td; 1717 1718 td = curthread; 1719 if (td->td_md.md_spinlock_count == 0) 1720 td->td_md.md_saved_flags = intr_disable(); 1721 td->td_md.md_spinlock_count++; 1722 critical_enter(); 1723} 1724 1725void 1726spinlock_exit(void) 1727{ 1728 struct thread *td; 1729 1730 td = curthread; 1731 critical_exit(); 1732 td->td_md.md_spinlock_count--; 1733 if (td->td_md.md_spinlock_count == 0) 1734 intr_restore(td->td_md.md_saved_flags); 1735} 1736 1737/* 1738 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1739 * we want to start a backtrace from the function that caused us to enter 1740 * the debugger. We have the context in the trapframe, but base the trace 1741 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1742 * enough for a backtrace. 1743 */ 1744void 1745makectx(struct trapframe *tf, struct pcb *pcb) 1746{ 1747 1748 pcb->pcb_r12 = tf->tf_r12; 1749 pcb->pcb_r13 = tf->tf_r13; 1750 pcb->pcb_r14 = tf->tf_r14; 1751 pcb->pcb_r15 = tf->tf_r15; 1752 pcb->pcb_rbp = tf->tf_rbp; 1753 pcb->pcb_rbx = tf->tf_rbx; 1754 pcb->pcb_rip = tf->tf_rip; 1755 pcb->pcb_rsp = (ISPL(tf->tf_cs)) ? tf->tf_rsp : (long)(tf + 1) - 8; 1756} 1757 1758int 1759ptrace_set_pc(struct thread *td, unsigned long addr) 1760{ 1761 td->td_frame->tf_rip = addr; 1762 return (0); 1763} 1764 1765int 1766ptrace_single_step(struct thread *td) 1767{ 1768 td->td_frame->tf_rflags |= PSL_T; 1769 return (0); 1770} 1771 1772int 1773ptrace_clear_single_step(struct thread *td) 1774{ 1775 td->td_frame->tf_rflags &= ~PSL_T; 1776 return (0); 1777} 1778 1779int 1780fill_regs(struct thread *td, struct reg *regs) 1781{ 1782 struct trapframe *tp; 1783 1784 tp = td->td_frame; 1785 regs->r_r15 = tp->tf_r15; 1786 regs->r_r14 = tp->tf_r14; 1787 regs->r_r13 = tp->tf_r13; 1788 regs->r_r12 = tp->tf_r12; 1789 regs->r_r11 = tp->tf_r11; 1790 regs->r_r10 = tp->tf_r10; 1791 regs->r_r9 = tp->tf_r9; 1792 regs->r_r8 = tp->tf_r8; 1793 regs->r_rdi = tp->tf_rdi; 1794 regs->r_rsi = tp->tf_rsi; 1795 regs->r_rbp = tp->tf_rbp; 1796 regs->r_rbx = tp->tf_rbx; 1797 regs->r_rdx = tp->tf_rdx; 1798 regs->r_rcx = tp->tf_rcx; 1799 regs->r_rax = tp->tf_rax; 1800 regs->r_rip = tp->tf_rip; 1801 regs->r_cs = tp->tf_cs; 1802 regs->r_rflags = tp->tf_rflags; 1803 regs->r_rsp = tp->tf_rsp; 1804 regs->r_ss = tp->tf_ss; 1805 if (tp->tf_flags & TF_HASSEGS) { 1806 regs->r_ds = tp->tf_ds; 1807 regs->r_es = tp->tf_es; 1808 regs->r_fs = tp->tf_fs; 1809 regs->r_gs = tp->tf_gs; 1810 } else { 1811 regs->r_ds = 0; 1812 regs->r_es = 0; 1813 regs->r_fs = 0; 1814 regs->r_gs = 0; 1815 } 1816 return (0); 1817} 1818 1819int 1820set_regs(struct thread *td, struct reg *regs) 1821{ 1822 struct trapframe *tp; 1823 register_t rflags; 1824 1825 tp = td->td_frame; 1826 rflags = regs->r_rflags & 0xffffffff; 1827 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1828 return (EINVAL); 1829 tp->tf_r15 = regs->r_r15; 1830 tp->tf_r14 = regs->r_r14; 1831 tp->tf_r13 = regs->r_r13; 1832 tp->tf_r12 = regs->r_r12; 1833 tp->tf_r11 = regs->r_r11; 1834 tp->tf_r10 = regs->r_r10; 1835 tp->tf_r9 = regs->r_r9; 1836 tp->tf_r8 = regs->r_r8; 1837 tp->tf_rdi = regs->r_rdi; 1838 tp->tf_rsi = regs->r_rsi; 1839 tp->tf_rbp = regs->r_rbp; 1840 tp->tf_rbx = regs->r_rbx; 1841 tp->tf_rdx = regs->r_rdx; 1842 tp->tf_rcx = regs->r_rcx; 1843 tp->tf_rax = regs->r_rax; 1844 tp->tf_rip = regs->r_rip; 1845 tp->tf_cs = regs->r_cs; 1846 tp->tf_rflags = rflags; 1847 tp->tf_rsp = regs->r_rsp; 1848 tp->tf_ss = regs->r_ss; 1849 if (0) { /* XXXKIB */ 1850 tp->tf_ds = regs->r_ds; 1851 tp->tf_es = regs->r_es; 1852 tp->tf_fs = regs->r_fs; 1853 tp->tf_gs = regs->r_gs; 1854 tp->tf_flags = TF_HASSEGS; 1855 } 1856 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1857 return (0); 1858} 1859 1860/* XXX check all this stuff! */ 1861/* externalize from sv_xmm */ 1862static void 1863fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1864{ 1865 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1866 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1867 int i; 1868 1869 /* pcb -> fpregs */ 1870 bzero(fpregs, sizeof(*fpregs)); 1871 1872 /* FPU control/status */ 1873 penv_fpreg->en_cw = penv_xmm->en_cw; 1874 penv_fpreg->en_sw = penv_xmm->en_sw; 1875 penv_fpreg->en_tw = penv_xmm->en_tw; 1876 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1877 penv_fpreg->en_rip = penv_xmm->en_rip; 1878 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1879 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1880 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1881 1882 /* FPU registers */ 1883 for (i = 0; i < 8; ++i) 1884 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1885 1886 /* SSE registers */ 1887 for (i = 0; i < 16; ++i) 1888 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1889} 1890 1891/* internalize from fpregs into sv_xmm */ 1892static void 1893set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1894{ 1895 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1896 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1897 int i; 1898 1899 /* fpregs -> pcb */ 1900 /* FPU control/status */ 1901 penv_xmm->en_cw = penv_fpreg->en_cw; 1902 penv_xmm->en_sw = penv_fpreg->en_sw; 1903 penv_xmm->en_tw = penv_fpreg->en_tw; 1904 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1905 penv_xmm->en_rip = penv_fpreg->en_rip; 1906 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1907 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1908 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1909 1910 /* FPU registers */ 1911 for (i = 0; i < 8; ++i) 1912 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1913 1914 /* SSE registers */ 1915 for (i = 0; i < 16; ++i) 1916 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1917} 1918 1919/* externalize from td->pcb */ 1920int 1921fill_fpregs(struct thread *td, struct fpreg *fpregs) 1922{ 1923 1924 fill_fpregs_xmm(&td->td_pcb->pcb_save, fpregs); 1925 return (0); 1926} 1927 1928/* internalize to td->pcb */ 1929int 1930set_fpregs(struct thread *td, struct fpreg *fpregs) 1931{ 1932 1933 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_save); 1934 return (0); 1935} 1936 1937/* 1938 * Get machine context. 1939 */ 1940int 1941get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1942{ 1943 struct trapframe *tp; 1944 1945 tp = td->td_frame; 1946 PROC_LOCK(curthread->td_proc); 1947 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1948 PROC_UNLOCK(curthread->td_proc); 1949 mcp->mc_r15 = tp->tf_r15; 1950 mcp->mc_r14 = tp->tf_r14; 1951 mcp->mc_r13 = tp->tf_r13; 1952 mcp->mc_r12 = tp->tf_r12; 1953 mcp->mc_r11 = tp->tf_r11; 1954 mcp->mc_r10 = tp->tf_r10; 1955 mcp->mc_r9 = tp->tf_r9; 1956 mcp->mc_r8 = tp->tf_r8; 1957 mcp->mc_rdi = tp->tf_rdi; 1958 mcp->mc_rsi = tp->tf_rsi; 1959 mcp->mc_rbp = tp->tf_rbp; 1960 mcp->mc_rbx = tp->tf_rbx; 1961 mcp->mc_rcx = tp->tf_rcx; 1962 mcp->mc_rflags = tp->tf_rflags; 1963 if (flags & GET_MC_CLEAR_RET) { 1964 mcp->mc_rax = 0; 1965 mcp->mc_rdx = 0; 1966 mcp->mc_rflags &= ~PSL_C; 1967 } else { 1968 mcp->mc_rax = tp->tf_rax; 1969 mcp->mc_rdx = tp->tf_rdx; 1970 } 1971 mcp->mc_rip = tp->tf_rip; 1972 mcp->mc_cs = tp->tf_cs; 1973 mcp->mc_rsp = tp->tf_rsp; 1974 mcp->mc_ss = tp->tf_ss; 1975 mcp->mc_ds = tp->tf_ds; 1976 mcp->mc_es = tp->tf_es; 1977 mcp->mc_fs = tp->tf_fs; 1978 mcp->mc_gs = tp->tf_gs; 1979 mcp->mc_flags = tp->tf_flags; 1980 mcp->mc_len = sizeof(*mcp); 1981 get_fpcontext(td, mcp); 1982 mcp->mc_fsbase = td->td_pcb->pcb_fsbase; 1983 mcp->mc_gsbase = td->td_pcb->pcb_gsbase; 1984 return (0); 1985} 1986 1987/* 1988 * Set machine context. 1989 * 1990 * However, we don't set any but the user modifiable flags, and we won't 1991 * touch the cs selector. 1992 */ 1993int 1994set_mcontext(struct thread *td, const mcontext_t *mcp) 1995{ 1996 struct trapframe *tp; 1997 long rflags; 1998 int ret; 1999 2000 tp = td->td_frame; 2001 if (mcp->mc_len != sizeof(*mcp) || 2002 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2003 return (EINVAL); 2004 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2005 (tp->tf_rflags & ~PSL_USERCHANGE); 2006 ret = set_fpcontext(td, mcp); 2007 if (ret != 0) 2008 return (ret); 2009 tp->tf_r15 = mcp->mc_r15; 2010 tp->tf_r14 = mcp->mc_r14; 2011 tp->tf_r13 = mcp->mc_r13; 2012 tp->tf_r12 = mcp->mc_r12; 2013 tp->tf_r11 = mcp->mc_r11; 2014 tp->tf_r10 = mcp->mc_r10; 2015 tp->tf_r9 = mcp->mc_r9; 2016 tp->tf_r8 = mcp->mc_r8; 2017 tp->tf_rdi = mcp->mc_rdi; 2018 tp->tf_rsi = mcp->mc_rsi; 2019 tp->tf_rbp = mcp->mc_rbp; 2020 tp->tf_rbx = mcp->mc_rbx; 2021 tp->tf_rdx = mcp->mc_rdx; 2022 tp->tf_rcx = mcp->mc_rcx; 2023 tp->tf_rax = mcp->mc_rax; 2024 tp->tf_rip = mcp->mc_rip; 2025 tp->tf_rflags = rflags; 2026 tp->tf_rsp = mcp->mc_rsp; 2027 tp->tf_ss = mcp->mc_ss; 2028 tp->tf_flags = mcp->mc_flags; 2029 if (tp->tf_flags & TF_HASSEGS) { 2030 tp->tf_ds = mcp->mc_ds; 2031 tp->tf_es = mcp->mc_es; 2032 tp->tf_fs = mcp->mc_fs; 2033 tp->tf_gs = mcp->mc_gs; 2034 } 2035 if (mcp->mc_flags & _MC_HASBASES) { 2036 td->td_pcb->pcb_fsbase = mcp->mc_fsbase; 2037 td->td_pcb->pcb_gsbase = mcp->mc_gsbase; 2038 } 2039 td->td_pcb->pcb_flags |= PCB_FULLCTX; 2040 td->td_pcb->pcb_full_iret = 1; 2041 return (0); 2042} 2043 2044static void 2045get_fpcontext(struct thread *td, mcontext_t *mcp) 2046{ 2047 2048 mcp->mc_ownedfp = fpugetregs(td, (struct savefpu *)&mcp->mc_fpstate); 2049 mcp->mc_fpformat = fpuformat(); 2050} 2051 2052static int 2053set_fpcontext(struct thread *td, const mcontext_t *mcp) 2054{ 2055 struct savefpu *fpstate; 2056 2057 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2058 return (0); 2059 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2060 return (EINVAL); 2061 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2062 /* We don't care what state is left in the FPU or PCB. */ 2063 fpstate_drop(td); 2064 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2065 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2066 /* 2067 * XXX we violate the dubious requirement that fpusetregs() 2068 * be called with interrupts disabled. 2069 * XXX obsolete on trap-16 systems? 2070 */ 2071 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2072 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2073 fpusetregs(td, fpstate); 2074 } else 2075 return (EINVAL); 2076 return (0); 2077} 2078 2079void 2080fpstate_drop(struct thread *td) 2081{ 2082 register_t s; 2083 2084 s = intr_disable(); 2085 if (PCPU_GET(fpcurthread) == td) 2086 fpudrop(); 2087 /* 2088 * XXX force a full drop of the fpu. The above only drops it if we 2089 * owned it. 2090 * 2091 * XXX I don't much like fpugetregs()'s semantics of doing a full 2092 * drop. Dropping only to the pcb matches fnsave's behaviour. 2093 * We only need to drop to !PCB_INITDONE in sendsig(). But 2094 * sendsig() is the only caller of fpugetregs()... perhaps we just 2095 * have too many layers. 2096 */ 2097 curthread->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 2098 intr_restore(s); 2099} 2100 2101int 2102fill_dbregs(struct thread *td, struct dbreg *dbregs) 2103{ 2104 struct pcb *pcb; 2105 2106 if (td == NULL) { 2107 dbregs->dr[0] = rdr0(); 2108 dbregs->dr[1] = rdr1(); 2109 dbregs->dr[2] = rdr2(); 2110 dbregs->dr[3] = rdr3(); 2111 dbregs->dr[6] = rdr6(); 2112 dbregs->dr[7] = rdr7(); 2113 } else { 2114 pcb = td->td_pcb; 2115 dbregs->dr[0] = pcb->pcb_dr0; 2116 dbregs->dr[1] = pcb->pcb_dr1; 2117 dbregs->dr[2] = pcb->pcb_dr2; 2118 dbregs->dr[3] = pcb->pcb_dr3; 2119 dbregs->dr[6] = pcb->pcb_dr6; 2120 dbregs->dr[7] = pcb->pcb_dr7; 2121 } 2122 dbregs->dr[4] = 0; 2123 dbregs->dr[5] = 0; 2124 dbregs->dr[8] = 0; 2125 dbregs->dr[9] = 0; 2126 dbregs->dr[10] = 0; 2127 dbregs->dr[11] = 0; 2128 dbregs->dr[12] = 0; 2129 dbregs->dr[13] = 0; 2130 dbregs->dr[14] = 0; 2131 dbregs->dr[15] = 0; 2132 return (0); 2133} 2134 2135int 2136set_dbregs(struct thread *td, struct dbreg *dbregs) 2137{ 2138 struct pcb *pcb; 2139 int i; 2140 2141 if (td == NULL) { 2142 load_dr0(dbregs->dr[0]); 2143 load_dr1(dbregs->dr[1]); 2144 load_dr2(dbregs->dr[2]); 2145 load_dr3(dbregs->dr[3]); 2146 load_dr6(dbregs->dr[6]); 2147 load_dr7(dbregs->dr[7]); 2148 } else { 2149 /* 2150 * Don't let an illegal value for dr7 get set. Specifically, 2151 * check for undefined settings. Setting these bit patterns 2152 * result in undefined behaviour and can lead to an unexpected 2153 * TRCTRAP or a general protection fault right here. 2154 * Upper bits of dr6 and dr7 must not be set 2155 */ 2156 for (i = 0; i < 4; i++) { 2157 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2158 return (EINVAL); 2159 if (td->td_frame->tf_cs == _ucode32sel && 2160 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2161 return (EINVAL); 2162 } 2163 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2164 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2165 return (EINVAL); 2166 2167 pcb = td->td_pcb; 2168 2169 /* 2170 * Don't let a process set a breakpoint that is not within the 2171 * process's address space. If a process could do this, it 2172 * could halt the system by setting a breakpoint in the kernel 2173 * (if ddb was enabled). Thus, we need to check to make sure 2174 * that no breakpoints are being enabled for addresses outside 2175 * process's address space. 2176 * 2177 * XXX - what about when the watched area of the user's 2178 * address space is written into from within the kernel 2179 * ... wouldn't that still cause a breakpoint to be generated 2180 * from within kernel mode? 2181 */ 2182 2183 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2184 /* dr0 is enabled */ 2185 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2186 return (EINVAL); 2187 } 2188 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2189 /* dr1 is enabled */ 2190 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2191 return (EINVAL); 2192 } 2193 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2194 /* dr2 is enabled */ 2195 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2196 return (EINVAL); 2197 } 2198 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2199 /* dr3 is enabled */ 2200 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2201 return (EINVAL); 2202 } 2203 2204 pcb->pcb_dr0 = dbregs->dr[0]; 2205 pcb->pcb_dr1 = dbregs->dr[1]; 2206 pcb->pcb_dr2 = dbregs->dr[2]; 2207 pcb->pcb_dr3 = dbregs->dr[3]; 2208 pcb->pcb_dr6 = dbregs->dr[6]; 2209 pcb->pcb_dr7 = dbregs->dr[7]; 2210 2211 pcb->pcb_flags |= PCB_DBREGS; 2212 } 2213 2214 return (0); 2215} 2216 2217void 2218reset_dbregs(void) 2219{ 2220 2221 load_dr7(0); /* Turn off the control bits first */ 2222 load_dr0(0); 2223 load_dr1(0); 2224 load_dr2(0); 2225 load_dr3(0); 2226 load_dr6(0); 2227} 2228 2229/* 2230 * Return > 0 if a hardware breakpoint has been hit, and the 2231 * breakpoint was in user space. Return 0, otherwise. 2232 */ 2233int 2234user_dbreg_trap(void) 2235{ 2236 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2237 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2238 int nbp; /* number of breakpoints that triggered */ 2239 caddr_t addr[4]; /* breakpoint addresses */ 2240 int i; 2241 2242 dr7 = rdr7(); 2243 if ((dr7 & 0x000000ff) == 0) { 2244 /* 2245 * all GE and LE bits in the dr7 register are zero, 2246 * thus the trap couldn't have been caused by the 2247 * hardware debug registers 2248 */ 2249 return 0; 2250 } 2251 2252 nbp = 0; 2253 dr6 = rdr6(); 2254 bp = dr6 & 0x0000000f; 2255 2256 if (!bp) { 2257 /* 2258 * None of the breakpoint bits are set meaning this 2259 * trap was not caused by any of the debug registers 2260 */ 2261 return 0; 2262 } 2263 2264 /* 2265 * at least one of the breakpoints were hit, check to see 2266 * which ones and if any of them are user space addresses 2267 */ 2268 2269 if (bp & 0x01) { 2270 addr[nbp++] = (caddr_t)rdr0(); 2271 } 2272 if (bp & 0x02) { 2273 addr[nbp++] = (caddr_t)rdr1(); 2274 } 2275 if (bp & 0x04) { 2276 addr[nbp++] = (caddr_t)rdr2(); 2277 } 2278 if (bp & 0x08) { 2279 addr[nbp++] = (caddr_t)rdr3(); 2280 } 2281 2282 for (i = 0; i < nbp; i++) { 2283 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2284 /* 2285 * addr[i] is in user space 2286 */ 2287 return nbp; 2288 } 2289 } 2290 2291 /* 2292 * None of the breakpoints are in user space. 2293 */ 2294 return 0; 2295} 2296 2297#ifdef KDB 2298 2299/* 2300 * Provide inb() and outb() as functions. They are normally only available as 2301 * inline functions, thus cannot be called from the debugger. 2302 */ 2303 2304/* silence compiler warnings */ 2305u_char inb_(u_short); 2306void outb_(u_short, u_char); 2307 2308u_char 2309inb_(u_short port) 2310{ 2311 return inb(port); 2312} 2313 2314void 2315outb_(u_short port, u_char data) 2316{ 2317 outb(port, data); 2318} 2319 2320#endif /* KDB */ 2321