fpu.c revision 85268
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 85268 2001-10-21 05:18:30Z bde $ 36 */ 37 38#include "opt_cpu.h" 39#include "opt_debug_npx.h" 40#include "opt_math_emulate.h" 41#include "opt_npx.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kernel.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/mutex.h> 52#include <sys/proc.h> 53#include <sys/sysctl.h> 54#include <machine/bus.h> 55#include <sys/rman.h> 56#ifdef NPX_DEBUG 57#include <sys/syslog.h> 58#endif 59#include <sys/signalvar.h> 60#include <sys/user.h> 61 62#ifndef SMP 63#include <machine/asmacros.h> 64#endif 65#include <machine/cputypes.h> 66#include <machine/frame.h> 67#include <machine/md_var.h> 68#include <machine/pcb.h> 69#include <machine/psl.h> 70#ifndef SMP 71#include <machine/clock.h> 72#endif 73#include <machine/resource.h> 74#include <machine/specialreg.h> 75#include <machine/segments.h> 76 77#ifndef SMP 78#include <i386/isa/icu.h> 79#include <i386/isa/isa.h> 80#endif 81#include <isa/isavar.h> 82 83/* 84 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 85 */ 86 87/* Configuration flags. */ 88#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 89#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 90#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 91#define NPX_PREFER_EMULATOR (1 << 3) 92 93#ifdef __GNUC__ 94 95#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 96#define fnclex() __asm("fnclex") 97#define fninit() __asm("fninit") 98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 103#ifdef CPU_ENABLE_SSE 104#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 105#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 106#endif 107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 108 : : "n" (CR0_TS) : "ax") 109#define stop_emulating() __asm("clts") 110 111#else /* not __GNUC__ */ 112 113void fldcw __P((caddr_t addr)); 114void fnclex __P((void)); 115void fninit __P((void)); 116void fnsave __P((caddr_t addr)); 117void fnstcw __P((caddr_t addr)); 118void fnstsw __P((caddr_t addr)); 119void fp_divide_by_0 __P((void)); 120void frstor __P((caddr_t addr)); 121#ifdef CPU_ENABLE_SSE 122void fxsave __P((caddr_t addr)); 123void fxrstor __P((caddr_t addr)); 124#endif 125void start_emulating __P((void)); 126void stop_emulating __P((void)); 127 128#endif /* __GNUC__ */ 129 130#ifdef CPU_ENABLE_SSE 131#define GET_FPU_CW(thread) \ 132 (cpu_fxsr ? \ 133 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 134 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 135#define GET_FPU_SW(thread) \ 136 (cpu_fxsr ? \ 137 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 138 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 139#define GET_FPU_EXSW_PTR(pcb) \ 140 (cpu_fxsr ? \ 141 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ 142 &(pcb)->pcb_save.sv_87.sv_ex_sw) 143#else /* CPU_ENABLE_SSE */ 144#define GET_FPU_CW(thread) \ 145 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 146#define GET_FPU_SW(thread) \ 147 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 148#define GET_FPU_EXSW_PTR(pcb) \ 149 (&(pcb)->pcb_save.sv_87.sv_ex_sw) 150#endif /* CPU_ENABLE_SSE */ 151 152typedef u_char bool_t; 153 154static int npx_attach __P((device_t dev)); 155static void npx_identify __P((driver_t *driver, device_t parent)); 156#ifndef SMP 157static void npx_intr __P((void *)); 158#endif 159static int npx_probe __P((device_t dev)); 160static void fpusave __P((union savefpu *)); 161static void fpurstor __P((union savefpu *)); 162#ifdef I586_CPU_XXX 163static long timezero __P((const char *funcname, 164 void (*func)(void *buf, size_t len))); 165#endif /* I586_CPU */ 166 167int hw_float; /* XXX currently just alias for npx_exists */ 168 169SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 170 CTLFLAG_RD, &hw_float, 0, 171 "Floatingpoint instructions executed in hardware"); 172 173#ifndef SMP 174static volatile u_int npx_intrs_while_probing; 175static volatile u_int npx_traps_while_probing; 176#endif 177 178static bool_t npx_ex16; 179static bool_t npx_exists; 180static bool_t npx_irq13; 181 182#ifndef SMP 183alias_for_inthand_t probetrap; 184__asm(" \n\ 185 .text \n\ 186 .p2align 2,0x90 \n\ 187 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 188" __XSTRING(CNAME(probetrap)) ": \n\ 189 ss \n\ 190 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 191 fnclex \n\ 192 iret \n\ 193"); 194#endif /* SMP */ 195 196/* 197 * Identify routine. Create a connection point on our parent for probing. 198 */ 199static void 200npx_identify(driver, parent) 201 driver_t *driver; 202 device_t parent; 203{ 204 device_t child; 205 206 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 207 if (child == NULL) 208 panic("npx_identify"); 209} 210 211#ifndef SMP 212/* 213 * Do minimal handling of npx interrupts to convert them to traps. 214 */ 215static void 216npx_intr(dummy) 217 void *dummy; 218{ 219 struct thread *td; 220 221#ifndef SMP 222 npx_intrs_while_probing++; 223#endif 224 225 /* 226 * The BUSY# latch must be cleared in all cases so that the next 227 * unmasked npx exception causes an interrupt. 228 */ 229 outb(0xf0, 0); 230 231 /* 232 * npxthread is normally non-null here. In that case, schedule an 233 * AST to finish the exception handling in the correct context 234 * (this interrupt may occur after the thread has entered the 235 * kernel via a syscall or an interrupt). Otherwise, the npx 236 * state of the thread that caused this interrupt must have been 237 * pushed to the thread's pcb, and clearing of the busy latch 238 * above has finished the (essentially null) handling of this 239 * interrupt. Control will eventually return to the instruction 240 * that caused it and it will repeat. We will eventually (usually 241 * soon) win the race to handle the interrupt properly. 242 */ 243 td = PCPU_GET(npxthread); 244 if (td != NULL) { 245 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 246 mtx_lock_spin(&sched_lock); 247 td->td_kse->ke_flags |= KEF_ASTPENDING; 248 mtx_unlock_spin(&sched_lock); 249 } 250} 251#endif /* !SMP */ 252 253/* 254 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 255 * whether the device exists or not (XXX should be elsewhere). Set flags 256 * to tell npxattach() what to do. Modify device struct if npx doesn't 257 * need to use interrupts. Return 0 if device exists. 258 */ 259static int 260npx_probe(dev) 261 device_t dev; 262{ 263#ifndef SMP 264 struct gate_descriptor save_idt_npxtrap; 265 struct resource *ioport_res, *irq_res; 266 void *irq_cookie; 267 int ioport_rid, irq_num, irq_rid; 268 u_short control; 269 u_short status; 270 271 save_idt_npxtrap = idt[16]; 272 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 273 ioport_rid = 0; 274 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 275 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 276 if (ioport_res == NULL) 277 panic("npx: can't get ports"); 278 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 279 irq_num = 13; 280 irq_rid = 0; 281 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num, 282 irq_num, 1, RF_ACTIVE); 283 if (irq_res == NULL) 284 panic("npx: can't get IRQ"); 285 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 286 NULL, &irq_cookie) != 0) 287 panic("npx: can't create intr"); 288#endif /* !SMP */ 289 290 /* 291 * Partially reset the coprocessor, if any. Some BIOS's don't reset 292 * it after a warm boot. 293 */ 294 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 295 outb(0xf0, 0); /* clear BUSY# latch */ 296 /* 297 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 298 * instructions. We must set the CR0_MP bit and use the CR0_TS 299 * bit to control the trap, because setting the CR0_EM bit does 300 * not cause WAIT instructions to trap. It's important to trap 301 * WAIT instructions - otherwise the "wait" variants of no-wait 302 * control instructions would degenerate to the "no-wait" variants 303 * after FP context switches but work correctly otherwise. It's 304 * particularly important to trap WAITs when there is no NPX - 305 * otherwise the "wait" variants would always degenerate. 306 * 307 * Try setting CR0_NE to get correct error reporting on 486DX's. 308 * Setting it should fail or do nothing on lesser processors. 309 */ 310 load_cr0(rcr0() | CR0_MP | CR0_NE); 311 /* 312 * But don't trap while we're probing. 313 */ 314 stop_emulating(); 315 /* 316 * Finish resetting the coprocessor, if any. If there is an error 317 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 318 * it OK. Bogus halts have never been observed, but we enabled 319 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 320 */ 321 fninit(); 322 323 device_set_desc(dev, "math processor"); 324 325#ifdef SMP 326 327 /* 328 * Exception 16 MUST work for SMP. 329 */ 330 npx_ex16 = hw_float = npx_exists = 1; 331 return (0); 332 333#else /* !SMP */ 334 335 /* 336 * Don't use fwait here because it might hang. 337 * Don't use fnop here because it usually hangs if there is no FPU. 338 */ 339 DELAY(1000); /* wait for any IRQ13 */ 340#ifdef DIAGNOSTIC 341 if (npx_intrs_while_probing != 0) 342 printf("fninit caused %u bogus npx interrupt(s)\n", 343 npx_intrs_while_probing); 344 if (npx_traps_while_probing != 0) 345 printf("fninit caused %u bogus npx trap(s)\n", 346 npx_traps_while_probing); 347#endif 348 /* 349 * Check for a status of mostly zero. 350 */ 351 status = 0x5a5a; 352 fnstsw(&status); 353 if ((status & 0xb8ff) == 0) { 354 /* 355 * Good, now check for a proper control word. 356 */ 357 control = 0x5a5a; 358 fnstcw(&control); 359 if ((control & 0x1f3f) == 0x033f) { 360 hw_float = npx_exists = 1; 361 /* 362 * We have an npx, now divide by 0 to see if exception 363 * 16 works. 364 */ 365 control &= ~(1 << 2); /* enable divide by 0 trap */ 366 fldcw(&control); 367#ifdef FPU_ERROR_BROKEN 368 /* 369 * FPU error signal doesn't work on some CPU 370 * accelerator board. 371 */ 372 npx_ex16 = 1; 373 return (0); 374#endif 375 npx_traps_while_probing = npx_intrs_while_probing = 0; 376 fp_divide_by_0(); 377 if (npx_traps_while_probing != 0) { 378 /* 379 * Good, exception 16 works. 380 */ 381 npx_ex16 = 1; 382 goto no_irq13; 383 } 384 if (npx_intrs_while_probing != 0) { 385 /* 386 * Bad, we are stuck with IRQ13. 387 */ 388 npx_irq13 = 1; 389 idt[16] = save_idt_npxtrap; 390 return (0); 391 } 392 /* 393 * Worse, even IRQ13 is broken. Use emulator. 394 */ 395 } 396 } 397 /* 398 * Probe failed, but we want to get to npxattach to initialize the 399 * emulator and say that it has been installed. XXX handle devices 400 * that aren't really devices better. 401 */ 402 /* FALLTHROUGH */ 403no_irq13: 404 idt[16] = save_idt_npxtrap; 405 bus_teardown_intr(dev, irq_res, irq_cookie); 406 407 /* 408 * XXX hack around brokenness of bus_teardown_intr(). If we left the 409 * irq active then we would get it instead of exception 16. 410 */ 411 INTRDIS(1 << irq_num); 412 413 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 414 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 415 return (0); 416 417#endif /* SMP */ 418} 419 420/* 421 * Attach routine - announce which it is, and wire into system 422 */ 423int 424npx_attach(dev) 425 device_t dev; 426{ 427 int flags; 428 429 if (resource_int_value("npx", 0, "flags", &flags) != 0) 430 flags = 0; 431 432 if (flags) 433 device_printf(dev, "flags 0x%x ", flags); 434 if (npx_irq13) { 435 device_printf(dev, "using IRQ 13 interface\n"); 436 } else { 437#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 438 if (npx_ex16) { 439 if (!(flags & NPX_PREFER_EMULATOR)) 440 device_printf(dev, "INT 16 interface\n"); 441 else { 442 device_printf(dev, "FPU exists, but flags request " 443 "emulator\n"); 444 hw_float = npx_exists = 0; 445 } 446 } else if (npx_exists) { 447 device_printf(dev, "error reporting broken; using 387 emulator\n"); 448 hw_float = npx_exists = 0; 449 } else 450 device_printf(dev, "387 emulator\n"); 451#else 452 if (npx_ex16) { 453 device_printf(dev, "INT 16 interface\n"); 454 if (flags & NPX_PREFER_EMULATOR) { 455 device_printf(dev, "emulator requested, but none compiled " 456 "into kernel, using FPU\n"); 457 } 458 } else 459 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 460#endif 461 } 462 npxinit(__INITIAL_NPXCW__); 463 464#ifdef I586_CPU_XXX 465 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 466 timezero("i586_bzero()", i586_bzero) < 467 timezero("bzero()", bzero) * 4 / 5) { 468 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 469 bcopy_vector = i586_bcopy; 470 ovbcopy_vector = i586_bcopy; 471 } 472 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 473 bzero = i586_bzero; 474 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 475 copyin_vector = i586_copyin; 476 copyout_vector = i586_copyout; 477 } 478 } 479#endif 480 481 return (0); /* XXX unused */ 482} 483 484/* 485 * Initialize floating point unit. 486 */ 487void 488npxinit(control) 489 u_short control; 490{ 491 static union savefpu dummy; 492 critical_t savecrit; 493 494 if (!npx_exists) 495 return; 496 /* 497 * fninit has the same h/w bugs as fnsave. Use the detoxified 498 * fnsave to throw away any junk in the fpu. npxsave() initializes 499 * the fpu and sets npxthread = NULL as important side effects. 500 */ 501 savecrit = critical_enter(); 502 npxsave(&dummy); 503 stop_emulating(); 504#ifdef CPU_ENABLE_SSE 505 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 506 if (cpu_fxsr) 507 fninit(); 508#endif 509 fldcw(&control); 510 if (PCPU_GET(curpcb) != NULL) 511 fpusave(&PCPU_GET(curpcb)->pcb_save); 512 start_emulating(); 513 critical_exit(savecrit); 514} 515 516/* 517 * Free coprocessor (if we have it). 518 */ 519void 520npxexit(td) 521 struct thread *td; 522{ 523 critical_t savecrit; 524 525 savecrit = critical_enter(); 526 if (td == PCPU_GET(npxthread)) 527 npxsave(&PCPU_GET(curpcb)->pcb_save); 528 critical_exit(savecrit); 529#ifdef NPX_DEBUG 530 if (npx_exists) { 531 u_int masked_exceptions; 532 533 masked_exceptions = PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_cw 534 & PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_sw & 0x7f; 535 /* 536 * Log exceptions that would have trapped with the old 537 * control word (overflow, divide by 0, and invalid operand). 538 */ 539 if (masked_exceptions & 0x0d) 540 log(LOG_ERR, 541 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 542 td->td_proc->p_pid, td->td_proc->p_comm, 543 masked_exceptions); 544 } 545#endif 546} 547 548/* 549 * The following mechanism is used to ensure that the FPE_... value 550 * that is passed as a trapcode to the signal handler of the user 551 * process does not have more than one bit set. 552 * 553 * Multiple bits may be set if the user process modifies the control 554 * word while a status word bit is already set. While this is a sign 555 * of bad coding, we have no choise than to narrow them down to one 556 * bit, since we must not send a trapcode that is not exactly one of 557 * the FPE_ macros. 558 * 559 * The mechanism has a static table with 127 entries. Each combination 560 * of the 7 FPU status word exception bits directly translates to a 561 * position in this table, where a single FPE_... value is stored. 562 * This FPE_... value stored there is considered the "most important" 563 * of the exception bits and will be sent as the signal code. The 564 * precedence of the bits is based upon Intel Document "Numerical 565 * Applications", Chapter "Special Computational Situations". 566 * 567 * The macro to choose one of these values does these steps: 1) Throw 568 * away status word bits that cannot be masked. 2) Throw away the bits 569 * currently masked in the control word, assuming the user isn't 570 * interested in them anymore. 3) Reinsert status word bit 7 (stack 571 * fault) if it is set, which cannot be masked but must be presered. 572 * 4) Use the remaining bits to point into the trapcode table. 573 * 574 * The 6 maskable bits in order of their preference, as stated in the 575 * above referenced Intel manual: 576 * 1 Invalid operation (FP_X_INV) 577 * 1a Stack underflow 578 * 1b Stack overflow 579 * 1c Operand of unsupported format 580 * 1d SNaN operand. 581 * 2 QNaN operand (not an exception, irrelavant here) 582 * 3 Any other invalid-operation not mentioned above or zero divide 583 * (FP_X_INV, FP_X_DZ) 584 * 4 Denormal operand (FP_X_DNML) 585 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 586 * 6 Inexact result (FP_X_IMP) 587 */ 588static char fpetable[128] = { 589 0, 590 FPE_FLTINV, /* 1 - INV */ 591 FPE_FLTUND, /* 2 - DNML */ 592 FPE_FLTINV, /* 3 - INV | DNML */ 593 FPE_FLTDIV, /* 4 - DZ */ 594 FPE_FLTINV, /* 5 - INV | DZ */ 595 FPE_FLTDIV, /* 6 - DNML | DZ */ 596 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 597 FPE_FLTOVF, /* 8 - OFL */ 598 FPE_FLTINV, /* 9 - INV | OFL */ 599 FPE_FLTUND, /* A - DNML | OFL */ 600 FPE_FLTINV, /* B - INV | DNML | OFL */ 601 FPE_FLTDIV, /* C - DZ | OFL */ 602 FPE_FLTINV, /* D - INV | DZ | OFL */ 603 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 604 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 605 FPE_FLTUND, /* 10 - UFL */ 606 FPE_FLTINV, /* 11 - INV | UFL */ 607 FPE_FLTUND, /* 12 - DNML | UFL */ 608 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 609 FPE_FLTDIV, /* 14 - DZ | UFL */ 610 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 611 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 612 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 613 FPE_FLTOVF, /* 18 - OFL | UFL */ 614 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 615 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 616 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 617 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 618 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 619 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 620 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 621 FPE_FLTRES, /* 20 - IMP */ 622 FPE_FLTINV, /* 21 - INV | IMP */ 623 FPE_FLTUND, /* 22 - DNML | IMP */ 624 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 625 FPE_FLTDIV, /* 24 - DZ | IMP */ 626 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 627 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 628 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 629 FPE_FLTOVF, /* 28 - OFL | IMP */ 630 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 631 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 632 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 633 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 634 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 635 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 636 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 637 FPE_FLTUND, /* 30 - UFL | IMP */ 638 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 639 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 640 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 641 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 642 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 643 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 644 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 645 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 646 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 647 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 648 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 649 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 650 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 651 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 652 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 653 FPE_FLTSUB, /* 40 - STK */ 654 FPE_FLTSUB, /* 41 - INV | STK */ 655 FPE_FLTUND, /* 42 - DNML | STK */ 656 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 657 FPE_FLTDIV, /* 44 - DZ | STK */ 658 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 659 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 660 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 661 FPE_FLTOVF, /* 48 - OFL | STK */ 662 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 663 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 664 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 665 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 666 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 667 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 668 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 669 FPE_FLTUND, /* 50 - UFL | STK */ 670 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 671 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 672 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 673 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 674 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 675 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 676 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 677 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 678 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 679 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 680 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 681 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 682 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 683 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 684 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 685 FPE_FLTRES, /* 60 - IMP | STK */ 686 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 687 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 688 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 689 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 690 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 691 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 692 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 693 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 694 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 695 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 696 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 697 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 698 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 699 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 700 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 701 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 702 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 703 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 704 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 705 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 706 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 707 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 708 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 709 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 710 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 711 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 712 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 713 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 714 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 715 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 716 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 717}; 718 719/* 720 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 721 * 722 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 723 * depend on longjmp() restoring a usable state. Restoring the state 724 * or examining it might fail if we didn't clear exceptions. 725 * 726 * The error code chosen will be one of the FPE_... macros. It will be 727 * sent as the second argument to old BSD-style signal handlers and as 728 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 729 * 730 * XXX the FP state is not preserved across signal handlers. So signal 731 * handlers cannot afford to do FP unless they preserve the state or 732 * longjmp() out. Both preserving the state and longjmp()ing may be 733 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 734 * solution for signals other than SIGFPE. 735 */ 736int 737npxtrap() 738{ 739 critical_t savecrit; 740 u_short control, status; 741 u_long *exstat; 742 743 if (!npx_exists) { 744 printf("npxtrap: npxthread = %p, curthread = %p, npx_exists = %d\n", 745 PCPU_GET(npxthread), curthread, npx_exists); 746 panic("npxtrap from nowhere"); 747 } 748 savecrit = critical_enter(); 749 750 /* 751 * Interrupt handling (for another interrupt) may have pushed the 752 * state to memory. Fetch the relevant parts of the state from 753 * wherever they are. 754 */ 755 if (PCPU_GET(npxthread) != curthread) { 756 control = GET_FPU_CW(curthread); 757 status = GET_FPU_SW(curthread); 758 } else { 759 fnstcw(&control); 760 fnstsw(&status); 761 } 762 763 exstat = GET_FPU_EXSW_PTR(curthread->td_pcb); 764 *exstat = status; 765 if (PCPU_GET(npxthread) != curthread) 766 GET_FPU_SW(curthread) &= ~0x80bf; 767 else 768 fnclex(); 769 critical_exit(savecrit); 770 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 771} 772 773/* 774 * Implement device not available (DNA) exception 775 * 776 * It would be better to switch FP context here (if curthread != npxthread) 777 * and not necessarily for every context switch, but it is too hard to 778 * access foreign pcb's. 779 */ 780int 781npxdna() 782{ 783 u_long *exstat; 784 critical_t s; 785 786 if (!npx_exists) 787 return (0); 788 if (PCPU_GET(npxthread) != NULL) { 789 printf("npxdna: npxthread = %p, curthread = %p\n", 790 PCPU_GET(npxthread), curthread); 791 panic("npxdna"); 792 } 793 s = critical_enter(); 794 stop_emulating(); 795 /* 796 * Record new context early in case frstor causes an IRQ13. 797 */ 798 PCPU_SET(npxthread, curthread); 799 800 exstat = GET_FPU_EXSW_PTR(PCPU_GET(curpcb)); 801 *exstat = 0; 802 /* 803 * The following frstor may cause an IRQ13 when the state being 804 * restored has a pending error. The error will appear to have been 805 * triggered by the current (npx) user instruction even when that 806 * instruction is a no-wait instruction that should not trigger an 807 * error (e.g., fnclex). On at least one 486 system all of the 808 * no-wait instructions are broken the same as frstor, so our 809 * treatment does not amplify the breakage. On at least one 810 * 386/Cyrix 387 system, fnclex works correctly while frstor and 811 * fnsave are broken, so our treatment breaks fnclex if it is the 812 * first FPU instruction after a context switch. 813 */ 814 fpurstor(&PCPU_GET(curpcb)->pcb_save); 815 critical_exit(s); 816 817 return (1); 818} 819 820/* 821 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 822 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 823 * no-wait npx instructions. See the Intel application note AP-578 for 824 * details. This doesn't cause any additional complications here. IRQ13's 825 * are inherently asynchronous unless the CPU is frozen to deliver them -- 826 * one that started in userland may be delivered many instructions later, 827 * after the process has entered the kernel. It may even be delivered after 828 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 829 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 830 * it is normally ignored at first because we set npxthread to NULL; it is 831 * normally retriggered in npxdna() after return to user mode. 832 * 833 * npxsave() must be called with interrupts disabled, so that it clears 834 * npxthread atomically with saving the state. We require callers to do the 835 * disabling, since most callers need to disable interrupts anyway to call 836 * npxsave() atomically with checking npxthread. 837 * 838 * A previous version of npxsave() went to great lengths to excecute fnsave 839 * with interrupts enabled in case executing it froze the CPU. This case 840 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 841 * spurious freezes. 842 */ 843void 844npxsave(addr) 845 union savefpu *addr; 846{ 847 848 stop_emulating(); 849 fpusave(addr); 850 851 start_emulating(); 852 PCPU_SET(npxthread, NULL); 853} 854 855static void 856fpusave(addr) 857 union savefpu *addr; 858{ 859 860#ifdef CPU_ENABLE_SSE 861 if (cpu_fxsr) 862 fxsave(addr); 863 else 864#endif 865 fnsave(addr); 866} 867 868static void 869fpurstor(addr) 870 union savefpu *addr; 871{ 872 873#ifdef CPU_ENABLE_SSE 874 if (cpu_fxsr) 875 fxrstor(addr); 876 else 877#endif 878 frstor(addr); 879} 880 881#ifdef I586_CPU_XXX 882static long 883timezero(funcname, func) 884 const char *funcname; 885 void (*func) __P((void *buf, size_t len)); 886 887{ 888 void *buf; 889#define BUFSIZE 1048576 890 long usec; 891 struct timeval finish, start; 892 893 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 894 if (buf == NULL) 895 return (BUFSIZE); 896 microtime(&start); 897 (*func)(buf, BUFSIZE); 898 microtime(&finish); 899 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 900 finish.tv_usec - start.tv_usec; 901 if (usec <= 0) 902 usec = 1; 903 if (bootverbose) 904 printf("%s bandwidth = %u kBps\n", funcname, 905 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 906 free(buf, M_TEMP); 907 return (usec); 908} 909#endif /* I586_CPU */ 910 911static device_method_t npx_methods[] = { 912 /* Device interface */ 913 DEVMETHOD(device_identify, npx_identify), 914 DEVMETHOD(device_probe, npx_probe), 915 DEVMETHOD(device_attach, npx_attach), 916 DEVMETHOD(device_detach, bus_generic_detach), 917 DEVMETHOD(device_shutdown, bus_generic_shutdown), 918 DEVMETHOD(device_suspend, bus_generic_suspend), 919 DEVMETHOD(device_resume, bus_generic_resume), 920 921 { 0, 0 } 922}; 923 924static driver_t npx_driver = { 925 "npx", 926 npx_methods, 927 1, /* no softc */ 928}; 929 930static devclass_t npx_devclass; 931 932/* 933 * We prefer to attach to the root nexus so that the usual case (exception 16) 934 * doesn't describe the processor as being `on isa'. 935 */ 936DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 937 938/* 939 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 940 */ 941static struct isa_pnp_id npxisa_ids[] = { 942 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 943 { 0 } 944}; 945 946static int 947npxisa_probe(device_t dev) 948{ 949 int result; 950 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 951 device_quiet(dev); 952 } 953 return(result); 954} 955 956static int 957npxisa_attach(device_t dev) 958{ 959 return (0); 960} 961 962static device_method_t npxisa_methods[] = { 963 /* Device interface */ 964 DEVMETHOD(device_probe, npxisa_probe), 965 DEVMETHOD(device_attach, npxisa_attach), 966 DEVMETHOD(device_detach, bus_generic_detach), 967 DEVMETHOD(device_shutdown, bus_generic_shutdown), 968 DEVMETHOD(device_suspend, bus_generic_suspend), 969 DEVMETHOD(device_resume, bus_generic_resume), 970 971 { 0, 0 } 972}; 973 974static driver_t npxisa_driver = { 975 "npxisa", 976 npxisa_methods, 977 1, /* no softc */ 978}; 979 980static devclass_t npxisa_devclass; 981 982DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 983DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 984 985