fpu.c revision 85029
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 85029 2001-10-16 14:12:35Z bde $ 36 */ 37 38#include "opt_cpu.h" 39#include "opt_debug_npx.h" 40#include "opt_math_emulate.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/malloc.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/mutex.h> 51#include <sys/proc.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59#include <sys/user.h> 60 61#ifndef SMP 62#include <machine/asmacros.h> 63#endif 64#include <machine/cputypes.h> 65#include <machine/frame.h> 66#include <machine/md_var.h> 67#include <machine/pcb.h> 68#include <machine/psl.h> 69#ifndef SMP 70#include <machine/clock.h> 71#endif 72#include <machine/resource.h> 73#include <machine/specialreg.h> 74#include <machine/segments.h> 75 76#ifndef SMP 77#include <i386/isa/icu.h> 78#include <i386/isa/isa.h> 79#endif 80#include <isa/isavar.h> 81 82/* 83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 84 */ 85 86/* Configuration flags. */ 87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 90#define NPX_PREFER_EMULATOR (1 << 3) 91 92#ifdef __GNUC__ 93 94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 95#define fnclex() __asm("fnclex") 96#define fninit() __asm("fninit") 97#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 98#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 99#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 100#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 101#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 102#ifdef CPU_ENABLE_SSE 103#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 104#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 105#endif 106#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 107 : : "n" (CR0_TS) : "ax") 108#define stop_emulating() __asm("clts") 109 110#else /* not __GNUC__ */ 111 112void fldcw __P((caddr_t addr)); 113void fnclex __P((void)); 114void fninit __P((void)); 115void fnsave __P((caddr_t addr)); 116void fnstcw __P((caddr_t addr)); 117void fnstsw __P((caddr_t addr)); 118void fp_divide_by_0 __P((void)); 119void frstor __P((caddr_t addr)); 120#ifdef CPU_ENABLE_SSE 121void fxsave __P((caddr_t addr)); 122void fxrstor __P((caddr_t addr)); 123#endif 124void start_emulating __P((void)); 125void stop_emulating __P((void)); 126 127#endif /* __GNUC__ */ 128 129#ifdef CPU_ENABLE_SSE 130#define GET_FPU_CW(thread) \ 131 (cpu_fxsr ? \ 132 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 133 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 134#define GET_FPU_SW(thread) \ 135 (cpu_fxsr ? \ 136 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 137 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 138#define GET_FPU_EXSW_PTR(pcb) \ 139 (cpu_fxsr ? \ 140 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ 141 &(pcb)->pcb_save.sv_87.sv_ex_sw) 142#else /* CPU_ENABLE_SSE */ 143#define GET_FPU_CW(thread) \ 144 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 145#define GET_FPU_SW(thread) \ 146 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 147#define GET_FPU_EXSW_PTR(pcb) \ 148 (&(pcb)->pcb_save.sv_87.sv_ex_sw) 149#endif /* CPU_ENABLE_SSE */ 150 151typedef u_char bool_t; 152 153static int npx_attach __P((device_t dev)); 154static void npx_identify __P((driver_t *driver, device_t parent)); 155#ifndef SMP 156static void npx_intr __P((void *)); 157#endif 158static int npx_probe __P((device_t dev)); 159static void fpusave __P((union savefpu *)); 160static void fpurstor __P((union savefpu *)); 161#ifdef I586_CPU_XXX 162static long timezero __P((const char *funcname, 163 void (*func)(void *buf, size_t len))); 164#endif /* I586_CPU */ 165 166int hw_float; /* XXX currently just alias for npx_exists */ 167 168SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 169 CTLFLAG_RD, &hw_float, 0, 170 "Floatingpoint instructions executed in hardware"); 171 172#ifndef SMP 173static volatile u_int npx_intrs_while_probing; 174static volatile u_int npx_traps_while_probing; 175#endif 176 177static bool_t npx_ex16; 178static bool_t npx_exists; 179static bool_t npx_irq13; 180 181#ifndef SMP 182alias_for_inthand_t probetrap; 183__asm(" \n\ 184 .text \n\ 185 .p2align 2,0x90 \n\ 186 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 187" __XSTRING(CNAME(probetrap)) ": \n\ 188 ss \n\ 189 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 190 fnclex \n\ 191 iret \n\ 192"); 193#endif /* SMP */ 194 195/* 196 * Identify routine. Create a connection point on our parent for probing. 197 */ 198static void 199npx_identify(driver, parent) 200 driver_t *driver; 201 device_t parent; 202{ 203 device_t child; 204 205 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 206 if (child == NULL) 207 panic("npx_identify"); 208} 209 210#ifndef SMP 211/* 212 * Do minimal handling of npx interrupts to convert them to traps. 213 */ 214static void 215npx_intr(dummy) 216 void *dummy; 217{ 218 struct thread *td; 219 220#ifndef SMP 221 npx_intrs_while_probing++; 222#endif 223 224 /* 225 * The BUSY# latch must be cleared in all cases so that the next 226 * unmasked npx exception causes an interrupt. 227 */ 228 outb(0xf0, 0); 229 230 /* 231 * npxthread is normally non-null here. In that case, schedule an 232 * AST to finish the exception handling in the correct context 233 * (this interrupt may occur after the thread has entered the 234 * kernel via a syscall or an interrupt). Otherwise, the npx 235 * state of the thread that caused this interrupt must have been 236 * pushed to the thread's pcb, and clearing of the busy latch 237 * above has finished the (essentially null) handling of this 238 * interrupt. Control will eventually return to the instruction 239 * that caused it and it will repeat. We will eventually (usually 240 * soon) win the race to handle the interrupt properly. 241 */ 242 td = PCPU_GET(npxthread); 243 if (td != NULL) { 244 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 245 mtx_lock_spin(&sched_lock); 246 td->td_kse->ke_flags |= KEF_ASTPENDING; 247 mtx_unlock_spin(&sched_lock); 248 } 249} 250#endif /* !SMP */ 251 252/* 253 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 254 * whether the device exists or not (XXX should be elsewhere). Set flags 255 * to tell npxattach() what to do. Modify device struct if npx doesn't 256 * need to use interrupts. Return 0 if device exists. 257 */ 258static int 259npx_probe(dev) 260 device_t dev; 261{ 262#ifndef SMP 263 struct gate_descriptor save_idt_npxtrap; 264 struct resource *ioport_res, *irq_res; 265 void *irq_cookie; 266 int ioport_rid, irq_num, irq_rid; 267 u_short control; 268 u_short status; 269 270 save_idt_npxtrap = idt[16]; 271 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 272 ioport_rid = 0; 273 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 274 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 275 if (ioport_res == NULL) 276 panic("npx: can't get ports"); 277 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 278 irq_num = 13; 279 irq_rid = 0; 280 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num, 281 irq_num, 1, RF_ACTIVE); 282 if (irq_res == NULL) 283 panic("npx: can't get IRQ"); 284 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 285 NULL, &irq_cookie) != 0) 286 panic("npx: can't create intr"); 287#endif /* !SMP */ 288 289 /* 290 * Partially reset the coprocessor, if any. Some BIOS's don't reset 291 * it after a warm boot. 292 */ 293 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 294 outb(0xf0, 0); /* clear BUSY# latch */ 295 /* 296 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 297 * instructions. We must set the CR0_MP bit and use the CR0_TS 298 * bit to control the trap, because setting the CR0_EM bit does 299 * not cause WAIT instructions to trap. It's important to trap 300 * WAIT instructions - otherwise the "wait" variants of no-wait 301 * control instructions would degenerate to the "no-wait" variants 302 * after FP context switches but work correctly otherwise. It's 303 * particularly important to trap WAITs when there is no NPX - 304 * otherwise the "wait" variants would always degenerate. 305 * 306 * Try setting CR0_NE to get correct error reporting on 486DX's. 307 * Setting it should fail or do nothing on lesser processors. 308 */ 309 load_cr0(rcr0() | CR0_MP | CR0_NE); 310 /* 311 * But don't trap while we're probing. 312 */ 313 stop_emulating(); 314 /* 315 * Finish resetting the coprocessor, if any. If there is an error 316 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 317 * it OK. Bogus halts have never been observed, but we enabled 318 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 319 */ 320 fninit(); 321 322 device_set_desc(dev, "math processor"); 323 324#ifdef SMP 325 326 /* 327 * Exception 16 MUST work for SMP. 328 */ 329 npx_ex16 = hw_float = npx_exists = 1; 330 return (0); 331 332#else /* !SMP */ 333 334 /* 335 * Don't use fwait here because it might hang. 336 * Don't use fnop here because it usually hangs if there is no FPU. 337 */ 338 DELAY(1000); /* wait for any IRQ13 */ 339#ifdef DIAGNOSTIC 340 if (npx_intrs_while_probing != 0) 341 printf("fninit caused %u bogus npx interrupt(s)\n", 342 npx_intrs_while_probing); 343 if (npx_traps_while_probing != 0) 344 printf("fninit caused %u bogus npx trap(s)\n", 345 npx_traps_while_probing); 346#endif 347 /* 348 * Check for a status of mostly zero. 349 */ 350 status = 0x5a5a; 351 fnstsw(&status); 352 if ((status & 0xb8ff) == 0) { 353 /* 354 * Good, now check for a proper control word. 355 */ 356 control = 0x5a5a; 357 fnstcw(&control); 358 if ((control & 0x1f3f) == 0x033f) { 359 hw_float = npx_exists = 1; 360 /* 361 * We have an npx, now divide by 0 to see if exception 362 * 16 works. 363 */ 364 control &= ~(1 << 2); /* enable divide by 0 trap */ 365 fldcw(&control); 366 npx_traps_while_probing = npx_intrs_while_probing = 0; 367 fp_divide_by_0(); 368 if (npx_traps_while_probing != 0) { 369 /* 370 * Good, exception 16 works. 371 */ 372 npx_ex16 = 1; 373 goto no_irq13; 374 } 375 if (npx_intrs_while_probing != 0) { 376 /* 377 * Bad, we are stuck with IRQ13. 378 */ 379 npx_irq13 = 1; 380 idt[16] = save_idt_npxtrap; 381 return (0); 382 } 383 /* 384 * Worse, even IRQ13 is broken. Use emulator. 385 */ 386 } 387 } 388 /* 389 * Probe failed, but we want to get to npxattach to initialize the 390 * emulator and say that it has been installed. XXX handle devices 391 * that aren't really devices better. 392 */ 393 /* FALLTHROUGH */ 394no_irq13: 395 idt[16] = save_idt_npxtrap; 396 bus_teardown_intr(dev, irq_res, irq_cookie); 397 398 /* 399 * XXX hack around brokenness of bus_teardown_intr(). If we left the 400 * irq active then we would get it instead of exception 16. 401 */ 402 INTRDIS(1 << irq_num); 403 404 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 405 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 406 return (0); 407 408#endif /* SMP */ 409} 410 411/* 412 * Attach routine - announce which it is, and wire into system 413 */ 414int 415npx_attach(dev) 416 device_t dev; 417{ 418 int flags; 419 420 if (resource_int_value("npx", 0, "flags", &flags) != 0) 421 flags = 0; 422 423 if (flags) 424 device_printf(dev, "flags 0x%x ", flags); 425 if (npx_irq13) { 426 device_printf(dev, "using IRQ 13 interface\n"); 427 } else { 428#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 429 if (npx_ex16) { 430 if (!(flags & NPX_PREFER_EMULATOR)) 431 device_printf(dev, "INT 16 interface\n"); 432 else { 433 device_printf(dev, "FPU exists, but flags request " 434 "emulator\n"); 435 hw_float = npx_exists = 0; 436 } 437 } else if (npx_exists) { 438 device_printf(dev, "error reporting broken; using 387 emulator\n"); 439 hw_float = npx_exists = 0; 440 } else 441 device_printf(dev, "387 emulator\n"); 442#else 443 if (npx_ex16) { 444 device_printf(dev, "INT 16 interface\n"); 445 if (flags & NPX_PREFER_EMULATOR) { 446 device_printf(dev, "emulator requested, but none compiled " 447 "into kernel, using FPU\n"); 448 } 449 } else 450 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 451#endif 452 } 453 npxinit(__INITIAL_NPXCW__); 454 455#ifdef I586_CPU_XXX 456 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 457 timezero("i586_bzero()", i586_bzero) < 458 timezero("bzero()", bzero) * 4 / 5) { 459 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 460 bcopy_vector = i586_bcopy; 461 ovbcopy_vector = i586_bcopy; 462 } 463 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 464 bzero = i586_bzero; 465 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 466 copyin_vector = i586_copyin; 467 copyout_vector = i586_copyout; 468 } 469 } 470#endif 471 472 return (0); /* XXX unused */ 473} 474 475/* 476 * Initialize floating point unit. 477 */ 478void 479npxinit(control) 480 u_short control; 481{ 482 static union savefpu dummy; 483 critical_t savecrit; 484 485 if (!npx_exists) 486 return; 487 /* 488 * fninit has the same h/w bugs as fnsave. Use the detoxified 489 * fnsave to throw away any junk in the fpu. npxsave() initializes 490 * the fpu and sets npxthread = NULL as important side effects. 491 */ 492 savecrit = critical_enter(); 493 npxsave(&dummy); 494 stop_emulating(); 495#ifdef CPU_ENABLE_SSE 496 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 497 if (cpu_fxsr) 498 fninit(); 499#endif 500 fldcw(&control); 501 if (PCPU_GET(curpcb) != NULL) 502 fpusave(&PCPU_GET(curpcb)->pcb_save); 503 start_emulating(); 504 critical_exit(savecrit); 505} 506 507/* 508 * Free coprocessor (if we have it). 509 */ 510void 511npxexit(td) 512 struct thread *td; 513{ 514 critical_t savecrit; 515 516 savecrit = critical_enter(); 517 if (td == PCPU_GET(npxthread)) 518 npxsave(&PCPU_GET(curpcb)->pcb_save); 519 critical_exit(savecrit); 520#ifdef NPX_DEBUG 521 if (npx_exists) { 522 u_int masked_exceptions; 523 524 masked_exceptions = PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_cw 525 & PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_sw & 0x7f; 526 /* 527 * Log exceptions that would have trapped with the old 528 * control word (overflow, divide by 0, and invalid operand). 529 */ 530 if (masked_exceptions & 0x0d) 531 log(LOG_ERR, 532 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 533 td->td_proc->p_pid, td->td_proc->p_comm, 534 masked_exceptions); 535 } 536#endif 537} 538 539/* 540 * The following mechanism is used to ensure that the FPE_... value 541 * that is passed as a trapcode to the signal handler of the user 542 * process does not have more than one bit set. 543 * 544 * Multiple bits may be set if the user process modifies the control 545 * word while a status word bit is already set. While this is a sign 546 * of bad coding, we have no choise than to narrow them down to one 547 * bit, since we must not send a trapcode that is not exactly one of 548 * the FPE_ macros. 549 * 550 * The mechanism has a static table with 127 entries. Each combination 551 * of the 7 FPU status word exception bits directly translates to a 552 * position in this table, where a single FPE_... value is stored. 553 * This FPE_... value stored there is considered the "most important" 554 * of the exception bits and will be sent as the signal code. The 555 * precedence of the bits is based upon Intel Document "Numerical 556 * Applications", Chapter "Special Computational Situations". 557 * 558 * The macro to choose one of these values does these steps: 1) Throw 559 * away status word bits that cannot be masked. 2) Throw away the bits 560 * currently masked in the control word, assuming the user isn't 561 * interested in them anymore. 3) Reinsert status word bit 7 (stack 562 * fault) if it is set, which cannot be masked but must be presered. 563 * 4) Use the remaining bits to point into the trapcode table. 564 * 565 * The 6 maskable bits in order of their preference, as stated in the 566 * above referenced Intel manual: 567 * 1 Invalid operation (FP_X_INV) 568 * 1a Stack underflow 569 * 1b Stack overflow 570 * 1c Operand of unsupported format 571 * 1d SNaN operand. 572 * 2 QNaN operand (not an exception, irrelavant here) 573 * 3 Any other invalid-operation not mentioned above or zero divide 574 * (FP_X_INV, FP_X_DZ) 575 * 4 Denormal operand (FP_X_DNML) 576 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 577 * 6 Inexact result (FP_X_IMP) 578 */ 579static char fpetable[128] = { 580 0, 581 FPE_FLTINV, /* 1 - INV */ 582 FPE_FLTUND, /* 2 - DNML */ 583 FPE_FLTINV, /* 3 - INV | DNML */ 584 FPE_FLTDIV, /* 4 - DZ */ 585 FPE_FLTINV, /* 5 - INV | DZ */ 586 FPE_FLTDIV, /* 6 - DNML | DZ */ 587 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 588 FPE_FLTOVF, /* 8 - OFL */ 589 FPE_FLTINV, /* 9 - INV | OFL */ 590 FPE_FLTUND, /* A - DNML | OFL */ 591 FPE_FLTINV, /* B - INV | DNML | OFL */ 592 FPE_FLTDIV, /* C - DZ | OFL */ 593 FPE_FLTINV, /* D - INV | DZ | OFL */ 594 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 595 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 596 FPE_FLTUND, /* 10 - UFL */ 597 FPE_FLTINV, /* 11 - INV | UFL */ 598 FPE_FLTUND, /* 12 - DNML | UFL */ 599 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 600 FPE_FLTDIV, /* 14 - DZ | UFL */ 601 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 602 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 603 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 604 FPE_FLTOVF, /* 18 - OFL | UFL */ 605 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 606 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 607 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 608 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 609 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 610 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 611 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 612 FPE_FLTRES, /* 20 - IMP */ 613 FPE_FLTINV, /* 21 - INV | IMP */ 614 FPE_FLTUND, /* 22 - DNML | IMP */ 615 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 616 FPE_FLTDIV, /* 24 - DZ | IMP */ 617 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 618 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 619 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 620 FPE_FLTOVF, /* 28 - OFL | IMP */ 621 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 622 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 623 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 624 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 625 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 626 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 627 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 628 FPE_FLTUND, /* 30 - UFL | IMP */ 629 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 630 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 631 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 632 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 633 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 634 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 635 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 636 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 637 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 638 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 639 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 640 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 641 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 642 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 643 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 644 FPE_FLTSUB, /* 40 - STK */ 645 FPE_FLTSUB, /* 41 - INV | STK */ 646 FPE_FLTUND, /* 42 - DNML | STK */ 647 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 648 FPE_FLTDIV, /* 44 - DZ | STK */ 649 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 650 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 651 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 652 FPE_FLTOVF, /* 48 - OFL | STK */ 653 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 654 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 655 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 656 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 657 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 658 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 659 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 660 FPE_FLTUND, /* 50 - UFL | STK */ 661 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 662 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 663 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 664 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 665 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 666 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 667 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 668 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 669 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 670 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 671 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 672 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 673 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 674 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 675 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 676 FPE_FLTRES, /* 60 - IMP | STK */ 677 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 678 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 679 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 680 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 681 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 682 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 683 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 684 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 685 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 686 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 687 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 688 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 689 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 690 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 691 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 692 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 693 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 694 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 695 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 696 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 697 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 698 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 699 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 700 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 701 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 702 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 703 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 704 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 705 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 706 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 707 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 708}; 709 710/* 711 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 712 * 713 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 714 * depend on longjmp() restoring a usable state. Restoring the state 715 * or examining it might fail if we didn't clear exceptions. 716 * 717 * The error code chosen will be one of the FPE_... macros. It will be 718 * sent as the second argument to old BSD-style signal handlers and as 719 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 720 * 721 * XXX the FP state is not preserved across signal handlers. So signal 722 * handlers cannot afford to do FP unless they preserve the state or 723 * longjmp() out. Both preserving the state and longjmp()ing may be 724 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 725 * solution for signals other than SIGFPE. 726 */ 727int 728npxtrap() 729{ 730 critical_t savecrit; 731 u_short control, status; 732 u_long *exstat; 733 734 if (!npx_exists) { 735 printf("npxtrap: npxthread = %p, curthread = %p, npx_exists = %d\n", 736 PCPU_GET(npxthread), curthread, npx_exists); 737 panic("npxtrap from nowhere"); 738 } 739 savecrit = critical_enter(); 740 741 /* 742 * Interrupt handling (for another interrupt) may have pushed the 743 * state to memory. Fetch the relevant parts of the state from 744 * wherever they are. 745 */ 746 if (PCPU_GET(npxthread) != curthread) { 747 control = GET_FPU_CW(curthread); 748 status = GET_FPU_SW(curthread); 749 } else { 750 fnstcw(&control); 751 fnstsw(&status); 752 } 753 754 exstat = GET_FPU_EXSW_PTR(curthread->td_pcb); 755 *exstat = status; 756 if (PCPU_GET(npxthread) != curthread) 757 GET_FPU_SW(curthread) &= ~0x80bf; 758 else 759 fnclex(); 760 critical_exit(savecrit); 761 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 762} 763 764/* 765 * Implement device not available (DNA) exception 766 * 767 * It would be better to switch FP context here (if curthread != npxthread) 768 * and not necessarily for every context switch, but it is too hard to 769 * access foreign pcb's. 770 */ 771int 772npxdna() 773{ 774 u_long *exstat; 775 critical_t s; 776 777 if (!npx_exists) 778 return (0); 779 if (PCPU_GET(npxthread) != NULL) { 780 printf("npxdna: npxthread = %p, curthread = %p\n", 781 PCPU_GET(npxthread), curthread); 782 panic("npxdna"); 783 } 784 s = critical_enter(); 785 stop_emulating(); 786 /* 787 * Record new context early in case frstor causes an IRQ13. 788 */ 789 PCPU_SET(npxthread, curthread); 790 791 exstat = GET_FPU_EXSW_PTR(PCPU_GET(curpcb)); 792 *exstat = 0; 793 /* 794 * The following frstor may cause an IRQ13 when the state being 795 * restored has a pending error. The error will appear to have been 796 * triggered by the current (npx) user instruction even when that 797 * instruction is a no-wait instruction that should not trigger an 798 * error (e.g., fnclex). On at least one 486 system all of the 799 * no-wait instructions are broken the same as frstor, so our 800 * treatment does not amplify the breakage. On at least one 801 * 386/Cyrix 387 system, fnclex works correctly while frstor and 802 * fnsave are broken, so our treatment breaks fnclex if it is the 803 * first FPU instruction after a context switch. 804 */ 805 fpurstor(&PCPU_GET(curpcb)->pcb_save); 806 critical_exit(s); 807 808 return (1); 809} 810 811/* 812 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 813 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 814 * no-wait npx instructions. See the Intel application note AP-578 for 815 * details. This doesn't cause any additional complications here. IRQ13's 816 * are inherently asynchronous unless the CPU is frozen to deliver them -- 817 * one that started in userland may be delivered many instructions later, 818 * after the process has entered the kernel. It may even be delivered after 819 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 820 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 821 * it is normally ignored at first because we set npxthread to NULL; it is 822 * normally retriggered in npxdna() after return to user mode. 823 * 824 * npxsave() must be called with interrupts disabled, so that it clears 825 * npxthread atomically with saving the state. We require callers to do the 826 * disabling, since most callers need to disable interrupts anyway to call 827 * npxsave() atomically with checking npxthread. 828 * 829 * A previous version of npxsave() went to great lengths to excecute fnsave 830 * with interrupts enabled in case executing it froze the CPU. This case 831 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 832 * spurious freezes. 833 */ 834void 835npxsave(addr) 836 union savefpu *addr; 837{ 838 839 stop_emulating(); 840 fpusave(addr); 841 842 start_emulating(); 843 PCPU_SET(npxthread, NULL); 844} 845 846static void 847fpusave(addr) 848 union savefpu *addr; 849{ 850 851#ifdef CPU_ENABLE_SSE 852 if (cpu_fxsr) 853 fxsave(addr); 854 else 855#endif 856 fnsave(addr); 857} 858 859static void 860fpurstor(addr) 861 union savefpu *addr; 862{ 863 864#ifdef CPU_ENABLE_SSE 865 if (cpu_fxsr) 866 fxrstor(addr); 867 else 868#endif 869 frstor(addr); 870} 871 872#ifdef I586_CPU_XXX 873static long 874timezero(funcname, func) 875 const char *funcname; 876 void (*func) __P((void *buf, size_t len)); 877 878{ 879 void *buf; 880#define BUFSIZE 1048576 881 long usec; 882 struct timeval finish, start; 883 884 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 885 if (buf == NULL) 886 return (BUFSIZE); 887 microtime(&start); 888 (*func)(buf, BUFSIZE); 889 microtime(&finish); 890 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 891 finish.tv_usec - start.tv_usec; 892 if (usec <= 0) 893 usec = 1; 894 if (bootverbose) 895 printf("%s bandwidth = %u kBps\n", funcname, 896 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 897 free(buf, M_TEMP); 898 return (usec); 899} 900#endif /* I586_CPU */ 901 902static device_method_t npx_methods[] = { 903 /* Device interface */ 904 DEVMETHOD(device_identify, npx_identify), 905 DEVMETHOD(device_probe, npx_probe), 906 DEVMETHOD(device_attach, npx_attach), 907 DEVMETHOD(device_detach, bus_generic_detach), 908 DEVMETHOD(device_shutdown, bus_generic_shutdown), 909 DEVMETHOD(device_suspend, bus_generic_suspend), 910 DEVMETHOD(device_resume, bus_generic_resume), 911 912 { 0, 0 } 913}; 914 915static driver_t npx_driver = { 916 "npx", 917 npx_methods, 918 1, /* no softc */ 919}; 920 921static devclass_t npx_devclass; 922 923/* 924 * We prefer to attach to the root nexus so that the usual case (exception 16) 925 * doesn't describe the processor as being `on isa'. 926 */ 927DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 928 929/* 930 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 931 */ 932static struct isa_pnp_id npxisa_ids[] = { 933 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 934 { 0 } 935}; 936 937static int 938npxisa_probe(device_t dev) 939{ 940 int result; 941 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 942 device_quiet(dev); 943 } 944 return(result); 945} 946 947static int 948npxisa_attach(device_t dev) 949{ 950 return (0); 951} 952 953static device_method_t npxisa_methods[] = { 954 /* Device interface */ 955 DEVMETHOD(device_probe, npxisa_probe), 956 DEVMETHOD(device_attach, npxisa_attach), 957 DEVMETHOD(device_detach, bus_generic_detach), 958 DEVMETHOD(device_shutdown, bus_generic_shutdown), 959 DEVMETHOD(device_suspend, bus_generic_suspend), 960 DEVMETHOD(device_resume, bus_generic_resume), 961 962 { 0, 0 } 963}; 964 965static driver_t npxisa_driver = { 966 "npxisa", 967 npxisa_methods, 968 1, /* no softc */ 969}; 970 971static devclass_t npxisa_devclass; 972 973DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 974DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 975 976