fpu.c revision 79609
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 79609 2001-07-12 06:32:51Z peter $ 36 */ 37 38#include "opt_cpu.h" 39#include "opt_debug_npx.h" 40#include "opt_math_emulate.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/malloc.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/mutex.h> 51#include <sys/proc.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59#include <sys/user.h> 60 61#ifndef SMP 62#include <machine/asmacros.h> 63#endif 64#include <machine/cputypes.h> 65#include <machine/frame.h> 66#include <machine/md_var.h> 67#include <machine/pcb.h> 68#include <machine/psl.h> 69#ifndef SMP 70#include <machine/clock.h> 71#endif 72#include <machine/resource.h> 73#include <machine/specialreg.h> 74#include <machine/segments.h> 75 76#ifndef SMP 77#include <i386/isa/icu.h> 78#include <i386/isa/intr_machdep.h> 79#include <i386/isa/isa.h> 80#endif 81#include <isa/isavar.h> 82 83/* 84 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 85 */ 86 87/* Configuration flags. */ 88#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 89#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 90#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 91#define NPX_PREFER_EMULATOR (1 << 3) 92 93#ifdef __GNUC__ 94 95#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 96#define fnclex() __asm("fnclex") 97#define fninit() __asm("fninit") 98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 103#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 104#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 105#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 106 : : "n" (CR0_TS) : "ax") 107#define stop_emulating() __asm("clts") 108 109#else /* not __GNUC__ */ 110 111void fldcw __P((caddr_t addr)); 112void fnclex __P((void)); 113void fninit __P((void)); 114void fnsave __P((caddr_t addr)); 115void fnstcw __P((caddr_t addr)); 116void fnstsw __P((caddr_t addr)); 117void fp_divide_by_0 __P((void)); 118void frstor __P((caddr_t addr)); 119void fxsave __P((caddr_t addr)); 120void fxrstor __P((caddr_t addr)); 121void start_emulating __P((void)); 122void stop_emulating __P((void)); 123 124#endif /* __GNUC__ */ 125 126#ifdef CPU_ENABLE_SSE 127#define GET_FPU_CW(proc) \ 128 (cpu_fxsr ? \ 129 (proc)->p_addr->u_pcb.pcb_save.sv_xmm.sv_env.en_cw : \ 130 (proc)->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_cw) 131#define GET_FPU_SW(proc) \ 132 (cpu_fxsr ? \ 133 (proc)->p_addr->u_pcb.pcb_save.sv_xmm.sv_env.en_sw : \ 134 (proc)->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_sw) 135#define MASK_FPU_SW(proc, mask) \ 136 (cpu_fxsr ? \ 137 (proc)->p_addr->u_pcb.pcb_save.sv_xmm.sv_env.en_sw & (mask) : \ 138 (proc)->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_sw & (mask)) 139#define GET_FPU_EXSW_PTR(pcb) \ 140 (cpu_fxsr ? \ 141 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ 142 &(pcb)->pcb_save.sv_87.sv_ex_sw) 143#else /* CPU_ENABLE_SSE */ 144#define GET_FPU_CW(proc) \ 145 (proc->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_cw) 146#define GET_FPU_SW(proc) \ 147 (proc->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_sw) 148#define MASK_FPU_SW(proc, mask) \ 149 ((proc)->p_addr->u_pcb.pcb_save.sv_87.sv_env.en_sw & (mask)) 150#define GET_FPU_EXSW_PTR(pcb) \ 151 (&(pcb)->pcb_save.sv_87.sv_ex_sw) 152#endif /* CPU_ENABLE_SSE */ 153 154typedef u_char bool_t; 155 156static int npx_attach __P((device_t dev)); 157static void npx_identify __P((driver_t *driver, device_t parent)); 158#ifndef SMP 159static void npx_intr __P((void *)); 160#endif 161static int npx_probe __P((device_t dev)); 162static int npx_probe1 __P((device_t dev)); 163static void fpusave __P((union savefpu *, u_char)); 164static void fpurstor __P((union savefpu *, u_char)); 165#ifdef I586_CPU_XXX 166static long timezero __P((const char *funcname, 167 void (*func)(void *buf, size_t len))); 168#endif /* I586_CPU */ 169 170int hw_float; /* XXX currently just alias for npx_exists */ 171 172SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 173 CTLFLAG_RD, &hw_float, 0, 174 "Floatingpoint instructions executed in hardware"); 175 176#ifndef SMP 177static volatile u_int npx_intrs_while_probing; 178static volatile u_int npx_traps_while_probing; 179#endif 180 181static bool_t npx_ex16; 182static bool_t npx_exists; 183static bool_t npx_irq13; 184static int npx_irq; /* irq number */ 185 186#ifndef SMP 187/* 188 * Special interrupt handlers. Someday intr0-intr15 will be used to count 189 * interrupts. We'll still need a special exception 16 handler. The busy 190 * latch stuff in probeintr() can be moved to npxprobe(). 191 */ 192inthand_t probeintr; 193__asm(" \n\ 194 .text \n\ 195 .p2align 2,0x90 \n\ 196 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 197" __XSTRING(CNAME(probeintr)) ": \n\ 198 ss \n\ 199 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 200 pushl %eax \n\ 201 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 202 outb %al,$0xa0 # IO_ICU2 \n\ 203 outb %al,$0x20 # IO_ICU1 \n\ 204 movb $0,%al \n\ 205 outb %al,$0xf0 # clear BUSY# latch \n\ 206 popl %eax \n\ 207 iret \n\ 208"); 209 210inthand_t probetrap; 211__asm(" \n\ 212 .text \n\ 213 .p2align 2,0x90 \n\ 214 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 215" __XSTRING(CNAME(probetrap)) ": \n\ 216 ss \n\ 217 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 218 fnclex \n\ 219 iret \n\ 220"); 221#endif /* SMP */ 222 223/* 224 * Identify routine. Create a connection point on our parent for probing. 225 */ 226static void 227npx_identify(driver, parent) 228 driver_t *driver; 229 device_t parent; 230{ 231 device_t child; 232 233 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 234 if (child == NULL) 235 panic("npx_identify"); 236} 237 238#ifndef SMP 239/* 240 * Do minimal handling of npx interrupts to convert them to traps. 241 */ 242static void 243npx_intr(dummy) 244 void *dummy; 245{ 246 struct proc *p; 247 248 /* 249 * The BUSY# latch must be cleared in all cases so that the next 250 * unmasked npx exception causes an interrupt. 251 */ 252 outb(0xf0, 0); 253 254 /* 255 * npxproc is normally non-null here. In that case, schedule an 256 * AST to finish the exception handling in the correct context 257 * (this interrupt may occur after the process has entered the 258 * kernel via a syscall or an interrupt). Otherwise, the npx 259 * state of the process that caused this interrupt must have been 260 * pushed to the process' pcb, and clearing of the busy latch 261 * above has finished the (essentially null) handling of this 262 * interrupt. Control will eventually return to the instruction 263 * that caused it and it will repeat. We will eventually (usually 264 * soon) win the race to handle the interrupt properly. 265 */ 266 p = PCPU_GET(npxproc); 267 if (p != NULL) { 268 p->p_addr->u_pcb.pcb_flags |= PCB_NPXTRAP; 269 mtx_lock_spin(&sched_lock); 270 aston(p); 271 mtx_unlock_spin(&sched_lock); 272 } 273} 274 275/* 276 * XXX these "local" variables of npx_probe() are non-local so that 277 * npxprobe1() can abuse them. 278 */ 279static int npx_intrno; 280static struct gate_descriptor save_idt_npxintr; 281#endif /* !SMP */ 282 283/* 284 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 285 * whether the device exists or not (XXX should be elsewhere). Set flags 286 * to tell npxattach() what to do. Modify device struct if npx doesn't 287 * need to use interrupts. Return 1 if device exists. 288 */ 289static int 290npx_probe(dev) 291 device_t dev; 292{ 293#ifdef SMP 294 295 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 296 npx_irq = 13; 297 return npx_probe1(dev); 298 299#else /* SMP */ 300 301 int result; 302 critical_t savecrit; 303 u_char save_icu1_mask; 304 u_char save_icu2_mask; 305 struct gate_descriptor save_idt_npxtrap; 306 /* 307 * This routine is now just a wrapper for npxprobe1(), to install 308 * special npx interrupt and trap handlers, to enable npx interrupts 309 * and to disable other interrupts. Someday isa_configure() will 310 * install suitable handlers and run with interrupts enabled so we 311 * won't need to do so much here. 312 */ 313 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 314 npx_irq = 13; 315 npx_intrno = NRSVIDT + npx_irq; 316 savecrit = critical_enter(); 317 save_icu1_mask = inb(IO_ICU1 + 1); 318 save_icu2_mask = inb(IO_ICU2 + 1); 319 save_idt_npxintr = idt[npx_intrno]; 320 save_idt_npxtrap = idt[16]; 321 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 322 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 323 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 324 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 325 326 /* 327 * XXX This looks highly bogus, but it appears that npc_probe1 328 * needs interrupts enabled. Does this make any difference 329 * here? 330 */ 331 critical_exit(savecrit); 332 result = npx_probe1(dev); 333 savecrit = critical_enter(); 334 outb(IO_ICU1 + 1, save_icu1_mask); 335 outb(IO_ICU2 + 1, save_icu2_mask); 336 idt[npx_intrno] = save_idt_npxintr; 337 idt[16] = save_idt_npxtrap; 338 critical_exit(savecrit); 339 return (result); 340 341#endif /* SMP */ 342} 343 344static int 345npx_probe1(dev) 346 device_t dev; 347{ 348#ifndef SMP 349 u_short control; 350 u_short status; 351#endif 352 353 /* 354 * Partially reset the coprocessor, if any. Some BIOS's don't reset 355 * it after a warm boot. 356 */ 357 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 358 outb(0xf0, 0); /* clear BUSY# latch */ 359 /* 360 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 361 * instructions. We must set the CR0_MP bit and use the CR0_TS 362 * bit to control the trap, because setting the CR0_EM bit does 363 * not cause WAIT instructions to trap. It's important to trap 364 * WAIT instructions - otherwise the "wait" variants of no-wait 365 * control instructions would degenerate to the "no-wait" variants 366 * after FP context switches but work correctly otherwise. It's 367 * particularly important to trap WAITs when there is no NPX - 368 * otherwise the "wait" variants would always degenerate. 369 * 370 * Try setting CR0_NE to get correct error reporting on 486DX's. 371 * Setting it should fail or do nothing on lesser processors. 372 */ 373 load_cr0(rcr0() | CR0_MP | CR0_NE); 374 /* 375 * But don't trap while we're probing. 376 */ 377 stop_emulating(); 378 /* 379 * Finish resetting the coprocessor, if any. If there is an error 380 * pending, then we may get a bogus IRQ13, but probeintr() will handle 381 * it OK. Bogus halts have never been observed, but we enabled 382 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 383 */ 384 fninit(); 385 386#ifdef SMP 387 /* 388 * Exception 16 MUST work for SMP. 389 */ 390 npx_irq13 = 0; 391 npx_ex16 = hw_float = npx_exists = 1; 392 device_set_desc(dev, "math processor"); 393 return (0); 394 395#else /* !SMP */ 396 device_set_desc(dev, "math processor"); 397 398 /* 399 * Don't use fwait here because it might hang. 400 * Don't use fnop here because it usually hangs if there is no FPU. 401 */ 402 DELAY(1000); /* wait for any IRQ13 */ 403#ifdef DIAGNOSTIC 404 if (npx_intrs_while_probing != 0) 405 printf("fninit caused %u bogus npx interrupt(s)\n", 406 npx_intrs_while_probing); 407 if (npx_traps_while_probing != 0) 408 printf("fninit caused %u bogus npx trap(s)\n", 409 npx_traps_while_probing); 410#endif 411 /* 412 * Check for a status of mostly zero. 413 */ 414 status = 0x5a5a; 415 fnstsw(&status); 416 if ((status & 0xb8ff) == 0) { 417 /* 418 * Good, now check for a proper control word. 419 */ 420 control = 0x5a5a; 421 fnstcw(&control); 422 if ((control & 0x1f3f) == 0x033f) { 423 hw_float = npx_exists = 1; 424 /* 425 * We have an npx, now divide by 0 to see if exception 426 * 16 works. 427 */ 428 control &= ~(1 << 2); /* enable divide by 0 trap */ 429 fldcw(&control); 430 npx_traps_while_probing = npx_intrs_while_probing = 0; 431 fp_divide_by_0(); 432 if (npx_traps_while_probing != 0) { 433 /* 434 * Good, exception 16 works. 435 */ 436 npx_ex16 = 1; 437 return (0); 438 } 439 if (npx_intrs_while_probing != 0) { 440 int rid; 441 struct resource *r; 442 void *intr; 443 /* 444 * Bad, we are stuck with IRQ13. 445 */ 446 npx_irq13 = 1; 447 448 /* 449 * We allocate these resources permanently, 450 * so there is no need to keep track of them. 451 */ 452 rid = 0; 453 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 454 &rid, IO_NPX, IO_NPX, 455 IO_NPXSIZE, RF_ACTIVE); 456 if (r == 0) 457 panic("npx: can't get ports"); 458 rid = 0; 459 r = bus_alloc_resource(dev, SYS_RES_IRQ, 460 &rid, npx_irq, npx_irq, 461 1, RF_ACTIVE); 462 if (r == 0) 463 panic("npx: can't get IRQ"); 464 BUS_SETUP_INTR(device_get_parent(dev), 465 dev, r, 466 INTR_TYPE_MISC | INTR_FAST, 467 npx_intr, 0, &intr); 468 if (intr == 0) 469 panic("npx: can't create intr"); 470 471 /* 472 * XXX BUS_SETUP_INTR() has changed 473 * idt[npx_intrno] to point to Xfastintr0 474 * instead of Xfastintr0. Adjust 475 * save_idt_npxintr so that npxprobe() 476 * doesn't undo this. 477 */ 478 save_idt_npxintr = idt[npx_intrno]; 479 480 return (0); 481 } 482 /* 483 * Worse, even IRQ13 is broken. Use emulator. 484 */ 485 } 486 } 487 /* 488 * Probe failed, but we want to get to npxattach to initialize the 489 * emulator and say that it has been installed. XXX handle devices 490 * that aren't really devices better. 491 */ 492 return (0); 493#endif /* SMP */ 494} 495 496/* 497 * Attach routine - announce which it is, and wire into system 498 */ 499int 500npx_attach(dev) 501 device_t dev; 502{ 503 int flags; 504 505 if (resource_int_value("npx", 0, "flags", &flags) != 0) 506 flags = 0; 507 508 if (flags) 509 device_printf(dev, "flags 0x%x ", flags); 510 if (npx_irq13) { 511 device_printf(dev, "using IRQ 13 interface\n"); 512 } else { 513#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 514 if (npx_ex16) { 515 if (!(flags & NPX_PREFER_EMULATOR)) 516 device_printf(dev, "INT 16 interface\n"); 517 else { 518 device_printf(dev, "FPU exists, but flags request " 519 "emulator\n"); 520 hw_float = npx_exists = 0; 521 } 522 } else if (npx_exists) { 523 device_printf(dev, "error reporting broken; using 387 emulator\n"); 524 hw_float = npx_exists = 0; 525 } else 526 device_printf(dev, "387 emulator\n"); 527#else 528 if (npx_ex16) { 529 device_printf(dev, "INT 16 interface\n"); 530 if (flags & NPX_PREFER_EMULATOR) { 531 device_printf(dev, "emulator requested, but none compiled " 532 "into kernel, using FPU\n"); 533 } 534 } else 535 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 536#endif 537 } 538 npxinit(__INITIAL_NPXCW__); 539 540#ifdef I586_CPU_XXX 541 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 542 timezero("i586_bzero()", i586_bzero) < 543 timezero("bzero()", bzero) * 4 / 5) { 544 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 545 bcopy_vector = i586_bcopy; 546 ovbcopy_vector = i586_bcopy; 547 } 548 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 549 bzero = i586_bzero; 550 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 551 copyin_vector = i586_copyin; 552 copyout_vector = i586_copyout; 553 } 554 } 555#endif 556 557 return (0); /* XXX unused */ 558} 559 560/* 561 * Initialize floating point unit. 562 */ 563void 564npxinit(control) 565 u_short control; 566{ 567 union savefpu dummy; 568 critical_t savecrit; 569 570 if (!npx_exists) 571 return; 572 /* 573 * fninit has the same h/w bugs as fnsave. Use the detoxified 574 * fnsave to throw away any junk in the fpu. npxsave() initializes 575 * the fpu and sets npxproc = NULL as important side effects. 576 */ 577 savecrit = critical_enter(); 578 npxsave(&dummy); 579 stop_emulating(); 580 fldcw(&control); 581 if (PCPU_GET(curpcb) != NULL) 582 fpusave(&PCPU_GET(curpcb)->pcb_save, curproc->p_oncpu); 583 start_emulating(); 584 critical_exit(savecrit); 585} 586 587/* 588 * Free coprocessor (if we have it). 589 */ 590void 591npxexit(p) 592 struct proc *p; 593{ 594 critical_t savecrit; 595 596 savecrit = critical_enter(); 597 if (p == PCPU_GET(npxproc)) 598 npxsave(&PCPU_GET(curpcb)->pcb_save); 599 critical_exit(savecrit); 600#ifdef NPX_DEBUG 601 if (npx_exists) { 602 u_int masked_exceptions; 603 604 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 605 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 606 /* 607 * Log exceptions that would have trapped with the old 608 * control word (overflow, divide by 0, and invalid operand). 609 */ 610 if (masked_exceptions & 0x0d) 611 log(LOG_ERR, 612 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 613 p->p_pid, p->p_comm, masked_exceptions); 614 } 615#endif 616} 617 618/* 619 * The following mechanism is used to ensure that the FPE_... value 620 * that is passed as a trapcode to the signal handler of the user 621 * process does not have more than one bit set. 622 * 623 * Multiple bits may be set if the user process modifies the control 624 * word while a status word bit is already set. While this is a sign 625 * of bad coding, we have no choise than to narrow them down to one 626 * bit, since we must not send a trapcode that is not exactly one of 627 * the FPE_ macros. 628 * 629 * The mechanism has a static table with 127 entries. Each combination 630 * of the 7 FPU status word exception bits directly translates to a 631 * position in this table, where a single FPE_... value is stored. 632 * This FPE_... value stored there is considered the "most important" 633 * of the exception bits and will be sent as the signal code. The 634 * precedence of the bits is based upon Intel Document "Numerical 635 * Applications", Chapter "Special Computational Situations". 636 * 637 * The macro to choose one of these values does these steps: 1) Throw 638 * away status word bits that cannot be masked. 2) Throw away the bits 639 * currently masked in the control word, assuming the user isn't 640 * interested in them anymore. 3) Reinsert status word bit 7 (stack 641 * fault) if it is set, which cannot be masked but must be presered. 642 * 4) Use the remaining bits to point into the trapcode table. 643 * 644 * The 6 maskable bits in order of their preference, as stated in the 645 * above referenced Intel manual: 646 * 1 Invalid operation (FP_X_INV) 647 * 1a Stack underflow 648 * 1b Stack overflow 649 * 1c Operand of unsupported format 650 * 1d SNaN operand. 651 * 2 QNaN operand (not an exception, irrelavant here) 652 * 3 Any other invalid-operation not mentioned above or zero divide 653 * (FP_X_INV, FP_X_DZ) 654 * 4 Denormal operand (FP_X_DNML) 655 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 656 * 6 Inexact result (FP_X_IMP) 657 */ 658static char fpetable[128] = { 659 0, 660 FPE_FLTINV, /* 1 - INV */ 661 FPE_FLTUND, /* 2 - DNML */ 662 FPE_FLTINV, /* 3 - INV | DNML */ 663 FPE_FLTDIV, /* 4 - DZ */ 664 FPE_FLTINV, /* 5 - INV | DZ */ 665 FPE_FLTDIV, /* 6 - DNML | DZ */ 666 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 667 FPE_FLTOVF, /* 8 - OFL */ 668 FPE_FLTINV, /* 9 - INV | OFL */ 669 FPE_FLTUND, /* A - DNML | OFL */ 670 FPE_FLTINV, /* B - INV | DNML | OFL */ 671 FPE_FLTDIV, /* C - DZ | OFL */ 672 FPE_FLTINV, /* D - INV | DZ | OFL */ 673 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 674 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 675 FPE_FLTUND, /* 10 - UFL */ 676 FPE_FLTINV, /* 11 - INV | UFL */ 677 FPE_FLTUND, /* 12 - DNML | UFL */ 678 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 679 FPE_FLTDIV, /* 14 - DZ | UFL */ 680 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 681 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 682 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 683 FPE_FLTOVF, /* 18 - OFL | UFL */ 684 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 685 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 686 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 687 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 688 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 689 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 690 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 691 FPE_FLTRES, /* 20 - IMP */ 692 FPE_FLTINV, /* 21 - INV | IMP */ 693 FPE_FLTUND, /* 22 - DNML | IMP */ 694 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 695 FPE_FLTDIV, /* 24 - DZ | IMP */ 696 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 697 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 698 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 699 FPE_FLTOVF, /* 28 - OFL | IMP */ 700 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 701 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 702 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 703 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 704 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 705 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 706 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 707 FPE_FLTUND, /* 30 - UFL | IMP */ 708 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 709 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 710 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 711 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 712 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 713 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 714 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 715 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 716 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 717 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 718 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 719 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 720 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 721 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 722 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 723 FPE_FLTSUB, /* 40 - STK */ 724 FPE_FLTSUB, /* 41 - INV | STK */ 725 FPE_FLTUND, /* 42 - DNML | STK */ 726 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 727 FPE_FLTDIV, /* 44 - DZ | STK */ 728 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 729 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 730 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 731 FPE_FLTOVF, /* 48 - OFL | STK */ 732 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 733 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 734 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 735 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 736 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 737 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 738 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 739 FPE_FLTUND, /* 50 - UFL | STK */ 740 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 741 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 742 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 743 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 744 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 745 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 746 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 747 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 748 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 749 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 750 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 751 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 752 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 753 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 754 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 755 FPE_FLTRES, /* 60 - IMP | STK */ 756 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 757 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 758 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 759 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 760 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 761 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 762 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 763 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 764 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 765 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 766 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 767 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 768 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 769 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 770 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 771 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 772 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 773 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 774 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 775 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 776 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 777 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 778 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 779 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 780 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 781 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 782 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 783 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 784 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 785 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 786 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 787}; 788 789/* 790 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 791 * 792 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 793 * depend on longjmp() restoring a usable state. Restoring the state 794 * or examining it might fail if we didn't clear exceptions. 795 * 796 * The error code chosen will be one of the FPE_... macros. It will be 797 * sent as the second argument to old BSD-style signal handlers and as 798 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 799 * 800 * XXX the FP state is not preserved across signal handlers. So signal 801 * handlers cannot afford to do FP unless they preserve the state or 802 * longjmp() out. Both preserving the state and longjmp()ing may be 803 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 804 * solution for signals other than SIGFPE. 805 */ 806int 807npxtrap() 808{ 809 critical_t savecrit; 810 u_short control, status; 811 u_long *exstat; 812 813 if (!npx_exists) { 814 printf("npxtrap: npxproc = %p, curproc = %p, npx_exists = %d\n", 815 PCPU_GET(npxproc), curproc, npx_exists); 816 panic("npxtrap from nowhere"); 817 } 818 savecrit = critical_enter(); 819 820 /* 821 * Interrupt handling (for another interrupt) may have pushed the 822 * state to memory. Fetch the relevant parts of the state from 823 * wherever they are. 824 */ 825 if (PCPU_GET(npxproc) != curproc) { 826 control = GET_FPU_CW(curproc); 827 status = GET_FPU_SW(curproc); 828 } else { 829 fnstcw(&control); 830 fnstsw(&status); 831 } 832 833 exstat = GET_FPU_EXSW_PTR(&curproc->p_addr->u_pcb); 834 *exstat = status; 835 if (PCPU_GET(npxproc) != curproc) 836 MASK_FPU_SW(curproc, ~0x80bf); 837 else 838 fnclex(); 839 critical_exit(savecrit); 840 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 841} 842 843/* 844 * Implement device not available (DNA) exception 845 * 846 * It would be better to switch FP context here (if curproc != npxproc) 847 * and not necessarily for every context switch, but it is too hard to 848 * access foreign pcb's. 849 */ 850int 851npxdna() 852{ 853 u_long *exstat; 854 critical_t s; 855 856 if (!npx_exists) 857 return (0); 858 if (PCPU_GET(npxproc) != NULL) { 859 printf("npxdna: npxproc = %p, curproc = %p\n", 860 PCPU_GET(npxproc), curproc); 861 panic("npxdna"); 862 } 863 s = critical_enter(); 864 stop_emulating(); 865 /* 866 * Record new context early in case frstor causes an IRQ13. 867 */ 868 PCPU_SET(npxproc, CURPROC); 869 870 exstat = GET_FPU_EXSW_PTR(PCPU_GET(curpcb)); 871 *exstat = 0; 872 /* 873 * The following frstor may cause an IRQ13 when the state being 874 * restored has a pending error. The error will appear to have been 875 * triggered by the current (npx) user instruction even when that 876 * instruction is a no-wait instruction that should not trigger an 877 * error (e.g., fnclex). On at least one 486 system all of the 878 * no-wait instructions are broken the same as frstor, so our 879 * treatment does not amplify the breakage. On at least one 880 * 386/Cyrix 387 system, fnclex works correctly while frstor and 881 * fnsave are broken, so our treatment breaks fnclex if it is the 882 * first FPU instruction after a context switch. 883 */ 884 fpurstor(&PCPU_GET(curpcb)->pcb_save, curproc->p_oncpu); 885 critical_exit(s); 886 887 return (1); 888} 889 890/* 891 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 892 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 893 * no-wait npx instructions. See the Intel application note AP-578 for 894 * details. This doesn't cause any additional complications here. IRQ13's 895 * are inherently asynchronous unless the CPU is frozen to deliver them -- 896 * one that started in userland may be delivered many instructions later, 897 * after the process has entered the kernel. It may even be delivered after 898 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 899 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 900 * it is normally ignored at first because we set npxproc to NULL; it is 901 * normally retriggered in npxdna() after return to user mode. 902 * 903 * npxsave() must be called with interrupts disabled, so that it clears 904 * npxproc atomically with saving the state. We require callers to do the 905 * disabling, since most callers need to disable interrupts anyway to call 906 * npxsave() atomically with checking npxproc. 907 * 908 * A previous version of npxsave() went to great lengths to excecute fnsave 909 * with interrupts enabled in case executing it froze the CPU. This case 910 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 911 * spurious freezes. 912 */ 913void 914npxsave(addr) 915 union savefpu *addr; 916{ 917 918 stop_emulating(); 919 fpusave(addr, curproc->p_oncpu); 920 921 start_emulating(); 922 PCPU_SET(npxproc, NULL); 923} 924 925static void 926fpusave(addr, oncpu) 927 union savefpu *addr; 928 u_char oncpu; 929{ 930 static struct savexmm svxmm[MAXCPU]; 931 932 if (!cpu_fxsr) 933 fnsave(addr); 934 else { 935 fxsave(&svxmm[oncpu]); 936 bcopy(&svxmm[oncpu], addr, sizeof(struct savexmm)); 937 } 938} 939 940static void 941fpurstor(addr, oncpu) 942 union savefpu *addr; 943 u_char oncpu; 944{ 945 static struct savexmm svxmm[MAXCPU]; 946 947 if (!cpu_fxsr) 948 frstor(addr); 949 else { 950 bcopy(addr, &svxmm[oncpu], sizeof (struct savexmm)); 951 fxrstor(&svxmm[oncpu]); 952 } 953} 954 955#ifdef I586_CPU_XXX 956static long 957timezero(funcname, func) 958 const char *funcname; 959 void (*func) __P((void *buf, size_t len)); 960 961{ 962 void *buf; 963#define BUFSIZE 1048576 964 long usec; 965 struct timeval finish, start; 966 967 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 968 if (buf == NULL) 969 return (BUFSIZE); 970 microtime(&start); 971 (*func)(buf, BUFSIZE); 972 microtime(&finish); 973 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 974 finish.tv_usec - start.tv_usec; 975 if (usec <= 0) 976 usec = 1; 977 if (bootverbose) 978 printf("%s bandwidth = %u kBps\n", funcname, 979 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 980 free(buf, M_TEMP); 981 return (usec); 982} 983#endif /* I586_CPU */ 984 985static device_method_t npx_methods[] = { 986 /* Device interface */ 987 DEVMETHOD(device_identify, npx_identify), 988 DEVMETHOD(device_probe, npx_probe), 989 DEVMETHOD(device_attach, npx_attach), 990 DEVMETHOD(device_detach, bus_generic_detach), 991 DEVMETHOD(device_shutdown, bus_generic_shutdown), 992 DEVMETHOD(device_suspend, bus_generic_suspend), 993 DEVMETHOD(device_resume, bus_generic_resume), 994 995 { 0, 0 } 996}; 997 998static driver_t npx_driver = { 999 "npx", 1000 npx_methods, 1001 1, /* no softc */ 1002}; 1003 1004static devclass_t npx_devclass; 1005 1006/* 1007 * We prefer to attach to the root nexus so that the usual case (exception 16) 1008 * doesn't describe the processor as being `on isa'. 1009 */ 1010DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1011 1012/* 1013 * This sucks up the legacy ISA support assignments from PNPBIOS. 1014 */ 1015static struct isa_pnp_id npxisa_ids[] = { 1016 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1017 { 0 } 1018}; 1019 1020static int 1021npxisa_probe(device_t dev) 1022{ 1023 int result; 1024 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1025 device_quiet(dev); 1026 } 1027 return(result); 1028} 1029 1030static int 1031npxisa_attach(device_t dev) 1032{ 1033 return (0); 1034} 1035 1036static device_method_t npxisa_methods[] = { 1037 /* Device interface */ 1038 DEVMETHOD(device_probe, npxisa_probe), 1039 DEVMETHOD(device_attach, npxisa_attach), 1040 DEVMETHOD(device_detach, bus_generic_detach), 1041 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1042 DEVMETHOD(device_suspend, bus_generic_suspend), 1043 DEVMETHOD(device_resume, bus_generic_resume), 1044 1045 { 0, 0 } 1046}; 1047 1048static driver_t npxisa_driver = { 1049 "npxisa", 1050 npxisa_methods, 1051 1, /* no softc */ 1052}; 1053 1054static devclass_t npxisa_devclass; 1055 1056DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1057 1058