fpu.c revision 71249
1166124Srafan/*-
2166124Srafan * Copyright (c) 1990 William Jolitz.
3166124Srafan * Copyright (c) 1991 The Regents of the University of California.
4166124Srafan * All rights reserved.
5166124Srafan *
6166124Srafan * Redistribution and use in source and binary forms, with or without
7166124Srafan * modification, are permitted provided that the following conditions
8166124Srafan * are met:
9166124Srafan * 1. Redistributions of source code must retain the above copyright
10166124Srafan *    notice, this list of conditions and the following disclaimer.
11166124Srafan * 2. Redistributions in binary form must reproduce the above copyright
12166124Srafan *    notice, this list of conditions and the following disclaimer in the
13166124Srafan *    documentation and/or other materials provided with the distribution.
14166124Srafan * 3. All advertising materials mentioning features or use of this software
15166124Srafan *    must display the following acknowledgement:
16166124Srafan *	This product includes software developed by the University of
17166124Srafan *	California, Berkeley and its contributors.
18166124Srafan * 4. Neither the name of the University nor the names of its contributors
19166124Srafan *    may be used to endorse or promote products derived from this software
20166124Srafan *    without specific prior written permission.
21166124Srafan *
22166124Srafan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23166124Srafan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24166124Srafan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25166124Srafan * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26166124Srafan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27166124Srafan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28166124Srafan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29166124Srafan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
3050276Speter * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
3150276Speter * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
3250276Speter * SUCH DAMAGE.
3350276Speter *
3450276Speter *	from: @(#)npx.c	7.2 (Berkeley) 5/12/91
3550276Speter * $FreeBSD: head/sys/amd64/amd64/fpu.c 71249 2001-01-19 11:43:13Z jhb $
3650276Speter */
37
38#include "opt_debug_npx.h"
39#include "opt_math_emulate.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/ipl.h>
45#include <sys/kernel.h>
46#include <sys/malloc.h>
47#include <sys/module.h>
48#include <sys/sysctl.h>
49#include <sys/proc.h>
50#include <machine/bus.h>
51#include <sys/rman.h>
52#ifdef NPX_DEBUG
53#include <sys/syslog.h>
54#endif
55#include <sys/signalvar.h>
56
57#ifndef SMP
58#include <machine/asmacros.h>
59#endif
60#include <machine/cputypes.h>
61#include <machine/frame.h>
62#include <machine/md_var.h>
63#include <machine/pcb.h>
64#include <machine/psl.h>
65#ifndef SMP
66#include <machine/clock.h>
67#endif
68#include <machine/resource.h>
69#include <machine/specialreg.h>
70#include <machine/segments.h>
71
72#ifndef SMP
73#include <i386/isa/icu.h>
74#include <i386/isa/intr_machdep.h>
75#include <i386/isa/isa.h>
76#endif
77#include <isa/isavar.h>
78
79/*
80 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
81 */
82
83/* Configuration flags. */
84#define	NPX_DISABLE_I586_OPTIMIZED_BCOPY	(1 << 0)
85#define	NPX_DISABLE_I586_OPTIMIZED_BZERO	(1 << 1)
86#define	NPX_DISABLE_I586_OPTIMIZED_COPYIO	(1 << 2)
87#define	NPX_PREFER_EMULATOR			(1 << 3)
88
89#ifdef	__GNUC__
90
91#define	fldcw(addr)		__asm("fldcw %0" : : "m" (*(addr)))
92#define	fnclex()		__asm("fnclex")
93#define	fninit()		__asm("fninit")
94#define	fnop()			__asm("fnop")
95#define	fnsave(addr)		__asm __volatile("fnsave %0" : "=m" (*(addr)))
96#define	fnstcw(addr)		__asm __volatile("fnstcw %0" : "=m" (*(addr)))
97#define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=m" (*(addr)))
98#define	fp_divide_by_0()	__asm("fldz; fld1; fdiv %st,%st(1); fnop")
99#define	frstor(addr)		__asm("frstor %0" : : "m" (*(addr)))
100#define	start_emulating()	__asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
101				      : : "n" (CR0_TS) : "ax")
102#define	stop_emulating()	__asm("clts")
103
104#else	/* not __GNUC__ */
105
106void	fldcw		__P((caddr_t addr));
107void	fnclex		__P((void));
108void	fninit		__P((void));
109void	fnop		__P((void));
110void	fnsave		__P((caddr_t addr));
111void	fnstcw		__P((caddr_t addr));
112void	fnstsw		__P((caddr_t addr));
113void	fp_divide_by_0	__P((void));
114void	frstor		__P((caddr_t addr));
115void	start_emulating	__P((void));
116void	stop_emulating	__P((void));
117
118#endif	/* __GNUC__ */
119
120typedef u_char bool_t;
121
122static	int	npx_attach	__P((device_t dev));
123	void	npx_intr	__P((void *));
124static	void	npx_identify	__P((driver_t *driver, device_t parent));
125static	int	npx_probe	__P((device_t dev));
126static	int	npx_probe1	__P((device_t dev));
127#ifdef I586_CPU
128static	long	timezero	__P((const char *funcname,
129				     void (*func)(void *buf, size_t len)));
130#endif /* I586_CPU */
131
132int	hw_float;		/* XXX currently just alias for npx_exists */
133
134SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
135	CTLFLAG_RD, &hw_float, 0,
136	"Floatingpoint instructions executed in hardware");
137
138#ifndef SMP
139static	u_int			npx0_imask = 0;
140static	struct gate_descriptor	npx_idt_probeintr;
141static	int			npx_intrno;
142static	volatile u_int		npx_intrs_while_probing;
143static	volatile u_int		npx_traps_while_probing;
144#endif
145
146static	bool_t			npx_ex16;
147static	bool_t			npx_exists;
148static	bool_t			npx_irq13;
149static	int			npx_irq;	/* irq number */
150
151#ifndef SMP
152/*
153 * Special interrupt handlers.  Someday intr0-intr15 will be used to count
154 * interrupts.  We'll still need a special exception 16 handler.  The busy
155 * latch stuff in probeintr() can be moved to npxprobe().
156 */
157inthand_t probeintr;
158__asm("								\n\
159	.text							\n\
160	.p2align 2,0x90						\n\
161	.type	" __XSTRING(CNAME(probeintr)) ",@function	\n\
162" __XSTRING(CNAME(probeintr)) ":				\n\
163	ss							\n\
164	incl	" __XSTRING(CNAME(npx_intrs_while_probing)) "	\n\
165	pushl	%eax						\n\
166	movb	$0x20,%al	# EOI (asm in strings loses cpp features) \n\
167	outb	%al,$0xa0	# IO_ICU2			\n\
168	outb	%al,$0x20	# IO_ICU1			\n\
169	movb	$0,%al						\n\
170	outb	%al,$0xf0	# clear BUSY# latch		\n\
171	popl	%eax						\n\
172	iret							\n\
173");
174
175inthand_t probetrap;
176__asm("								\n\
177	.text							\n\
178	.p2align 2,0x90						\n\
179	.type	" __XSTRING(CNAME(probetrap)) ",@function	\n\
180" __XSTRING(CNAME(probetrap)) ":				\n\
181	ss							\n\
182	incl	" __XSTRING(CNAME(npx_traps_while_probing)) "	\n\
183	fnclex							\n\
184	iret							\n\
185");
186#endif /* SMP */
187
188/*
189 * Identify routine.  Create a connection point on our parent for probing.
190 */
191static void
192npx_identify(driver, parent)
193	driver_t *driver;
194	device_t parent;
195{
196	device_t child;
197
198	child = BUS_ADD_CHILD(parent, 0, "npx", 0);
199	if (child == NULL)
200		panic("npx_identify");
201}
202
203/*
204 * Probe routine.  Initialize cr0 to give correct behaviour for [f]wait
205 * whether the device exists or not (XXX should be elsewhere).  Set flags
206 * to tell npxattach() what to do.  Modify device struct if npx doesn't
207 * need to use interrupts.  Return 1 if device exists.
208 */
209static int
210npx_probe(dev)
211	device_t dev;
212{
213#ifdef SMP
214
215	if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
216		npx_irq = 13;
217	return npx_probe1(dev);
218
219#else /* SMP */
220
221	int	result;
222	u_long	save_eflags;
223	u_char	save_icu1_mask;
224	u_char	save_icu2_mask;
225	struct	gate_descriptor save_idt_npxintr;
226	struct	gate_descriptor save_idt_npxtrap;
227	/*
228	 * This routine is now just a wrapper for npxprobe1(), to install
229	 * special npx interrupt and trap handlers, to enable npx interrupts
230	 * and to disable other interrupts.  Someday isa_configure() will
231	 * install suitable handlers and run with interrupts enabled so we
232	 * won't need to do so much here.
233	 */
234	if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
235		npx_irq = 13;
236	npx_intrno = NRSVIDT + npx_irq;
237	save_eflags = read_eflags();
238	disable_intr();
239	save_icu1_mask = inb(IO_ICU1 + 1);
240	save_icu2_mask = inb(IO_ICU2 + 1);
241	save_idt_npxintr = idt[npx_intrno];
242	save_idt_npxtrap = idt[16];
243	outb(IO_ICU1 + 1, ~IRQ_SLAVE);
244	outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
245	setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
246	setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
247	npx_idt_probeintr = idt[npx_intrno];
248
249	/*
250	 * XXX This looks highly bogus, but it appears that npc_probe1
251	 * needs interrupts enabled.  Does this make any difference
252	 * here?
253	 */
254	enable_intr();
255	result = npx_probe1(dev);
256	disable_intr();
257	outb(IO_ICU1 + 1, save_icu1_mask);
258	outb(IO_ICU2 + 1, save_icu2_mask);
259	idt[npx_intrno] = save_idt_npxintr;
260	idt[16] = save_idt_npxtrap;
261	write_eflags(save_eflags);
262	return (result);
263
264#endif /* SMP */
265}
266
267static int
268npx_probe1(dev)
269	device_t dev;
270{
271#ifndef SMP
272	u_short control;
273	u_short status;
274#endif
275
276	/*
277	 * Partially reset the coprocessor, if any.  Some BIOS's don't reset
278	 * it after a warm boot.
279	 */
280	outb(0xf1, 0);		/* full reset on some systems, NOP on others */
281	outb(0xf0, 0);		/* clear BUSY# latch */
282	/*
283	 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
284	 * instructions.  We must set the CR0_MP bit and use the CR0_TS
285	 * bit to control the trap, because setting the CR0_EM bit does
286	 * not cause WAIT instructions to trap.  It's important to trap
287	 * WAIT instructions - otherwise the "wait" variants of no-wait
288	 * control instructions would degenerate to the "no-wait" variants
289	 * after FP context switches but work correctly otherwise.  It's
290	 * particularly important to trap WAITs when there is no NPX -
291	 * otherwise the "wait" variants would always degenerate.
292	 *
293	 * Try setting CR0_NE to get correct error reporting on 486DX's.
294	 * Setting it should fail or do nothing on lesser processors.
295	 */
296	load_cr0(rcr0() | CR0_MP | CR0_NE);
297	/*
298	 * But don't trap while we're probing.
299	 */
300	stop_emulating();
301	/*
302	 * Finish resetting the coprocessor, if any.  If there is an error
303	 * pending, then we may get a bogus IRQ13, but probeintr() will handle
304	 * it OK.  Bogus halts have never been observed, but we enabled
305	 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
306	 */
307	fninit();
308
309#ifdef SMP
310	/*
311	 * Exception 16 MUST work for SMP.
312	 */
313	npx_irq13 = 0;
314	npx_ex16 = hw_float = npx_exists = 1;
315	device_set_desc(dev, "math processor");
316	return (0);
317
318#else /* !SMP */
319	device_set_desc(dev, "math processor");
320
321	/*
322	 * Don't use fwait here because it might hang.
323	 * Don't use fnop here because it usually hangs if there is no FPU.
324	 */
325	DELAY(1000);		/* wait for any IRQ13 */
326#ifdef DIAGNOSTIC
327	if (npx_intrs_while_probing != 0)
328		printf("fninit caused %u bogus npx interrupt(s)\n",
329		       npx_intrs_while_probing);
330	if (npx_traps_while_probing != 0)
331		printf("fninit caused %u bogus npx trap(s)\n",
332		       npx_traps_while_probing);
333#endif
334	/*
335	 * Check for a status of mostly zero.
336	 */
337	status = 0x5a5a;
338	fnstsw(&status);
339	if ((status & 0xb8ff) == 0) {
340		/*
341		 * Good, now check for a proper control word.
342		 */
343		control = 0x5a5a;
344		fnstcw(&control);
345		if ((control & 0x1f3f) == 0x033f) {
346			hw_float = npx_exists = 1;
347			/*
348			 * We have an npx, now divide by 0 to see if exception
349			 * 16 works.
350			 */
351			control &= ~(1 << 2);	/* enable divide by 0 trap */
352			fldcw(&control);
353			npx_traps_while_probing = npx_intrs_while_probing = 0;
354			fp_divide_by_0();
355			if (npx_traps_while_probing != 0) {
356				/*
357				 * Good, exception 16 works.
358				 */
359				npx_ex16 = 1;
360				return (0);
361			}
362			if (npx_intrs_while_probing != 0) {
363				int	rid;
364				struct	resource *r;
365				void	*intr;
366				/*
367				 * Bad, we are stuck with IRQ13.
368				 */
369				npx_irq13 = 1;
370				/*
371				 * npxattach would be too late to set npx0_imask
372				 */
373				npx0_imask |= (1 << npx_irq);
374
375				/*
376				 * We allocate these resources permanently,
377				 * so there is no need to keep track of them.
378				 */
379				rid = 0;
380				r = bus_alloc_resource(dev, SYS_RES_IOPORT,
381						       &rid, IO_NPX, IO_NPX,
382						       IO_NPXSIZE, RF_ACTIVE);
383				if (r == 0)
384					panic("npx: can't get ports");
385				rid = 0;
386				r = bus_alloc_resource(dev, SYS_RES_IRQ,
387						       &rid, npx_irq, npx_irq,
388						       1, RF_ACTIVE);
389				if (r == 0)
390					panic("npx: can't get IRQ");
391				BUS_SETUP_INTR(device_get_parent(dev),
392					       dev, r, INTR_TYPE_MISC,
393					       npx_intr, 0, &intr);
394				if (intr == 0)
395					panic("npx: can't create intr");
396
397				return (0);
398			}
399			/*
400			 * Worse, even IRQ13 is broken.  Use emulator.
401			 */
402		}
403	}
404	/*
405	 * Probe failed, but we want to get to npxattach to initialize the
406	 * emulator and say that it has been installed.  XXX handle devices
407	 * that aren't really devices better.
408	 */
409	return (0);
410#endif /* SMP */
411}
412
413/*
414 * Attach routine - announce which it is, and wire into system
415 */
416int
417npx_attach(dev)
418	device_t dev;
419{
420	int flags;
421
422	if (resource_int_value("npx", 0, "flags", &flags) != 0)
423		flags = 0;
424
425	if (flags)
426		device_printf(dev, "flags 0x%x ", flags);
427	if (npx_irq13) {
428		device_printf(dev, "using IRQ 13 interface\n");
429	} else {
430#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE)
431		if (npx_ex16) {
432			if (!(flags & NPX_PREFER_EMULATOR))
433				device_printf(dev, "INT 16 interface\n");
434			else {
435				device_printf(dev, "FPU exists, but flags request "
436				    "emulator\n");
437				hw_float = npx_exists = 0;
438			}
439		} else if (npx_exists) {
440			device_printf(dev, "error reporting broken; using 387 emulator\n");
441			hw_float = npx_exists = 0;
442		} else
443			device_printf(dev, "387 emulator\n");
444#else
445		if (npx_ex16) {
446			device_printf(dev, "INT 16 interface\n");
447			if (flags & NPX_PREFER_EMULATOR) {
448				device_printf(dev, "emulator requested, but none compiled "
449				    "into kernel, using FPU\n");
450			}
451		} else
452			device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
453#endif
454	}
455	npxinit(__INITIAL_NPXCW__);
456
457#ifdef I586_CPU
458	if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
459	    timezero("i586_bzero()", i586_bzero) <
460	    timezero("bzero()", bzero) * 4 / 5) {
461		if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
462			bcopy_vector = i586_bcopy;
463			ovbcopy_vector = i586_bcopy;
464		}
465		if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
466			bzero = i586_bzero;
467		if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
468			copyin_vector = i586_copyin;
469			copyout_vector = i586_copyout;
470		}
471	}
472#endif
473
474	return (0);		/* XXX unused */
475}
476
477/*
478 * Initialize floating point unit.
479 */
480void
481npxinit(control)
482	u_short control;
483{
484	struct save87 dummy;
485
486	if (!npx_exists)
487		return;
488	/*
489	 * fninit has the same h/w bugs as fnsave.  Use the detoxified
490	 * fnsave to throw away any junk in the fpu.  npxsave() initializes
491	 * the fpu and sets npxproc = NULL as important side effects.
492	 */
493	npxsave(&dummy);
494	stop_emulating();
495	fldcw(&control);
496	if (PCPU_GET(curpcb) != NULL)
497		fnsave(&PCPU_GET(curpcb)->pcb_savefpu);
498	start_emulating();
499}
500
501/*
502 * Free coprocessor (if we have it).
503 */
504void
505npxexit(p)
506	struct proc *p;
507{
508
509	if (p == PCPU_GET(npxproc))
510		npxsave(&PCPU_GET(curpcb)->pcb_savefpu);
511#ifdef NPX_DEBUG
512	if (npx_exists) {
513		u_int	masked_exceptions;
514
515		masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw
516		    & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f;
517		/*
518		 * Log exceptions that would have trapped with the old
519		 * control word (overflow, divide by 0, and invalid operand).
520		 */
521		if (masked_exceptions & 0x0d)
522			log(LOG_ERR,
523	"pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
524			    p->p_pid, p->p_comm, masked_exceptions);
525	}
526#endif
527}
528
529/*
530 * The following mechanism is used to ensure that the FPE_... value
531 * that is passed as a trapcode to the signal handler of the user
532 * process does not have more than one bit set.
533 *
534 * Multiple bits may be set if the user process modifies the control
535 * word while a status word bit is already set.  While this is a sign
536 * of bad coding, we have no choise than to narrow them down to one
537 * bit, since we must not send a trapcode that is not exactly one of
538 * the FPE_ macros.
539 *
540 * The mechanism has a static table with 127 entries.  Each combination
541 * of the 7 FPU status word exception bits directly translates to a
542 * position in this table, where a single FPE_... value is stored.
543 * This FPE_... value stored there is considered the "most important"
544 * of the exception bits and will be sent as the signal code.  The
545 * precedence of the bits is based upon Intel Document "Numerical
546 * Applications", Chapter "Special Computational Situations".
547 *
548 * The macro to choose one of these values does these steps: 1) Throw
549 * away status word bits that cannot be masked.  2) Throw away the bits
550 * currently masked in the control word, assuming the user isn't
551 * interested in them anymore.  3) Reinsert status word bit 7 (stack
552 * fault) if it is set, which cannot be masked but must be presered.
553 * 4) Use the remaining bits to point into the trapcode table.
554 *
555 * The 6 maskable bits in order of their preference, as stated in the
556 * above referenced Intel manual:
557 * 1  Invalid operation (FP_X_INV)
558 * 1a   Stack underflow
559 * 1b   Stack overflow
560 * 1c   Operand of unsupported format
561 * 1d   SNaN operand.
562 * 2  QNaN operand (not an exception, irrelavant here)
563 * 3  Any other invalid-operation not mentioned above or zero divide
564 *      (FP_X_INV, FP_X_DZ)
565 * 4  Denormal operand (FP_X_DNML)
566 * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
567 * 6  Inexact result (FP_X_IMP)
568 */
569static char fpetable[128] = {
570	0,
571	FPE_FLTINV,	/*  1 - INV */
572	FPE_FLTUND,	/*  2 - DNML */
573	FPE_FLTINV,	/*  3 - INV | DNML */
574	FPE_FLTDIV,	/*  4 - DZ */
575	FPE_FLTINV,	/*  5 - INV | DZ */
576	FPE_FLTDIV,	/*  6 - DNML | DZ */
577	FPE_FLTINV,	/*  7 - INV | DNML | DZ */
578	FPE_FLTOVF,	/*  8 - OFL */
579	FPE_FLTINV,	/*  9 - INV | OFL */
580	FPE_FLTUND,	/*  A - DNML | OFL */
581	FPE_FLTINV,	/*  B - INV | DNML | OFL */
582	FPE_FLTDIV,	/*  C - DZ | OFL */
583	FPE_FLTINV,	/*  D - INV | DZ | OFL */
584	FPE_FLTDIV,	/*  E - DNML | DZ | OFL */
585	FPE_FLTINV,	/*  F - INV | DNML | DZ | OFL */
586	FPE_FLTUND,	/* 10 - UFL */
587	FPE_FLTINV,	/* 11 - INV | UFL */
588	FPE_FLTUND,	/* 12 - DNML | UFL */
589	FPE_FLTINV,	/* 13 - INV | DNML | UFL */
590	FPE_FLTDIV,	/* 14 - DZ | UFL */
591	FPE_FLTINV,	/* 15 - INV | DZ | UFL */
592	FPE_FLTDIV,	/* 16 - DNML | DZ | UFL */
593	FPE_FLTINV,	/* 17 - INV | DNML | DZ | UFL */
594	FPE_FLTOVF,	/* 18 - OFL | UFL */
595	FPE_FLTINV,	/* 19 - INV | OFL | UFL */
596	FPE_FLTUND,	/* 1A - DNML | OFL | UFL */
597	FPE_FLTINV,	/* 1B - INV | DNML | OFL | UFL */
598	FPE_FLTDIV,	/* 1C - DZ | OFL | UFL */
599	FPE_FLTINV,	/* 1D - INV | DZ | OFL | UFL */
600	FPE_FLTDIV,	/* 1E - DNML | DZ | OFL | UFL */
601	FPE_FLTINV,	/* 1F - INV | DNML | DZ | OFL | UFL */
602	FPE_FLTRES,	/* 20 - IMP */
603	FPE_FLTINV,	/* 21 - INV | IMP */
604	FPE_FLTUND,	/* 22 - DNML | IMP */
605	FPE_FLTINV,	/* 23 - INV | DNML | IMP */
606	FPE_FLTDIV,	/* 24 - DZ | IMP */
607	FPE_FLTINV,	/* 25 - INV | DZ | IMP */
608	FPE_FLTDIV,	/* 26 - DNML | DZ | IMP */
609	FPE_FLTINV,	/* 27 - INV | DNML | DZ | IMP */
610	FPE_FLTOVF,	/* 28 - OFL | IMP */
611	FPE_FLTINV,	/* 29 - INV | OFL | IMP */
612	FPE_FLTUND,	/* 2A - DNML | OFL | IMP */
613	FPE_FLTINV,	/* 2B - INV | DNML | OFL | IMP */
614	FPE_FLTDIV,	/* 2C - DZ | OFL | IMP */
615	FPE_FLTINV,	/* 2D - INV | DZ | OFL | IMP */
616	FPE_FLTDIV,	/* 2E - DNML | DZ | OFL | IMP */
617	FPE_FLTINV,	/* 2F - INV | DNML | DZ | OFL | IMP */
618	FPE_FLTUND,	/* 30 - UFL | IMP */
619	FPE_FLTINV,	/* 31 - INV | UFL | IMP */
620	FPE_FLTUND,	/* 32 - DNML | UFL | IMP */
621	FPE_FLTINV,	/* 33 - INV | DNML | UFL | IMP */
622	FPE_FLTDIV,	/* 34 - DZ | UFL | IMP */
623	FPE_FLTINV,	/* 35 - INV | DZ | UFL | IMP */
624	FPE_FLTDIV,	/* 36 - DNML | DZ | UFL | IMP */
625	FPE_FLTINV,	/* 37 - INV | DNML | DZ | UFL | IMP */
626	FPE_FLTOVF,	/* 38 - OFL | UFL | IMP */
627	FPE_FLTINV,	/* 39 - INV | OFL | UFL | IMP */
628	FPE_FLTUND,	/* 3A - DNML | OFL | UFL | IMP */
629	FPE_FLTINV,	/* 3B - INV | DNML | OFL | UFL | IMP */
630	FPE_FLTDIV,	/* 3C - DZ | OFL | UFL | IMP */
631	FPE_FLTINV,	/* 3D - INV | DZ | OFL | UFL | IMP */
632	FPE_FLTDIV,	/* 3E - DNML | DZ | OFL | UFL | IMP */
633	FPE_FLTINV,	/* 3F - INV | DNML | DZ | OFL | UFL | IMP */
634	FPE_FLTSUB,	/* 40 - STK */
635	FPE_FLTSUB,	/* 41 - INV | STK */
636	FPE_FLTUND,	/* 42 - DNML | STK */
637	FPE_FLTSUB,	/* 43 - INV | DNML | STK */
638	FPE_FLTDIV,	/* 44 - DZ | STK */
639	FPE_FLTSUB,	/* 45 - INV | DZ | STK */
640	FPE_FLTDIV,	/* 46 - DNML | DZ | STK */
641	FPE_FLTSUB,	/* 47 - INV | DNML | DZ | STK */
642	FPE_FLTOVF,	/* 48 - OFL | STK */
643	FPE_FLTSUB,	/* 49 - INV | OFL | STK */
644	FPE_FLTUND,	/* 4A - DNML | OFL | STK */
645	FPE_FLTSUB,	/* 4B - INV | DNML | OFL | STK */
646	FPE_FLTDIV,	/* 4C - DZ | OFL | STK */
647	FPE_FLTSUB,	/* 4D - INV | DZ | OFL | STK */
648	FPE_FLTDIV,	/* 4E - DNML | DZ | OFL | STK */
649	FPE_FLTSUB,	/* 4F - INV | DNML | DZ | OFL | STK */
650	FPE_FLTUND,	/* 50 - UFL | STK */
651	FPE_FLTSUB,	/* 51 - INV | UFL | STK */
652	FPE_FLTUND,	/* 52 - DNML | UFL | STK */
653	FPE_FLTSUB,	/* 53 - INV | DNML | UFL | STK */
654	FPE_FLTDIV,	/* 54 - DZ | UFL | STK */
655	FPE_FLTSUB,	/* 55 - INV | DZ | UFL | STK */
656	FPE_FLTDIV,	/* 56 - DNML | DZ | UFL | STK */
657	FPE_FLTSUB,	/* 57 - INV | DNML | DZ | UFL | STK */
658	FPE_FLTOVF,	/* 58 - OFL | UFL | STK */
659	FPE_FLTSUB,	/* 59 - INV | OFL | UFL | STK */
660	FPE_FLTUND,	/* 5A - DNML | OFL | UFL | STK */
661	FPE_FLTSUB,	/* 5B - INV | DNML | OFL | UFL | STK */
662	FPE_FLTDIV,	/* 5C - DZ | OFL | UFL | STK */
663	FPE_FLTSUB,	/* 5D - INV | DZ | OFL | UFL | STK */
664	FPE_FLTDIV,	/* 5E - DNML | DZ | OFL | UFL | STK */
665	FPE_FLTSUB,	/* 5F - INV | DNML | DZ | OFL | UFL | STK */
666	FPE_FLTRES,	/* 60 - IMP | STK */
667	FPE_FLTSUB,	/* 61 - INV | IMP | STK */
668	FPE_FLTUND,	/* 62 - DNML | IMP | STK */
669	FPE_FLTSUB,	/* 63 - INV | DNML | IMP | STK */
670	FPE_FLTDIV,	/* 64 - DZ | IMP | STK */
671	FPE_FLTSUB,	/* 65 - INV | DZ | IMP | STK */
672	FPE_FLTDIV,	/* 66 - DNML | DZ | IMP | STK */
673	FPE_FLTSUB,	/* 67 - INV | DNML | DZ | IMP | STK */
674	FPE_FLTOVF,	/* 68 - OFL | IMP | STK */
675	FPE_FLTSUB,	/* 69 - INV | OFL | IMP | STK */
676	FPE_FLTUND,	/* 6A - DNML | OFL | IMP | STK */
677	FPE_FLTSUB,	/* 6B - INV | DNML | OFL | IMP | STK */
678	FPE_FLTDIV,	/* 6C - DZ | OFL | IMP | STK */
679	FPE_FLTSUB,	/* 6D - INV | DZ | OFL | IMP | STK */
680	FPE_FLTDIV,	/* 6E - DNML | DZ | OFL | IMP | STK */
681	FPE_FLTSUB,	/* 6F - INV | DNML | DZ | OFL | IMP | STK */
682	FPE_FLTUND,	/* 70 - UFL | IMP | STK */
683	FPE_FLTSUB,	/* 71 - INV | UFL | IMP | STK */
684	FPE_FLTUND,	/* 72 - DNML | UFL | IMP | STK */
685	FPE_FLTSUB,	/* 73 - INV | DNML | UFL | IMP | STK */
686	FPE_FLTDIV,	/* 74 - DZ | UFL | IMP | STK */
687	FPE_FLTSUB,	/* 75 - INV | DZ | UFL | IMP | STK */
688	FPE_FLTDIV,	/* 76 - DNML | DZ | UFL | IMP | STK */
689	FPE_FLTSUB,	/* 77 - INV | DNML | DZ | UFL | IMP | STK */
690	FPE_FLTOVF,	/* 78 - OFL | UFL | IMP | STK */
691	FPE_FLTSUB,	/* 79 - INV | OFL | UFL | IMP | STK */
692	FPE_FLTUND,	/* 7A - DNML | OFL | UFL | IMP | STK */
693	FPE_FLTSUB,	/* 7B - INV | DNML | OFL | UFL | IMP | STK */
694	FPE_FLTDIV,	/* 7C - DZ | OFL | UFL | IMP | STK */
695	FPE_FLTSUB,	/* 7D - INV | DZ | OFL | UFL | IMP | STK */
696	FPE_FLTDIV,	/* 7E - DNML | DZ | OFL | UFL | IMP | STK */
697	FPE_FLTSUB,	/* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
698};
699
700/*
701 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
702 *
703 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
704 * depend on longjmp() restoring a usable state.  Restoring the state
705 * or examining it might fail if we didn't clear exceptions.
706 *
707 * The error code chosen will be one of the FPE_... macros. It will be
708 * sent as the second argument to old BSD-style signal handlers and as
709 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
710 *
711 * XXX the FP state is not preserved across signal handlers.  So signal
712 * handlers cannot afford to do FP unless they preserve the state or
713 * longjmp() out.  Both preserving the state and longjmp()ing may be
714 * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
715 * solution for signals other than SIGFPE.
716 */
717void
718npx_intr(dummy)
719	void *dummy;
720{
721	int code;
722	u_short control;
723	struct intrframe *frame;
724
725	if (PCPU_GET(npxproc) == NULL || !npx_exists) {
726		printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n",
727		       PCPU_GET(npxproc), curproc, npx_exists);
728		panic("npxintr from nowhere");
729	}
730	if (PCPU_GET(npxproc) != curproc) {
731		printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n",
732		       PCPU_GET(npxproc), curproc, npx_exists);
733		panic("npxintr from non-current process");
734	}
735
736	outb(0xf0, 0);
737	fnstsw(&PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw);
738	fnstcw(&control);
739	fnclex();
740
741	/*
742	 * Pass exception to process.
743	 */
744	frame = (struct intrframe *)&dummy;	/* XXX */
745	if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
746		/*
747		 * Interrupt is essentially a trap, so we can afford to call
748		 * the SIGFPE handler (if any) as soon as the interrupt
749		 * returns.
750		 *
751		 * XXX little or nothing is gained from this, and plenty is
752		 * lost - the interrupt frame has to contain the trap frame
753		 * (this is otherwise only necessary for the rescheduling trap
754		 * in doreti, and the frame for that could easily be set up
755		 * just before it is used).
756		 */
757		curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
758		/*
759		 * Encode the appropriate code for detailed information on
760		 * this exception.
761		 */
762		code =
763		    fpetable[(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & ~control & 0x3f) |
764			(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & 0x40)];
765		trapsignal(curproc, SIGFPE, code);
766	} else {
767		/*
768		 * Nested interrupt.  These losers occur when:
769		 *	o an IRQ13 is bogusly generated at a bogus time, e.g.:
770		 *		o immediately after an fnsave or frstor of an
771		 *		  error state.
772		 *		o a couple of 386 instructions after
773		 *		  "fstpl _memvar" causes a stack overflow.
774		 *	  These are especially nasty when combined with a
775		 *	  trace trap.
776		 *	o an IRQ13 occurs at the same time as another higher-
777		 *	  priority interrupt.
778		 *
779		 * Treat them like a true async interrupt.
780		 */
781		psignal(curproc, SIGFPE);
782	}
783}
784
785/*
786 * Implement device not available (DNA) exception
787 *
788 * It would be better to switch FP context here (if curproc != npxproc)
789 * and not necessarily for every context switch, but it is too hard to
790 * access foreign pcb's.
791 */
792int
793npxdna()
794{
795	if (!npx_exists)
796		return (0);
797	if (PCPU_GET(npxproc) != NULL) {
798		printf("npxdna: npxproc = %p, curproc = %p\n",
799		       PCPU_GET(npxproc), curproc);
800		panic("npxdna");
801	}
802	stop_emulating();
803	/*
804	 * Record new context early in case frstor causes an IRQ13.
805	 */
806	PCPU_SET(npxproc, CURPROC);
807	PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw = 0;
808	/*
809	 * The following frstor may cause an IRQ13 when the state being
810	 * restored has a pending error.  The error will appear to have been
811	 * triggered by the current (npx) user instruction even when that
812	 * instruction is a no-wait instruction that should not trigger an
813	 * error (e.g., fnclex).  On at least one 486 system all of the
814	 * no-wait instructions are broken the same as frstor, so our
815	 * treatment does not amplify the breakage.  On at least one
816	 * 386/Cyrix 387 system, fnclex works correctly while frstor and
817	 * fnsave are broken, so our treatment breaks fnclex if it is the
818	 * first FPU instruction after a context switch.
819	 */
820	frstor(&PCPU_GET(curpcb)->pcb_savefpu);
821
822	return (1);
823}
824
825/*
826 * Wrapper for fnsave instruction to handle h/w bugs.  If there is an error
827 * pending, then fnsave generates a bogus IRQ13 on some systems.  Force
828 * any IRQ13 to be handled immediately, and then ignore it.  This routine is
829 * often called at splhigh so it must not use many system services.  In
830 * particular, it's much easier to install a special handler than to
831 * guarantee that it's safe to use npxintr() and its supporting code.
832 */
833void
834npxsave(addr)
835	struct save87 *addr;
836{
837#ifdef SMP
838
839	stop_emulating();
840	fnsave(addr);
841	/* fnop(); */
842	start_emulating();
843	PCPU_SET(npxproc, NULL);
844
845#else /* SMP */
846
847	int	intrstate;
848	u_char	icu1_mask;
849	u_char	icu2_mask;
850	u_char	old_icu1_mask;
851	u_char	old_icu2_mask;
852	struct gate_descriptor	save_idt_npxintr;
853
854	intrstate = save_intr();
855	disable_intr();
856	old_icu1_mask = inb(IO_ICU1 + 1);
857	old_icu2_mask = inb(IO_ICU2 + 1);
858	save_idt_npxintr = idt[npx_intrno];
859	outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
860	outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
861	idt[npx_intrno] = npx_idt_probeintr;
862	write_eflags(intrstate);
863	stop_emulating();
864	fnsave(addr);
865	fnop();
866	start_emulating();
867	PCPU_SET(npxproc, NULL);
868	disable_intr();
869	icu1_mask = inb(IO_ICU1 + 1);	/* masks may have changed */
870	icu2_mask = inb(IO_ICU2 + 1);
871	outb(IO_ICU1 + 1,
872	     (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
873	outb(IO_ICU2 + 1,
874	     (icu2_mask & ~(npx0_imask >> 8))
875	     | (old_icu2_mask & (npx0_imask >> 8)));
876	idt[npx_intrno] = save_idt_npxintr;
877	restore_intr(intrstate);	/* back to previous state */
878
879#endif /* SMP */
880}
881
882#ifdef I586_CPU
883static long
884timezero(funcname, func)
885	const char *funcname;
886	void (*func) __P((void *buf, size_t len));
887
888{
889	void *buf;
890#define	BUFSIZE		1000000
891	long usec;
892	struct timeval finish, start;
893
894	buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
895	if (buf == NULL)
896		return (BUFSIZE);
897	microtime(&start);
898	(*func)(buf, BUFSIZE);
899	microtime(&finish);
900	usec = 1000000 * (finish.tv_sec - start.tv_sec) +
901	    finish.tv_usec - start.tv_usec;
902	if (usec <= 0)
903		usec = 1;
904	if (bootverbose)
905		printf("%s bandwidth = %ld bytes/sec\n",
906		    funcname, (long)(BUFSIZE * (int64_t)1000000 / usec));
907	free(buf, M_TEMP);
908	return (usec);
909}
910#endif /* I586_CPU */
911
912static device_method_t npx_methods[] = {
913	/* Device interface */
914	DEVMETHOD(device_identify,	npx_identify),
915	DEVMETHOD(device_probe,		npx_probe),
916	DEVMETHOD(device_attach,	npx_attach),
917	DEVMETHOD(device_detach,	bus_generic_detach),
918	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
919	DEVMETHOD(device_suspend,	bus_generic_suspend),
920	DEVMETHOD(device_resume,	bus_generic_resume),
921
922	{ 0, 0 }
923};
924
925static driver_t npx_driver = {
926	"npx",
927	npx_methods,
928	1,			/* no softc */
929};
930
931static devclass_t npx_devclass;
932
933/*
934 * We prefer to attach to the root nexus so that the usual case (exception 16)
935 * doesn't describe the processor as being `on isa'.
936 */
937DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
938
939/*
940 * This sucks up the legacy ISA support assignments from PNPBIOS.
941 */
942static struct isa_pnp_id npxisa_ids[] = {
943	{ 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
944	{ 0 }
945};
946
947static int
948npxisa_probe(device_t dev)
949{
950	int result;
951	if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
952		device_quiet(dev);
953	}
954	return(result);
955}
956
957static int
958npxisa_attach(device_t dev)
959{
960	return (0);
961}
962
963static device_method_t npxisa_methods[] = {
964	/* Device interface */
965	DEVMETHOD(device_probe,		npxisa_probe),
966	DEVMETHOD(device_attach,	npxisa_attach),
967	DEVMETHOD(device_detach,	bus_generic_detach),
968	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
969	DEVMETHOD(device_suspend,	bus_generic_suspend),
970	DEVMETHOD(device_resume,	bus_generic_resume),
971
972	{ 0, 0 }
973};
974
975static driver_t npxisa_driver = {
976	"npxisa",
977	npxisa_methods,
978	1,			/* no softc */
979};
980
981static devclass_t npxisa_devclass;
982
983DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
984
985