fpu.c revision 60008
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 60008 2000-05-04 23:57:32Z wollman $ 36 */ 37 38#include "opt_debug_npx.h" 39#include "opt_math_emulate.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/sysctl.h> 48#include <sys/proc.h> 49#include <machine/bus.h> 50#include <sys/rman.h> 51#ifdef NPX_DEBUG 52#include <sys/syslog.h> 53#endif 54#include <sys/signalvar.h> 55 56#ifndef SMP 57#include <machine/asmacros.h> 58#endif 59#include <machine/cputypes.h> 60#include <machine/frame.h> 61#include <machine/ipl.h> 62#include <machine/md_var.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#ifndef SMP 66#include <machine/clock.h> 67#endif 68#include <machine/resource.h> 69#include <machine/specialreg.h> 70#include <machine/segments.h> 71 72#ifndef SMP 73#include <i386/isa/icu.h> 74#include <i386/isa/intr_machdep.h> 75#include <i386/isa/isa.h> 76#endif 77#include <isa/isavar.h> 78 79/* 80 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 81 */ 82 83/* Configuration flags. */ 84#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 85#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 86#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 87#define NPX_PREFER_EMULATOR (1 << 3) 88 89#ifdef __GNUC__ 90 91#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 92#define fnclex() __asm("fnclex") 93#define fninit() __asm("fninit") 94#define fnop() __asm("fnop") 95#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 96#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 97#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 98#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 99#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 100#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 101 : : "n" (CR0_TS) : "ax") 102#define stop_emulating() __asm("clts") 103 104#else /* not __GNUC__ */ 105 106void fldcw __P((caddr_t addr)); 107void fnclex __P((void)); 108void fninit __P((void)); 109void fnop __P((void)); 110void fnsave __P((caddr_t addr)); 111void fnstcw __P((caddr_t addr)); 112void fnstsw __P((caddr_t addr)); 113void fp_divide_by_0 __P((void)); 114void frstor __P((caddr_t addr)); 115void start_emulating __P((void)); 116void stop_emulating __P((void)); 117 118#endif /* __GNUC__ */ 119 120typedef u_char bool_t; 121 122static int npx_attach __P((device_t dev)); 123 void npx_intr __P((void *)); 124static void npx_identify __P((driver_t *driver, device_t parent)); 125static int npx_probe __P((device_t dev)); 126static int npx_probe1 __P((device_t dev)); 127#ifdef I586_CPU 128static long timezero __P((const char *funcname, 129 void (*func)(void *buf, size_t len))); 130#endif /* I586_CPU */ 131 132int hw_float; /* XXX currently just alias for npx_exists */ 133 134SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 135 CTLFLAG_RD, &hw_float, 0, 136 "Floatingpoint instructions executed in hardware"); 137 138#ifndef SMP 139static u_int npx0_imask = SWI_CLOCK_MASK; 140static struct gate_descriptor npx_idt_probeintr; 141static int npx_intrno; 142static volatile u_int npx_intrs_while_probing; 143static volatile u_int npx_traps_while_probing; 144#endif 145 146static bool_t npx_ex16; 147static bool_t npx_exists; 148static bool_t npx_irq13; 149static int npx_irq; /* irq number */ 150 151#ifndef SMP 152/* 153 * Special interrupt handlers. Someday intr0-intr15 will be used to count 154 * interrupts. We'll still need a special exception 16 handler. The busy 155 * latch stuff in probeintr() can be moved to npxprobe(). 156 */ 157inthand_t probeintr; 158__asm(" \n\ 159 .text \n\ 160 .p2align 2,0x90 \n\ 161 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 162" __XSTRING(CNAME(probeintr)) ": \n\ 163 ss \n\ 164 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 165 pushl %eax \n\ 166 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 167 outb %al,$0xa0 # IO_ICU2 \n\ 168 outb %al,$0x20 # IO_ICU1 \n\ 169 movb $0,%al \n\ 170 outb %al,$0xf0 # clear BUSY# latch \n\ 171 popl %eax \n\ 172 iret \n\ 173"); 174 175inthand_t probetrap; 176__asm(" \n\ 177 .text \n\ 178 .p2align 2,0x90 \n\ 179 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 180" __XSTRING(CNAME(probetrap)) ": \n\ 181 ss \n\ 182 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 183 fnclex \n\ 184 iret \n\ 185"); 186#endif /* SMP */ 187 188/* 189 * Identify routine. Create a connection point on our parent for probing. 190 */ 191static void 192npx_identify(driver, parent) 193 driver_t *driver; 194 device_t parent; 195{ 196 device_t child; 197 198 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 199 if (child == NULL) 200 panic("npx_identify"); 201} 202 203/* 204 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 205 * whether the device exists or not (XXX should be elsewhere). Set flags 206 * to tell npxattach() what to do. Modify device struct if npx doesn't 207 * need to use interrupts. Return 1 if device exists. 208 */ 209static int 210npx_probe(dev) 211 device_t dev; 212{ 213#ifdef SMP 214 215 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 216 npx_irq = 13; 217 return npx_probe1(dev); 218 219#else /* SMP */ 220 221 int result; 222 u_long save_eflags; 223 u_char save_icu1_mask; 224 u_char save_icu2_mask; 225 struct gate_descriptor save_idt_npxintr; 226 struct gate_descriptor save_idt_npxtrap; 227 /* 228 * This routine is now just a wrapper for npxprobe1(), to install 229 * special npx interrupt and trap handlers, to enable npx interrupts 230 * and to disable other interrupts. Someday isa_configure() will 231 * install suitable handlers and run with interrupts enabled so we 232 * won't need to do so much here. 233 */ 234 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 235 npx_irq = 13; 236 npx_intrno = NRSVIDT + npx_irq; 237 save_eflags = read_eflags(); 238 disable_intr(); 239 save_icu1_mask = inb(IO_ICU1 + 1); 240 save_icu2_mask = inb(IO_ICU2 + 1); 241 save_idt_npxintr = idt[npx_intrno]; 242 save_idt_npxtrap = idt[16]; 243 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 244 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 245 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 246 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 247 npx_idt_probeintr = idt[npx_intrno]; 248 enable_intr(); 249 result = npx_probe1(dev); 250 disable_intr(); 251 outb(IO_ICU1 + 1, save_icu1_mask); 252 outb(IO_ICU2 + 1, save_icu2_mask); 253 idt[npx_intrno] = save_idt_npxintr; 254 idt[16] = save_idt_npxtrap; 255 write_eflags(save_eflags); 256 return (result); 257 258#endif /* SMP */ 259} 260 261static int 262npx_probe1(dev) 263 device_t dev; 264{ 265#ifndef SMP 266 u_short control; 267 u_short status; 268#endif 269 270 /* 271 * Partially reset the coprocessor, if any. Some BIOS's don't reset 272 * it after a warm boot. 273 */ 274 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 275 outb(0xf0, 0); /* clear BUSY# latch */ 276 /* 277 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 278 * instructions. We must set the CR0_MP bit and use the CR0_TS 279 * bit to control the trap, because setting the CR0_EM bit does 280 * not cause WAIT instructions to trap. It's important to trap 281 * WAIT instructions - otherwise the "wait" variants of no-wait 282 * control instructions would degenerate to the "no-wait" variants 283 * after FP context switches but work correctly otherwise. It's 284 * particularly important to trap WAITs when there is no NPX - 285 * otherwise the "wait" variants would always degenerate. 286 * 287 * Try setting CR0_NE to get correct error reporting on 486DX's. 288 * Setting it should fail or do nothing on lesser processors. 289 */ 290 load_cr0(rcr0() | CR0_MP | CR0_NE); 291 /* 292 * But don't trap while we're probing. 293 */ 294 stop_emulating(); 295 /* 296 * Finish resetting the coprocessor, if any. If there is an error 297 * pending, then we may get a bogus IRQ13, but probeintr() will handle 298 * it OK. Bogus halts have never been observed, but we enabled 299 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 300 */ 301 fninit(); 302 303#ifdef SMP 304 /* 305 * Exception 16 MUST work for SMP. 306 */ 307 npx_irq13 = 0; 308 npx_ex16 = hw_float = npx_exists = 1; 309 device_set_desc(dev, "math processor"); 310 return (0); 311 312#else /* !SMP */ 313 device_set_desc(dev, "math processor"); 314 315 /* 316 * Don't use fwait here because it might hang. 317 * Don't use fnop here because it usually hangs if there is no FPU. 318 */ 319 DELAY(1000); /* wait for any IRQ13 */ 320#ifdef DIAGNOSTIC 321 if (npx_intrs_while_probing != 0) 322 printf("fninit caused %u bogus npx interrupt(s)\n", 323 npx_intrs_while_probing); 324 if (npx_traps_while_probing != 0) 325 printf("fninit caused %u bogus npx trap(s)\n", 326 npx_traps_while_probing); 327#endif 328 /* 329 * Check for a status of mostly zero. 330 */ 331 status = 0x5a5a; 332 fnstsw(&status); 333 if ((status & 0xb8ff) == 0) { 334 /* 335 * Good, now check for a proper control word. 336 */ 337 control = 0x5a5a; 338 fnstcw(&control); 339 if ((control & 0x1f3f) == 0x033f) { 340 hw_float = npx_exists = 1; 341 /* 342 * We have an npx, now divide by 0 to see if exception 343 * 16 works. 344 */ 345 control &= ~(1 << 2); /* enable divide by 0 trap */ 346 fldcw(&control); 347 npx_traps_while_probing = npx_intrs_while_probing = 0; 348 fp_divide_by_0(); 349 if (npx_traps_while_probing != 0) { 350 /* 351 * Good, exception 16 works. 352 */ 353 npx_ex16 = 1; 354 return (0); 355 } 356 if (npx_intrs_while_probing != 0) { 357 int rid; 358 struct resource *r; 359 void *intr; 360 /* 361 * Bad, we are stuck with IRQ13. 362 */ 363 npx_irq13 = 1; 364 /* 365 * npxattach would be too late to set npx0_imask 366 */ 367 npx0_imask |= (1 << npx_irq); 368 369 /* 370 * We allocate these resources permanently, 371 * so there is no need to keep track of them. 372 */ 373 rid = 0; 374 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 375 &rid, IO_NPX, IO_NPX, 376 IO_NPXSIZE, RF_ACTIVE); 377 if (r == 0) 378 panic("npx: can't get ports"); 379 rid = 0; 380 r = bus_alloc_resource(dev, SYS_RES_IRQ, 381 &rid, npx_irq, npx_irq, 382 1, RF_ACTIVE); 383 if (r == 0) 384 panic("npx: can't get IRQ"); 385 BUS_SETUP_INTR(device_get_parent(dev), 386 dev, r, INTR_TYPE_MISC, 387 npx_intr, 0, &intr); 388 if (intr == 0) 389 panic("npx: can't create intr"); 390 391 return (0); 392 } 393 /* 394 * Worse, even IRQ13 is broken. Use emulator. 395 */ 396 } 397 } 398 /* 399 * Probe failed, but we want to get to npxattach to initialize the 400 * emulator and say that it has been installed. XXX handle devices 401 * that aren't really devices better. 402 */ 403 return (0); 404#endif /* SMP */ 405} 406 407/* 408 * Attach routine - announce which it is, and wire into system 409 */ 410int 411npx_attach(dev) 412 device_t dev; 413{ 414 int flags; 415 416 if (resource_int_value("npx", 0, "flags", &flags) != 0) 417 flags = 0; 418 419 if (flags) 420 device_printf(dev, "flags 0x%x ", flags); 421 if (npx_irq13) { 422 device_printf(dev, "using IRQ 13 interface\n"); 423 } else { 424#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 425 if (npx_ex16) { 426 if (!(flags & NPX_PREFER_EMULATOR)) 427 device_printf(dev, "INT 16 interface\n"); 428 else { 429 device_printf(dev, "FPU exists, but flags request " 430 "emulator\n"); 431 hw_float = npx_exists = 0; 432 } 433 } else if (npx_exists) { 434 device_printf(dev, "error reporting broken; using 387 emulator\n"); 435 hw_float = npx_exists = 0; 436 } else 437 device_printf(dev, "387 emulator\n"); 438#else 439 if (npx_ex16) { 440 device_printf(dev, "INT 16 interface\n"); 441 if (flags & NPX_PREFER_EMULATOR) { 442 device_printf(dev, "emulator requested, but none compiled " 443 "into kernel, using FPU\n"); 444 } 445 } else 446 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 447#endif 448 } 449 npxinit(__INITIAL_NPXCW__); 450 451#ifdef I586_CPU 452 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 453 timezero("i586_bzero()", i586_bzero) < 454 timezero("bzero()", bzero) * 4 / 5) { 455 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 456 bcopy_vector = i586_bcopy; 457 ovbcopy_vector = i586_bcopy; 458 } 459 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 460 bzero = i586_bzero; 461 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 462 copyin_vector = i586_copyin; 463 copyout_vector = i586_copyout; 464 } 465 } 466#endif 467 468 return (0); /* XXX unused */ 469} 470 471/* 472 * Initialize floating point unit. 473 */ 474void 475npxinit(control) 476 u_short control; 477{ 478 struct save87 dummy; 479 480 if (!npx_exists) 481 return; 482 /* 483 * fninit has the same h/w bugs as fnsave. Use the detoxified 484 * fnsave to throw away any junk in the fpu. npxsave() initializes 485 * the fpu and sets npxproc = NULL as important side effects. 486 */ 487 npxsave(&dummy); 488 stop_emulating(); 489 fldcw(&control); 490 if (curpcb != NULL) 491 fnsave(&curpcb->pcb_savefpu); 492 start_emulating(); 493} 494 495/* 496 * Free coprocessor (if we have it). 497 */ 498void 499npxexit(p) 500 struct proc *p; 501{ 502 503 if (p == npxproc) 504 npxsave(&curpcb->pcb_savefpu); 505#ifdef NPX_DEBUG 506 if (npx_exists) { 507 u_int masked_exceptions; 508 509 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 510 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 511 /* 512 * Log exceptions that would have trapped with the old 513 * control word (overflow, divide by 0, and invalid operand). 514 */ 515 if (masked_exceptions & 0x0d) 516 log(LOG_ERR, 517 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 518 p->p_pid, p->p_comm, masked_exceptions); 519 } 520#endif 521} 522 523/* 524 * The following mechanism is used to ensure that the FPE_... value 525 * that is passed as a trapcode to the signal handler of the user 526 * process does not have more than one bit set. 527 * 528 * Multiple bits may be set if the user process modifies the control 529 * word while a status word bit is already set. While this is a sign 530 * of bad coding, we have no choise than to narrow them down to one 531 * bit, since we must not send a trapcode that is not exactly one of 532 * the FPE_ macros. 533 * 534 * The mechanism has a static table with 127 entries. Each combination 535 * of the 7 FPU status word exception bits directly translates to a 536 * position in this table, where a single FPE_... value is stored. 537 * This FPE_... value stored there is considered the "most important" 538 * of the exception bits and will be sent as the signal code. The 539 * precedence of the bits is based upon Intel Document "Numerical 540 * Applications", Chapter "Special Computational Situations". 541 * 542 * The macro to choose one of these values does these steps: 1) Throw 543 * away status word bits that cannot be masked. 2) Throw away the bits 544 * currently masked in the control word, assuming the user isn't 545 * interested in them anymore. 3) Reinsert status word bit 7 (stack 546 * fault) if it is set, which cannot be masked but must be presered. 547 * 4) Use the remaining bits to point into the trapcode table. 548 * 549 * The 6 maskable bits in order of their preference, as stated in the 550 * above referenced Intel manual: 551 * 1 Invalid operation (FP_X_INV) 552 * 1a Stack underflow 553 * 1b Stack overflow 554 * 1c Operand of unsupported format 555 * 1d SNaN operand. 556 * 2 QNaN operand (not an exception, irrelavant here) 557 * 3 Any other invalid-operation not mentioned above or zero divide 558 * (FP_X_INV, FP_X_DZ) 559 * 4 Denormal operand (FP_X_DNML) 560 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 561 * 6 Inexact result (FP_X_IMP) 562 */ 563static char fpetable[128] = { 564 0, 565 FPE_FLTINV, /* 1 - INV */ 566 FPE_FLTUND, /* 2 - DNML */ 567 FPE_FLTINV, /* 3 - INV | DNML */ 568 FPE_FLTDIV, /* 4 - DZ */ 569 FPE_FLTINV, /* 5 - INV | DZ */ 570 FPE_FLTDIV, /* 6 - DNML | DZ */ 571 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 572 FPE_FLTOVF, /* 8 - OFL */ 573 FPE_FLTINV, /* 9 - INV | OFL */ 574 FPE_FLTUND, /* A - DNML | OFL */ 575 FPE_FLTINV, /* B - INV | DNML | OFL */ 576 FPE_FLTDIV, /* C - DZ | OFL */ 577 FPE_FLTINV, /* D - INV | DZ | OFL */ 578 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 579 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 580 FPE_FLTUND, /* 10 - UFL */ 581 FPE_FLTINV, /* 11 - INV | UFL */ 582 FPE_FLTUND, /* 12 - DNML | UFL */ 583 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 584 FPE_FLTDIV, /* 14 - DZ | UFL */ 585 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 586 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 587 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 588 FPE_FLTOVF, /* 18 - OFL | UFL */ 589 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 590 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 591 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 592 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 593 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 594 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 595 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 596 FPE_FLTRES, /* 20 - IMP */ 597 FPE_FLTINV, /* 21 - INV | IMP */ 598 FPE_FLTUND, /* 22 - DNML | IMP */ 599 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 600 FPE_FLTDIV, /* 24 - DZ | IMP */ 601 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 602 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 603 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 604 FPE_FLTOVF, /* 28 - OFL | IMP */ 605 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 606 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 607 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 608 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 609 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 610 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 611 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 612 FPE_FLTUND, /* 30 - UFL | IMP */ 613 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 614 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 615 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 616 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 617 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 618 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 619 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 620 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 621 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 622 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 623 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 624 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 625 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 626 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 627 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 628 FPE_FLTSUB, /* 40 - STK */ 629 FPE_FLTSUB, /* 41 - INV | STK */ 630 FPE_FLTUND, /* 42 - DNML | STK */ 631 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 632 FPE_FLTDIV, /* 44 - DZ | STK */ 633 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 634 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 635 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 636 FPE_FLTOVF, /* 48 - OFL | STK */ 637 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 638 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 639 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 640 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 641 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 642 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 643 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 644 FPE_FLTUND, /* 50 - UFL | STK */ 645 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 646 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 647 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 648 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 649 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 650 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 651 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 652 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 653 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 654 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 655 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 656 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 657 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 658 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 659 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 660 FPE_FLTRES, /* 60 - IMP | STK */ 661 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 662 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 663 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 664 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 665 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 666 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 667 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 668 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 669 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 670 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 671 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 672 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 673 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 674 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 675 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 676 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 677 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 678 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 679 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 680 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 681 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 682 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 683 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 684 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 685 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 686 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 687 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 688 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 689 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 690 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 691 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 692}; 693 694/* 695 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 696 * 697 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 698 * depend on longjmp() restoring a usable state. Restoring the state 699 * or examining it might fail if we didn't clear exceptions. 700 * 701 * The error code chosen will be one of the FPE_... macros. It will be 702 * sent as the second argument to old BSD-style signal handlers and as 703 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 704 * 705 * XXX the FP state is not preserved across signal handlers. So signal 706 * handlers cannot afford to do FP unless they preserve the state or 707 * longjmp() out. Both preserving the state and longjmp()ing may be 708 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 709 * solution for signals other than SIGFPE. 710 */ 711void 712npx_intr(dummy) 713 void *dummy; 714{ 715 int code; 716 u_short control; 717 struct intrframe *frame; 718 719 if (npxproc == NULL || !npx_exists) { 720 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 721 npxproc, curproc, npx_exists); 722 panic("npxintr from nowhere"); 723 } 724 if (npxproc != curproc) { 725 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 726 npxproc, curproc, npx_exists); 727 panic("npxintr from non-current process"); 728 } 729 730 outb(0xf0, 0); 731 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 732 fnstcw(&control); 733 fnclex(); 734 735 /* 736 * Pass exception to process. 737 */ 738 frame = (struct intrframe *)&dummy; /* XXX */ 739 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 740 /* 741 * Interrupt is essentially a trap, so we can afford to call 742 * the SIGFPE handler (if any) as soon as the interrupt 743 * returns. 744 * 745 * XXX little or nothing is gained from this, and plenty is 746 * lost - the interrupt frame has to contain the trap frame 747 * (this is otherwise only necessary for the rescheduling trap 748 * in doreti, and the frame for that could easily be set up 749 * just before it is used). 750 */ 751 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 752 /* 753 * Encode the appropriate code for detailed information on 754 * this exception. 755 */ 756 code = 757 fpetable[(curpcb->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 758 (curpcb->pcb_savefpu.sv_ex_sw & 0x40)]; 759 trapsignal(curproc, SIGFPE, code); 760 } else { 761 /* 762 * Nested interrupt. These losers occur when: 763 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 764 * o immediately after an fnsave or frstor of an 765 * error state. 766 * o a couple of 386 instructions after 767 * "fstpl _memvar" causes a stack overflow. 768 * These are especially nasty when combined with a 769 * trace trap. 770 * o an IRQ13 occurs at the same time as another higher- 771 * priority interrupt. 772 * 773 * Treat them like a true async interrupt. 774 */ 775 psignal(curproc, SIGFPE); 776 } 777} 778 779/* 780 * Implement device not available (DNA) exception 781 * 782 * It would be better to switch FP context here (if curproc != npxproc) 783 * and not necessarily for every context switch, but it is too hard to 784 * access foreign pcb's. 785 */ 786int 787npxdna() 788{ 789 if (!npx_exists) 790 return (0); 791 if (npxproc != NULL) { 792 printf("npxdna: npxproc = %p, curproc = %p\n", 793 npxproc, curproc); 794 panic("npxdna"); 795 } 796 stop_emulating(); 797 /* 798 * Record new context early in case frstor causes an IRQ13. 799 */ 800 npxproc = curproc; 801 curpcb->pcb_savefpu.sv_ex_sw = 0; 802 /* 803 * The following frstor may cause an IRQ13 when the state being 804 * restored has a pending error. The error will appear to have been 805 * triggered by the current (npx) user instruction even when that 806 * instruction is a no-wait instruction that should not trigger an 807 * error (e.g., fnclex). On at least one 486 system all of the 808 * no-wait instructions are broken the same as frstor, so our 809 * treatment does not amplify the breakage. On at least one 810 * 386/Cyrix 387 system, fnclex works correctly while frstor and 811 * fnsave are broken, so our treatment breaks fnclex if it is the 812 * first FPU instruction after a context switch. 813 */ 814 frstor(&curpcb->pcb_savefpu); 815 816 return (1); 817} 818 819/* 820 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 821 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 822 * any IRQ13 to be handled immediately, and then ignore it. This routine is 823 * often called at splhigh so it must not use many system services. In 824 * particular, it's much easier to install a special handler than to 825 * guarantee that it's safe to use npxintr() and its supporting code. 826 */ 827void 828npxsave(addr) 829 struct save87 *addr; 830{ 831#ifdef SMP 832 833 stop_emulating(); 834 fnsave(addr); 835 /* fnop(); */ 836 start_emulating(); 837 npxproc = NULL; 838 839#else /* SMP */ 840 841 u_char icu1_mask; 842 u_char icu2_mask; 843 u_char old_icu1_mask; 844 u_char old_icu2_mask; 845 struct gate_descriptor save_idt_npxintr; 846 847 disable_intr(); 848 old_icu1_mask = inb(IO_ICU1 + 1); 849 old_icu2_mask = inb(IO_ICU2 + 1); 850 save_idt_npxintr = idt[npx_intrno]; 851 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 852 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 853 idt[npx_intrno] = npx_idt_probeintr; 854 enable_intr(); 855 stop_emulating(); 856 fnsave(addr); 857 fnop(); 858 start_emulating(); 859 npxproc = NULL; 860 disable_intr(); 861 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 862 icu2_mask = inb(IO_ICU2 + 1); 863 outb(IO_ICU1 + 1, 864 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 865 outb(IO_ICU2 + 1, 866 (icu2_mask & ~(npx0_imask >> 8)) 867 | (old_icu2_mask & (npx0_imask >> 8))); 868 idt[npx_intrno] = save_idt_npxintr; 869 enable_intr(); /* back to usual state */ 870 871#endif /* SMP */ 872} 873 874#ifdef I586_CPU 875static long 876timezero(funcname, func) 877 const char *funcname; 878 void (*func) __P((void *buf, size_t len)); 879 880{ 881 void *buf; 882#define BUFSIZE 1000000 883 long usec; 884 struct timeval finish, start; 885 886 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 887 if (buf == NULL) 888 return (BUFSIZE); 889 microtime(&start); 890 (*func)(buf, BUFSIZE); 891 microtime(&finish); 892 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 893 finish.tv_usec - start.tv_usec; 894 if (usec <= 0) 895 usec = 1; 896 if (bootverbose) 897 printf("%s bandwidth = %ld bytes/sec\n", 898 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 899 free(buf, M_TEMP); 900 return (usec); 901} 902#endif /* I586_CPU */ 903 904static device_method_t npx_methods[] = { 905 /* Device interface */ 906 DEVMETHOD(device_identify, npx_identify), 907 DEVMETHOD(device_probe, npx_probe), 908 DEVMETHOD(device_attach, npx_attach), 909 DEVMETHOD(device_detach, bus_generic_detach), 910 DEVMETHOD(device_shutdown, bus_generic_shutdown), 911 DEVMETHOD(device_suspend, bus_generic_suspend), 912 DEVMETHOD(device_resume, bus_generic_resume), 913 914 { 0, 0 } 915}; 916 917static driver_t npx_driver = { 918 "npx", 919 npx_methods, 920 1, /* no softc */ 921}; 922 923static devclass_t npx_devclass; 924 925/* 926 * We prefer to attach to the root nexus so that the usual case (exception 16) 927 * doesn't describe the processor as being `on isa'. 928 */ 929DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 930 931/* 932 * This sucks up the legacy ISA support assignments from PNPBIOS. 933 */ 934static struct isa_pnp_id npxisa_ids[] = { 935 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 936 { 0 } 937}; 938 939static int 940npxisa_probe(device_t dev) 941{ 942 return (ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)); 943} 944 945static int 946npxisa_attach(device_t dev) 947{ 948 return (0); 949} 950 951static device_method_t npxisa_methods[] = { 952 /* Device interface */ 953 DEVMETHOD(device_probe, npxisa_probe), 954 DEVMETHOD(device_attach, npxisa_attach), 955 DEVMETHOD(device_detach, bus_generic_detach), 956 DEVMETHOD(device_shutdown, bus_generic_shutdown), 957 DEVMETHOD(device_suspend, bus_generic_suspend), 958 DEVMETHOD(device_resume, bus_generic_resume), 959 960 { 0, 0 } 961}; 962 963static driver_t npxisa_driver = { 964 "npxisa", 965 npxisa_methods, 966 1, /* no softc */ 967}; 968 969static devclass_t npxisa_devclass; 970 971DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 972 973