fpu.c revision 40565
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $Id: npx.c,v 1.61 1998/06/21 18:02:39 bde Exp $ 36 */ 37 38#include "npx.h" 39#if NNPX > 0 40 41#include "opt_debug_npx.h" 42#include "opt_math_emulate.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/malloc.h> 48#include <sys/sysctl.h> 49#include <sys/proc.h> 50#ifdef NPX_DEBUG 51#include <sys/syslog.h> 52#endif 53#include <sys/signalvar.h> 54 55#ifndef SMP 56#include <machine/asmacros.h> 57#endif 58#include <machine/cputypes.h> 59#include <machine/frame.h> 60#include <machine/ipl.h> 61#ifndef SMP 62#include <machine/md_var.h> 63#endif 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#ifndef SMP 67#include <machine/clock.h> 68#endif 69#include <machine/specialreg.h> 70#include <machine/segments.h> 71 72#ifndef SMP 73#include <i386/isa/icu.h> 74#include <i386/isa/intr_machdep.h> 75#include <i386/isa/isa.h> 76#endif 77#include <i386/isa/isa_device.h> 78 79/* 80 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 81 */ 82 83/* Configuration flags. */ 84#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 85#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 86#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 87 88/* XXX - should be in header file. */ 89extern void (*bcopy_vector) __P((const void *from, void *to, size_t len)); 90extern void (*ovbcopy_vector) __P((const void *from, void *to, size_t len)); 91extern int (*copyin_vector) __P((const void *udaddr, void *kaddr, size_t len)); 92extern int (*copyout_vector) __P((const void *kaddr, void *udaddr, size_t len)); 93 94void i586_bcopy __P((const void *from, void *to, size_t len)); 95void i586_bzero __P((void *buf, size_t len)); 96int i586_copyin __P((const void *udaddr, void *kaddr, size_t len)); 97int i586_copyout __P((const void *kaddr, void *udaddr, size_t len)); 98ointhand2_t npxintr; 99 100#ifdef __GNUC__ 101 102#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 103#define fnclex() __asm("fnclex") 104#define fninit() __asm("fninit") 105#define fnop() __asm("fnop") 106#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 107#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 108#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 109#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 110#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 111#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 112 : : "n" (CR0_TS) : "ax") 113#define stop_emulating() __asm("clts") 114 115#else /* not __GNUC__ */ 116 117void fldcw __P((caddr_t addr)); 118void fnclex __P((void)); 119void fninit __P((void)); 120void fnop __P((void)); 121void fnsave __P((caddr_t addr)); 122void fnstcw __P((caddr_t addr)); 123void fnstsw __P((caddr_t addr)); 124void fp_divide_by_0 __P((void)); 125void frstor __P((caddr_t addr)); 126void start_emulating __P((void)); 127void stop_emulating __P((void)); 128 129#endif /* __GNUC__ */ 130 131typedef u_char bool_t; 132 133static int npxattach __P((struct isa_device *dvp)); 134static int npxprobe __P((struct isa_device *dvp)); 135static int npxprobe1 __P((struct isa_device *dvp)); 136static long timezero __P((const char *funcname, 137 void (*func)(void *buf, size_t len))); 138 139struct isa_driver npxdriver = { 140 npxprobe, npxattach, "npx", 141}; 142 143int hw_float; /* XXX currently just alias for npx_exists */ 144 145SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 146 CTLFLAG_RD, &hw_float, 0, 147 "Floatingpoint instructions executed in hardware"); 148 149static u_int npx0_imask = SWI_CLOCK_MASK; 150 151static bool_t npx_ex16; 152static bool_t npx_exists; 153static struct gate_descriptor npx_idt_probeintr; 154static int npx_intrno; 155static volatile u_int npx_intrs_while_probing; 156static bool_t npx_irq13; 157static volatile u_int npx_traps_while_probing; 158 159#ifndef SMP 160/* 161 * Special interrupt handlers. Someday intr0-intr15 will be used to count 162 * interrupts. We'll still need a special exception 16 handler. The busy 163 * latch stuff in probeintr() can be moved to npxprobe(). 164 */ 165inthand_t probeintr; 166__asm(" \n\ 167 .text \n\ 168 .p2align 2,0x90 \n\ 169" __XSTRING(CNAME(probeintr)) ": \n\ 170 ss \n\ 171 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 172 pushl %eax \n\ 173 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 174 outb %al,$0xa0 # IO_ICU2 \n\ 175 outb %al,$0x20 # IO_ICU1 \n\ 176 movb $0,%al \n\ 177 outb %al,$0xf0 # clear BUSY# latch \n\ 178 popl %eax \n\ 179 iret \n\ 180"); 181 182inthand_t probetrap; 183__asm(" \n\ 184 .text \n\ 185 .p2align 2,0x90 \n\ 186" __XSTRING(CNAME(probetrap)) ": \n\ 187 ss \n\ 188 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 189 fnclex \n\ 190 iret \n\ 191"); 192#endif /* SMP */ 193 194/* 195 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 196 * whether the device exists or not (XXX should be elsewhere). Set flags 197 * to tell npxattach() what to do. Modify device struct if npx doesn't 198 * need to use interrupts. Return 1 if device exists. 199 */ 200static int 201npxprobe(dvp) 202 struct isa_device *dvp; 203{ 204#ifdef SMP 205 206 return npxprobe1(dvp); 207 208#else /* SMP */ 209 210 int result; 211 u_long save_eflags; 212 u_char save_icu1_mask; 213 u_char save_icu2_mask; 214 struct gate_descriptor save_idt_npxintr; 215 struct gate_descriptor save_idt_npxtrap; 216 /* 217 * This routine is now just a wrapper for npxprobe1(), to install 218 * special npx interrupt and trap handlers, to enable npx interrupts 219 * and to disable other interrupts. Someday isa_configure() will 220 * install suitable handlers and run with interrupts enabled so we 221 * won't need to do so much here. 222 */ 223 npx_intrno = NRSVIDT + ffs(dvp->id_irq) - 1; 224 save_eflags = read_eflags(); 225 disable_intr(); 226 save_icu1_mask = inb(IO_ICU1 + 1); 227 save_icu2_mask = inb(IO_ICU2 + 1); 228 save_idt_npxintr = idt[npx_intrno]; 229 save_idt_npxtrap = idt[16]; 230 outb(IO_ICU1 + 1, ~(IRQ_SLAVE | dvp->id_irq)); 231 outb(IO_ICU2 + 1, ~(dvp->id_irq >> 8)); 232 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 233 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 234 npx_idt_probeintr = idt[npx_intrno]; 235 enable_intr(); 236 result = npxprobe1(dvp); 237 disable_intr(); 238 outb(IO_ICU1 + 1, save_icu1_mask); 239 outb(IO_ICU2 + 1, save_icu2_mask); 240 idt[npx_intrno] = save_idt_npxintr; 241 idt[16] = save_idt_npxtrap; 242 write_eflags(save_eflags); 243 return (result); 244 245#endif /* SMP */ 246} 247 248static int 249npxprobe1(dvp) 250 struct isa_device *dvp; 251{ 252 u_short control; 253 u_short status; 254 255 /* 256 * Partially reset the coprocessor, if any. Some BIOS's don't reset 257 * it after a warm boot. 258 */ 259 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 260 outb(0xf0, 0); /* clear BUSY# latch */ 261 /* 262 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 263 * instructions. We must set the CR0_MP bit and use the CR0_TS 264 * bit to control the trap, because setting the CR0_EM bit does 265 * not cause WAIT instructions to trap. It's important to trap 266 * WAIT instructions - otherwise the "wait" variants of no-wait 267 * control instructions would degenerate to the "no-wait" variants 268 * after FP context switches but work correctly otherwise. It's 269 * particularly important to trap WAITs when there is no NPX - 270 * otherwise the "wait" variants would always degenerate. 271 * 272 * Try setting CR0_NE to get correct error reporting on 486DX's. 273 * Setting it should fail or do nothing on lesser processors. 274 */ 275 load_cr0(rcr0() | CR0_MP | CR0_NE); 276 /* 277 * But don't trap while we're probing. 278 */ 279 stop_emulating(); 280 /* 281 * Finish resetting the coprocessor, if any. If there is an error 282 * pending, then we may get a bogus IRQ13, but probeintr() will handle 283 * it OK. Bogus halts have never been observed, but we enabled 284 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 285 */ 286 fninit(); 287 288#ifdef SMP 289 290 /* 291 * Exception 16 MUST work for SMP. 292 */ 293 npx_irq13 = 0; 294 npx_ex16 = hw_float = npx_exists = 1; 295 dvp->id_irq = 0; /* zap the interrupt */ 296 /* 297 * special return value to flag that we do not 298 * actually use any I/O registers 299 */ 300 return (-1); 301 302#else /* SMP */ 303 304 /* 305 * Don't use fwait here because it might hang. 306 * Don't use fnop here because it usually hangs if there is no FPU. 307 */ 308 DELAY(1000); /* wait for any IRQ13 */ 309#ifdef DIAGNOSTIC 310 if (npx_intrs_while_probing != 0) 311 printf("fninit caused %u bogus npx interrupt(s)\n", 312 npx_intrs_while_probing); 313 if (npx_traps_while_probing != 0) 314 printf("fninit caused %u bogus npx trap(s)\n", 315 npx_traps_while_probing); 316#endif 317 /* 318 * Check for a status of mostly zero. 319 */ 320 status = 0x5a5a; 321 fnstsw(&status); 322 if ((status & 0xb8ff) == 0) { 323 /* 324 * Good, now check for a proper control word. 325 */ 326 control = 0x5a5a; 327 fnstcw(&control); 328 if ((control & 0x1f3f) == 0x033f) { 329 hw_float = npx_exists = 1; 330 /* 331 * We have an npx, now divide by 0 to see if exception 332 * 16 works. 333 */ 334 control &= ~(1 << 2); /* enable divide by 0 trap */ 335 fldcw(&control); 336 npx_traps_while_probing = npx_intrs_while_probing = 0; 337 fp_divide_by_0(); 338 if (npx_traps_while_probing != 0) { 339 /* 340 * Good, exception 16 works. 341 */ 342 npx_ex16 = 1; 343 dvp->id_irq = 0; /* zap the interrupt */ 344 /* 345 * special return value to flag that we do not 346 * actually use any I/O registers 347 */ 348 return (-1); 349 } 350 if (npx_intrs_while_probing != 0) { 351 /* 352 * Bad, we are stuck with IRQ13. 353 */ 354 npx_irq13 = 1; 355 /* 356 * npxattach would be too late to set npx0_imask. 357 */ 358 npx0_imask |= dvp->id_irq; 359 return (IO_NPXSIZE); 360 } 361 /* 362 * Worse, even IRQ13 is broken. Use emulator. 363 */ 364 } 365 } 366 /* 367 * Probe failed, but we want to get to npxattach to initialize the 368 * emulator and say that it has been installed. XXX handle devices 369 * that aren't really devices better. 370 */ 371 dvp->id_irq = 0; 372 /* 373 * special return value to flag that we do not 374 * actually use any I/O registers 375 */ 376 return (-1); 377 378#endif /* SMP */ 379} 380 381/* 382 * Attach routine - announce which it is, and wire into system 383 */ 384int 385npxattach(dvp) 386 struct isa_device *dvp; 387{ 388 dvp->id_ointr = npxintr; 389 390 /* The caller has printed "irq 13" for the npx_irq13 case. */ 391 if (!npx_irq13) { 392 printf("npx%d: ", dvp->id_unit); 393 if (npx_ex16) 394 printf("INT 16 interface\n"); 395#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 396 else if (npx_exists) { 397 printf("error reporting broken; using 387 emulator\n"); 398 hw_float = npx_exists = 0; 399 } else 400 printf("387 emulator\n"); 401#else 402 else 403 printf("no 387 emulator in kernel!\n"); 404#endif 405 } 406 npxinit(__INITIAL_NPXCW__); 407 408#ifdef I586_CPU 409 if (cpu_class == CPUCLASS_586 && npx_ex16 && 410 timezero("i586_bzero()", i586_bzero) < 411 timezero("bzero()", bzero) * 4 / 5) { 412 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 413 bcopy_vector = i586_bcopy; 414 ovbcopy_vector = i586_bcopy; 415 } 416 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 417 bzero = i586_bzero; 418 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 419 copyin_vector = i586_copyin; 420 copyout_vector = i586_copyout; 421 } 422 } 423#endif 424 425 return (1); /* XXX unused */ 426} 427 428/* 429 * Initialize floating point unit. 430 */ 431void 432npxinit(control) 433 u_short control; 434{ 435 struct save87 dummy; 436 437 if (!npx_exists) 438 return; 439 /* 440 * fninit has the same h/w bugs as fnsave. Use the detoxified 441 * fnsave to throw away any junk in the fpu. npxsave() initializes 442 * the fpu and sets npxproc = NULL as important side effects. 443 */ 444 npxsave(&dummy); 445 stop_emulating(); 446 fldcw(&control); 447 if (curpcb != NULL) 448 fnsave(&curpcb->pcb_savefpu); 449 start_emulating(); 450} 451 452/* 453 * Free coprocessor (if we have it). 454 */ 455void 456npxexit(p) 457 struct proc *p; 458{ 459 460 if (p == npxproc) 461 npxsave(&curpcb->pcb_savefpu); 462#ifdef NPX_DEBUG 463 if (npx_exists) { 464 u_int masked_exceptions; 465 466 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 467 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 468 /* 469 * Log exceptions that would have trapped with the old 470 * control word (overflow, divide by 0, and invalid operand). 471 */ 472 if (masked_exceptions & 0x0d) 473 log(LOG_ERR, 474 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 475 p->p_pid, p->p_comm, masked_exceptions); 476 } 477#endif 478} 479 480/* 481 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 482 * 483 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 484 * depend on longjmp() restoring a usable state. Restoring the state 485 * or examining it might fail if we didn't clear exceptions. 486 * 487 * XXX there is no standard way to tell SIGFPE handlers about the error 488 * state. The old interface: 489 * 490 * void handler(int sig, int code, struct sigcontext *scp); 491 * 492 * is broken because it is non-ANSI and because the FP state is not in 493 * struct sigcontext. 494 * 495 * XXX the FP state is not preserved across signal handlers. So signal 496 * handlers cannot afford to do FP unless they preserve the state or 497 * longjmp() out. Both preserving the state and longjmp()ing may be 498 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 499 * solution for signals other than SIGFPE. 500 */ 501void 502npxintr(unit) 503 int unit; 504{ 505 int code; 506 struct intrframe *frame; 507 508 if (npxproc == NULL || !npx_exists) { 509 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 510 npxproc, curproc, npx_exists); 511 panic("npxintr from nowhere"); 512 } 513 if (npxproc != curproc) { 514 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 515 npxproc, curproc, npx_exists); 516 panic("npxintr from non-current process"); 517 } 518 519 outb(0xf0, 0); 520 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 521 fnclex(); 522 523 /* 524 * Pass exception to process. 525 */ 526 frame = (struct intrframe *)&unit; /* XXX */ 527 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 528 /* 529 * Interrupt is essentially a trap, so we can afford to call 530 * the SIGFPE handler (if any) as soon as the interrupt 531 * returns. 532 * 533 * XXX little or nothing is gained from this, and plenty is 534 * lost - the interrupt frame has to contain the trap frame 535 * (this is otherwise only necessary for the rescheduling trap 536 * in doreti, and the frame for that could easily be set up 537 * just before it is used). 538 */ 539 curproc->p_md.md_regs = (struct trapframe *)&frame->if_es; 540#ifdef notyet 541 /* 542 * Encode the appropriate code for detailed information on 543 * this exception. 544 */ 545 code = XXX_ENCODE(curpcb->pcb_savefpu.sv_ex_sw); 546#else 547 code = 0; /* XXX */ 548#endif 549 trapsignal(curproc, SIGFPE, code); 550 } else { 551 /* 552 * Nested interrupt. These losers occur when: 553 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 554 * o immediately after an fnsave or frstor of an 555 * error state. 556 * o a couple of 386 instructions after 557 * "fstpl _memvar" causes a stack overflow. 558 * These are especially nasty when combined with a 559 * trace trap. 560 * o an IRQ13 occurs at the same time as another higher- 561 * priority interrupt. 562 * 563 * Treat them like a true async interrupt. 564 */ 565 psignal(curproc, SIGFPE); 566 } 567} 568 569/* 570 * Implement device not available (DNA) exception 571 * 572 * It would be better to switch FP context here (if curproc != npxproc) 573 * and not necessarily for every context switch, but it is too hard to 574 * access foreign pcb's. 575 */ 576int 577npxdna() 578{ 579 if (!npx_exists) 580 return (0); 581 if (npxproc != NULL) { 582 printf("npxdna: npxproc = %p, curproc = %p\n", 583 npxproc, curproc); 584 panic("npxdna"); 585 } 586 stop_emulating(); 587 /* 588 * Record new context early in case frstor causes an IRQ13. 589 */ 590 npxproc = curproc; 591 curpcb->pcb_savefpu.sv_ex_sw = 0; 592 /* 593 * The following frstor may cause an IRQ13 when the state being 594 * restored has a pending error. The error will appear to have been 595 * triggered by the current (npx) user instruction even when that 596 * instruction is a no-wait instruction that should not trigger an 597 * error (e.g., fnclex). On at least one 486 system all of the 598 * no-wait instructions are broken the same as frstor, so our 599 * treatment does not amplify the breakage. On at least one 600 * 386/Cyrix 387 system, fnclex works correctly while frstor and 601 * fnsave are broken, so our treatment breaks fnclex if it is the 602 * first FPU instruction after a context switch. 603 */ 604 frstor(&curpcb->pcb_savefpu); 605 606 return (1); 607} 608 609/* 610 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 611 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 612 * any IRQ13 to be handled immediately, and then ignore it. This routine is 613 * often called at splhigh so it must not use many system services. In 614 * particular, it's much easier to install a special handler than to 615 * guarantee that it's safe to use npxintr() and its supporting code. 616 */ 617void 618npxsave(addr) 619 struct save87 *addr; 620{ 621#ifdef SMP 622 623 stop_emulating(); 624 fnsave(addr); 625 /* fnop(); */ 626 start_emulating(); 627 npxproc = NULL; 628 629#else /* SMP */ 630 631 u_char icu1_mask; 632 u_char icu2_mask; 633 u_char old_icu1_mask; 634 u_char old_icu2_mask; 635 struct gate_descriptor save_idt_npxintr; 636 637 disable_intr(); 638 old_icu1_mask = inb(IO_ICU1 + 1); 639 old_icu2_mask = inb(IO_ICU2 + 1); 640 save_idt_npxintr = idt[npx_intrno]; 641 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 642 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 643 idt[npx_intrno] = npx_idt_probeintr; 644 enable_intr(); 645 stop_emulating(); 646 fnsave(addr); 647 fnop(); 648 start_emulating(); 649 npxproc = NULL; 650 disable_intr(); 651 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 652 icu2_mask = inb(IO_ICU2 + 1); 653 outb(IO_ICU1 + 1, 654 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 655 outb(IO_ICU2 + 1, 656 (icu2_mask & ~(npx0_imask >> 8)) 657 | (old_icu2_mask & (npx0_imask >> 8))); 658 idt[npx_intrno] = save_idt_npxintr; 659 enable_intr(); /* back to usual state */ 660 661#endif /* SMP */ 662} 663 664#ifdef I586_CPU 665static long 666timezero(funcname, func) 667 const char *funcname; 668 void (*func) __P((void *buf, size_t len)); 669 670{ 671 void *buf; 672#define BUFSIZE 1000000 673 long usec; 674 struct timeval finish, start; 675 676 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 677 if (buf == NULL) 678 return (BUFSIZE); 679 microtime(&start); 680 (*func)(buf, BUFSIZE); 681 microtime(&finish); 682 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 683 finish.tv_usec - start.tv_usec; 684 if (usec <= 0) 685 usec = 1; 686 if (bootverbose) 687 printf("%s bandwidth = %ld bytes/sec\n", 688 funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); 689 free(buf, M_TEMP); 690 return (usec); 691} 692#endif /* I586_CPU */ 693 694#endif /* NNPX > 0 */ 695