fpu.c revision 271747
1187160Sthompsa/*- 2187160Sthompsa * Copyright (c) 1990 William Jolitz. 3187160Sthompsa * Copyright (c) 1991 The Regents of the University of California. 4187160Sthompsa * All rights reserved. 5187160Sthompsa * 6187160Sthompsa * Redistribution and use in source and binary forms, with or without 7187160Sthompsa * modification, are permitted provided that the following conditions 8187160Sthompsa * are met: 9187160Sthompsa * 1. Redistributions of source code must retain the above copyright 10187160Sthompsa * notice, this list of conditions and the following disclaimer. 11187160Sthompsa * 2. Redistributions in binary form must reproduce the above copyright 12187160Sthompsa * notice, this list of conditions and the following disclaimer in the 13187160Sthompsa * documentation and/or other materials provided with the distribution. 14187160Sthompsa * 4. Neither the name of the University nor the names of its contributors 15187160Sthompsa * may be used to endorse or promote products derived from this software 16187160Sthompsa * without specific prior written permission. 17187160Sthompsa * 18187160Sthompsa * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19187160Sthompsa * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20187160Sthompsa * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21187160Sthompsa * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22187160Sthompsa * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23187160Sthompsa * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24187160Sthompsa * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25187160Sthompsa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26187160Sthompsa * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27187160Sthompsa * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28190754Sthompsa * SUCH DAMAGE. 29190754Sthompsa * 30187160Sthompsa * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31187160Sthompsa */ 32187160Sthompsa 33187160Sthompsa#include <sys/cdefs.h> 34187160Sthompsa__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 271747 2014-09-18 09:13:20Z kib $"); 35187160Sthompsa 36187160Sthompsa#include <sys/param.h> 37192446Sthompsa#include <sys/systm.h> 38192446Sthompsa#include <sys/bus.h> 39192446Sthompsa#include <sys/kernel.h> 40192446Sthompsa#include <sys/lock.h> 41187160Sthompsa#include <sys/malloc.h> 42187160Sthompsa#include <sys/module.h> 43187160Sthompsa#include <sys/mutex.h> 44187160Sthompsa#include <sys/mutex.h> 45187160Sthompsa#include <sys/proc.h> 46187160Sthompsa#include <sys/sysctl.h> 47187160Sthompsa#include <machine/bus.h> 48187160Sthompsa#include <sys/rman.h> 49187160Sthompsa#include <sys/signalvar.h> 50187160Sthompsa#include <vm/uma.h> 51187160Sthompsa 52187160Sthompsa#include <machine/cputypes.h> 53187160Sthompsa#include <machine/frame.h> 54187160Sthompsa#include <machine/intr_machdep.h> 55187160Sthompsa#include <machine/md_var.h> 56187160Sthompsa#include <machine/pcb.h> 57187160Sthompsa#include <machine/psl.h> 58187160Sthompsa#include <machine/resource.h> 59187160Sthompsa#include <machine/specialreg.h> 60187160Sthompsa#include <machine/segments.h> 61187160Sthompsa#include <machine/ucontext.h> 62187160Sthompsa 63187160Sthompsa/* 64187160Sthompsa * Floating point support. 65187160Sthompsa */ 66187160Sthompsa 67187160Sthompsa#if defined(__GNUCLIKE_ASM) && !defined(lint) 68187160Sthompsa 69187160Sthompsa#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 70187160Sthompsa#define fnclex() __asm __volatile("fnclex") 71187160Sthompsa#define fninit() __asm __volatile("fninit") 72187160Sthompsa#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73187160Sthompsa#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 74187160Sthompsa#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 75187160Sthompsa#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 76187160Sthompsa#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 77187160Sthompsa#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 78187160Sthompsa 79187160Sthompsastatic __inline void 80187160Sthompsaxrstor(char *addr, uint64_t mask) 81187160Sthompsa{ 82187160Sthompsa uint32_t low, hi; 83187160Sthompsa 84187160Sthompsa low = mask; 85187160Sthompsa hi = mask >> 32; 86187160Sthompsa __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 87187160Sthompsa} 88187160Sthompsa 89187160Sthompsastatic __inline void 90187160Sthompsaxsave(char *addr, uint64_t mask) 91187160Sthompsa{ 92187160Sthompsa uint32_t low, hi; 93187160Sthompsa 94187160Sthompsa low = mask; 95187160Sthompsa hi = mask >> 32; 96187160Sthompsa __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 97187160Sthompsa "memory"); 98187160Sthompsa} 99187160Sthompsa 100187160Sthompsa#else /* !(__GNUCLIKE_ASM && !lint) */ 101187160Sthompsa 102187160Sthompsavoid fldcw(u_short cw); 103187160Sthompsavoid fnclex(void); 104187160Sthompsavoid fninit(void); 105187160Sthompsavoid fnstcw(caddr_t addr); 106187160Sthompsavoid fnstsw(caddr_t addr); 107187160Sthompsavoid fxsave(caddr_t addr); 108187160Sthompsavoid fxrstor(caddr_t addr); 109187160Sthompsavoid ldmxcsr(u_int csr); 110187160Sthompsavoid stmxcsr(u_int *csr); 111187160Sthompsavoid xrstor(char *addr, uint64_t mask); 112187160Sthompsavoid xsave(char *addr, uint64_t mask); 113187160Sthompsa 114187160Sthompsa#endif /* __GNUCLIKE_ASM && !lint */ 115187160Sthompsa 116187160Sthompsa#define start_emulating() load_cr0(rcr0() | CR0_TS) 117187160Sthompsa#define stop_emulating() clts() 118187160Sthompsa 119187160SthompsaCTASSERT(sizeof(struct savefpu) == 512); 120187160SthompsaCTASSERT(sizeof(struct xstate_hdr) == 64); 121187160SthompsaCTASSERT(sizeof(struct savefpu_ymm) == 832); 122187160Sthompsa 123187160Sthompsa/* 124187160Sthompsa * This requirement is to make it easier for asm code to calculate 125187160Sthompsa * offset of the fpu save area from the pcb address. FPU save area 126187160Sthompsa * must be 64-byte aligned. 127187160Sthompsa */ 128187160SthompsaCTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 129187160Sthompsa 130187160Sthompsastatic void fpu_clean_state(void); 131187160Sthompsa 132187160SthompsaSYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 133187160Sthompsa NULL, 1, "Floating point instructions executed in hardware"); 134187160Sthompsa 135187160Sthompsaint use_xsave; /* non-static for cpu_switch.S */ 136187160Sthompsauint64_t xsave_mask; /* the same */ 137187160Sthompsastatic uma_zone_t fpu_save_area_zone; 138187160Sthompsastatic struct savefpu *fpu_initialstate; 139187160Sthompsa 140187160Sthompsastruct xsave_area_elm_descr { 141187160Sthompsa u_int offset; 142187160Sthompsa u_int size; 143192446Sthompsa} *xsave_area_desc; 144192446Sthompsa 145192446Sthompsavoid 146192446Sthompsafpusave(void *addr) 147192446Sthompsa{ 148192446Sthompsa 149192446Sthompsa if (use_xsave) 150192446Sthompsa xsave((char *)addr, xsave_mask); 151192446Sthompsa else 152192446Sthompsa fxsave((char *)addr); 153187160Sthompsa} 154187160Sthompsa 155192446Sthompsavoid 156187160Sthompsafpurestore(void *addr) 157187160Sthompsa{ 158187160Sthompsa 159187160Sthompsa if (use_xsave) 160187160Sthompsa xrstor((char *)addr, xsave_mask); 161187160Sthompsa else 162187160Sthompsa fxrstor((char *)addr); 163192446Sthompsa} 164187160Sthompsa 165187160Sthompsavoid 166187160Sthompsafpususpend(void *addr) 167187160Sthompsa{ 168187160Sthompsa u_long cr0; 169187160Sthompsa 170189677Sthompsa cr0 = rcr0(); 171189677Sthompsa stop_emulating(); 172189677Sthompsa fpusave(addr); 173187160Sthompsa load_cr0(cr0); 174187160Sthompsa} 175187160Sthompsa 176187160Sthompsavoid 177187160Sthompsafpuresume(void *addr) 178187160Sthompsa{ 179187160Sthompsa u_long cr0; 180187160Sthompsa 181187160Sthompsa cr0 = rcr0(); 182187160Sthompsa stop_emulating(); 183187160Sthompsa fninit(); 184187160Sthompsa if (use_xsave) 185187160Sthompsa load_xcr(XCR0, xsave_mask); 186187160Sthompsa fpurestore(addr); 187187160Sthompsa load_cr0(cr0); 188187160Sthompsa} 189187160Sthompsa 190187160Sthompsa/* 191187160Sthompsa * Enable XSAVE if supported and allowed by user. 192187160Sthompsa * Calculate the xsave_mask. 193187160Sthompsa */ 194192984Sthompsastatic void 195187160Sthompsafpuinit_bsp1(void) 196187160Sthompsa{ 197187160Sthompsa u_int cp[4]; 198187160Sthompsa uint64_t xsave_mask_user; 199192984Sthompsa 200187160Sthompsa if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 201187160Sthompsa use_xsave = 1; 202187160Sthompsa TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 203187160Sthompsa } 204187160Sthompsa if (!use_xsave) 205187160Sthompsa return; 206187160Sthompsa 207187160Sthompsa cpuid_count(0xd, 0x0, cp); 208187160Sthompsa xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 209187160Sthompsa if ((cp[0] & xsave_mask) != xsave_mask) 210187160Sthompsa panic("CPU0 does not support X87 or SSE: %x", cp[0]); 211187160Sthompsa xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 212187160Sthompsa xsave_mask_user = xsave_mask; 213192984Sthompsa TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 214187160Sthompsa xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 215187160Sthompsa xsave_mask &= xsave_mask_user; 216187160Sthompsa if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 217187160Sthompsa xsave_mask &= ~XFEATURE_AVX512; 218187160Sthompsa if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 219187160Sthompsa xsave_mask &= ~XFEATURE_MPX; 220187160Sthompsa 221187160Sthompsa cpuid_count(0xd, 0x1, cp); 222187160Sthompsa if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 223187160Sthompsa /* 224187160Sthompsa * Patch the XSAVE instruction in the cpu_switch code 225192552Sthompsa * to XSAVEOPT. We assume that XSAVE encoding used 226187160Sthompsa * REX byte, and set the bit 4 of the r/m byte. 227187160Sthompsa */ 228187160Sthompsa ctx_switch_xsave[3] |= 0x10; 229192984Sthompsa } 230192984Sthompsa} 231192984Sthompsa 232187160Sthompsa/* 233187160Sthompsa * Calculate the fpu save area size. 234187160Sthompsa */ 235187160Sthompsastatic void 236192984Sthompsafpuinit_bsp2(void) 237187160Sthompsa{ 238187160Sthompsa u_int cp[4]; 239187160Sthompsa 240187160Sthompsa if (use_xsave) { 241187160Sthompsa cpuid_count(0xd, 0x0, cp); 242187160Sthompsa cpu_max_ext_state_size = cp[1]; 243187160Sthompsa 244187160Sthompsa /* 245187160Sthompsa * Reload the cpu_feature2, since we enabled OSXSAVE. 246187160Sthompsa */ 247187160Sthompsa do_cpuid(1, cp); 248187160Sthompsa cpu_feature2 = cp[2]; 249187160Sthompsa } else 250187160Sthompsa cpu_max_ext_state_size = sizeof(struct savefpu); 251187160Sthompsa} 252187160Sthompsa 253187160Sthompsa/* 254192984Sthompsa * Initialize the floating point unit. 255187160Sthompsa */ 256187160Sthompsavoid 257187160Sthompsafpuinit(void) 258187160Sthompsa{ 259187160Sthompsa register_t saveintr; 260187160Sthompsa u_int mxcsr; 261192984Sthompsa u_short control; 262187160Sthompsa 263187160Sthompsa if (IS_BSP()) 264187160Sthompsa fpuinit_bsp1(); 265187160Sthompsa 266187160Sthompsa if (use_xsave) { 267190735Sthompsa load_cr4(rcr4() | CR4_XSAVE); 268187160Sthompsa load_xcr(XCR0, xsave_mask); 269187160Sthompsa } 270187160Sthompsa 271187160Sthompsa /* 272187160Sthompsa * XCR0 shall be set up before CPU can report the save area size. 273187160Sthompsa */ 274187160Sthompsa if (IS_BSP()) 275187160Sthompsa fpuinit_bsp2(); 276187160Sthompsa 277187160Sthompsa /* 278187160Sthompsa * It is too early for critical_enter() to work on AP. 279193045Sthompsa */ 280187160Sthompsa saveintr = intr_disable(); 281187160Sthompsa stop_emulating(); 282187160Sthompsa fninit(); 283187160Sthompsa control = __INITIAL_FPUCW__; 284 fldcw(control); 285 mxcsr = __INITIAL_MXCSR__; 286 ldmxcsr(mxcsr); 287 start_emulating(); 288 intr_restore(saveintr); 289} 290 291/* 292 * On the boot CPU we generate a clean state that is used to 293 * initialize the floating point unit when it is first used by a 294 * process. 295 */ 296static void 297fpuinitstate(void *arg __unused) 298{ 299 register_t saveintr; 300 int cp[4], i, max_ext_n; 301 302 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 303 M_WAITOK | M_ZERO); 304 saveintr = intr_disable(); 305 stop_emulating(); 306 307 fpusave(fpu_initialstate); 308 if (fpu_initialstate->sv_env.en_mxcsr_mask) 309 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 310 else 311 cpu_mxcsr_mask = 0xFFBF; 312 313 /* 314 * The fninit instruction does not modify XMM registers. The 315 * fpusave call dumped the garbage contained in the registers 316 * after reset to the initial state saved. Clear XMM 317 * registers file image to make the startup program state and 318 * signal handler XMM register content predictable. 319 */ 320 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc)); 321 322 /* 323 * Create a table describing the layout of the CPU Extended 324 * Save Area. 325 */ 326 if (use_xsave) { 327 max_ext_n = flsl(xsave_mask); 328 xsave_area_desc = malloc(max_ext_n * sizeof(struct 329 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 330 /* x87 state */ 331 xsave_area_desc[0].offset = 0; 332 xsave_area_desc[0].size = 160; 333 /* XMM */ 334 xsave_area_desc[1].offset = 160; 335 xsave_area_desc[1].size = 288 - 160; 336 337 for (i = 2; i < max_ext_n; i++) { 338 cpuid_count(0xd, i, cp); 339 xsave_area_desc[i].offset = cp[1]; 340 xsave_area_desc[i].size = cp[0]; 341 } 342 } 343 344 fpu_save_area_zone = uma_zcreate("FPU_save_area", 345 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 346 XSAVE_AREA_ALIGN - 1, 0); 347 348 start_emulating(); 349 intr_restore(saveintr); 350} 351SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL); 352 353/* 354 * Free coprocessor (if we have it). 355 */ 356void 357fpuexit(struct thread *td) 358{ 359 360 critical_enter(); 361 if (curthread == PCPU_GET(fpcurthread)) { 362 stop_emulating(); 363 fpusave(curpcb->pcb_save); 364 start_emulating(); 365 PCPU_SET(fpcurthread, NULL); 366 } 367 critical_exit(); 368} 369 370int 371fpuformat() 372{ 373 374 return (_MC_FPFMT_XMM); 375} 376 377/* 378 * The following mechanism is used to ensure that the FPE_... value 379 * that is passed as a trapcode to the signal handler of the user 380 * process does not have more than one bit set. 381 * 382 * Multiple bits may be set if the user process modifies the control 383 * word while a status word bit is already set. While this is a sign 384 * of bad coding, we have no choise than to narrow them down to one 385 * bit, since we must not send a trapcode that is not exactly one of 386 * the FPE_ macros. 387 * 388 * The mechanism has a static table with 127 entries. Each combination 389 * of the 7 FPU status word exception bits directly translates to a 390 * position in this table, where a single FPE_... value is stored. 391 * This FPE_... value stored there is considered the "most important" 392 * of the exception bits and will be sent as the signal code. The 393 * precedence of the bits is based upon Intel Document "Numerical 394 * Applications", Chapter "Special Computational Situations". 395 * 396 * The macro to choose one of these values does these steps: 1) Throw 397 * away status word bits that cannot be masked. 2) Throw away the bits 398 * currently masked in the control word, assuming the user isn't 399 * interested in them anymore. 3) Reinsert status word bit 7 (stack 400 * fault) if it is set, which cannot be masked but must be presered. 401 * 4) Use the remaining bits to point into the trapcode table. 402 * 403 * The 6 maskable bits in order of their preference, as stated in the 404 * above referenced Intel manual: 405 * 1 Invalid operation (FP_X_INV) 406 * 1a Stack underflow 407 * 1b Stack overflow 408 * 1c Operand of unsupported format 409 * 1d SNaN operand. 410 * 2 QNaN operand (not an exception, irrelavant here) 411 * 3 Any other invalid-operation not mentioned above or zero divide 412 * (FP_X_INV, FP_X_DZ) 413 * 4 Denormal operand (FP_X_DNML) 414 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 415 * 6 Inexact result (FP_X_IMP) 416 */ 417static char fpetable[128] = { 418 0, 419 FPE_FLTINV, /* 1 - INV */ 420 FPE_FLTUND, /* 2 - DNML */ 421 FPE_FLTINV, /* 3 - INV | DNML */ 422 FPE_FLTDIV, /* 4 - DZ */ 423 FPE_FLTINV, /* 5 - INV | DZ */ 424 FPE_FLTDIV, /* 6 - DNML | DZ */ 425 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 426 FPE_FLTOVF, /* 8 - OFL */ 427 FPE_FLTINV, /* 9 - INV | OFL */ 428 FPE_FLTUND, /* A - DNML | OFL */ 429 FPE_FLTINV, /* B - INV | DNML | OFL */ 430 FPE_FLTDIV, /* C - DZ | OFL */ 431 FPE_FLTINV, /* D - INV | DZ | OFL */ 432 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 433 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 434 FPE_FLTUND, /* 10 - UFL */ 435 FPE_FLTINV, /* 11 - INV | UFL */ 436 FPE_FLTUND, /* 12 - DNML | UFL */ 437 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 438 FPE_FLTDIV, /* 14 - DZ | UFL */ 439 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 440 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 441 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 442 FPE_FLTOVF, /* 18 - OFL | UFL */ 443 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 444 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 445 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 446 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 447 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 448 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 449 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 450 FPE_FLTRES, /* 20 - IMP */ 451 FPE_FLTINV, /* 21 - INV | IMP */ 452 FPE_FLTUND, /* 22 - DNML | IMP */ 453 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 454 FPE_FLTDIV, /* 24 - DZ | IMP */ 455 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 456 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 457 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 458 FPE_FLTOVF, /* 28 - OFL | IMP */ 459 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 460 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 461 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 462 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 463 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 464 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 465 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 466 FPE_FLTUND, /* 30 - UFL | IMP */ 467 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 468 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 469 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 470 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 471 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 472 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 473 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 474 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 475 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 476 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 477 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 478 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 479 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 480 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 481 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 482 FPE_FLTSUB, /* 40 - STK */ 483 FPE_FLTSUB, /* 41 - INV | STK */ 484 FPE_FLTUND, /* 42 - DNML | STK */ 485 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 486 FPE_FLTDIV, /* 44 - DZ | STK */ 487 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 488 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 489 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 490 FPE_FLTOVF, /* 48 - OFL | STK */ 491 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 492 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 493 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 494 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 495 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 496 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 497 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 498 FPE_FLTUND, /* 50 - UFL | STK */ 499 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 500 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 501 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 502 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 503 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 504 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 505 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 506 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 507 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 508 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 509 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 510 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 511 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 512 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 513 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 514 FPE_FLTRES, /* 60 - IMP | STK */ 515 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 516 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 517 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 518 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 519 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 520 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 521 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 522 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 523 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 524 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 525 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 526 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 527 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 528 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 529 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 530 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 531 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 532 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 533 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 534 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 535 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 536 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 537 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 538 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 539 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 540 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 541 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 542 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 543 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 544 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 545 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 546}; 547 548/* 549 * Read the FP status and control words, then generate si_code value 550 * for SIGFPE. The error code chosen will be one of the 551 * FPE_... macros. It will be sent as the second argument to old 552 * BSD-style signal handlers and as "siginfo_t->si_code" (second 553 * argument) to SA_SIGINFO signal handlers. 554 * 555 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 556 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 557 * usermode code which understands the FPU hardware enough to enable 558 * the exceptions, can also handle clearing the exception state in the 559 * handler. The only consequence of not clearing the exception is the 560 * rethrow of the SIGFPE on return from the signal handler and 561 * reexecution of the corresponding instruction. 562 * 563 * For XMM traps, the exceptions were never cleared. 564 */ 565int 566fputrap_x87(void) 567{ 568 struct savefpu *pcb_save; 569 u_short control, status; 570 571 critical_enter(); 572 573 /* 574 * Interrupt handling (for another interrupt) may have pushed the 575 * state to memory. Fetch the relevant parts of the state from 576 * wherever they are. 577 */ 578 if (PCPU_GET(fpcurthread) != curthread) { 579 pcb_save = curpcb->pcb_save; 580 control = pcb_save->sv_env.en_cw; 581 status = pcb_save->sv_env.en_sw; 582 } else { 583 fnstcw(&control); 584 fnstsw(&status); 585 } 586 587 critical_exit(); 588 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 589} 590 591int 592fputrap_sse(void) 593{ 594 u_int mxcsr; 595 596 critical_enter(); 597 if (PCPU_GET(fpcurthread) != curthread) 598 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 599 else 600 stmxcsr(&mxcsr); 601 critical_exit(); 602 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 603} 604 605static int err_count = 0; 606 607/* 608 * Device Not Available (DNA, #NM) exception handler. 609 * 610 * It would be better to switch FP context here (if curthread != 611 * fpcurthread) and not necessarily for every context switch, but it 612 * is too hard to access foreign pcb's. 613 * 614 * The handler is entered with interrupts enabled, which allows the 615 * context switch to happen before critical enter() is executed, and 616 * causes restoration of FPU context on CPU other than that caused 617 * DNA. It is fine, since context switch started emulation on the 618 * current CPU as well. 619 */ 620void 621fpudna(void) 622{ 623 624 critical_enter(); 625 if (PCPU_GET(fpcurthread) == curthread) { 626 printf("fpudna: fpcurthread == curthread %d times\n", 627 ++err_count); 628 stop_emulating(); 629 critical_exit(); 630 return; 631 } 632 if (PCPU_GET(fpcurthread) != NULL) { 633 panic("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 634 PCPU_GET(fpcurthread), PCPU_GET(fpcurthread)->td_tid, 635 curthread, curthread->td_tid); 636 } 637 stop_emulating(); 638 /* 639 * Record new context early in case frstor causes a trap. 640 */ 641 PCPU_SET(fpcurthread, curthread); 642 643 fpu_clean_state(); 644 645 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) { 646 /* 647 * This is the first time this thread has used the FPU or 648 * the PCB doesn't contain a clean FPU state. Explicitly 649 * load an initial state. 650 * 651 * We prefer to restore the state from the actual save 652 * area in PCB instead of directly loading from 653 * fpu_initialstate, to ignite the XSAVEOPT 654 * tracking engine. 655 */ 656 bcopy(fpu_initialstate, curpcb->pcb_save, cpu_max_ext_state_size); 657 fpurestore(curpcb->pcb_save); 658 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 659 fldcw(curpcb->pcb_initial_fpucw); 660 if (PCB_USER_FPU(curpcb)) 661 set_pcb_flags(curpcb, 662 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 663 else 664 set_pcb_flags(curpcb, PCB_FPUINITDONE); 665 } else 666 fpurestore(curpcb->pcb_save); 667 critical_exit(); 668} 669 670void 671fpudrop() 672{ 673 struct thread *td; 674 675 td = PCPU_GET(fpcurthread); 676 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 677 CRITICAL_ASSERT(td); 678 PCPU_SET(fpcurthread, NULL); 679 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 680 start_emulating(); 681} 682 683/* 684 * Get the user state of the FPU into pcb->pcb_user_save without 685 * dropping ownership (if possible). It returns the FPU ownership 686 * status. 687 */ 688int 689fpugetregs(struct thread *td) 690{ 691 struct pcb *pcb; 692 uint64_t *xstate_bv, bit; 693 char *sa; 694 int max_ext_n, i, owned; 695 696 pcb = td->td_pcb; 697 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 698 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 699 cpu_max_ext_state_size); 700 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 701 pcb->pcb_initial_fpucw; 702 fpuuserinited(td); 703 return (_MC_FPOWNED_PCB); 704 } 705 critical_enter(); 706 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 707 fpusave(get_pcb_user_save_pcb(pcb)); 708 owned = _MC_FPOWNED_FPU; 709 } else { 710 owned = _MC_FPOWNED_PCB; 711 } 712 critical_exit(); 713 if (use_xsave) { 714 /* 715 * Handle partially saved state. 716 */ 717 sa = (char *)get_pcb_user_save_pcb(pcb); 718 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 719 offsetof(struct xstate_hdr, xstate_bv)); 720 max_ext_n = flsl(xsave_mask); 721 for (i = 0; i < max_ext_n; i++) { 722 bit = 1ULL << i; 723 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 724 continue; 725 bcopy((char *)fpu_initialstate + 726 xsave_area_desc[i].offset, 727 sa + xsave_area_desc[i].offset, 728 xsave_area_desc[i].size); 729 *xstate_bv |= bit; 730 } 731 } 732 return (owned); 733} 734 735void 736fpuuserinited(struct thread *td) 737{ 738 struct pcb *pcb; 739 740 pcb = td->td_pcb; 741 if (PCB_USER_FPU(pcb)) 742 set_pcb_flags(pcb, 743 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 744 else 745 set_pcb_flags(pcb, PCB_FPUINITDONE); 746} 747 748int 749fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 750{ 751 struct xstate_hdr *hdr, *ehdr; 752 size_t len, max_len; 753 uint64_t bv; 754 755 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 756 if (xfpustate == NULL) 757 return (0); 758 if (!use_xsave) 759 return (EOPNOTSUPP); 760 761 len = xfpustate_size; 762 if (len < sizeof(struct xstate_hdr)) 763 return (EINVAL); 764 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 765 if (len > max_len) 766 return (EINVAL); 767 768 ehdr = (struct xstate_hdr *)xfpustate; 769 bv = ehdr->xstate_bv; 770 771 /* 772 * Avoid #gp. 773 */ 774 if (bv & ~xsave_mask) 775 return (EINVAL); 776 777 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 778 779 hdr->xstate_bv = bv; 780 bcopy(xfpustate + sizeof(struct xstate_hdr), 781 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 782 783 return (0); 784} 785 786/* 787 * Set the state of the FPU. 788 */ 789int 790fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 791 size_t xfpustate_size) 792{ 793 struct pcb *pcb; 794 int error; 795 796 pcb = td->td_pcb; 797 critical_enter(); 798 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 799 error = fpusetxstate(td, xfpustate, xfpustate_size); 800 if (error != 0) { 801 critical_exit(); 802 return (error); 803 } 804 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 805 fpurestore(get_pcb_user_save_td(td)); 806 critical_exit(); 807 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE); 808 } else { 809 critical_exit(); 810 error = fpusetxstate(td, xfpustate, xfpustate_size); 811 if (error != 0) 812 return (error); 813 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 814 fpuuserinited(td); 815 } 816 return (0); 817} 818 819/* 820 * On AuthenticAMD processors, the fxrstor instruction does not restore 821 * the x87's stored last instruction pointer, last data pointer, and last 822 * opcode values, except in the rare case in which the exception summary 823 * (ES) bit in the x87 status word is set to 1. 824 * 825 * In order to avoid leaking this information across processes, we clean 826 * these values by performing a dummy load before executing fxrstor(). 827 */ 828static void 829fpu_clean_state(void) 830{ 831 static float dummy_variable = 0.0; 832 u_short status; 833 834 /* 835 * Clear the ES bit in the x87 status word if it is currently 836 * set, in order to avoid causing a fault in the upcoming load. 837 */ 838 fnstsw(&status); 839 if (status & 0x80) 840 fnclex(); 841 842 /* 843 * Load the dummy variable into the x87 stack. This mangles 844 * the x87 stack, but we don't care since we're about to call 845 * fxrstor() anyway. 846 */ 847 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 848} 849 850/* 851 * This really sucks. We want the acpi version only, but it requires 852 * the isa_if.h file in order to get the definitions. 853 */ 854#include "opt_isa.h" 855#ifdef DEV_ISA 856#include <isa/isavar.h> 857/* 858 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 859 */ 860static struct isa_pnp_id fpupnp_ids[] = { 861 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 862 { 0 } 863}; 864 865static int 866fpupnp_probe(device_t dev) 867{ 868 int result; 869 870 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 871 if (result <= 0) 872 device_quiet(dev); 873 return (result); 874} 875 876static int 877fpupnp_attach(device_t dev) 878{ 879 880 return (0); 881} 882 883static device_method_t fpupnp_methods[] = { 884 /* Device interface */ 885 DEVMETHOD(device_probe, fpupnp_probe), 886 DEVMETHOD(device_attach, fpupnp_attach), 887 DEVMETHOD(device_detach, bus_generic_detach), 888 DEVMETHOD(device_shutdown, bus_generic_shutdown), 889 DEVMETHOD(device_suspend, bus_generic_suspend), 890 DEVMETHOD(device_resume, bus_generic_resume), 891 892 { 0, 0 } 893}; 894 895static driver_t fpupnp_driver = { 896 "fpupnp", 897 fpupnp_methods, 898 1, /* no softc */ 899}; 900 901static devclass_t fpupnp_devclass; 902 903DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 904#endif /* DEV_ISA */ 905 906static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 907 "Kernel contexts for FPU state"); 908 909#define FPU_KERN_CTX_FPUINITDONE 0x01 910#define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 911 912struct fpu_kern_ctx { 913 struct savefpu *prev; 914 uint32_t flags; 915 char hwstate1[]; 916}; 917 918struct fpu_kern_ctx * 919fpu_kern_alloc_ctx(u_int flags) 920{ 921 struct fpu_kern_ctx *res; 922 size_t sz; 923 924 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 925 cpu_max_ext_state_size; 926 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 927 M_NOWAIT : M_WAITOK) | M_ZERO); 928 return (res); 929} 930 931void 932fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 933{ 934 935 /* XXXKIB clear the memory ? */ 936 free(ctx, M_FPUKERN_CTX); 937} 938 939static struct savefpu * 940fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 941{ 942 vm_offset_t p; 943 944 p = (vm_offset_t)&ctx->hwstate1; 945 p = roundup2(p, XSAVE_AREA_ALIGN); 946 return ((struct savefpu *)p); 947} 948 949int 950fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 951{ 952 struct pcb *pcb; 953 954 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 955 ctx->flags = FPU_KERN_CTX_DUMMY; 956 return (0); 957 } 958 pcb = td->td_pcb; 959 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 960 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 961 ctx->flags = 0; 962 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 963 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 964 fpuexit(td); 965 ctx->prev = pcb->pcb_save; 966 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 967 set_pcb_flags(pcb, PCB_KERNFPU); 968 clear_pcb_flags(pcb, PCB_FPUINITDONE); 969 return (0); 970} 971 972int 973fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 974{ 975 struct pcb *pcb; 976 977 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 978 return (0); 979 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, ("dummy ctx")); 980 pcb = td->td_pcb; 981 critical_enter(); 982 if (curthread == PCPU_GET(fpcurthread)) 983 fpudrop(); 984 critical_exit(); 985 pcb->pcb_save = ctx->prev; 986 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 987 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 988 set_pcb_flags(pcb, PCB_FPUINITDONE); 989 clear_pcb_flags(pcb, PCB_KERNFPU); 990 } else 991 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 992 } else { 993 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 994 set_pcb_flags(pcb, PCB_FPUINITDONE); 995 else 996 clear_pcb_flags(pcb, PCB_FPUINITDONE); 997 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 998 } 999 return (0); 1000} 1001 1002int 1003fpu_kern_thread(u_int flags) 1004{ 1005 1006 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1007 ("Only kthread may use fpu_kern_thread")); 1008 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1009 ("mangled pcb_save")); 1010 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1011 1012 set_pcb_flags(curpcb, PCB_KERNFPU); 1013 return (0); 1014} 1015 1016int 1017is_fpu_kern_thread(u_int flags) 1018{ 1019 1020 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1021 return (0); 1022 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 1023} 1024 1025/* 1026 * FPU save area alloc/free/init utility routines 1027 */ 1028struct savefpu * 1029fpu_save_area_alloc(void) 1030{ 1031 1032 return (uma_zalloc(fpu_save_area_zone, 0)); 1033} 1034 1035void 1036fpu_save_area_free(struct savefpu *fsa) 1037{ 1038 1039 uma_zfree(fpu_save_area_zone, fsa); 1040} 1041 1042void 1043fpu_save_area_reset(struct savefpu *fsa) 1044{ 1045 1046 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1047} 1048