fpu.c revision 238668
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 238668 2012-07-21 13:05:34Z kib $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50 51#include <machine/cputypes.h> 52#include <machine/frame.h> 53#include <machine/intr_machdep.h> 54#include <machine/md_var.h> 55#include <machine/pcb.h> 56#include <machine/psl.h> 57#include <machine/resource.h> 58#include <machine/specialreg.h> 59#include <machine/segments.h> 60#include <machine/ucontext.h> 61 62/* 63 * Floating point support. 64 */ 65 66#if defined(__GNUCLIKE_ASM) && !defined(lint) 67 68#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 69#define fnclex() __asm __volatile("fnclex") 70#define fninit() __asm __volatile("fninit") 71#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 72#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 73#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 74#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 76#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 77 78static __inline void 79xrstor(char *addr, uint64_t mask) 80{ 81 uint32_t low, hi; 82 83 low = mask; 84 hi = mask >> 32; 85 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 86} 87 88static __inline void 89xsave(char *addr, uint64_t mask) 90{ 91 uint32_t low, hi; 92 93 low = mask; 94 hi = mask >> 32; 95 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 96 "memory"); 97} 98 99#else /* !(__GNUCLIKE_ASM && !lint) */ 100 101void fldcw(u_short cw); 102void fnclex(void); 103void fninit(void); 104void fnstcw(caddr_t addr); 105void fnstsw(caddr_t addr); 106void fxsave(caddr_t addr); 107void fxrstor(caddr_t addr); 108void ldmxcsr(u_int csr); 109void stmxcsr(u_int csr); 110void xrstor(char *addr, uint64_t mask); 111void xsave(char *addr, uint64_t mask); 112 113#endif /* __GNUCLIKE_ASM && !lint */ 114 115#define start_emulating() load_cr0(rcr0() | CR0_TS) 116#define stop_emulating() clts() 117 118CTASSERT(sizeof(struct savefpu) == 512); 119CTASSERT(sizeof(struct xstate_hdr) == 64); 120CTASSERT(sizeof(struct savefpu_ymm) == 832); 121 122/* 123 * This requirement is to make it easier for asm code to calculate 124 * offset of the fpu save area from the pcb address. FPU save area 125 * must be 64-byte aligned. 126 */ 127CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 128 129static void fpu_clean_state(void); 130 131SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 132 NULL, 1, "Floating point instructions executed in hardware"); 133 134static int use_xsaveopt; 135int use_xsave; /* non-static for cpu_switch.S */ 136uint64_t xsave_mask; /* the same */ 137static struct savefpu *fpu_initialstate; 138 139struct xsave_area_elm_descr { 140 u_int offset; 141 u_int size; 142} *xsave_area_desc; 143 144void 145fpusave(void *addr) 146{ 147 148 if (use_xsave) 149 xsave((char *)addr, xsave_mask); 150 else 151 fxsave((char *)addr); 152} 153 154static void 155fpurestore(void *addr) 156{ 157 158 if (use_xsave) 159 xrstor((char *)addr, xsave_mask); 160 else 161 fxrstor((char *)addr); 162} 163 164/* 165 * Enable XSAVE if supported and allowed by user. 166 * Calculate the xsave_mask. 167 */ 168static void 169fpuinit_bsp1(void) 170{ 171 u_int cp[4]; 172 uint64_t xsave_mask_user; 173 174 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 175 use_xsave = 1; 176 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 177 } 178 if (!use_xsave) 179 return; 180 181 cpuid_count(0xd, 0x0, cp); 182 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 183 if ((cp[0] & xsave_mask) != xsave_mask) 184 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 185 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 186 xsave_mask_user = xsave_mask; 187 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 188 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 189 xsave_mask &= xsave_mask_user; 190 191 cpuid_count(0xd, 0x1, cp); 192 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 193 /* 194 * Patch the XSAVE instruction in the cpu_switch code 195 * to XSAVEOPT. We assume that XSAVE encoding used 196 * REX byte, and set the bit 4 of the r/m byte. 197 */ 198 ctx_switch_xsave[3] |= 0x10; 199 use_xsaveopt = 1; 200 } 201} 202 203/* 204 * Calculate the fpu save area size. 205 */ 206static void 207fpuinit_bsp2(void) 208{ 209 u_int cp[4]; 210 211 if (use_xsave) { 212 cpuid_count(0xd, 0x0, cp); 213 cpu_max_ext_state_size = cp[1]; 214 215 /* 216 * Reload the cpu_feature2, since we enabled OSXSAVE. 217 */ 218 do_cpuid(1, cp); 219 cpu_feature2 = cp[2]; 220 } else 221 cpu_max_ext_state_size = sizeof(struct savefpu); 222} 223 224/* 225 * Initialize the floating point unit. 226 */ 227void 228fpuinit(void) 229{ 230 register_t saveintr; 231 u_int mxcsr; 232 u_short control; 233 234 if (IS_BSP()) 235 fpuinit_bsp1(); 236 237 if (use_xsave) { 238 load_cr4(rcr4() | CR4_XSAVE); 239 load_xcr(XCR0, xsave_mask); 240 } 241 242 /* 243 * XCR0 shall be set up before CPU can report the save area size. 244 */ 245 if (IS_BSP()) 246 fpuinit_bsp2(); 247 248 /* 249 * It is too early for critical_enter() to work on AP. 250 */ 251 saveintr = intr_disable(); 252 stop_emulating(); 253 fninit(); 254 control = __INITIAL_FPUCW__; 255 fldcw(control); 256 mxcsr = __INITIAL_MXCSR__; 257 ldmxcsr(mxcsr); 258 start_emulating(); 259 intr_restore(saveintr); 260} 261 262/* 263 * On the boot CPU we generate a clean state that is used to 264 * initialize the floating point unit when it is first used by a 265 * process. 266 */ 267static void 268fpuinitstate(void *arg __unused) 269{ 270 register_t saveintr; 271 int cp[4], i, max_ext_n; 272 273 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 274 M_WAITOK | M_ZERO); 275 saveintr = intr_disable(); 276 stop_emulating(); 277 278 fpusave(fpu_initialstate); 279 if (fpu_initialstate->sv_env.en_mxcsr_mask) 280 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 281 else 282 cpu_mxcsr_mask = 0xFFBF; 283 284 /* 285 * The fninit instruction does not modify XMM registers. The 286 * fpusave call dumped the garbage contained in the registers 287 * after reset to the initial state saved. Clear XMM 288 * registers file image to make the startup program state and 289 * signal handler XMM register content predictable. 290 */ 291 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc)); 292 293 /* 294 * Create a table describing the layout of the CPU Extended 295 * Save Area. 296 */ 297 if (use_xsaveopt) { 298 max_ext_n = flsl(xsave_mask); 299 xsave_area_desc = malloc(max_ext_n * sizeof(struct 300 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 301 /* x87 state */ 302 xsave_area_desc[0].offset = 0; 303 xsave_area_desc[0].size = 160; 304 /* XMM */ 305 xsave_area_desc[1].offset = 160; 306 xsave_area_desc[1].size = 288 - 160; 307 308 for (i = 2; i < max_ext_n; i++) { 309 cpuid_count(0xd, i, cp); 310 xsave_area_desc[i].offset = cp[1]; 311 xsave_area_desc[i].size = cp[0]; 312 } 313 } 314 315 start_emulating(); 316 intr_restore(saveintr); 317} 318SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL); 319 320/* 321 * Free coprocessor (if we have it). 322 */ 323void 324fpuexit(struct thread *td) 325{ 326 327 critical_enter(); 328 if (curthread == PCPU_GET(fpcurthread)) { 329 stop_emulating(); 330 fpusave(curpcb->pcb_save); 331 start_emulating(); 332 PCPU_SET(fpcurthread, 0); 333 } 334 critical_exit(); 335} 336 337int 338fpuformat() 339{ 340 341 return (_MC_FPFMT_XMM); 342} 343 344/* 345 * The following mechanism is used to ensure that the FPE_... value 346 * that is passed as a trapcode to the signal handler of the user 347 * process does not have more than one bit set. 348 * 349 * Multiple bits may be set if the user process modifies the control 350 * word while a status word bit is already set. While this is a sign 351 * of bad coding, we have no choise than to narrow them down to one 352 * bit, since we must not send a trapcode that is not exactly one of 353 * the FPE_ macros. 354 * 355 * The mechanism has a static table with 127 entries. Each combination 356 * of the 7 FPU status word exception bits directly translates to a 357 * position in this table, where a single FPE_... value is stored. 358 * This FPE_... value stored there is considered the "most important" 359 * of the exception bits and will be sent as the signal code. The 360 * precedence of the bits is based upon Intel Document "Numerical 361 * Applications", Chapter "Special Computational Situations". 362 * 363 * The macro to choose one of these values does these steps: 1) Throw 364 * away status word bits that cannot be masked. 2) Throw away the bits 365 * currently masked in the control word, assuming the user isn't 366 * interested in them anymore. 3) Reinsert status word bit 7 (stack 367 * fault) if it is set, which cannot be masked but must be presered. 368 * 4) Use the remaining bits to point into the trapcode table. 369 * 370 * The 6 maskable bits in order of their preference, as stated in the 371 * above referenced Intel manual: 372 * 1 Invalid operation (FP_X_INV) 373 * 1a Stack underflow 374 * 1b Stack overflow 375 * 1c Operand of unsupported format 376 * 1d SNaN operand. 377 * 2 QNaN operand (not an exception, irrelavant here) 378 * 3 Any other invalid-operation not mentioned above or zero divide 379 * (FP_X_INV, FP_X_DZ) 380 * 4 Denormal operand (FP_X_DNML) 381 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 382 * 6 Inexact result (FP_X_IMP) 383 */ 384static char fpetable[128] = { 385 0, 386 FPE_FLTINV, /* 1 - INV */ 387 FPE_FLTUND, /* 2 - DNML */ 388 FPE_FLTINV, /* 3 - INV | DNML */ 389 FPE_FLTDIV, /* 4 - DZ */ 390 FPE_FLTINV, /* 5 - INV | DZ */ 391 FPE_FLTDIV, /* 6 - DNML | DZ */ 392 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 393 FPE_FLTOVF, /* 8 - OFL */ 394 FPE_FLTINV, /* 9 - INV | OFL */ 395 FPE_FLTUND, /* A - DNML | OFL */ 396 FPE_FLTINV, /* B - INV | DNML | OFL */ 397 FPE_FLTDIV, /* C - DZ | OFL */ 398 FPE_FLTINV, /* D - INV | DZ | OFL */ 399 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 400 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 401 FPE_FLTUND, /* 10 - UFL */ 402 FPE_FLTINV, /* 11 - INV | UFL */ 403 FPE_FLTUND, /* 12 - DNML | UFL */ 404 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 405 FPE_FLTDIV, /* 14 - DZ | UFL */ 406 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 407 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 408 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 409 FPE_FLTOVF, /* 18 - OFL | UFL */ 410 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 411 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 412 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 413 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 414 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 415 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 416 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 417 FPE_FLTRES, /* 20 - IMP */ 418 FPE_FLTINV, /* 21 - INV | IMP */ 419 FPE_FLTUND, /* 22 - DNML | IMP */ 420 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 421 FPE_FLTDIV, /* 24 - DZ | IMP */ 422 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 423 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 424 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 425 FPE_FLTOVF, /* 28 - OFL | IMP */ 426 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 427 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 428 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 429 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 430 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 431 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 432 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 433 FPE_FLTUND, /* 30 - UFL | IMP */ 434 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 435 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 436 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 437 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 438 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 439 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 440 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 441 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 442 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 443 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 444 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 445 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 446 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 447 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 448 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 449 FPE_FLTSUB, /* 40 - STK */ 450 FPE_FLTSUB, /* 41 - INV | STK */ 451 FPE_FLTUND, /* 42 - DNML | STK */ 452 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 453 FPE_FLTDIV, /* 44 - DZ | STK */ 454 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 455 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 456 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 457 FPE_FLTOVF, /* 48 - OFL | STK */ 458 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 459 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 460 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 461 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 462 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 463 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 464 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 465 FPE_FLTUND, /* 50 - UFL | STK */ 466 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 467 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 468 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 469 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 470 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 471 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 472 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 473 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 474 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 475 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 476 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 477 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 478 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 479 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 480 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 481 FPE_FLTRES, /* 60 - IMP | STK */ 482 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 483 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 484 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 485 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 486 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 487 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 488 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 489 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 490 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 491 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 492 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 493 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 494 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 495 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 496 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 497 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 498 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 499 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 500 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 501 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 502 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 503 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 504 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 505 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 506 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 507 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 508 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 509 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 510 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 511 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 512 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 513}; 514 515/* 516 * Read the FP status and control words, then generate si_code value 517 * for SIGFPE. The error code chosen will be one of the 518 * FPE_... macros. It will be sent as the second argument to old 519 * BSD-style signal handlers and as "siginfo_t->si_code" (second 520 * argument) to SA_SIGINFO signal handlers. 521 * 522 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 523 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 524 * usermode code which understands the FPU hardware enough to enable 525 * the exceptions, can also handle clearing the exception state in the 526 * handler. The only consequence of not clearing the exception is the 527 * rethrow of the SIGFPE on return from the signal handler and 528 * reexecution of the corresponding instruction. 529 * 530 * For XMM traps, the exceptions were never cleared. 531 */ 532int 533fputrap_x87(void) 534{ 535 struct savefpu *pcb_save; 536 u_short control, status; 537 538 critical_enter(); 539 540 /* 541 * Interrupt handling (for another interrupt) may have pushed the 542 * state to memory. Fetch the relevant parts of the state from 543 * wherever they are. 544 */ 545 if (PCPU_GET(fpcurthread) != curthread) { 546 pcb_save = curpcb->pcb_save; 547 control = pcb_save->sv_env.en_cw; 548 status = pcb_save->sv_env.en_sw; 549 } else { 550 fnstcw(&control); 551 fnstsw(&status); 552 } 553 554 critical_exit(); 555 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 556} 557 558int 559fputrap_sse(void) 560{ 561 u_int mxcsr; 562 563 critical_enter(); 564 if (PCPU_GET(fpcurthread) != curthread) 565 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 566 else 567 stmxcsr(&mxcsr); 568 critical_exit(); 569 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 570} 571 572/* 573 * Implement device not available (DNA) exception 574 * 575 * It would be better to switch FP context here (if curthread != fpcurthread) 576 * and not necessarily for every context switch, but it is too hard to 577 * access foreign pcb's. 578 */ 579 580static int err_count = 0; 581 582void 583fpudna(void) 584{ 585 struct pcb *pcb; 586 587 critical_enter(); 588 if (PCPU_GET(fpcurthread) == curthread) { 589 printf("fpudna: fpcurthread == curthread %d times\n", 590 ++err_count); 591 stop_emulating(); 592 critical_exit(); 593 return; 594 } 595 if (PCPU_GET(fpcurthread) != NULL) { 596 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 597 PCPU_GET(fpcurthread), 598 PCPU_GET(fpcurthread)->td_proc->p_pid, 599 curthread, curthread->td_proc->p_pid); 600 panic("fpudna"); 601 } 602 stop_emulating(); 603 /* 604 * Record new context early in case frstor causes a trap. 605 */ 606 PCPU_SET(fpcurthread, curthread); 607 pcb = curpcb; 608 609 fpu_clean_state(); 610 611 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 612 /* 613 * This is the first time this thread has used the FPU or 614 * the PCB doesn't contain a clean FPU state. Explicitly 615 * load an initial state. 616 * 617 * We prefer to restore the state from the actual save 618 * area in PCB instead of directly loading from 619 * fpu_initialstate, to ignite the XSAVEOPT 620 * tracking engine. 621 */ 622 bcopy(fpu_initialstate, pcb->pcb_save, cpu_max_ext_state_size); 623 fpurestore(pcb->pcb_save); 624 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 625 fldcw(pcb->pcb_initial_fpucw); 626 if (PCB_USER_FPU(pcb)) 627 set_pcb_flags(pcb, 628 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 629 else 630 set_pcb_flags(pcb, PCB_FPUINITDONE); 631 } else 632 fpurestore(pcb->pcb_save); 633 critical_exit(); 634} 635 636void 637fpudrop() 638{ 639 struct thread *td; 640 641 td = PCPU_GET(fpcurthread); 642 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 643 CRITICAL_ASSERT(td); 644 PCPU_SET(fpcurthread, NULL); 645 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 646 start_emulating(); 647} 648 649/* 650 * Get the user state of the FPU into pcb->pcb_user_save without 651 * dropping ownership (if possible). It returns the FPU ownership 652 * status. 653 */ 654int 655fpugetregs(struct thread *td) 656{ 657 struct pcb *pcb; 658 uint64_t *xstate_bv, bit; 659 char *sa; 660 int max_ext_n, i; 661 662 pcb = td->td_pcb; 663 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 664 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 665 cpu_max_ext_state_size); 666 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 667 pcb->pcb_initial_fpucw; 668 fpuuserinited(td); 669 return (_MC_FPOWNED_PCB); 670 } 671 critical_enter(); 672 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 673 fpusave(get_pcb_user_save_pcb(pcb)); 674 critical_exit(); 675 return (_MC_FPOWNED_FPU); 676 } else { 677 critical_exit(); 678 if (use_xsaveopt) { 679 /* 680 * Handle partially saved state. 681 */ 682 sa = (char *)get_pcb_user_save_pcb(pcb); 683 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 684 offsetof(struct xstate_hdr, xstate_bv)); 685 max_ext_n = flsl(xsave_mask); 686 for (i = 0; i < max_ext_n; i++) { 687 bit = 1 << i; 688 if ((*xstate_bv & bit) != 0) 689 continue; 690 bcopy((char *)fpu_initialstate + 691 xsave_area_desc[i].offset, 692 sa + xsave_area_desc[i].offset, 693 xsave_area_desc[i].size); 694 *xstate_bv |= bit; 695 } 696 } 697 return (_MC_FPOWNED_PCB); 698 } 699} 700 701void 702fpuuserinited(struct thread *td) 703{ 704 struct pcb *pcb; 705 706 pcb = td->td_pcb; 707 if (PCB_USER_FPU(pcb)) 708 set_pcb_flags(pcb, 709 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 710 else 711 set_pcb_flags(pcb, PCB_FPUINITDONE); 712} 713 714int 715fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 716{ 717 struct xstate_hdr *hdr, *ehdr; 718 size_t len, max_len; 719 uint64_t bv; 720 721 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 722 if (xfpustate == NULL) 723 return (0); 724 if (!use_xsave) 725 return (EOPNOTSUPP); 726 727 len = xfpustate_size; 728 if (len < sizeof(struct xstate_hdr)) 729 return (EINVAL); 730 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 731 if (len > max_len) 732 return (EINVAL); 733 734 ehdr = (struct xstate_hdr *)xfpustate; 735 bv = ehdr->xstate_bv; 736 737 /* 738 * Avoid #gp. 739 */ 740 if (bv & ~xsave_mask) 741 return (EINVAL); 742 if ((bv & (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE)) != 743 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE)) 744 return (EINVAL); 745 746 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 747 748 hdr->xstate_bv = bv; 749 bcopy(xfpustate + sizeof(struct xstate_hdr), 750 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 751 752 return (0); 753} 754 755/* 756 * Set the state of the FPU. 757 */ 758int 759fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 760 size_t xfpustate_size) 761{ 762 struct pcb *pcb; 763 int error; 764 765 pcb = td->td_pcb; 766 critical_enter(); 767 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 768 error = fpusetxstate(td, xfpustate, xfpustate_size); 769 if (error != 0) { 770 critical_exit(); 771 return (error); 772 } 773 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 774 fpurestore(get_pcb_user_save_td(td)); 775 critical_exit(); 776 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE); 777 } else { 778 critical_exit(); 779 error = fpusetxstate(td, xfpustate, xfpustate_size); 780 if (error != 0) 781 return (error); 782 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 783 fpuuserinited(td); 784 } 785 return (0); 786} 787 788/* 789 * On AuthenticAMD processors, the fxrstor instruction does not restore 790 * the x87's stored last instruction pointer, last data pointer, and last 791 * opcode values, except in the rare case in which the exception summary 792 * (ES) bit in the x87 status word is set to 1. 793 * 794 * In order to avoid leaking this information across processes, we clean 795 * these values by performing a dummy load before executing fxrstor(). 796 */ 797static void 798fpu_clean_state(void) 799{ 800 static float dummy_variable = 0.0; 801 u_short status; 802 803 /* 804 * Clear the ES bit in the x87 status word if it is currently 805 * set, in order to avoid causing a fault in the upcoming load. 806 */ 807 fnstsw(&status); 808 if (status & 0x80) 809 fnclex(); 810 811 /* 812 * Load the dummy variable into the x87 stack. This mangles 813 * the x87 stack, but we don't care since we're about to call 814 * fxrstor() anyway. 815 */ 816 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 817} 818 819/* 820 * This really sucks. We want the acpi version only, but it requires 821 * the isa_if.h file in order to get the definitions. 822 */ 823#include "opt_isa.h" 824#ifdef DEV_ISA 825#include <isa/isavar.h> 826/* 827 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 828 */ 829static struct isa_pnp_id fpupnp_ids[] = { 830 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 831 { 0 } 832}; 833 834static int 835fpupnp_probe(device_t dev) 836{ 837 int result; 838 839 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 840 if (result <= 0) 841 device_quiet(dev); 842 return (result); 843} 844 845static int 846fpupnp_attach(device_t dev) 847{ 848 849 return (0); 850} 851 852static device_method_t fpupnp_methods[] = { 853 /* Device interface */ 854 DEVMETHOD(device_probe, fpupnp_probe), 855 DEVMETHOD(device_attach, fpupnp_attach), 856 DEVMETHOD(device_detach, bus_generic_detach), 857 DEVMETHOD(device_shutdown, bus_generic_shutdown), 858 DEVMETHOD(device_suspend, bus_generic_suspend), 859 DEVMETHOD(device_resume, bus_generic_resume), 860 861 { 0, 0 } 862}; 863 864static driver_t fpupnp_driver = { 865 "fpupnp", 866 fpupnp_methods, 867 1, /* no softc */ 868}; 869 870static devclass_t fpupnp_devclass; 871 872DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 873#endif /* DEV_ISA */ 874 875static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 876 "Kernel contexts for FPU state"); 877 878#define FPU_KERN_CTX_FPUINITDONE 0x01 879 880struct fpu_kern_ctx { 881 struct savefpu *prev; 882 uint32_t flags; 883 char hwstate1[]; 884}; 885 886struct fpu_kern_ctx * 887fpu_kern_alloc_ctx(u_int flags) 888{ 889 struct fpu_kern_ctx *res; 890 size_t sz; 891 892 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 893 cpu_max_ext_state_size; 894 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 895 M_NOWAIT : M_WAITOK) | M_ZERO); 896 return (res); 897} 898 899void 900fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 901{ 902 903 /* XXXKIB clear the memory ? */ 904 free(ctx, M_FPUKERN_CTX); 905} 906 907static struct savefpu * 908fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 909{ 910 vm_offset_t p; 911 912 p = (vm_offset_t)&ctx->hwstate1; 913 p = roundup2(p, XSAVE_AREA_ALIGN); 914 return ((struct savefpu *)p); 915} 916 917int 918fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 919{ 920 struct pcb *pcb; 921 922 pcb = td->td_pcb; 923 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 924 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 925 ctx->flags = 0; 926 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 927 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 928 fpuexit(td); 929 ctx->prev = pcb->pcb_save; 930 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 931 set_pcb_flags(pcb, PCB_KERNFPU); 932 clear_pcb_flags(pcb, PCB_FPUINITDONE); 933 return (0); 934} 935 936int 937fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 938{ 939 struct pcb *pcb; 940 941 pcb = td->td_pcb; 942 critical_enter(); 943 if (curthread == PCPU_GET(fpcurthread)) 944 fpudrop(); 945 critical_exit(); 946 pcb->pcb_save = ctx->prev; 947 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 948 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 949 set_pcb_flags(pcb, PCB_FPUINITDONE); 950 clear_pcb_flags(pcb, PCB_KERNFPU); 951 } else 952 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 953 } else { 954 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 955 set_pcb_flags(pcb, PCB_FPUINITDONE); 956 else 957 clear_pcb_flags(pcb, PCB_FPUINITDONE); 958 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 959 } 960 return (0); 961} 962 963int 964fpu_kern_thread(u_int flags) 965{ 966 struct pcb *pcb; 967 968 pcb = curpcb; 969 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 970 ("Only kthread may use fpu_kern_thread")); 971 KASSERT(pcb->pcb_save == get_pcb_user_save_pcb(pcb), 972 ("mangled pcb_save")); 973 KASSERT(PCB_USER_FPU(pcb), ("recursive call")); 974 975 set_pcb_flags(pcb, PCB_KERNFPU); 976 return (0); 977} 978 979int 980is_fpu_kern_thread(u_int flags) 981{ 982 983 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 984 return (0); 985 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0); 986} 987