fpu.c revision 157860
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 157860 2006-04-19 07:00:19Z cperciva $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50 51#include <machine/cputypes.h> 52#include <machine/frame.h> 53#include <machine/intr_machdep.h> 54#include <machine/md_var.h> 55#include <machine/pcb.h> 56#include <machine/psl.h> 57#include <machine/resource.h> 58#include <machine/specialreg.h> 59#include <machine/segments.h> 60#include <machine/ucontext.h> 61 62/* 63 * Floating point support. 64 */ 65 66#if defined(__GNUCLIKE_ASM) && !defined(lint) 67 68#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 69#define fnclex() __asm("fnclex") 70#define fninit() __asm("fninit") 71#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 72#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 73#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 74#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75#define ldmxcsr(r) __asm __volatile("ldmxcsr %0" : : "m" (r)) 76#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 77 : : "n" (CR0_TS) : "ax") 78#define stop_emulating() __asm("clts") 79 80#else /* !(__GNUCLIKE_ASM && !lint) */ 81 82void fldcw(caddr_t addr); 83void fnclex(void); 84void fninit(void); 85void fnstcw(caddr_t addr); 86void fnstsw(caddr_t addr); 87void fxsave(caddr_t addr); 88void fxrstor(caddr_t addr); 89void start_emulating(void); 90void stop_emulating(void); 91 92#endif /* __GNUCLIKE_ASM && !lint */ 93 94#define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw) 95#define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw) 96 97typedef u_char bool_t; 98 99static void fpu_clean_state(void); 100 101int hw_float = 1; 102SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 103 CTLFLAG_RD, &hw_float, 0, 104 "Floatingpoint instructions executed in hardware"); 105 106static struct savefpu fpu_cleanstate; 107static bool_t fpu_cleanstate_ready; 108 109/* 110 * Initialize floating point unit. 111 */ 112void 113fpuinit(void) 114{ 115 register_t savecrit; 116 u_int mxcsr; 117 u_short control; 118 119 savecrit = intr_disable(); 120 PCPU_SET(fpcurthread, 0); 121 stop_emulating(); 122 fninit(); 123 control = __INITIAL_FPUCW__; 124 fldcw(&control); 125 mxcsr = __INITIAL_MXCSR__; 126 ldmxcsr(mxcsr); 127 fxsave(&fpu_cleanstate); 128 start_emulating(); 129 bzero(fpu_cleanstate.sv_fp, sizeof(fpu_cleanstate.sv_fp)); 130 bzero(fpu_cleanstate.sv_xmm, sizeof(fpu_cleanstate.sv_xmm)); 131 fpu_cleanstate_ready = 1; 132 intr_restore(savecrit); 133} 134 135/* 136 * Free coprocessor (if we have it). 137 */ 138void 139fpuexit(struct thread *td) 140{ 141 register_t savecrit; 142 143 savecrit = intr_disable(); 144 if (curthread == PCPU_GET(fpcurthread)) { 145 stop_emulating(); 146 fxsave(&PCPU_GET(curpcb)->pcb_save); 147 start_emulating(); 148 PCPU_SET(fpcurthread, 0); 149 } 150 intr_restore(savecrit); 151} 152 153int 154fpuformat() 155{ 156 157 return (_MC_FPFMT_XMM); 158} 159 160/* 161 * The following mechanism is used to ensure that the FPE_... value 162 * that is passed as a trapcode to the signal handler of the user 163 * process does not have more than one bit set. 164 * 165 * Multiple bits may be set if the user process modifies the control 166 * word while a status word bit is already set. While this is a sign 167 * of bad coding, we have no choise than to narrow them down to one 168 * bit, since we must not send a trapcode that is not exactly one of 169 * the FPE_ macros. 170 * 171 * The mechanism has a static table with 127 entries. Each combination 172 * of the 7 FPU status word exception bits directly translates to a 173 * position in this table, where a single FPE_... value is stored. 174 * This FPE_... value stored there is considered the "most important" 175 * of the exception bits and will be sent as the signal code. The 176 * precedence of the bits is based upon Intel Document "Numerical 177 * Applications", Chapter "Special Computational Situations". 178 * 179 * The macro to choose one of these values does these steps: 1) Throw 180 * away status word bits that cannot be masked. 2) Throw away the bits 181 * currently masked in the control word, assuming the user isn't 182 * interested in them anymore. 3) Reinsert status word bit 7 (stack 183 * fault) if it is set, which cannot be masked but must be presered. 184 * 4) Use the remaining bits to point into the trapcode table. 185 * 186 * The 6 maskable bits in order of their preference, as stated in the 187 * above referenced Intel manual: 188 * 1 Invalid operation (FP_X_INV) 189 * 1a Stack underflow 190 * 1b Stack overflow 191 * 1c Operand of unsupported format 192 * 1d SNaN operand. 193 * 2 QNaN operand (not an exception, irrelavant here) 194 * 3 Any other invalid-operation not mentioned above or zero divide 195 * (FP_X_INV, FP_X_DZ) 196 * 4 Denormal operand (FP_X_DNML) 197 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 198 * 6 Inexact result (FP_X_IMP) 199 */ 200static char fpetable[128] = { 201 0, 202 FPE_FLTINV, /* 1 - INV */ 203 FPE_FLTUND, /* 2 - DNML */ 204 FPE_FLTINV, /* 3 - INV | DNML */ 205 FPE_FLTDIV, /* 4 - DZ */ 206 FPE_FLTINV, /* 5 - INV | DZ */ 207 FPE_FLTDIV, /* 6 - DNML | DZ */ 208 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 209 FPE_FLTOVF, /* 8 - OFL */ 210 FPE_FLTINV, /* 9 - INV | OFL */ 211 FPE_FLTUND, /* A - DNML | OFL */ 212 FPE_FLTINV, /* B - INV | DNML | OFL */ 213 FPE_FLTDIV, /* C - DZ | OFL */ 214 FPE_FLTINV, /* D - INV | DZ | OFL */ 215 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 216 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 217 FPE_FLTUND, /* 10 - UFL */ 218 FPE_FLTINV, /* 11 - INV | UFL */ 219 FPE_FLTUND, /* 12 - DNML | UFL */ 220 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 221 FPE_FLTDIV, /* 14 - DZ | UFL */ 222 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 223 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 224 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 225 FPE_FLTOVF, /* 18 - OFL | UFL */ 226 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 227 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 228 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 229 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 230 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 231 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 232 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 233 FPE_FLTRES, /* 20 - IMP */ 234 FPE_FLTINV, /* 21 - INV | IMP */ 235 FPE_FLTUND, /* 22 - DNML | IMP */ 236 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 237 FPE_FLTDIV, /* 24 - DZ | IMP */ 238 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 239 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 240 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 241 FPE_FLTOVF, /* 28 - OFL | IMP */ 242 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 243 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 244 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 245 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 246 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 247 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 248 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 249 FPE_FLTUND, /* 30 - UFL | IMP */ 250 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 251 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 252 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 253 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 254 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 255 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 256 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 257 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 258 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 259 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 260 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 261 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 262 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 263 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 264 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 265 FPE_FLTSUB, /* 40 - STK */ 266 FPE_FLTSUB, /* 41 - INV | STK */ 267 FPE_FLTUND, /* 42 - DNML | STK */ 268 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 269 FPE_FLTDIV, /* 44 - DZ | STK */ 270 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 271 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 272 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 273 FPE_FLTOVF, /* 48 - OFL | STK */ 274 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 275 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 276 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 277 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 278 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 279 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 280 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 281 FPE_FLTUND, /* 50 - UFL | STK */ 282 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 283 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 284 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 285 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 286 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 287 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 288 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 289 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 290 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 291 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 292 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 293 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 294 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 295 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 296 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 297 FPE_FLTRES, /* 60 - IMP | STK */ 298 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 299 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 300 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 301 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 302 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 303 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 304 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 305 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 306 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 307 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 308 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 309 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 310 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 311 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 312 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 313 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 314 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 315 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 316 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 317 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 318 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 319 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 320 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 321 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 322 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 323 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 324 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 325 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 326 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 327 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 328 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 329}; 330 331/* 332 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 333 * 334 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 335 * depend on longjmp() restoring a usable state. Restoring the state 336 * or examining it might fail if we didn't clear exceptions. 337 * 338 * The error code chosen will be one of the FPE_... macros. It will be 339 * sent as the second argument to old BSD-style signal handlers and as 340 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 341 * 342 * XXX the FP state is not preserved across signal handlers. So signal 343 * handlers cannot afford to do FP unless they preserve the state or 344 * longjmp() out. Both preserving the state and longjmp()ing may be 345 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 346 * solution for signals other than SIGFPE. 347 */ 348int 349fputrap() 350{ 351 register_t savecrit; 352 u_short control, status; 353 354 savecrit = intr_disable(); 355 356 /* 357 * Interrupt handling (for another interrupt) may have pushed the 358 * state to memory. Fetch the relevant parts of the state from 359 * wherever they are. 360 */ 361 if (PCPU_GET(fpcurthread) != curthread) { 362 control = GET_FPU_CW(curthread); 363 status = GET_FPU_SW(curthread); 364 } else { 365 fnstcw(&control); 366 fnstsw(&status); 367 } 368 369 if (PCPU_GET(fpcurthread) == curthread) 370 fnclex(); 371 intr_restore(savecrit); 372 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 373} 374 375/* 376 * Implement device not available (DNA) exception 377 * 378 * It would be better to switch FP context here (if curthread != fpcurthread) 379 * and not necessarily for every context switch, but it is too hard to 380 * access foreign pcb's. 381 */ 382 383static int err_count = 0; 384 385int 386fpudna() 387{ 388 struct pcb *pcb; 389 register_t s; 390 391 if (PCPU_GET(fpcurthread) == curthread) { 392 printf("fpudna: fpcurthread == curthread %d times\n", 393 ++err_count); 394 stop_emulating(); 395 return (1); 396 } 397 if (PCPU_GET(fpcurthread) != NULL) { 398 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 399 PCPU_GET(fpcurthread), 400 PCPU_GET(fpcurthread)->td_proc->p_pid, 401 curthread, curthread->td_proc->p_pid); 402 panic("fpudna"); 403 } 404 s = intr_disable(); 405 stop_emulating(); 406 /* 407 * Record new context early in case frstor causes a trap. 408 */ 409 PCPU_SET(fpcurthread, curthread); 410 pcb = PCPU_GET(curpcb); 411 412 fpu_clean_state(); 413 414 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 415 /* 416 * This is the first time this thread has used the FPU, 417 * explicitly load sanitized registers. 418 */ 419 fxrstor(&fpu_cleanstate); 420 pcb->pcb_flags |= PCB_FPUINITDONE; 421 } else 422 fxrstor(&pcb->pcb_save); 423 intr_restore(s); 424 425 return (1); 426} 427 428/* 429 * This should be called with interrupts disabled and only when the owning 430 * FPU thread is non-null. 431 */ 432void 433fpudrop() 434{ 435 struct thread *td; 436 437 td = PCPU_GET(fpcurthread); 438 PCPU_SET(fpcurthread, NULL); 439 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 440 start_emulating(); 441} 442 443/* 444 * Get the state of the FPU without dropping ownership (if possible). 445 * It returns the FPU ownership status. 446 */ 447int 448fpugetregs(struct thread *td, struct savefpu *addr) 449{ 450 register_t s; 451 452 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 453 if (fpu_cleanstate_ready) 454 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate)); 455 else 456 bzero(addr, sizeof(*addr)); 457 return (_MC_FPOWNED_NONE); 458 } 459 s = intr_disable(); 460 if (td == PCPU_GET(fpcurthread)) { 461 fxsave(addr); 462 intr_restore(s); 463 return (_MC_FPOWNED_FPU); 464 } else { 465 intr_restore(s); 466 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 467 return (_MC_FPOWNED_PCB); 468 } 469} 470 471/* 472 * Set the state of the FPU. 473 */ 474void 475fpusetregs(struct thread *td, struct savefpu *addr) 476{ 477 register_t s; 478 479 s = intr_disable(); 480 if (td == PCPU_GET(fpcurthread)) { 481 fpu_clean_state(); 482 fxrstor(addr); 483 intr_restore(s); 484 } else { 485 intr_restore(s); 486 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 487 } 488 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE; 489} 490 491/* 492 * On AuthenticAMD processors, the fxrstor instruction does not restore 493 * the x87's stored last instruction pointer, last data pointer, and last 494 * opcode values, except in the rare case in which the exception summary 495 * (ES) bit in the x87 status word is set to 1. 496 * 497 * In order to avoid leaking this information across processes, we clean 498 * these values by performing a dummy load before executing fxrstor(). 499 */ 500static double dummy_variable = 0.0; 501static void 502fpu_clean_state(void) 503{ 504 u_short status; 505 506 /* 507 * Clear the ES bit in the x87 status word if it is currently 508 * set, in order to avoid causing a fault in the upcoming load. 509 */ 510 fnstsw(&status); 511 if (status & 0x80) 512 fnclex(); 513 514 /* 515 * Load the dummy variable into the x87 stack. This mangles 516 * the x87 stack, but we don't care since we're about to call 517 * fxrstor() anyway. 518 */ 519 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 520} 521 522/* 523 * This really sucks. We want the acpi version only, but it requires 524 * the isa_if.h file in order to get the definitions. 525 */ 526#include "opt_isa.h" 527#ifdef DEV_ISA 528#include <isa/isavar.h> 529/* 530 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 531 */ 532static struct isa_pnp_id fpupnp_ids[] = { 533 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 534 { 0 } 535}; 536 537static int 538fpupnp_probe(device_t dev) 539{ 540 int result; 541 542 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 543 if (result <= 0) 544 device_quiet(dev); 545 return (result); 546} 547 548static int 549fpupnp_attach(device_t dev) 550{ 551 552 return (0); 553} 554 555static device_method_t fpupnp_methods[] = { 556 /* Device interface */ 557 DEVMETHOD(device_probe, fpupnp_probe), 558 DEVMETHOD(device_attach, fpupnp_attach), 559 DEVMETHOD(device_detach, bus_generic_detach), 560 DEVMETHOD(device_shutdown, bus_generic_shutdown), 561 DEVMETHOD(device_suspend, bus_generic_suspend), 562 DEVMETHOD(device_resume, bus_generic_resume), 563 564 { 0, 0 } 565}; 566 567static driver_t fpupnp_driver = { 568 "fpupnp", 569 fpupnp_methods, 570 1, /* no softc */ 571}; 572 573static devclass_t fpupnp_devclass; 574 575DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 576#endif /* DEV_ISA */ 577