fpu.c revision 143063
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 143063 2005-03-02 21:33:29Z joerg $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50 51#include <machine/cputypes.h> 52#include <machine/frame.h> 53#include <machine/intr_machdep.h> 54#include <machine/md_var.h> 55#include <machine/pcb.h> 56#include <machine/psl.h> 57#include <machine/resource.h> 58#include <machine/specialreg.h> 59#include <machine/segments.h> 60#include <machine/ucontext.h> 61 62/* 63 * Floating point support. 64 */ 65 66#if defined(__GNUCLIKE_ASM) && !defined(lint) 67 68#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 69#define fnclex() __asm("fnclex") 70#define fninit() __asm("fninit") 71#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 72#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 73#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 74#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75#define ldmxcsr(r) __asm __volatile("ldmxcsr %0" : : "m" (r)) 76#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 77 : : "n" (CR0_TS) : "ax") 78#define stop_emulating() __asm("clts") 79 80#else /* !__GNUCLIKE_ASM */ 81 82void fldcw(caddr_t addr); 83void fnclex(void); 84void fninit(void); 85void fnstcw(caddr_t addr); 86void fnstsw(caddr_t addr); 87void fxsave(caddr_t addr); 88void fxrstor(caddr_t addr); 89void start_emulating(void); 90void stop_emulating(void); 91 92#endif /* __GNUCLIKE_ASM */ 93 94#define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw) 95#define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw) 96 97typedef u_char bool_t; 98 99int hw_float = 1; 100SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 101 CTLFLAG_RD, &hw_float, 0, 102 "Floatingpoint instructions executed in hardware"); 103 104static struct savefpu fpu_cleanstate; 105static bool_t fpu_cleanstate_ready; 106 107/* 108 * Initialize floating point unit. 109 */ 110void 111fpuinit(void) 112{ 113 register_t savecrit; 114 u_int mxcsr; 115 u_short control; 116 117 savecrit = intr_disable(); 118 PCPU_SET(fpcurthread, 0); 119 stop_emulating(); 120 fninit(); 121 control = __INITIAL_FPUCW__; 122 fldcw(&control); 123 mxcsr = __INITIAL_MXCSR__; 124 ldmxcsr(mxcsr); 125 fxsave(&fpu_cleanstate); 126 start_emulating(); 127 bzero(fpu_cleanstate.sv_fp, sizeof(fpu_cleanstate.sv_fp)); 128 bzero(fpu_cleanstate.sv_xmm, sizeof(fpu_cleanstate.sv_xmm)); 129 fpu_cleanstate_ready = 1; 130 intr_restore(savecrit); 131} 132 133/* 134 * Free coprocessor (if we have it). 135 */ 136void 137fpuexit(struct thread *td) 138{ 139 register_t savecrit; 140 141 savecrit = intr_disable(); 142 if (curthread == PCPU_GET(fpcurthread)) { 143 stop_emulating(); 144 fxsave(&PCPU_GET(curpcb)->pcb_save); 145 start_emulating(); 146 PCPU_SET(fpcurthread, 0); 147 } 148 intr_restore(savecrit); 149} 150 151int 152fpuformat() 153{ 154 155 return (_MC_FPFMT_XMM); 156} 157 158/* 159 * The following mechanism is used to ensure that the FPE_... value 160 * that is passed as a trapcode to the signal handler of the user 161 * process does not have more than one bit set. 162 * 163 * Multiple bits may be set if the user process modifies the control 164 * word while a status word bit is already set. While this is a sign 165 * of bad coding, we have no choise than to narrow them down to one 166 * bit, since we must not send a trapcode that is not exactly one of 167 * the FPE_ macros. 168 * 169 * The mechanism has a static table with 127 entries. Each combination 170 * of the 7 FPU status word exception bits directly translates to a 171 * position in this table, where a single FPE_... value is stored. 172 * This FPE_... value stored there is considered the "most important" 173 * of the exception bits and will be sent as the signal code. The 174 * precedence of the bits is based upon Intel Document "Numerical 175 * Applications", Chapter "Special Computational Situations". 176 * 177 * The macro to choose one of these values does these steps: 1) Throw 178 * away status word bits that cannot be masked. 2) Throw away the bits 179 * currently masked in the control word, assuming the user isn't 180 * interested in them anymore. 3) Reinsert status word bit 7 (stack 181 * fault) if it is set, which cannot be masked but must be presered. 182 * 4) Use the remaining bits to point into the trapcode table. 183 * 184 * The 6 maskable bits in order of their preference, as stated in the 185 * above referenced Intel manual: 186 * 1 Invalid operation (FP_X_INV) 187 * 1a Stack underflow 188 * 1b Stack overflow 189 * 1c Operand of unsupported format 190 * 1d SNaN operand. 191 * 2 QNaN operand (not an exception, irrelavant here) 192 * 3 Any other invalid-operation not mentioned above or zero divide 193 * (FP_X_INV, FP_X_DZ) 194 * 4 Denormal operand (FP_X_DNML) 195 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 196 * 6 Inexact result (FP_X_IMP) 197 */ 198static char fpetable[128] = { 199 0, 200 FPE_FLTINV, /* 1 - INV */ 201 FPE_FLTUND, /* 2 - DNML */ 202 FPE_FLTINV, /* 3 - INV | DNML */ 203 FPE_FLTDIV, /* 4 - DZ */ 204 FPE_FLTINV, /* 5 - INV | DZ */ 205 FPE_FLTDIV, /* 6 - DNML | DZ */ 206 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 207 FPE_FLTOVF, /* 8 - OFL */ 208 FPE_FLTINV, /* 9 - INV | OFL */ 209 FPE_FLTUND, /* A - DNML | OFL */ 210 FPE_FLTINV, /* B - INV | DNML | OFL */ 211 FPE_FLTDIV, /* C - DZ | OFL */ 212 FPE_FLTINV, /* D - INV | DZ | OFL */ 213 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 214 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 215 FPE_FLTUND, /* 10 - UFL */ 216 FPE_FLTINV, /* 11 - INV | UFL */ 217 FPE_FLTUND, /* 12 - DNML | UFL */ 218 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 219 FPE_FLTDIV, /* 14 - DZ | UFL */ 220 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 221 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 222 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 223 FPE_FLTOVF, /* 18 - OFL | UFL */ 224 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 225 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 226 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 227 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 228 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 229 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 230 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 231 FPE_FLTRES, /* 20 - IMP */ 232 FPE_FLTINV, /* 21 - INV | IMP */ 233 FPE_FLTUND, /* 22 - DNML | IMP */ 234 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 235 FPE_FLTDIV, /* 24 - DZ | IMP */ 236 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 237 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 238 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 239 FPE_FLTOVF, /* 28 - OFL | IMP */ 240 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 241 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 242 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 243 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 244 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 245 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 246 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 247 FPE_FLTUND, /* 30 - UFL | IMP */ 248 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 249 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 250 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 251 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 252 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 253 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 254 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 255 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 256 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 257 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 258 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 259 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 260 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 261 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 262 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 263 FPE_FLTSUB, /* 40 - STK */ 264 FPE_FLTSUB, /* 41 - INV | STK */ 265 FPE_FLTUND, /* 42 - DNML | STK */ 266 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 267 FPE_FLTDIV, /* 44 - DZ | STK */ 268 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 269 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 270 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 271 FPE_FLTOVF, /* 48 - OFL | STK */ 272 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 273 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 274 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 275 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 276 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 277 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 278 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 279 FPE_FLTUND, /* 50 - UFL | STK */ 280 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 281 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 282 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 283 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 284 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 285 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 286 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 287 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 288 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 289 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 290 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 291 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 292 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 293 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 294 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 295 FPE_FLTRES, /* 60 - IMP | STK */ 296 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 297 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 298 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 299 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 300 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 301 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 302 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 303 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 304 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 305 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 306 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 307 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 308 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 309 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 310 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 311 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 312 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 313 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 314 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 315 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 316 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 317 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 318 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 319 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 320 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 321 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 322 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 323 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 324 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 325 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 326 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 327}; 328 329/* 330 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 331 * 332 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 333 * depend on longjmp() restoring a usable state. Restoring the state 334 * or examining it might fail if we didn't clear exceptions. 335 * 336 * The error code chosen will be one of the FPE_... macros. It will be 337 * sent as the second argument to old BSD-style signal handlers and as 338 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 339 * 340 * XXX the FP state is not preserved across signal handlers. So signal 341 * handlers cannot afford to do FP unless they preserve the state or 342 * longjmp() out. Both preserving the state and longjmp()ing may be 343 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 344 * solution for signals other than SIGFPE. 345 */ 346int 347fputrap() 348{ 349 register_t savecrit; 350 u_short control, status; 351 352 savecrit = intr_disable(); 353 354 /* 355 * Interrupt handling (for another interrupt) may have pushed the 356 * state to memory. Fetch the relevant parts of the state from 357 * wherever they are. 358 */ 359 if (PCPU_GET(fpcurthread) != curthread) { 360 control = GET_FPU_CW(curthread); 361 status = GET_FPU_SW(curthread); 362 } else { 363 fnstcw(&control); 364 fnstsw(&status); 365 } 366 367 if (PCPU_GET(fpcurthread) == curthread) 368 fnclex(); 369 intr_restore(savecrit); 370 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 371} 372 373/* 374 * Implement device not available (DNA) exception 375 * 376 * It would be better to switch FP context here (if curthread != fpcurthread) 377 * and not necessarily for every context switch, but it is too hard to 378 * access foreign pcb's. 379 */ 380 381static int err_count = 0; 382 383int 384fpudna() 385{ 386 struct pcb *pcb; 387 register_t s; 388 389 if (PCPU_GET(fpcurthread) == curthread) { 390 printf("fpudna: fpcurthread == curthread %d times\n", 391 ++err_count); 392 stop_emulating(); 393 return (1); 394 } 395 if (PCPU_GET(fpcurthread) != NULL) { 396 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 397 PCPU_GET(fpcurthread), 398 PCPU_GET(fpcurthread)->td_proc->p_pid, 399 curthread, curthread->td_proc->p_pid); 400 panic("fpudna"); 401 } 402 s = intr_disable(); 403 stop_emulating(); 404 /* 405 * Record new context early in case frstor causes a trap. 406 */ 407 PCPU_SET(fpcurthread, curthread); 408 pcb = PCPU_GET(curpcb); 409 410 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 411 /* 412 * This is the first time this thread has used the FPU, 413 * explicitly load sanitized registers. 414 */ 415 fxrstor(&fpu_cleanstate); 416 pcb->pcb_flags |= PCB_FPUINITDONE; 417 } else 418 fxrstor(&pcb->pcb_save); 419 intr_restore(s); 420 421 return (1); 422} 423 424/* 425 * This should be called with interrupts disabled and only when the owning 426 * FPU thread is non-null. 427 */ 428void 429fpudrop() 430{ 431 struct thread *td; 432 433 td = PCPU_GET(fpcurthread); 434 PCPU_SET(fpcurthread, NULL); 435 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 436 start_emulating(); 437} 438 439/* 440 * Get the state of the FPU without dropping ownership (if possible). 441 * It returns the FPU ownership status. 442 */ 443int 444fpugetregs(struct thread *td, struct savefpu *addr) 445{ 446 register_t s; 447 448 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 449 if (fpu_cleanstate_ready) 450 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate)); 451 else 452 bzero(addr, sizeof(*addr)); 453 return (_MC_FPOWNED_NONE); 454 } 455 s = intr_disable(); 456 if (td == PCPU_GET(fpcurthread)) { 457 fxsave(addr); 458 intr_restore(s); 459 return (_MC_FPOWNED_FPU); 460 } else { 461 intr_restore(s); 462 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 463 return (_MC_FPOWNED_PCB); 464 } 465} 466 467/* 468 * Set the state of the FPU. 469 */ 470void 471fpusetregs(struct thread *td, struct savefpu *addr) 472{ 473 register_t s; 474 475 s = intr_disable(); 476 if (td == PCPU_GET(fpcurthread)) { 477 fxrstor(addr); 478 intr_restore(s); 479 } else { 480 intr_restore(s); 481 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 482 } 483 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE; 484} 485 486/* 487 * This really sucks. We want the acpi version only, but it requires 488 * the isa_if.h file in order to get the definitions. 489 */ 490#include "opt_isa.h" 491#ifdef DEV_ISA 492#include <isa/isavar.h> 493/* 494 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 495 */ 496static struct isa_pnp_id fpupnp_ids[] = { 497 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 498 { 0 } 499}; 500 501static int 502fpupnp_probe(device_t dev) 503{ 504 int result; 505 506 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 507 if (result <= 0) 508 device_quiet(dev); 509 return (result); 510} 511 512static int 513fpupnp_attach(device_t dev) 514{ 515 516 return (0); 517} 518 519static device_method_t fpupnp_methods[] = { 520 /* Device interface */ 521 DEVMETHOD(device_probe, fpupnp_probe), 522 DEVMETHOD(device_attach, fpupnp_attach), 523 DEVMETHOD(device_detach, bus_generic_detach), 524 DEVMETHOD(device_shutdown, bus_generic_shutdown), 525 DEVMETHOD(device_suspend, bus_generic_suspend), 526 DEVMETHOD(device_resume, bus_generic_resume), 527 528 { 0, 0 } 529}; 530 531static driver_t fpupnp_driver = { 532 "fpupnp", 533 fpupnp_methods, 534 1, /* no softc */ 535}; 536 537static devclass_t fpupnp_devclass; 538 539DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 540#endif /* DEV_ISA */ 541