fpu.c revision 130228
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 130228 2004-06-08 01:35:48Z peter $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50#include <sys/user.h> 51 52#include <machine/cputypes.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/md_var.h> 56#include <machine/pcb.h> 57#include <machine/psl.h> 58#include <machine/resource.h> 59#include <machine/specialreg.h> 60#include <machine/segments.h> 61#include <machine/ucontext.h> 62 63/* 64 * Floating point support. 65 */ 66 67#if defined(__GNUC__) && !defined(lint) 68 69#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 70#define fnclex() __asm("fnclex") 71#define fninit() __asm("fninit") 72#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 74#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 75#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 76#define ldmxcsr(r) __asm __volatile("ldmxcsr %0" : : "m" (r)) 77#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 78 : : "n" (CR0_TS) : "ax") 79#define stop_emulating() __asm("clts") 80 81#else /* not __GNUC__ */ 82 83void fldcw(caddr_t addr); 84void fnclex(void); 85void fninit(void); 86void fnstcw(caddr_t addr); 87void fnstsw(caddr_t addr); 88void fxsave(caddr_t addr); 89void fxrstor(caddr_t addr); 90void start_emulating(void); 91void stop_emulating(void); 92 93#endif /* __GNUC__ */ 94 95#define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw) 96#define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw) 97 98typedef u_char bool_t; 99 100int hw_float = 1; 101SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 102 CTLFLAG_RD, &hw_float, 0, 103 "Floatingpoint instructions executed in hardware"); 104 105static struct savefpu fpu_cleanstate; 106static bool_t fpu_cleanstate_ready; 107 108/* 109 * Initialize floating point unit. 110 */ 111void 112fpuinit(void) 113{ 114 register_t savecrit; 115 u_int mxcsr; 116 u_short control; 117 118 savecrit = intr_disable(); 119 PCPU_SET(fpcurthread, 0); 120 stop_emulating(); 121 fninit(); 122 control = __INITIAL_FPUCW__; 123 fldcw(&control); 124 mxcsr = __INITIAL_MXCSR__; 125 ldmxcsr(mxcsr); 126 fxsave(&fpu_cleanstate); 127 start_emulating(); 128 fpu_cleanstate_ready = 1; 129 intr_restore(savecrit); 130} 131 132/* 133 * Free coprocessor (if we have it). 134 */ 135void 136fpuexit(struct thread *td) 137{ 138 register_t savecrit; 139 140 savecrit = intr_disable(); 141 if (curthread == PCPU_GET(fpcurthread)) { 142 stop_emulating(); 143 fxsave(&PCPU_GET(curpcb)->pcb_save); 144 start_emulating(); 145 PCPU_SET(fpcurthread, 0); 146 } 147 intr_restore(savecrit); 148} 149 150int 151fpuformat() 152{ 153 154 return (_MC_FPFMT_XMM); 155} 156 157/* 158 * The following mechanism is used to ensure that the FPE_... value 159 * that is passed as a trapcode to the signal handler of the user 160 * process does not have more than one bit set. 161 * 162 * Multiple bits may be set if the user process modifies the control 163 * word while a status word bit is already set. While this is a sign 164 * of bad coding, we have no choise than to narrow them down to one 165 * bit, since we must not send a trapcode that is not exactly one of 166 * the FPE_ macros. 167 * 168 * The mechanism has a static table with 127 entries. Each combination 169 * of the 7 FPU status word exception bits directly translates to a 170 * position in this table, where a single FPE_... value is stored. 171 * This FPE_... value stored there is considered the "most important" 172 * of the exception bits and will be sent as the signal code. The 173 * precedence of the bits is based upon Intel Document "Numerical 174 * Applications", Chapter "Special Computational Situations". 175 * 176 * The macro to choose one of these values does these steps: 1) Throw 177 * away status word bits that cannot be masked. 2) Throw away the bits 178 * currently masked in the control word, assuming the user isn't 179 * interested in them anymore. 3) Reinsert status word bit 7 (stack 180 * fault) if it is set, which cannot be masked but must be presered. 181 * 4) Use the remaining bits to point into the trapcode table. 182 * 183 * The 6 maskable bits in order of their preference, as stated in the 184 * above referenced Intel manual: 185 * 1 Invalid operation (FP_X_INV) 186 * 1a Stack underflow 187 * 1b Stack overflow 188 * 1c Operand of unsupported format 189 * 1d SNaN operand. 190 * 2 QNaN operand (not an exception, irrelavant here) 191 * 3 Any other invalid-operation not mentioned above or zero divide 192 * (FP_X_INV, FP_X_DZ) 193 * 4 Denormal operand (FP_X_DNML) 194 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 195 * 6 Inexact result (FP_X_IMP) 196 */ 197static char fpetable[128] = { 198 0, 199 FPE_FLTINV, /* 1 - INV */ 200 FPE_FLTUND, /* 2 - DNML */ 201 FPE_FLTINV, /* 3 - INV | DNML */ 202 FPE_FLTDIV, /* 4 - DZ */ 203 FPE_FLTINV, /* 5 - INV | DZ */ 204 FPE_FLTDIV, /* 6 - DNML | DZ */ 205 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 206 FPE_FLTOVF, /* 8 - OFL */ 207 FPE_FLTINV, /* 9 - INV | OFL */ 208 FPE_FLTUND, /* A - DNML | OFL */ 209 FPE_FLTINV, /* B - INV | DNML | OFL */ 210 FPE_FLTDIV, /* C - DZ | OFL */ 211 FPE_FLTINV, /* D - INV | DZ | OFL */ 212 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 213 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 214 FPE_FLTUND, /* 10 - UFL */ 215 FPE_FLTINV, /* 11 - INV | UFL */ 216 FPE_FLTUND, /* 12 - DNML | UFL */ 217 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 218 FPE_FLTDIV, /* 14 - DZ | UFL */ 219 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 220 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 221 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 222 FPE_FLTOVF, /* 18 - OFL | UFL */ 223 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 224 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 225 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 226 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 227 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 228 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 229 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 230 FPE_FLTRES, /* 20 - IMP */ 231 FPE_FLTINV, /* 21 - INV | IMP */ 232 FPE_FLTUND, /* 22 - DNML | IMP */ 233 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 234 FPE_FLTDIV, /* 24 - DZ | IMP */ 235 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 236 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 237 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 238 FPE_FLTOVF, /* 28 - OFL | IMP */ 239 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 240 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 241 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 242 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 243 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 244 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 245 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 246 FPE_FLTUND, /* 30 - UFL | IMP */ 247 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 248 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 249 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 250 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 251 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 252 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 253 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 254 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 255 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 256 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 257 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 258 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 259 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 260 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 261 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 262 FPE_FLTSUB, /* 40 - STK */ 263 FPE_FLTSUB, /* 41 - INV | STK */ 264 FPE_FLTUND, /* 42 - DNML | STK */ 265 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 266 FPE_FLTDIV, /* 44 - DZ | STK */ 267 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 268 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 269 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 270 FPE_FLTOVF, /* 48 - OFL | STK */ 271 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 272 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 273 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 274 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 275 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 276 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 277 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 278 FPE_FLTUND, /* 50 - UFL | STK */ 279 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 280 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 281 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 282 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 283 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 284 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 285 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 286 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 287 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 288 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 289 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 290 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 291 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 292 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 293 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 294 FPE_FLTRES, /* 60 - IMP | STK */ 295 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 296 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 297 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 298 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 299 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 300 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 301 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 302 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 303 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 304 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 305 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 306 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 307 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 308 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 309 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 310 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 311 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 312 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 313 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 314 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 315 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 316 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 317 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 318 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 319 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 320 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 321 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 322 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 323 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 324 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 325 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 326}; 327 328/* 329 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 330 * 331 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 332 * depend on longjmp() restoring a usable state. Restoring the state 333 * or examining it might fail if we didn't clear exceptions. 334 * 335 * The error code chosen will be one of the FPE_... macros. It will be 336 * sent as the second argument to old BSD-style signal handlers and as 337 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 338 * 339 * XXX the FP state is not preserved across signal handlers. So signal 340 * handlers cannot afford to do FP unless they preserve the state or 341 * longjmp() out. Both preserving the state and longjmp()ing may be 342 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 343 * solution for signals other than SIGFPE. 344 */ 345int 346fputrap() 347{ 348 register_t savecrit; 349 u_short control, status; 350 351 savecrit = intr_disable(); 352 353 /* 354 * Interrupt handling (for another interrupt) may have pushed the 355 * state to memory. Fetch the relevant parts of the state from 356 * wherever they are. 357 */ 358 if (PCPU_GET(fpcurthread) != curthread) { 359 control = GET_FPU_CW(curthread); 360 status = GET_FPU_SW(curthread); 361 } else { 362 fnstcw(&control); 363 fnstsw(&status); 364 } 365 366 if (PCPU_GET(fpcurthread) == curthread) 367 fnclex(); 368 intr_restore(savecrit); 369 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 370} 371 372/* 373 * Implement device not available (DNA) exception 374 * 375 * It would be better to switch FP context here (if curthread != fpcurthread) 376 * and not necessarily for every context switch, but it is too hard to 377 * access foreign pcb's. 378 */ 379 380static int err_count = 0; 381 382int 383fpudna() 384{ 385 struct pcb *pcb; 386 register_t s; 387 u_short control; 388 389 if (PCPU_GET(fpcurthread) == curthread) { 390 printf("fpudna: fpcurthread == curthread %d times\n", 391 ++err_count); 392 stop_emulating(); 393 return (1); 394 } 395 if (PCPU_GET(fpcurthread) != NULL) { 396 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 397 PCPU_GET(fpcurthread), 398 PCPU_GET(fpcurthread)->td_proc->p_pid, 399 curthread, curthread->td_proc->p_pid); 400 panic("fpudna"); 401 } 402 s = intr_disable(); 403 stop_emulating(); 404 /* 405 * Record new context early in case frstor causes a trap. 406 */ 407 PCPU_SET(fpcurthread, curthread); 408 pcb = PCPU_GET(curpcb); 409 410 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 411 /* 412 * This is the first time this thread has used the FPU or 413 * the PCB doesn't contain a clean FPU state. Explicitly 414 * initialize the FPU and load the default control word. 415 */ 416 fninit(); 417 control = __INITIAL_FPUCW__; 418 fldcw(&control); 419 pcb->pcb_flags |= PCB_FPUINITDONE; 420 } else 421 fxrstor(&pcb->pcb_save); 422 intr_restore(s); 423 424 return (1); 425} 426 427/* 428 * This should be called with interrupts disabled and only when the owning 429 * FPU thread is non-null. 430 */ 431void 432fpudrop() 433{ 434 struct thread *td; 435 436 td = PCPU_GET(fpcurthread); 437 PCPU_SET(fpcurthread, NULL); 438 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 439 start_emulating(); 440} 441 442/* 443 * Get the state of the FPU without dropping ownership (if possible). 444 * It returns the FPU ownership status. 445 */ 446int 447fpugetregs(struct thread *td, struct savefpu *addr) 448{ 449 register_t s; 450 451 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 452 if (fpu_cleanstate_ready) 453 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate)); 454 else 455 bzero(addr, sizeof(*addr)); 456 return (_MC_FPOWNED_NONE); 457 } 458 s = intr_disable(); 459 if (td == PCPU_GET(fpcurthread)) { 460 fxsave(addr); 461 intr_restore(s); 462 return (_MC_FPOWNED_FPU); 463 } else { 464 intr_restore(s); 465 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 466 return (_MC_FPOWNED_PCB); 467 } 468} 469 470/* 471 * Set the state of the FPU. 472 */ 473void 474fpusetregs(struct thread *td, struct savefpu *addr) 475{ 476 register_t s; 477 478 s = intr_disable(); 479 if (td == PCPU_GET(fpcurthread)) { 480 fxrstor(addr); 481 intr_restore(s); 482 } else { 483 intr_restore(s); 484 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 485 } 486 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE; 487} 488 489/* 490 * This really sucks. We want the acpi version only, but it requires 491 * the isa_if.h file in order to get the definitions. 492 */ 493#include "opt_isa.h" 494#ifdef DEV_ISA 495#include <isa/isavar.h> 496/* 497 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 498 */ 499static struct isa_pnp_id fpupnp_ids[] = { 500 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 501 { 0 } 502}; 503 504static int 505fpupnp_probe(device_t dev) 506{ 507 int result; 508 509 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 510 if (result <= 0) 511 device_quiet(dev); 512 return (result); 513} 514 515static int 516fpupnp_attach(device_t dev) 517{ 518 519 return (0); 520} 521 522static device_method_t fpupnp_methods[] = { 523 /* Device interface */ 524 DEVMETHOD(device_probe, fpupnp_probe), 525 DEVMETHOD(device_attach, fpupnp_attach), 526 DEVMETHOD(device_detach, bus_generic_detach), 527 DEVMETHOD(device_shutdown, bus_generic_shutdown), 528 DEVMETHOD(device_suspend, bus_generic_suspend), 529 DEVMETHOD(device_resume, bus_generic_resume), 530 531 { 0, 0 } 532}; 533 534static driver_t fpupnp_driver = { 535 "fpupnp", 536 fpupnp_methods, 537 1, /* no softc */ 538}; 539 540static devclass_t fpupnp_devclass; 541 542DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 543#endif /* DEV_ISA */ 544