fpu.c revision 130140
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 130140 2004-06-06 09:16:02Z das $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/mutex.h> 44#include <sys/mutex.h> 45#include <sys/proc.h> 46#include <sys/sysctl.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <sys/signalvar.h> 50#include <sys/user.h> 51 52#include <machine/cputypes.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/md_var.h> 56#include <machine/pcb.h> 57#include <machine/psl.h> 58#include <machine/resource.h> 59#include <machine/specialreg.h> 60#include <machine/segments.h> 61#include <machine/ucontext.h> 62 63/* 64 * Floating point support. 65 */ 66 67#if defined(__GNUC__) && !defined(lint) 68 69#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 70#define fnclex() __asm("fnclex") 71#define fninit() __asm("fninit") 72#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 74#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 75#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 76#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 77 : : "n" (CR0_TS) : "ax") 78#define stop_emulating() __asm("clts") 79 80#else /* not __GNUC__ */ 81 82void fldcw(caddr_t addr); 83void fnclex(void); 84void fninit(void); 85void fnstcw(caddr_t addr); 86void fnstsw(caddr_t addr); 87void fxsave(caddr_t addr); 88void fxrstor(caddr_t addr); 89void start_emulating(void); 90void stop_emulating(void); 91 92#endif /* __GNUC__ */ 93 94#define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw) 95#define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw) 96 97typedef u_char bool_t; 98 99int hw_float = 1; 100SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 101 CTLFLAG_RD, &hw_float, 0, 102 "Floatingpoint instructions executed in hardware"); 103 104static struct savefpu fpu_cleanstate; 105static bool_t fpu_cleanstate_ready; 106 107/* 108 * Initialize floating point unit. 109 */ 110void 111fpuinit(void) 112{ 113 register_t savecrit; 114 u_short control; 115 116 savecrit = intr_disable(); 117 PCPU_SET(fpcurthread, 0); 118 stop_emulating(); 119 fninit(); 120 control = __INITIAL_FPUCW__; 121 fldcw(&control); 122 fxsave(&fpu_cleanstate); 123 start_emulating(); 124 fpu_cleanstate_ready = 1; 125 intr_restore(savecrit); 126} 127 128/* 129 * Free coprocessor (if we have it). 130 */ 131void 132fpuexit(struct thread *td) 133{ 134 register_t savecrit; 135 136 savecrit = intr_disable(); 137 if (curthread == PCPU_GET(fpcurthread)) { 138 stop_emulating(); 139 fxsave(&PCPU_GET(curpcb)->pcb_save); 140 start_emulating(); 141 PCPU_SET(fpcurthread, 0); 142 } 143 intr_restore(savecrit); 144} 145 146int 147fpuformat() 148{ 149 150 return (_MC_FPFMT_XMM); 151} 152 153/* 154 * The following mechanism is used to ensure that the FPE_... value 155 * that is passed as a trapcode to the signal handler of the user 156 * process does not have more than one bit set. 157 * 158 * Multiple bits may be set if the user process modifies the control 159 * word while a status word bit is already set. While this is a sign 160 * of bad coding, we have no choise than to narrow them down to one 161 * bit, since we must not send a trapcode that is not exactly one of 162 * the FPE_ macros. 163 * 164 * The mechanism has a static table with 127 entries. Each combination 165 * of the 7 FPU status word exception bits directly translates to a 166 * position in this table, where a single FPE_... value is stored. 167 * This FPE_... value stored there is considered the "most important" 168 * of the exception bits and will be sent as the signal code. The 169 * precedence of the bits is based upon Intel Document "Numerical 170 * Applications", Chapter "Special Computational Situations". 171 * 172 * The macro to choose one of these values does these steps: 1) Throw 173 * away status word bits that cannot be masked. 2) Throw away the bits 174 * currently masked in the control word, assuming the user isn't 175 * interested in them anymore. 3) Reinsert status word bit 7 (stack 176 * fault) if it is set, which cannot be masked but must be presered. 177 * 4) Use the remaining bits to point into the trapcode table. 178 * 179 * The 6 maskable bits in order of their preference, as stated in the 180 * above referenced Intel manual: 181 * 1 Invalid operation (FP_X_INV) 182 * 1a Stack underflow 183 * 1b Stack overflow 184 * 1c Operand of unsupported format 185 * 1d SNaN operand. 186 * 2 QNaN operand (not an exception, irrelavant here) 187 * 3 Any other invalid-operation not mentioned above or zero divide 188 * (FP_X_INV, FP_X_DZ) 189 * 4 Denormal operand (FP_X_DNML) 190 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 191 * 6 Inexact result (FP_X_IMP) 192 */ 193static char fpetable[128] = { 194 0, 195 FPE_FLTINV, /* 1 - INV */ 196 FPE_FLTUND, /* 2 - DNML */ 197 FPE_FLTINV, /* 3 - INV | DNML */ 198 FPE_FLTDIV, /* 4 - DZ */ 199 FPE_FLTINV, /* 5 - INV | DZ */ 200 FPE_FLTDIV, /* 6 - DNML | DZ */ 201 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 202 FPE_FLTOVF, /* 8 - OFL */ 203 FPE_FLTINV, /* 9 - INV | OFL */ 204 FPE_FLTUND, /* A - DNML | OFL */ 205 FPE_FLTINV, /* B - INV | DNML | OFL */ 206 FPE_FLTDIV, /* C - DZ | OFL */ 207 FPE_FLTINV, /* D - INV | DZ | OFL */ 208 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 209 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 210 FPE_FLTUND, /* 10 - UFL */ 211 FPE_FLTINV, /* 11 - INV | UFL */ 212 FPE_FLTUND, /* 12 - DNML | UFL */ 213 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 214 FPE_FLTDIV, /* 14 - DZ | UFL */ 215 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 216 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 217 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 218 FPE_FLTOVF, /* 18 - OFL | UFL */ 219 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 220 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 221 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 222 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 223 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 224 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 225 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 226 FPE_FLTRES, /* 20 - IMP */ 227 FPE_FLTINV, /* 21 - INV | IMP */ 228 FPE_FLTUND, /* 22 - DNML | IMP */ 229 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 230 FPE_FLTDIV, /* 24 - DZ | IMP */ 231 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 232 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 233 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 234 FPE_FLTOVF, /* 28 - OFL | IMP */ 235 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 236 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 237 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 238 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 239 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 240 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 241 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 242 FPE_FLTUND, /* 30 - UFL | IMP */ 243 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 244 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 245 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 246 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 247 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 248 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 249 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 250 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 251 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 252 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 253 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 254 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 255 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 256 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 257 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 258 FPE_FLTSUB, /* 40 - STK */ 259 FPE_FLTSUB, /* 41 - INV | STK */ 260 FPE_FLTUND, /* 42 - DNML | STK */ 261 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 262 FPE_FLTDIV, /* 44 - DZ | STK */ 263 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 264 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 265 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 266 FPE_FLTOVF, /* 48 - OFL | STK */ 267 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 268 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 269 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 270 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 271 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 272 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 273 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 274 FPE_FLTUND, /* 50 - UFL | STK */ 275 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 276 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 277 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 278 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 279 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 280 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 281 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 282 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 283 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 284 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 285 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 286 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 287 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 288 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 289 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 290 FPE_FLTRES, /* 60 - IMP | STK */ 291 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 292 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 293 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 294 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 295 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 296 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 297 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 298 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 299 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 300 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 301 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 302 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 303 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 304 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 305 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 306 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 307 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 308 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 309 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 310 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 311 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 312 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 313 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 314 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 315 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 316 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 317 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 318 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 319 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 320 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 321 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 322}; 323 324/* 325 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 326 * 327 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 328 * depend on longjmp() restoring a usable state. Restoring the state 329 * or examining it might fail if we didn't clear exceptions. 330 * 331 * The error code chosen will be one of the FPE_... macros. It will be 332 * sent as the second argument to old BSD-style signal handlers and as 333 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 334 * 335 * XXX the FP state is not preserved across signal handlers. So signal 336 * handlers cannot afford to do FP unless they preserve the state or 337 * longjmp() out. Both preserving the state and longjmp()ing may be 338 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 339 * solution for signals other than SIGFPE. 340 */ 341int 342fputrap() 343{ 344 register_t savecrit; 345 u_short control, status; 346 347 savecrit = intr_disable(); 348 349 /* 350 * Interrupt handling (for another interrupt) may have pushed the 351 * state to memory. Fetch the relevant parts of the state from 352 * wherever they are. 353 */ 354 if (PCPU_GET(fpcurthread) != curthread) { 355 control = GET_FPU_CW(curthread); 356 status = GET_FPU_SW(curthread); 357 } else { 358 fnstcw(&control); 359 fnstsw(&status); 360 } 361 362 if (PCPU_GET(fpcurthread) == curthread) 363 fnclex(); 364 intr_restore(savecrit); 365 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 366} 367 368/* 369 * Implement device not available (DNA) exception 370 * 371 * It would be better to switch FP context here (if curthread != fpcurthread) 372 * and not necessarily for every context switch, but it is too hard to 373 * access foreign pcb's. 374 */ 375 376static int err_count = 0; 377 378int 379fpudna() 380{ 381 struct pcb *pcb; 382 register_t s; 383 u_short control; 384 385 if (PCPU_GET(fpcurthread) == curthread) { 386 printf("fpudna: fpcurthread == curthread %d times\n", 387 ++err_count); 388 stop_emulating(); 389 return (1); 390 } 391 if (PCPU_GET(fpcurthread) != NULL) { 392 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 393 PCPU_GET(fpcurthread), 394 PCPU_GET(fpcurthread)->td_proc->p_pid, 395 curthread, curthread->td_proc->p_pid); 396 panic("fpudna"); 397 } 398 s = intr_disable(); 399 stop_emulating(); 400 /* 401 * Record new context early in case frstor causes a trap. 402 */ 403 PCPU_SET(fpcurthread, curthread); 404 pcb = PCPU_GET(curpcb); 405 406 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 407 /* 408 * This is the first time this thread has used the FPU or 409 * the PCB doesn't contain a clean FPU state. Explicitly 410 * initialize the FPU and load the default control word. 411 */ 412 fninit(); 413 control = __INITIAL_FPUCW__; 414 fldcw(&control); 415 pcb->pcb_flags |= PCB_FPUINITDONE; 416 } else 417 fxrstor(&pcb->pcb_save); 418 intr_restore(s); 419 420 return (1); 421} 422 423/* 424 * This should be called with interrupts disabled and only when the owning 425 * FPU thread is non-null. 426 */ 427void 428fpudrop() 429{ 430 struct thread *td; 431 432 td = PCPU_GET(fpcurthread); 433 PCPU_SET(fpcurthread, NULL); 434 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 435 start_emulating(); 436} 437 438/* 439 * Get the state of the FPU without dropping ownership (if possible). 440 * It returns the FPU ownership status. 441 */ 442int 443fpugetregs(struct thread *td, struct savefpu *addr) 444{ 445 register_t s; 446 447 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 448 if (fpu_cleanstate_ready) 449 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate)); 450 else 451 bzero(addr, sizeof(*addr)); 452 return (_MC_FPOWNED_NONE); 453 } 454 s = intr_disable(); 455 if (td == PCPU_GET(fpcurthread)) { 456 fxsave(addr); 457 intr_restore(s); 458 return (_MC_FPOWNED_FPU); 459 } else { 460 intr_restore(s); 461 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 462 return (_MC_FPOWNED_PCB); 463 } 464} 465 466/* 467 * Set the state of the FPU. 468 */ 469void 470fpusetregs(struct thread *td, struct savefpu *addr) 471{ 472 register_t s; 473 474 s = intr_disable(); 475 if (td == PCPU_GET(fpcurthread)) { 476 fxrstor(addr); 477 intr_restore(s); 478 } else { 479 intr_restore(s); 480 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 481 } 482 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE; 483} 484 485/* 486 * This really sucks. We want the acpi version only, but it requires 487 * the isa_if.h file in order to get the definitions. 488 */ 489#include "opt_isa.h" 490#ifdef DEV_ISA 491#include <isa/isavar.h> 492/* 493 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 494 */ 495static struct isa_pnp_id fpupnp_ids[] = { 496 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 497 { 0 } 498}; 499 500static int 501fpupnp_probe(device_t dev) 502{ 503 int result; 504 505 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 506 if (result <= 0) 507 device_quiet(dev); 508 return (result); 509} 510 511static int 512fpupnp_attach(device_t dev) 513{ 514 515 return (0); 516} 517 518static device_method_t fpupnp_methods[] = { 519 /* Device interface */ 520 DEVMETHOD(device_probe, fpupnp_probe), 521 DEVMETHOD(device_attach, fpupnp_attach), 522 DEVMETHOD(device_detach, bus_generic_detach), 523 DEVMETHOD(device_shutdown, bus_generic_shutdown), 524 DEVMETHOD(device_suspend, bus_generic_suspend), 525 DEVMETHOD(device_resume, bus_generic_resume), 526 527 { 0, 0 } 528}; 529 530static driver_t fpupnp_driver = { 531 "fpupnp", 532 fpupnp_methods, 533 1, /* no softc */ 534}; 535 536static devclass_t fpupnp_devclass; 537 538DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 539#endif /* DEV_ISA */ 540