fpu.c revision 122295
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)npx.c 7.2 (Berkeley) 5/12/91 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 122295 2003-11-08 04:37:54Z peter $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/sysctl.h> 51#include <machine/bus.h> 52#include <sys/rman.h> 53#include <sys/signalvar.h> 54#include <sys/user.h> 55 56#include <machine/cputypes.h> 57#include <machine/frame.h> 58#include <machine/md_var.h> 59#include <machine/pcb.h> 60#include <machine/psl.h> 61#include <machine/resource.h> 62#include <machine/specialreg.h> 63#include <machine/segments.h> 64#include <machine/ucontext.h> 65 66#include <amd64/isa/intr_machdep.h> 67 68/* 69 * Floating point support. 70 */ 71 72#if defined(__GNUC__) && !defined(lint) 73 74#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 75#define fnclex() __asm("fnclex") 76#define fninit() __asm("fninit") 77#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 78#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 79#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 80#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 81#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 82 : : "n" (CR0_TS) : "ax") 83#define stop_emulating() __asm("clts") 84 85#else /* not __GNUC__ */ 86 87void fldcw(caddr_t addr); 88void fnclex(void); 89void fninit(void); 90void fnstcw(caddr_t addr); 91void fnstsw(caddr_t addr); 92void fxsave(caddr_t addr); 93void fxrstor(caddr_t addr); 94void start_emulating(void); 95void stop_emulating(void); 96 97#endif /* __GNUC__ */ 98 99#define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw) 100#define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw) 101 102typedef u_char bool_t; 103 104int hw_float = 1; 105SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 106 CTLFLAG_RD, &hw_float, 0, 107 "Floatingpoint instructions executed in hardware"); 108 109static struct savefpu fpu_cleanstate; 110static bool_t fpu_cleanstate_ready; 111 112/* 113 * Initialize floating point unit. 114 */ 115void 116fpuinit() 117{ 118 register_t savecrit; 119 u_short control; 120 121 /* 122 * fpusave() initializes the fpu and sets fpcurthread = NULL 123 */ 124 savecrit = intr_disable(); 125 fpusave(&fpu_cleanstate); /* XXX borrow for now */ 126 stop_emulating(); 127 /* XXX fpusave() doesn't actually initialize the fpu in the SSE case. */ 128 fninit(); 129 control = __INITIAL_FPUCW__; 130 fldcw(&control); 131 start_emulating(); 132 intr_restore(savecrit); 133 134 savecrit = intr_disable(); 135 stop_emulating(); 136 fxsave(&fpu_cleanstate); 137 start_emulating(); 138 fpu_cleanstate_ready = 1; 139 intr_restore(savecrit); 140} 141 142/* 143 * Free coprocessor (if we have it). 144 */ 145void 146fpuexit(struct thread *td) 147{ 148 register_t savecrit; 149 150 savecrit = intr_disable(); 151 if (curthread == PCPU_GET(fpcurthread)) 152 fpusave(&PCPU_GET(curpcb)->pcb_save); 153 intr_restore(savecrit); 154} 155 156int 157fpuformat() 158{ 159 160 return (_MC_FPFMT_XMM); 161} 162 163/* 164 * The following mechanism is used to ensure that the FPE_... value 165 * that is passed as a trapcode to the signal handler of the user 166 * process does not have more than one bit set. 167 * 168 * Multiple bits may be set if the user process modifies the control 169 * word while a status word bit is already set. While this is a sign 170 * of bad coding, we have no choise than to narrow them down to one 171 * bit, since we must not send a trapcode that is not exactly one of 172 * the FPE_ macros. 173 * 174 * The mechanism has a static table with 127 entries. Each combination 175 * of the 7 FPU status word exception bits directly translates to a 176 * position in this table, where a single FPE_... value is stored. 177 * This FPE_... value stored there is considered the "most important" 178 * of the exception bits and will be sent as the signal code. The 179 * precedence of the bits is based upon Intel Document "Numerical 180 * Applications", Chapter "Special Computational Situations". 181 * 182 * The macro to choose one of these values does these steps: 1) Throw 183 * away status word bits that cannot be masked. 2) Throw away the bits 184 * currently masked in the control word, assuming the user isn't 185 * interested in them anymore. 3) Reinsert status word bit 7 (stack 186 * fault) if it is set, which cannot be masked but must be presered. 187 * 4) Use the remaining bits to point into the trapcode table. 188 * 189 * The 6 maskable bits in order of their preference, as stated in the 190 * above referenced Intel manual: 191 * 1 Invalid operation (FP_X_INV) 192 * 1a Stack underflow 193 * 1b Stack overflow 194 * 1c Operand of unsupported format 195 * 1d SNaN operand. 196 * 2 QNaN operand (not an exception, irrelavant here) 197 * 3 Any other invalid-operation not mentioned above or zero divide 198 * (FP_X_INV, FP_X_DZ) 199 * 4 Denormal operand (FP_X_DNML) 200 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 201 * 6 Inexact result (FP_X_IMP) 202 */ 203static char fpetable[128] = { 204 0, 205 FPE_FLTINV, /* 1 - INV */ 206 FPE_FLTUND, /* 2 - DNML */ 207 FPE_FLTINV, /* 3 - INV | DNML */ 208 FPE_FLTDIV, /* 4 - DZ */ 209 FPE_FLTINV, /* 5 - INV | DZ */ 210 FPE_FLTDIV, /* 6 - DNML | DZ */ 211 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 212 FPE_FLTOVF, /* 8 - OFL */ 213 FPE_FLTINV, /* 9 - INV | OFL */ 214 FPE_FLTUND, /* A - DNML | OFL */ 215 FPE_FLTINV, /* B - INV | DNML | OFL */ 216 FPE_FLTDIV, /* C - DZ | OFL */ 217 FPE_FLTINV, /* D - INV | DZ | OFL */ 218 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 219 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 220 FPE_FLTUND, /* 10 - UFL */ 221 FPE_FLTINV, /* 11 - INV | UFL */ 222 FPE_FLTUND, /* 12 - DNML | UFL */ 223 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 224 FPE_FLTDIV, /* 14 - DZ | UFL */ 225 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 226 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 227 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 228 FPE_FLTOVF, /* 18 - OFL | UFL */ 229 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 230 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 231 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 232 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 233 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 234 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 235 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 236 FPE_FLTRES, /* 20 - IMP */ 237 FPE_FLTINV, /* 21 - INV | IMP */ 238 FPE_FLTUND, /* 22 - DNML | IMP */ 239 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 240 FPE_FLTDIV, /* 24 - DZ | IMP */ 241 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 242 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 243 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 244 FPE_FLTOVF, /* 28 - OFL | IMP */ 245 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 246 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 247 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 248 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 249 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 250 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 251 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 252 FPE_FLTUND, /* 30 - UFL | IMP */ 253 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 254 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 255 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 256 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 257 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 258 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 259 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 260 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 261 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 262 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 263 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 264 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 265 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 266 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 267 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 268 FPE_FLTSUB, /* 40 - STK */ 269 FPE_FLTSUB, /* 41 - INV | STK */ 270 FPE_FLTUND, /* 42 - DNML | STK */ 271 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 272 FPE_FLTDIV, /* 44 - DZ | STK */ 273 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 274 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 275 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 276 FPE_FLTOVF, /* 48 - OFL | STK */ 277 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 278 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 279 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 280 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 281 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 282 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 283 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 284 FPE_FLTUND, /* 50 - UFL | STK */ 285 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 286 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 287 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 288 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 289 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 290 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 291 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 292 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 293 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 294 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 295 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 296 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 297 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 298 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 299 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 300 FPE_FLTRES, /* 60 - IMP | STK */ 301 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 302 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 303 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 304 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 305 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 306 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 307 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 308 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 309 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 310 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 311 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 312 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 313 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 314 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 315 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 316 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 317 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 318 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 319 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 320 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 321 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 322 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 323 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 324 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 325 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 326 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 327 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 328 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 329 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 330 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 331 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 332}; 333 334/* 335 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 336 * 337 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 338 * depend on longjmp() restoring a usable state. Restoring the state 339 * or examining it might fail if we didn't clear exceptions. 340 * 341 * The error code chosen will be one of the FPE_... macros. It will be 342 * sent as the second argument to old BSD-style signal handlers and as 343 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 344 * 345 * XXX the FP state is not preserved across signal handlers. So signal 346 * handlers cannot afford to do FP unless they preserve the state or 347 * longjmp() out. Both preserving the state and longjmp()ing may be 348 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 349 * solution for signals other than SIGFPE. 350 */ 351int 352fputrap() 353{ 354 register_t savecrit; 355 u_short control, status; 356 357 savecrit = intr_disable(); 358 359 /* 360 * Interrupt handling (for another interrupt) may have pushed the 361 * state to memory. Fetch the relevant parts of the state from 362 * wherever they are. 363 */ 364 if (PCPU_GET(fpcurthread) != curthread) { 365 control = GET_FPU_CW(curthread); 366 status = GET_FPU_SW(curthread); 367 } else { 368 fnstcw(&control); 369 fnstsw(&status); 370 } 371 372 if (PCPU_GET(fpcurthread) == curthread) 373 fnclex(); 374 intr_restore(savecrit); 375 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 376} 377 378/* 379 * Implement device not available (DNA) exception 380 * 381 * It would be better to switch FP context here (if curthread != fpcurthread) 382 * and not necessarily for every context switch, but it is too hard to 383 * access foreign pcb's. 384 */ 385 386static int err_count = 0; 387 388int 389fpudna() 390{ 391 struct pcb *pcb; 392 register_t s; 393 u_short control; 394 395 if (PCPU_GET(fpcurthread) == curthread) { 396 printf("fpudna: fpcurthread == curthread %d times\n", 397 ++err_count); 398 stop_emulating(); 399 return (1); 400 } 401 if (PCPU_GET(fpcurthread) != NULL) { 402 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 403 PCPU_GET(fpcurthread), 404 PCPU_GET(fpcurthread)->td_proc->p_pid, 405 curthread, curthread->td_proc->p_pid); 406 panic("fpudna"); 407 } 408 s = intr_disable(); 409 stop_emulating(); 410 /* 411 * Record new context early in case frstor causes a trap. 412 */ 413 PCPU_SET(fpcurthread, curthread); 414 pcb = PCPU_GET(curpcb); 415 416 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 417 /* 418 * This is the first time this thread has used the FPU or 419 * the PCB doesn't contain a clean FPU state. Explicitly 420 * initialize the FPU and load the default control word. 421 */ 422 fninit(); 423 control = __INITIAL_FPUCW__; 424 fldcw(&control); 425 pcb->pcb_flags |= PCB_FPUINITDONE; 426 } else { 427 /* 428 * The following frstor may cause a trap when the state 429 * being restored has a pending error. The error will 430 * appear to have been triggered by the current (fpu) user 431 * instruction even when that instruction is a no-wait 432 * instruction that should not trigger an error (e.g., 433 * instructions are broken the same as frstor, so our 434 * treatment does not amplify the breakage. 435 */ 436 fxrstor(&pcb->pcb_save); 437 } 438 intr_restore(s); 439 440 return (1); 441} 442 443/* 444 * Wrapper for fnsave instruction. 445 * 446 * fpusave() must be called with interrupts disabled, so that it clears 447 * fpcurthread atomically with saving the state. We require callers to do the 448 * disabling, since most callers need to disable interrupts anyway to call 449 * fpusave() atomically with checking fpcurthread. 450 */ 451void 452fpusave(struct savefpu *addr) 453{ 454 455 stop_emulating(); 456 fxsave(addr); 457 start_emulating(); 458 PCPU_SET(fpcurthread, NULL); 459} 460 461/* 462 * This should be called with interrupts disabled and only when the owning 463 * FPU thread is non-null. 464 */ 465void 466fpudrop() 467{ 468 struct thread *td; 469 470 td = PCPU_GET(fpcurthread); 471 PCPU_SET(fpcurthread, NULL); 472 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 473 start_emulating(); 474} 475 476/* 477 * Get the state of the FPU without dropping ownership (if possible). 478 * It returns the FPU ownership status. 479 */ 480int 481fpugetregs(struct thread *td, struct savefpu *addr) 482{ 483 register_t s; 484 485 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 486 if (fpu_cleanstate_ready) 487 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate)); 488 else 489 bzero(addr, sizeof(*addr)); 490 return (_MC_FPOWNED_NONE); 491 } 492 s = intr_disable(); 493 if (td == PCPU_GET(fpcurthread)) { 494 fxsave(addr); 495 intr_restore(s); 496 return (_MC_FPOWNED_FPU); 497 } else { 498 intr_restore(s); 499 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 500 return (_MC_FPOWNED_PCB); 501 } 502} 503 504/* 505 * Set the state of the FPU. 506 */ 507void 508fpusetregs(struct thread *td, struct savefpu *addr) 509{ 510 register_t s; 511 512 s = intr_disable(); 513 if (td == PCPU_GET(fpcurthread)) { 514 fxrstor(addr); 515 intr_restore(s); 516 } else { 517 intr_restore(s); 518 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 519 } 520 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE; 521} 522 523/* 524 * This really sucks. We want the acpi version only, but it requires 525 * the isa_if.h file in order to get the definitions. 526 */ 527#include "opt_isa.h" 528#ifdef DEV_ISA 529#include <isa/isavar.h> 530/* 531 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 532 */ 533static struct isa_pnp_id fpupnp_ids[] = { 534 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 535 { 0 } 536}; 537 538static int 539fpupnp_probe(device_t dev) 540{ 541 int result; 542 543 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 544 if (result <= 0) 545 device_quiet(dev); 546 return (result); 547} 548 549static int 550fpupnp_attach(device_t dev) 551{ 552 553 return (0); 554} 555 556static device_method_t fpupnp_methods[] = { 557 /* Device interface */ 558 DEVMETHOD(device_probe, fpupnp_probe), 559 DEVMETHOD(device_attach, fpupnp_attach), 560 DEVMETHOD(device_detach, bus_generic_detach), 561 DEVMETHOD(device_shutdown, bus_generic_shutdown), 562 DEVMETHOD(device_suspend, bus_generic_suspend), 563 DEVMETHOD(device_resume, bus_generic_resume), 564 565 { 0, 0 } 566}; 567 568static driver_t fpupnp_driver = { 569 "fpupnp", 570 fpupnp_methods, 571 1, /* no softc */ 572}; 573 574static devclass_t fpupnp_devclass; 575 576DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0); 577#endif /* DEV_ISA */ 578