fpu.c revision 105952
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 105952 2002-10-25 19:12:16Z peter $ 36 */ 37 38#include "opt_cpu.h" 39#include "opt_debug_npx.h" 40#include "opt_isa.h" 41#include "opt_math_emulate.h" 42#include "opt_npx.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kernel.h> 48#include <sys/lock.h> 49#include <sys/malloc.h> 50#include <sys/module.h> 51#include <sys/mutex.h> 52#include <sys/mutex.h> 53#include <sys/proc.h> 54#include <sys/sysctl.h> 55#include <machine/bus.h> 56#include <sys/rman.h> 57#ifdef NPX_DEBUG 58#include <sys/syslog.h> 59#endif 60#include <sys/signalvar.h> 61#include <sys/user.h> 62 63#ifndef SMP 64#include <machine/asmacros.h> 65#endif 66#include <machine/cputypes.h> 67#include <machine/frame.h> 68#include <machine/md_var.h> 69#include <machine/pcb.h> 70#include <machine/psl.h> 71#ifndef SMP 72#include <machine/clock.h> 73#endif 74#include <machine/resource.h> 75#include <machine/specialreg.h> 76#include <machine/segments.h> 77#include <machine/ucontext.h> 78 79#ifndef SMP 80#include <i386/isa/icu.h> 81#ifdef PC98 82#include <pc98/pc98/pc98.h> 83#else 84#include <i386/isa/isa.h> 85#endif 86#endif 87#include <i386/isa/intr_machdep.h> 88#ifdef DEV_ISA 89#include <isa/isavar.h> 90#endif 91 92#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 93#define CPU_ENABLE_SSE 94#endif 95#if defined(CPU_DISABLE_SSE) 96#undef CPU_ENABLE_SSE 97#endif 98 99/* 100 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 101 */ 102 103/* Configuration flags. */ 104#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 105#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 106#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 107#define NPX_PREFER_EMULATOR (1 << 3) 108 109#if defined(__GNUC__) && !defined(lint) 110 111#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 112#define fnclex() __asm("fnclex") 113#define fninit() __asm("fninit") 114#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 115#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 116#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 117#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 118#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 119#ifdef CPU_ENABLE_SSE 120#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 121#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 122#endif 123#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 124 : : "n" (CR0_TS) : "ax") 125#define stop_emulating() __asm("clts") 126 127#else /* not __GNUC__ */ 128 129void fldcw(caddr_t addr); 130void fnclex(void); 131void fninit(void); 132void fnsave(caddr_t addr); 133void fnstcw(caddr_t addr); 134void fnstsw(caddr_t addr); 135void fp_divide_by_0(void); 136void frstor(caddr_t addr); 137#ifdef CPU_ENABLE_SSE 138void fxsave(caddr_t addr); 139void fxrstor(caddr_t addr); 140#endif 141void start_emulating(void); 142void stop_emulating(void); 143 144#endif /* __GNUC__ */ 145 146#ifdef CPU_ENABLE_SSE 147#define GET_FPU_CW(thread) \ 148 (cpu_fxsr ? \ 149 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 150 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 151#define GET_FPU_SW(thread) \ 152 (cpu_fxsr ? \ 153 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 154 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 155#else /* CPU_ENABLE_SSE */ 156#define GET_FPU_CW(thread) \ 157 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 158#define GET_FPU_SW(thread) \ 159 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 160#endif /* CPU_ENABLE_SSE */ 161 162typedef u_char bool_t; 163 164static int npx_attach(device_t dev); 165static void npx_identify(driver_t *driver, device_t parent); 166#ifndef SMP 167static void npx_intr(void *); 168#endif 169static int npx_probe(device_t dev); 170static void fpusave(union savefpu *); 171static void fpurstor(union savefpu *); 172#ifdef I586_CPU_XXX 173static long timezero(const char *funcname, 174 void (*func)(void *buf, size_t len)); 175#endif /* I586_CPU */ 176 177int hw_float; /* XXX currently just alias for npx_exists */ 178 179SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 180 CTLFLAG_RD, &hw_float, 0, 181 "Floatingpoint instructions executed in hardware"); 182 183#ifndef SMP 184static volatile u_int npx_intrs_while_probing; 185static volatile u_int npx_traps_while_probing; 186#endif 187 188static union savefpu npx_cleanstate; 189static bool_t npx_cleanstate_ready; 190static bool_t npx_ex16; 191static bool_t npx_exists; 192static bool_t npx_irq13; 193 194#ifndef SMP 195alias_for_inthand_t probetrap; 196__asm(" \n\ 197 .text \n\ 198 .p2align 2,0x90 \n\ 199 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 200" __XSTRING(CNAME(probetrap)) ": \n\ 201 ss \n\ 202 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 203 fnclex \n\ 204 iret \n\ 205"); 206#endif /* SMP */ 207 208/* 209 * Identify routine. Create a connection point on our parent for probing. 210 */ 211static void 212npx_identify(driver, parent) 213 driver_t *driver; 214 device_t parent; 215{ 216 device_t child; 217 218 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 219 if (child == NULL) 220 panic("npx_identify"); 221} 222 223#ifndef SMP 224/* 225 * Do minimal handling of npx interrupts to convert them to traps. 226 */ 227static void 228npx_intr(dummy) 229 void *dummy; 230{ 231 struct thread *td; 232 233#ifndef SMP 234 npx_intrs_while_probing++; 235#endif 236 237 /* 238 * The BUSY# latch must be cleared in all cases so that the next 239 * unmasked npx exception causes an interrupt. 240 */ 241#ifdef PC98 242 outb(0xf8, 0); 243#else 244 outb(0xf0, 0); 245#endif 246 247 /* 248 * fpcurthread is normally non-null here. In that case, schedule an 249 * AST to finish the exception handling in the correct context 250 * (this interrupt may occur after the thread has entered the 251 * kernel via a syscall or an interrupt). Otherwise, the npx 252 * state of the thread that caused this interrupt must have been 253 * pushed to the thread's pcb, and clearing of the busy latch 254 * above has finished the (essentially null) handling of this 255 * interrupt. Control will eventually return to the instruction 256 * that caused it and it will repeat. We will eventually (usually 257 * soon) win the race to handle the interrupt properly. 258 */ 259 td = PCPU_GET(fpcurthread); 260 if (td != NULL) { 261 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 262 mtx_lock_spin(&sched_lock); 263 td->td_kse->ke_flags |= KEF_ASTPENDING; 264 mtx_unlock_spin(&sched_lock); 265 } 266} 267#endif /* !SMP */ 268 269/* 270 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 271 * whether the device exists or not (XXX should be elsewhere). Set flags 272 * to tell npxattach() what to do. Modify device struct if npx doesn't 273 * need to use interrupts. Return 0 if device exists. 274 */ 275static int 276npx_probe(dev) 277 device_t dev; 278{ 279#ifndef SMP 280 struct gate_descriptor save_idt_npxtrap; 281 struct resource *ioport_res, *irq_res; 282 void *irq_cookie; 283 int ioport_rid, irq_num, irq_rid; 284 u_short control; 285 u_short status; 286 287 save_idt_npxtrap = idt[16]; 288 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 289 ioport_rid = 0; 290 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 291 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 292 if (ioport_res == NULL) 293 panic("npx: can't get ports"); 294#ifdef PC98 295 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 296 irq_num = 8; 297#else 298 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 299 irq_num = 13; 300#endif 301 irq_rid = 0; 302 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num, 303 irq_num, 1, RF_ACTIVE); 304 if (irq_res == NULL) 305 panic("npx: can't get IRQ"); 306 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 307 NULL, &irq_cookie) != 0) 308 panic("npx: can't create intr"); 309#endif /* !SMP */ 310 311 /* 312 * Partially reset the coprocessor, if any. Some BIOS's don't reset 313 * it after a warm boot. 314 */ 315#ifdef PC98 316 outb(0xf8,0); 317#else 318 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 319 outb(0xf0, 0); /* clear BUSY# latch */ 320#endif 321 /* 322 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 323 * instructions. We must set the CR0_MP bit and use the CR0_TS 324 * bit to control the trap, because setting the CR0_EM bit does 325 * not cause WAIT instructions to trap. It's important to trap 326 * WAIT instructions - otherwise the "wait" variants of no-wait 327 * control instructions would degenerate to the "no-wait" variants 328 * after FP context switches but work correctly otherwise. It's 329 * particularly important to trap WAITs when there is no NPX - 330 * otherwise the "wait" variants would always degenerate. 331 * 332 * Try setting CR0_NE to get correct error reporting on 486DX's. 333 * Setting it should fail or do nothing on lesser processors. 334 */ 335 load_cr0(rcr0() | CR0_MP | CR0_NE); 336 /* 337 * But don't trap while we're probing. 338 */ 339 stop_emulating(); 340 /* 341 * Finish resetting the coprocessor, if any. If there is an error 342 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 343 * it OK. Bogus halts have never been observed, but we enabled 344 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 345 */ 346 fninit(); 347 348 device_set_desc(dev, "math processor"); 349 350#ifdef SMP 351 352 /* 353 * Exception 16 MUST work for SMP. 354 */ 355 npx_ex16 = hw_float = npx_exists = 1; 356 return (0); 357 358#else /* !SMP */ 359 360 /* 361 * Don't use fwait here because it might hang. 362 * Don't use fnop here because it usually hangs if there is no FPU. 363 */ 364 DELAY(1000); /* wait for any IRQ13 */ 365#ifdef DIAGNOSTIC 366 if (npx_intrs_while_probing != 0) 367 printf("fninit caused %u bogus npx interrupt(s)\n", 368 npx_intrs_while_probing); 369 if (npx_traps_while_probing != 0) 370 printf("fninit caused %u bogus npx trap(s)\n", 371 npx_traps_while_probing); 372#endif 373 /* 374 * Check for a status of mostly zero. 375 */ 376 status = 0x5a5a; 377 fnstsw(&status); 378 if ((status & 0xb8ff) == 0) { 379 /* 380 * Good, now check for a proper control word. 381 */ 382 control = 0x5a5a; 383 fnstcw(&control); 384 if ((control & 0x1f3f) == 0x033f) { 385 hw_float = npx_exists = 1; 386 /* 387 * We have an npx, now divide by 0 to see if exception 388 * 16 works. 389 */ 390 control &= ~(1 << 2); /* enable divide by 0 trap */ 391 fldcw(&control); 392#ifdef FPU_ERROR_BROKEN 393 /* 394 * FPU error signal doesn't work on some CPU 395 * accelerator board. 396 */ 397 npx_ex16 = 1; 398 return (0); 399#endif 400 npx_traps_while_probing = npx_intrs_while_probing = 0; 401 fp_divide_by_0(); 402 if (npx_traps_while_probing != 0) { 403 /* 404 * Good, exception 16 works. 405 */ 406 npx_ex16 = 1; 407 goto no_irq13; 408 } 409 if (npx_intrs_while_probing != 0) { 410 /* 411 * Bad, we are stuck with IRQ13. 412 */ 413 npx_irq13 = 1; 414 idt[16] = save_idt_npxtrap; 415 return (0); 416 } 417 /* 418 * Worse, even IRQ13 is broken. Use emulator. 419 */ 420 } 421 } 422 /* 423 * Probe failed, but we want to get to npxattach to initialize the 424 * emulator and say that it has been installed. XXX handle devices 425 * that aren't really devices better. 426 */ 427 /* FALLTHROUGH */ 428no_irq13: 429 idt[16] = save_idt_npxtrap; 430 bus_teardown_intr(dev, irq_res, irq_cookie); 431 432 /* 433 * XXX hack around brokenness of bus_teardown_intr(). If we left the 434 * irq active then we would get it instead of exception 16. 435 */ 436 { 437 register_t crit; 438 439 crit = intr_disable(); 440 mtx_lock_spin(&icu_lock); 441 INTRDIS(1 << irq_num); 442 mtx_unlock_spin(&icu_lock); 443 intr_restore(crit); 444 } 445 446 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 447 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 448 return (0); 449 450#endif /* SMP */ 451} 452 453/* 454 * Attach routine - announce which it is, and wire into system 455 */ 456static int 457npx_attach(dev) 458 device_t dev; 459{ 460 int flags; 461 register_t s; 462 463 if (resource_int_value("npx", 0, "flags", &flags) != 0) 464 flags = 0; 465 466 if (flags) 467 device_printf(dev, "flags 0x%x ", flags); 468 if (npx_irq13) { 469 device_printf(dev, "using IRQ 13 interface\n"); 470 } else { 471#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 472 if (npx_ex16) { 473 if (!(flags & NPX_PREFER_EMULATOR)) 474 device_printf(dev, "INT 16 interface\n"); 475 else { 476 device_printf(dev, "FPU exists, but flags request " 477 "emulator\n"); 478 hw_float = npx_exists = 0; 479 } 480 } else if (npx_exists) { 481 device_printf(dev, "error reporting broken; using 387 emulator\n"); 482 hw_float = npx_exists = 0; 483 } else 484 device_printf(dev, "387 emulator\n"); 485#else 486 if (npx_ex16) { 487 device_printf(dev, "INT 16 interface\n"); 488 if (flags & NPX_PREFER_EMULATOR) { 489 device_printf(dev, "emulator requested, but none compiled " 490 "into kernel, using FPU\n"); 491 } 492 } else 493 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 494#endif 495 } 496 npxinit(__INITIAL_NPXCW__); 497 498 if (npx_cleanstate_ready == 0) { 499 s = intr_disable(); 500 stop_emulating(); 501 fpusave(&npx_cleanstate); 502 start_emulating(); 503 npx_cleanstate_ready = 1; 504 intr_restore(s); 505 } 506#ifdef I586_CPU_XXX 507 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 508 timezero("i586_bzero()", i586_bzero) < 509 timezero("bzero()", bzero) * 4 / 5) { 510 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 511 bcopy_vector = i586_bcopy; 512 ovbcopy_vector = i586_bcopy; 513 } 514 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 515 bzero = i586_bzero; 516 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 517 copyin_vector = i586_copyin; 518 copyout_vector = i586_copyout; 519 } 520 } 521#endif 522 523 return (0); /* XXX unused */ 524} 525 526/* 527 * Initialize floating point unit. 528 */ 529void 530npxinit(control) 531 u_short control; 532{ 533 static union savefpu dummy; 534 register_t savecrit; 535 536 if (!npx_exists) 537 return; 538 /* 539 * fninit has the same h/w bugs as fnsave. Use the detoxified 540 * fnsave to throw away any junk in the fpu. npxsave() initializes 541 * the fpu and sets fpcurthread = NULL as important side effects. 542 */ 543 savecrit = intr_disable(); 544 npxsave(&dummy); 545 stop_emulating(); 546#ifdef CPU_ENABLE_SSE 547 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 548 if (cpu_fxsr) 549 fninit(); 550#endif 551 fldcw(&control); 552 start_emulating(); 553 intr_restore(savecrit); 554} 555 556/* 557 * Free coprocessor (if we have it). 558 */ 559void 560npxexit(td) 561 struct thread *td; 562{ 563 register_t savecrit; 564 565 savecrit = intr_disable(); 566 if (curthread == PCPU_GET(fpcurthread)) 567 npxsave(&PCPU_GET(curpcb)->pcb_save); 568 intr_restore(savecrit); 569#ifdef NPX_DEBUG 570 if (npx_exists) { 571 u_int masked_exceptions; 572 573 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 574 /* 575 * Log exceptions that would have trapped with the old 576 * control word (overflow, divide by 0, and invalid operand). 577 */ 578 if (masked_exceptions & 0x0d) 579 log(LOG_ERR, 580 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 581 td->td_proc->p_pid, td->td_proc->p_comm, 582 masked_exceptions); 583 } 584#endif 585} 586 587int 588npxformat() 589{ 590 591 if (!npx_exists) 592 return (_MC_FPFMT_NODEV); 593#ifdef CPU_ENABLE_SSE 594 if (cpu_fxsr) 595 return (_MC_FPFMT_XMM); 596#endif 597 return (_MC_FPFMT_387); 598} 599 600/* 601 * The following mechanism is used to ensure that the FPE_... value 602 * that is passed as a trapcode to the signal handler of the user 603 * process does not have more than one bit set. 604 * 605 * Multiple bits may be set if the user process modifies the control 606 * word while a status word bit is already set. While this is a sign 607 * of bad coding, we have no choise than to narrow them down to one 608 * bit, since we must not send a trapcode that is not exactly one of 609 * the FPE_ macros. 610 * 611 * The mechanism has a static table with 127 entries. Each combination 612 * of the 7 FPU status word exception bits directly translates to a 613 * position in this table, where a single FPE_... value is stored. 614 * This FPE_... value stored there is considered the "most important" 615 * of the exception bits and will be sent as the signal code. The 616 * precedence of the bits is based upon Intel Document "Numerical 617 * Applications", Chapter "Special Computational Situations". 618 * 619 * The macro to choose one of these values does these steps: 1) Throw 620 * away status word bits that cannot be masked. 2) Throw away the bits 621 * currently masked in the control word, assuming the user isn't 622 * interested in them anymore. 3) Reinsert status word bit 7 (stack 623 * fault) if it is set, which cannot be masked but must be presered. 624 * 4) Use the remaining bits to point into the trapcode table. 625 * 626 * The 6 maskable bits in order of their preference, as stated in the 627 * above referenced Intel manual: 628 * 1 Invalid operation (FP_X_INV) 629 * 1a Stack underflow 630 * 1b Stack overflow 631 * 1c Operand of unsupported format 632 * 1d SNaN operand. 633 * 2 QNaN operand (not an exception, irrelavant here) 634 * 3 Any other invalid-operation not mentioned above or zero divide 635 * (FP_X_INV, FP_X_DZ) 636 * 4 Denormal operand (FP_X_DNML) 637 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 638 * 6 Inexact result (FP_X_IMP) 639 */ 640static char fpetable[128] = { 641 0, 642 FPE_FLTINV, /* 1 - INV */ 643 FPE_FLTUND, /* 2 - DNML */ 644 FPE_FLTINV, /* 3 - INV | DNML */ 645 FPE_FLTDIV, /* 4 - DZ */ 646 FPE_FLTINV, /* 5 - INV | DZ */ 647 FPE_FLTDIV, /* 6 - DNML | DZ */ 648 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 649 FPE_FLTOVF, /* 8 - OFL */ 650 FPE_FLTINV, /* 9 - INV | OFL */ 651 FPE_FLTUND, /* A - DNML | OFL */ 652 FPE_FLTINV, /* B - INV | DNML | OFL */ 653 FPE_FLTDIV, /* C - DZ | OFL */ 654 FPE_FLTINV, /* D - INV | DZ | OFL */ 655 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 656 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 657 FPE_FLTUND, /* 10 - UFL */ 658 FPE_FLTINV, /* 11 - INV | UFL */ 659 FPE_FLTUND, /* 12 - DNML | UFL */ 660 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 661 FPE_FLTDIV, /* 14 - DZ | UFL */ 662 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 663 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 664 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 665 FPE_FLTOVF, /* 18 - OFL | UFL */ 666 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 667 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 668 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 669 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 670 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 671 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 672 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 673 FPE_FLTRES, /* 20 - IMP */ 674 FPE_FLTINV, /* 21 - INV | IMP */ 675 FPE_FLTUND, /* 22 - DNML | IMP */ 676 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 677 FPE_FLTDIV, /* 24 - DZ | IMP */ 678 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 679 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 680 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 681 FPE_FLTOVF, /* 28 - OFL | IMP */ 682 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 683 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 684 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 685 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 686 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 687 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 688 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 689 FPE_FLTUND, /* 30 - UFL | IMP */ 690 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 691 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 692 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 693 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 694 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 695 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 696 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 697 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 698 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 699 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 700 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 701 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 702 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 703 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 704 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 705 FPE_FLTSUB, /* 40 - STK */ 706 FPE_FLTSUB, /* 41 - INV | STK */ 707 FPE_FLTUND, /* 42 - DNML | STK */ 708 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 709 FPE_FLTDIV, /* 44 - DZ | STK */ 710 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 711 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 712 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 713 FPE_FLTOVF, /* 48 - OFL | STK */ 714 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 715 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 716 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 717 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 718 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 719 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 720 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 721 FPE_FLTUND, /* 50 - UFL | STK */ 722 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 723 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 724 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 725 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 726 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 727 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 728 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 729 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 730 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 731 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 732 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 733 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 734 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 735 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 736 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 737 FPE_FLTRES, /* 60 - IMP | STK */ 738 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 739 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 740 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 741 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 742 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 743 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 744 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 745 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 746 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 747 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 748 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 749 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 750 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 751 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 752 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 753 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 754 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 755 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 756 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 757 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 758 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 759 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 760 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 761 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 762 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 763 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 764 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 765 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 766 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 767 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 768 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 769}; 770 771/* 772 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 773 * 774 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 775 * depend on longjmp() restoring a usable state. Restoring the state 776 * or examining it might fail if we didn't clear exceptions. 777 * 778 * The error code chosen will be one of the FPE_... macros. It will be 779 * sent as the second argument to old BSD-style signal handlers and as 780 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 781 * 782 * XXX the FP state is not preserved across signal handlers. So signal 783 * handlers cannot afford to do FP unless they preserve the state or 784 * longjmp() out. Both preserving the state and longjmp()ing may be 785 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 786 * solution for signals other than SIGFPE. 787 */ 788int 789npxtrap() 790{ 791 register_t savecrit; 792 u_short control, status; 793 794 if (!npx_exists) { 795 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 796 PCPU_GET(fpcurthread), curthread, npx_exists); 797 panic("npxtrap from nowhere"); 798 } 799 savecrit = intr_disable(); 800 801 /* 802 * Interrupt handling (for another interrupt) may have pushed the 803 * state to memory. Fetch the relevant parts of the state from 804 * wherever they are. 805 */ 806 if (PCPU_GET(fpcurthread) != curthread) { 807 control = GET_FPU_CW(curthread); 808 status = GET_FPU_SW(curthread); 809 } else { 810 fnstcw(&control); 811 fnstsw(&status); 812 } 813 814 if (PCPU_GET(fpcurthread) == curthread) 815 fnclex(); 816 intr_restore(savecrit); 817 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 818} 819 820/* 821 * Implement device not available (DNA) exception 822 * 823 * It would be better to switch FP context here (if curthread != fpcurthread) 824 * and not necessarily for every context switch, but it is too hard to 825 * access foreign pcb's. 826 */ 827 828static int err_count = 0; 829 830int 831npxdna() 832{ 833 struct pcb *pcb; 834 register_t s; 835 u_short control; 836 837 if (!npx_exists) 838 return (0); 839 if (PCPU_GET(fpcurthread) == curthread) { 840 printf("npxdna: fpcurthread == curthread %d times\n", 841 ++err_count); 842 stop_emulating(); 843 return (1); 844 } 845 if (PCPU_GET(fpcurthread) != NULL) { 846 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 847 PCPU_GET(fpcurthread), 848 PCPU_GET(fpcurthread)->td_proc->p_pid, 849 curthread, curthread->td_proc->p_pid); 850 panic("npxdna"); 851 } 852 s = intr_disable(); 853 stop_emulating(); 854 /* 855 * Record new context early in case frstor causes an IRQ13. 856 */ 857 PCPU_SET(fpcurthread, curthread); 858 pcb = PCPU_GET(curpcb); 859 860 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 861 /* 862 * This is the first time this thread has used the FPU or 863 * the PCB doesn't contain a clean FPU state. Explicitly 864 * initialize the FPU and load the default control word. 865 */ 866 fninit(); 867 control = __INITIAL_NPXCW__; 868 fldcw(&control); 869 pcb->pcb_flags |= PCB_NPXINITDONE; 870 } else { 871 /* 872 * The following frstor may cause an IRQ13 when the state 873 * being restored has a pending error. The error will 874 * appear to have been triggered by the current (npx) user 875 * instruction even when that instruction is a no-wait 876 * instruction that should not trigger an error (e.g., 877 * fnclex). On at least one 486 system all of the no-wait 878 * instructions are broken the same as frstor, so our 879 * treatment does not amplify the breakage. On at least 880 * one 386/Cyrix 387 system, fnclex works correctly while 881 * frstor and fnsave are broken, so our treatment breaks 882 * fnclex if it is the first FPU instruction after a context 883 * switch. 884 */ 885 fpurstor(&pcb->pcb_save); 886 } 887 intr_restore(s); 888 889 return (1); 890} 891 892/* 893 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 894 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 895 * no-wait npx instructions. See the Intel application note AP-578 for 896 * details. This doesn't cause any additional complications here. IRQ13's 897 * are inherently asynchronous unless the CPU is frozen to deliver them -- 898 * one that started in userland may be delivered many instructions later, 899 * after the process has entered the kernel. It may even be delivered after 900 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 901 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 902 * it is normally ignored at first because we set fpcurthread to NULL; it is 903 * normally retriggered in npxdna() after return to user mode. 904 * 905 * npxsave() must be called with interrupts disabled, so that it clears 906 * fpcurthread atomically with saving the state. We require callers to do the 907 * disabling, since most callers need to disable interrupts anyway to call 908 * npxsave() atomically with checking fpcurthread. 909 * 910 * A previous version of npxsave() went to great lengths to excecute fnsave 911 * with interrupts enabled in case executing it froze the CPU. This case 912 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 913 * spurious freezes. 914 */ 915void 916npxsave(addr) 917 union savefpu *addr; 918{ 919 920 stop_emulating(); 921 fpusave(addr); 922 923 start_emulating(); 924 PCPU_SET(fpcurthread, NULL); 925} 926 927/* 928 * This should be called with interrupts disabled and only when the owning 929 * FPU thread is non-null. 930 */ 931void 932npxdrop() 933{ 934 struct thread *td; 935 936 td = PCPU_GET(fpcurthread); 937 PCPU_SET(fpcurthread, NULL); 938 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 939 start_emulating(); 940} 941 942/* 943 * Get the state of the FPU without dropping ownership (if possible). 944 * It returns the FPU ownership status. 945 */ 946int 947npxgetregs(td, addr) 948 struct thread *td; 949 union savefpu *addr; 950{ 951 register_t s; 952 953 if (!npx_exists) 954 return (_MC_FPOWNED_NONE); 955 956 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 957 if (npx_cleanstate_ready) 958 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 959 else 960 bzero(addr, sizeof(*addr)); 961 return (_MC_FPOWNED_NONE); 962 } 963 964 s = intr_disable(); 965 if (curthread == PCPU_GET(fpcurthread)) { 966 fpusave(addr); 967#ifdef CPU_ENABLE_SSE 968 if (!cpu_fxsr) 969#endif 970 /* 971 * fnsave initializes the FPU and destroys whatever 972 * context it contains. Make sure the FPU owner 973 * starts with a clean state next time. 974 */ 975 npxdrop(); 976 intr_restore(s); 977 return (_MC_FPOWNED_FPU); 978 } else { 979 intr_restore(s); 980 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 981 return (_MC_FPOWNED_PCB); 982 } 983} 984 985/* 986 * Set the state of the FPU. 987 */ 988void 989npxsetregs(td, addr) 990 struct thread *td; 991 union savefpu *addr; 992{ 993 register_t s; 994 995 if (!npx_exists) 996 return; 997 998 s = intr_disable(); 999 if (curthread == PCPU_GET(fpcurthread)) { 1000 fpurstor(addr); 1001 intr_restore(s); 1002 } else { 1003 intr_restore(s); 1004 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 1005 } 1006 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 1007} 1008 1009static void 1010fpusave(addr) 1011 union savefpu *addr; 1012{ 1013 1014#ifdef CPU_ENABLE_SSE 1015 if (cpu_fxsr) 1016 fxsave(addr); 1017 else 1018#endif 1019 fnsave(addr); 1020} 1021 1022static void 1023fpurstor(addr) 1024 union savefpu *addr; 1025{ 1026 1027#ifdef CPU_ENABLE_SSE 1028 if (cpu_fxsr) 1029 fxrstor(addr); 1030 else 1031#endif 1032 frstor(addr); 1033} 1034 1035#ifdef I586_CPU_XXX 1036static long 1037timezero(funcname, func) 1038 const char *funcname; 1039 void (*func)(void *buf, size_t len); 1040 1041{ 1042 void *buf; 1043#define BUFSIZE 1048576 1044 long usec; 1045 struct timeval finish, start; 1046 1047 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 1048 if (buf == NULL) 1049 return (BUFSIZE); 1050 microtime(&start); 1051 (*func)(buf, BUFSIZE); 1052 microtime(&finish); 1053 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1054 finish.tv_usec - start.tv_usec; 1055 if (usec <= 0) 1056 usec = 1; 1057 if (bootverbose) 1058 printf("%s bandwidth = %u kBps\n", funcname, 1059 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1060 free(buf, M_TEMP); 1061 return (usec); 1062} 1063#endif /* I586_CPU */ 1064 1065static device_method_t npx_methods[] = { 1066 /* Device interface */ 1067 DEVMETHOD(device_identify, npx_identify), 1068 DEVMETHOD(device_probe, npx_probe), 1069 DEVMETHOD(device_attach, npx_attach), 1070 DEVMETHOD(device_detach, bus_generic_detach), 1071 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1072 DEVMETHOD(device_suspend, bus_generic_suspend), 1073 DEVMETHOD(device_resume, bus_generic_resume), 1074 1075 { 0, 0 } 1076}; 1077 1078static driver_t npx_driver = { 1079 "npx", 1080 npx_methods, 1081 1, /* no softc */ 1082}; 1083 1084static devclass_t npx_devclass; 1085 1086#ifdef DEV_ISA 1087/* 1088 * We prefer to attach to the root nexus so that the usual case (exception 16) 1089 * doesn't describe the processor as being `on isa'. 1090 */ 1091DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1092 1093/* 1094 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1095 */ 1096static struct isa_pnp_id npxisa_ids[] = { 1097 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1098 { 0 } 1099}; 1100 1101static int 1102npxisa_probe(device_t dev) 1103{ 1104 int result; 1105 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1106 device_quiet(dev); 1107 } 1108 return(result); 1109} 1110 1111static int 1112npxisa_attach(device_t dev) 1113{ 1114 return (0); 1115} 1116 1117static device_method_t npxisa_methods[] = { 1118 /* Device interface */ 1119 DEVMETHOD(device_probe, npxisa_probe), 1120 DEVMETHOD(device_attach, npxisa_attach), 1121 DEVMETHOD(device_detach, bus_generic_detach), 1122 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1123 DEVMETHOD(device_suspend, bus_generic_suspend), 1124 DEVMETHOD(device_resume, bus_generic_resume), 1125 1126 { 0, 0 } 1127}; 1128 1129static driver_t npxisa_driver = { 1130 "npxisa", 1131 npxisa_methods, 1132 1, /* no softc */ 1133}; 1134 1135static devclass_t npxisa_devclass; 1136 1137DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1138#ifndef PC98 1139DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1140#endif 1141#endif /* DEV_ISA */ 1142