fpu.c revision 103064
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/amd64/amd64/fpu.c 103064 2002-09-07 07:02:12Z peter $ 36 */ 37 38#include "opt_cpu.h" 39#include "opt_debug_npx.h" 40#include "opt_isa.h" 41#include "opt_math_emulate.h" 42#include "opt_npx.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kernel.h> 48#include <sys/lock.h> 49#include <sys/malloc.h> 50#include <sys/module.h> 51#include <sys/mutex.h> 52#include <sys/mutex.h> 53#include <sys/proc.h> 54#include <sys/sysctl.h> 55#include <machine/bus.h> 56#include <sys/rman.h> 57#ifdef NPX_DEBUG 58#include <sys/syslog.h> 59#endif 60#include <sys/signalvar.h> 61#include <sys/user.h> 62 63#ifndef SMP 64#include <machine/asmacros.h> 65#endif 66#include <machine/cputypes.h> 67#include <machine/frame.h> 68#include <machine/md_var.h> 69#include <machine/pcb.h> 70#include <machine/psl.h> 71#ifndef SMP 72#include <machine/clock.h> 73#endif 74#include <machine/resource.h> 75#include <machine/specialreg.h> 76#include <machine/segments.h> 77 78#ifndef SMP 79#include <i386/isa/icu.h> 80#ifdef PC98 81#include <pc98/pc98/pc98.h> 82#else 83#include <i386/isa/isa.h> 84#endif 85#endif 86#include <i386/isa/intr_machdep.h> 87#ifdef DEV_ISA 88#include <isa/isavar.h> 89#endif 90 91#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 92#define CPU_ENABLE_SSE 93#endif 94#if defined(CPU_DISABLE_SSE) 95#undef CPU_ENABLE_SSE 96#endif 97 98/* 99 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 100 */ 101 102/* Configuration flags. */ 103#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 104#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 105#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 106#define NPX_PREFER_EMULATOR (1 << 3) 107 108#ifdef __GNUC__ 109 110#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 111#define fnclex() __asm("fnclex") 112#define fninit() __asm("fninit") 113#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 114#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 115#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 116#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 117#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 118#ifdef CPU_ENABLE_SSE 119#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 120#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 121#endif 122#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 123 : : "n" (CR0_TS) : "ax") 124#define stop_emulating() __asm("clts") 125 126#else /* not __GNUC__ */ 127 128void fldcw(caddr_t addr); 129void fnclex(void); 130void fninit(void); 131void fnsave(caddr_t addr); 132void fnstcw(caddr_t addr); 133void fnstsw(caddr_t addr); 134void fp_divide_by_0(void); 135void frstor(caddr_t addr); 136#ifdef CPU_ENABLE_SSE 137void fxsave(caddr_t addr); 138void fxrstor(caddr_t addr); 139#endif 140void start_emulating(void); 141void stop_emulating(void); 142 143#endif /* __GNUC__ */ 144 145#ifdef CPU_ENABLE_SSE 146#define GET_FPU_CW(thread) \ 147 (cpu_fxsr ? \ 148 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 149 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 150#define GET_FPU_SW(thread) \ 151 (cpu_fxsr ? \ 152 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 153 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 154#define GET_FPU_EXSW_PTR(pcb) \ 155 (cpu_fxsr ? \ 156 &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ 157 &(pcb)->pcb_save.sv_87.sv_ex_sw) 158#else /* CPU_ENABLE_SSE */ 159#define GET_FPU_CW(thread) \ 160 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 161#define GET_FPU_SW(thread) \ 162 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 163#define GET_FPU_EXSW_PTR(pcb) \ 164 (&(pcb)->pcb_save.sv_87.sv_ex_sw) 165#endif /* CPU_ENABLE_SSE */ 166 167typedef u_char bool_t; 168 169static int npx_attach(device_t dev); 170static void npx_identify(driver_t *driver, device_t parent); 171#ifndef SMP 172static void npx_intr(void *); 173#endif 174static int npx_probe(device_t dev); 175static void fpusave(union savefpu *); 176static void fpurstor(union savefpu *); 177#ifdef I586_CPU_XXX 178static long timezero(const char *funcname, 179 void (*func)(void *buf, size_t len)); 180#endif /* I586_CPU */ 181 182int hw_float; /* XXX currently just alias for npx_exists */ 183 184SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 185 CTLFLAG_RD, &hw_float, 0, 186 "Floatingpoint instructions executed in hardware"); 187 188#ifndef SMP 189static volatile u_int npx_intrs_while_probing; 190static volatile u_int npx_traps_while_probing; 191#endif 192 193static bool_t npx_ex16; 194static bool_t npx_exists; 195static bool_t npx_irq13; 196 197#ifndef SMP 198alias_for_inthand_t probetrap; 199__asm(" \n\ 200 .text \n\ 201 .p2align 2,0x90 \n\ 202 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 203" __XSTRING(CNAME(probetrap)) ": \n\ 204 ss \n\ 205 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 206 fnclex \n\ 207 iret \n\ 208"); 209#endif /* SMP */ 210 211/* 212 * Identify routine. Create a connection point on our parent for probing. 213 */ 214static void 215npx_identify(driver, parent) 216 driver_t *driver; 217 device_t parent; 218{ 219 device_t child; 220 221 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 222 if (child == NULL) 223 panic("npx_identify"); 224} 225 226#ifndef SMP 227/* 228 * Do minimal handling of npx interrupts to convert them to traps. 229 */ 230static void 231npx_intr(dummy) 232 void *dummy; 233{ 234 struct thread *td; 235 236#ifndef SMP 237 npx_intrs_while_probing++; 238#endif 239 240 /* 241 * The BUSY# latch must be cleared in all cases so that the next 242 * unmasked npx exception causes an interrupt. 243 */ 244#ifdef PC98 245 outb(0xf8, 0); 246#else 247 outb(0xf0, 0); 248#endif 249 250 /* 251 * fpcurthread is normally non-null here. In that case, schedule an 252 * AST to finish the exception handling in the correct context 253 * (this interrupt may occur after the thread has entered the 254 * kernel via a syscall or an interrupt). Otherwise, the npx 255 * state of the thread that caused this interrupt must have been 256 * pushed to the thread's pcb, and clearing of the busy latch 257 * above has finished the (essentially null) handling of this 258 * interrupt. Control will eventually return to the instruction 259 * that caused it and it will repeat. We will eventually (usually 260 * soon) win the race to handle the interrupt properly. 261 */ 262 td = PCPU_GET(fpcurthread); 263 if (td != NULL) { 264 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 265 mtx_lock_spin(&sched_lock); 266 td->td_kse->ke_flags |= KEF_ASTPENDING; 267 mtx_unlock_spin(&sched_lock); 268 } 269} 270#endif /* !SMP */ 271 272/* 273 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 274 * whether the device exists or not (XXX should be elsewhere). Set flags 275 * to tell npxattach() what to do. Modify device struct if npx doesn't 276 * need to use interrupts. Return 0 if device exists. 277 */ 278static int 279npx_probe(dev) 280 device_t dev; 281{ 282#ifndef SMP 283 struct gate_descriptor save_idt_npxtrap; 284 struct resource *ioport_res, *irq_res; 285 void *irq_cookie; 286 int ioport_rid, irq_num, irq_rid; 287 u_short control; 288 u_short status; 289 290 save_idt_npxtrap = idt[16]; 291 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 292 ioport_rid = 0; 293 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 294 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 295 if (ioport_res == NULL) 296 panic("npx: can't get ports"); 297#ifdef PC98 298 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 299 irq_num = 8; 300#else 301 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 302 irq_num = 13; 303#endif 304 irq_rid = 0; 305 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num, 306 irq_num, 1, RF_ACTIVE); 307 if (irq_res == NULL) 308 panic("npx: can't get IRQ"); 309 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 310 NULL, &irq_cookie) != 0) 311 panic("npx: can't create intr"); 312#endif /* !SMP */ 313 314 /* 315 * Partially reset the coprocessor, if any. Some BIOS's don't reset 316 * it after a warm boot. 317 */ 318#ifdef PC98 319 outb(0xf8,0); 320#else 321 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 322 outb(0xf0, 0); /* clear BUSY# latch */ 323#endif 324 /* 325 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 326 * instructions. We must set the CR0_MP bit and use the CR0_TS 327 * bit to control the trap, because setting the CR0_EM bit does 328 * not cause WAIT instructions to trap. It's important to trap 329 * WAIT instructions - otherwise the "wait" variants of no-wait 330 * control instructions would degenerate to the "no-wait" variants 331 * after FP context switches but work correctly otherwise. It's 332 * particularly important to trap WAITs when there is no NPX - 333 * otherwise the "wait" variants would always degenerate. 334 * 335 * Try setting CR0_NE to get correct error reporting on 486DX's. 336 * Setting it should fail or do nothing on lesser processors. 337 */ 338 load_cr0(rcr0() | CR0_MP | CR0_NE); 339 /* 340 * But don't trap while we're probing. 341 */ 342 stop_emulating(); 343 /* 344 * Finish resetting the coprocessor, if any. If there is an error 345 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 346 * it OK. Bogus halts have never been observed, but we enabled 347 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 348 */ 349 fninit(); 350 351 device_set_desc(dev, "math processor"); 352 353#ifdef SMP 354 355 /* 356 * Exception 16 MUST work for SMP. 357 */ 358 npx_ex16 = hw_float = npx_exists = 1; 359 return (0); 360 361#else /* !SMP */ 362 363 /* 364 * Don't use fwait here because it might hang. 365 * Don't use fnop here because it usually hangs if there is no FPU. 366 */ 367 DELAY(1000); /* wait for any IRQ13 */ 368#ifdef DIAGNOSTIC 369 if (npx_intrs_while_probing != 0) 370 printf("fninit caused %u bogus npx interrupt(s)\n", 371 npx_intrs_while_probing); 372 if (npx_traps_while_probing != 0) 373 printf("fninit caused %u bogus npx trap(s)\n", 374 npx_traps_while_probing); 375#endif 376 /* 377 * Check for a status of mostly zero. 378 */ 379 status = 0x5a5a; 380 fnstsw(&status); 381 if ((status & 0xb8ff) == 0) { 382 /* 383 * Good, now check for a proper control word. 384 */ 385 control = 0x5a5a; 386 fnstcw(&control); 387 if ((control & 0x1f3f) == 0x033f) { 388 hw_float = npx_exists = 1; 389 /* 390 * We have an npx, now divide by 0 to see if exception 391 * 16 works. 392 */ 393 control &= ~(1 << 2); /* enable divide by 0 trap */ 394 fldcw(&control); 395#ifdef FPU_ERROR_BROKEN 396 /* 397 * FPU error signal doesn't work on some CPU 398 * accelerator board. 399 */ 400 npx_ex16 = 1; 401 return (0); 402#endif 403 npx_traps_while_probing = npx_intrs_while_probing = 0; 404 fp_divide_by_0(); 405 if (npx_traps_while_probing != 0) { 406 /* 407 * Good, exception 16 works. 408 */ 409 npx_ex16 = 1; 410 goto no_irq13; 411 } 412 if (npx_intrs_while_probing != 0) { 413 /* 414 * Bad, we are stuck with IRQ13. 415 */ 416 npx_irq13 = 1; 417 idt[16] = save_idt_npxtrap; 418 return (0); 419 } 420 /* 421 * Worse, even IRQ13 is broken. Use emulator. 422 */ 423 } 424 } 425 /* 426 * Probe failed, but we want to get to npxattach to initialize the 427 * emulator and say that it has been installed. XXX handle devices 428 * that aren't really devices better. 429 */ 430 /* FALLTHROUGH */ 431no_irq13: 432 idt[16] = save_idt_npxtrap; 433 bus_teardown_intr(dev, irq_res, irq_cookie); 434 435 /* 436 * XXX hack around brokenness of bus_teardown_intr(). If we left the 437 * irq active then we would get it instead of exception 16. 438 */ 439 { 440 register_t crit; 441 442 crit = intr_disable(); 443 mtx_lock_spin(&icu_lock); 444 INTRDIS(1 << irq_num); 445 mtx_unlock_spin(&icu_lock); 446 intr_restore(crit); 447 } 448 449 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 450 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 451 return (0); 452 453#endif /* SMP */ 454} 455 456/* 457 * Attach routine - announce which it is, and wire into system 458 */ 459int 460npx_attach(dev) 461 device_t dev; 462{ 463 int flags; 464 465 if (resource_int_value("npx", 0, "flags", &flags) != 0) 466 flags = 0; 467 468 if (flags) 469 device_printf(dev, "flags 0x%x ", flags); 470 if (npx_irq13) { 471 device_printf(dev, "using IRQ 13 interface\n"); 472 } else { 473#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 474 if (npx_ex16) { 475 if (!(flags & NPX_PREFER_EMULATOR)) 476 device_printf(dev, "INT 16 interface\n"); 477 else { 478 device_printf(dev, "FPU exists, but flags request " 479 "emulator\n"); 480 hw_float = npx_exists = 0; 481 } 482 } else if (npx_exists) { 483 device_printf(dev, "error reporting broken; using 387 emulator\n"); 484 hw_float = npx_exists = 0; 485 } else 486 device_printf(dev, "387 emulator\n"); 487#else 488 if (npx_ex16) { 489 device_printf(dev, "INT 16 interface\n"); 490 if (flags & NPX_PREFER_EMULATOR) { 491 device_printf(dev, "emulator requested, but none compiled " 492 "into kernel, using FPU\n"); 493 } 494 } else 495 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 496#endif 497 } 498 npxinit(__INITIAL_NPXCW__); 499 500#ifdef I586_CPU_XXX 501 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 502 timezero("i586_bzero()", i586_bzero) < 503 timezero("bzero()", bzero) * 4 / 5) { 504 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 505 bcopy_vector = i586_bcopy; 506 ovbcopy_vector = i586_bcopy; 507 } 508 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 509 bzero = i586_bzero; 510 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 511 copyin_vector = i586_copyin; 512 copyout_vector = i586_copyout; 513 } 514 } 515#endif 516 517 return (0); /* XXX unused */ 518} 519 520/* 521 * Initialize floating point unit. 522 */ 523void 524npxinit(control) 525 u_short control; 526{ 527 static union savefpu dummy; 528 register_t savecrit; 529 530 if (!npx_exists) 531 return; 532 /* 533 * fninit has the same h/w bugs as fnsave. Use the detoxified 534 * fnsave to throw away any junk in the fpu. npxsave() initializes 535 * the fpu and sets fpcurthread = NULL as important side effects. 536 */ 537 savecrit = intr_disable(); 538 npxsave(&dummy); 539 stop_emulating(); 540#ifdef CPU_ENABLE_SSE 541 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 542 if (cpu_fxsr) 543 fninit(); 544#endif 545 fldcw(&control); 546 if (PCPU_GET(curpcb) != NULL) 547 fpusave(&PCPU_GET(curpcb)->pcb_save); 548 start_emulating(); 549 intr_restore(savecrit); 550} 551 552/* 553 * Free coprocessor (if we have it). 554 */ 555void 556npxexit(td) 557 struct thread *td; 558{ 559 register_t savecrit; 560 561 savecrit = intr_disable(); 562 if (td == PCPU_GET(fpcurthread)) 563 npxsave(&PCPU_GET(curpcb)->pcb_save); 564 intr_restore(savecrit); 565#ifdef NPX_DEBUG 566 if (npx_exists) { 567 u_int masked_exceptions; 568 569 masked_exceptions = PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_cw 570 & PCPU_GET(curpcb)->pcb_save.sv_87.sv_env.en_sw & 0x7f; 571 /* 572 * Log exceptions that would have trapped with the old 573 * control word (overflow, divide by 0, and invalid operand). 574 */ 575 if (masked_exceptions & 0x0d) 576 log(LOG_ERR, 577 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 578 td->td_proc->p_pid, td->td_proc->p_comm, 579 masked_exceptions); 580 } 581#endif 582} 583 584/* 585 * The following mechanism is used to ensure that the FPE_... value 586 * that is passed as a trapcode to the signal handler of the user 587 * process does not have more than one bit set. 588 * 589 * Multiple bits may be set if the user process modifies the control 590 * word while a status word bit is already set. While this is a sign 591 * of bad coding, we have no choise than to narrow them down to one 592 * bit, since we must not send a trapcode that is not exactly one of 593 * the FPE_ macros. 594 * 595 * The mechanism has a static table with 127 entries. Each combination 596 * of the 7 FPU status word exception bits directly translates to a 597 * position in this table, where a single FPE_... value is stored. 598 * This FPE_... value stored there is considered the "most important" 599 * of the exception bits and will be sent as the signal code. The 600 * precedence of the bits is based upon Intel Document "Numerical 601 * Applications", Chapter "Special Computational Situations". 602 * 603 * The macro to choose one of these values does these steps: 1) Throw 604 * away status word bits that cannot be masked. 2) Throw away the bits 605 * currently masked in the control word, assuming the user isn't 606 * interested in them anymore. 3) Reinsert status word bit 7 (stack 607 * fault) if it is set, which cannot be masked but must be presered. 608 * 4) Use the remaining bits to point into the trapcode table. 609 * 610 * The 6 maskable bits in order of their preference, as stated in the 611 * above referenced Intel manual: 612 * 1 Invalid operation (FP_X_INV) 613 * 1a Stack underflow 614 * 1b Stack overflow 615 * 1c Operand of unsupported format 616 * 1d SNaN operand. 617 * 2 QNaN operand (not an exception, irrelavant here) 618 * 3 Any other invalid-operation not mentioned above or zero divide 619 * (FP_X_INV, FP_X_DZ) 620 * 4 Denormal operand (FP_X_DNML) 621 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 622 * 6 Inexact result (FP_X_IMP) 623 */ 624static char fpetable[128] = { 625 0, 626 FPE_FLTINV, /* 1 - INV */ 627 FPE_FLTUND, /* 2 - DNML */ 628 FPE_FLTINV, /* 3 - INV | DNML */ 629 FPE_FLTDIV, /* 4 - DZ */ 630 FPE_FLTINV, /* 5 - INV | DZ */ 631 FPE_FLTDIV, /* 6 - DNML | DZ */ 632 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 633 FPE_FLTOVF, /* 8 - OFL */ 634 FPE_FLTINV, /* 9 - INV | OFL */ 635 FPE_FLTUND, /* A - DNML | OFL */ 636 FPE_FLTINV, /* B - INV | DNML | OFL */ 637 FPE_FLTDIV, /* C - DZ | OFL */ 638 FPE_FLTINV, /* D - INV | DZ | OFL */ 639 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 640 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 641 FPE_FLTUND, /* 10 - UFL */ 642 FPE_FLTINV, /* 11 - INV | UFL */ 643 FPE_FLTUND, /* 12 - DNML | UFL */ 644 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 645 FPE_FLTDIV, /* 14 - DZ | UFL */ 646 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 647 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 648 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 649 FPE_FLTOVF, /* 18 - OFL | UFL */ 650 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 651 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 652 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 653 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 654 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 655 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 656 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 657 FPE_FLTRES, /* 20 - IMP */ 658 FPE_FLTINV, /* 21 - INV | IMP */ 659 FPE_FLTUND, /* 22 - DNML | IMP */ 660 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 661 FPE_FLTDIV, /* 24 - DZ | IMP */ 662 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 663 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 664 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 665 FPE_FLTOVF, /* 28 - OFL | IMP */ 666 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 667 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 668 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 669 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 670 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 671 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 672 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 673 FPE_FLTUND, /* 30 - UFL | IMP */ 674 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 675 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 676 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 677 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 678 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 679 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 680 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 681 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 682 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 683 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 684 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 685 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 686 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 687 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 688 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 689 FPE_FLTSUB, /* 40 - STK */ 690 FPE_FLTSUB, /* 41 - INV | STK */ 691 FPE_FLTUND, /* 42 - DNML | STK */ 692 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 693 FPE_FLTDIV, /* 44 - DZ | STK */ 694 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 695 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 696 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 697 FPE_FLTOVF, /* 48 - OFL | STK */ 698 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 699 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 700 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 701 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 702 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 703 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 704 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 705 FPE_FLTUND, /* 50 - UFL | STK */ 706 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 707 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 708 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 709 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 710 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 711 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 712 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 713 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 714 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 715 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 716 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 717 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 718 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 719 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 720 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 721 FPE_FLTRES, /* 60 - IMP | STK */ 722 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 723 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 724 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 725 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 726 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 727 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 728 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 729 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 730 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 731 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 732 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 733 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 734 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 735 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 736 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 737 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 738 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 739 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 740 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 741 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 742 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 743 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 744 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 745 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 746 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 747 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 748 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 749 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 750 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 751 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 752 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 753}; 754 755/* 756 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 757 * 758 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 759 * depend on longjmp() restoring a usable state. Restoring the state 760 * or examining it might fail if we didn't clear exceptions. 761 * 762 * The error code chosen will be one of the FPE_... macros. It will be 763 * sent as the second argument to old BSD-style signal handlers and as 764 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 765 * 766 * XXX the FP state is not preserved across signal handlers. So signal 767 * handlers cannot afford to do FP unless they preserve the state or 768 * longjmp() out. Both preserving the state and longjmp()ing may be 769 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 770 * solution for signals other than SIGFPE. 771 */ 772int 773npxtrap() 774{ 775 register_t savecrit; 776 u_short control, status; 777 u_long *exstat; 778 779 if (!npx_exists) { 780 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 781 PCPU_GET(fpcurthread), curthread, npx_exists); 782 panic("npxtrap from nowhere"); 783 } 784 savecrit = intr_disable(); 785 786 /* 787 * Interrupt handling (for another interrupt) may have pushed the 788 * state to memory. Fetch the relevant parts of the state from 789 * wherever they are. 790 */ 791 if (PCPU_GET(fpcurthread) != curthread) { 792 control = GET_FPU_CW(curthread); 793 status = GET_FPU_SW(curthread); 794 } else { 795 fnstcw(&control); 796 fnstsw(&status); 797 } 798 799 exstat = GET_FPU_EXSW_PTR(curthread->td_pcb); 800 *exstat = status; 801 if (PCPU_GET(fpcurthread) != curthread) 802 GET_FPU_SW(curthread) &= ~0x80bf; 803 else 804 fnclex(); 805 intr_restore(savecrit); 806 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 807} 808 809/* 810 * Implement device not available (DNA) exception 811 * 812 * It would be better to switch FP context here (if curthread != fpcurthread) 813 * and not necessarily for every context switch, but it is too hard to 814 * access foreign pcb's. 815 */ 816int 817npxdna() 818{ 819 u_long *exstat; 820 register_t s; 821 822 if (!npx_exists) 823 return (0); 824 if (PCPU_GET(fpcurthread) != NULL) { 825 printf("npxdna: fpcurthread = %p, curthread = %p\n", 826 PCPU_GET(fpcurthread), curthread); 827 panic("npxdna"); 828 } 829 s = intr_disable(); 830 stop_emulating(); 831 /* 832 * Record new context early in case frstor causes an IRQ13. 833 */ 834 PCPU_SET(fpcurthread, curthread); 835 836 exstat = GET_FPU_EXSW_PTR(PCPU_GET(curpcb)); 837 *exstat = 0; 838 /* 839 * The following frstor may cause an IRQ13 when the state being 840 * restored has a pending error. The error will appear to have been 841 * triggered by the current (npx) user instruction even when that 842 * instruction is a no-wait instruction that should not trigger an 843 * error (e.g., fnclex). On at least one 486 system all of the 844 * no-wait instructions are broken the same as frstor, so our 845 * treatment does not amplify the breakage. On at least one 846 * 386/Cyrix 387 system, fnclex works correctly while frstor and 847 * fnsave are broken, so our treatment breaks fnclex if it is the 848 * first FPU instruction after a context switch. 849 */ 850 fpurstor(&PCPU_GET(curpcb)->pcb_save); 851 intr_restore(s); 852 853 return (1); 854} 855 856/* 857 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 858 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 859 * no-wait npx instructions. See the Intel application note AP-578 for 860 * details. This doesn't cause any additional complications here. IRQ13's 861 * are inherently asynchronous unless the CPU is frozen to deliver them -- 862 * one that started in userland may be delivered many instructions later, 863 * after the process has entered the kernel. It may even be delivered after 864 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 865 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 866 * it is normally ignored at first because we set fpcurthread to NULL; it is 867 * normally retriggered in npxdna() after return to user mode. 868 * 869 * npxsave() must be called with interrupts disabled, so that it clears 870 * fpcurthread atomically with saving the state. We require callers to do the 871 * disabling, since most callers need to disable interrupts anyway to call 872 * npxsave() atomically with checking fpcurthread. 873 * 874 * A previous version of npxsave() went to great lengths to excecute fnsave 875 * with interrupts enabled in case executing it froze the CPU. This case 876 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 877 * spurious freezes. 878 */ 879void 880npxsave(addr) 881 union savefpu *addr; 882{ 883 884 stop_emulating(); 885 fpusave(addr); 886 887 start_emulating(); 888 PCPU_SET(fpcurthread, NULL); 889} 890 891static void 892fpusave(addr) 893 union savefpu *addr; 894{ 895 896#ifdef CPU_ENABLE_SSE 897 if (cpu_fxsr) 898 fxsave(addr); 899 else 900#endif 901 fnsave(addr); 902} 903 904static void 905fpurstor(addr) 906 union savefpu *addr; 907{ 908 909#ifdef CPU_ENABLE_SSE 910 if (cpu_fxsr) 911 fxrstor(addr); 912 else 913#endif 914 frstor(addr); 915} 916 917#ifdef I586_CPU_XXX 918static long 919timezero(funcname, func) 920 const char *funcname; 921 void (*func)(void *buf, size_t len); 922 923{ 924 void *buf; 925#define BUFSIZE 1048576 926 long usec; 927 struct timeval finish, start; 928 929 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 930 if (buf == NULL) 931 return (BUFSIZE); 932 microtime(&start); 933 (*func)(buf, BUFSIZE); 934 microtime(&finish); 935 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 936 finish.tv_usec - start.tv_usec; 937 if (usec <= 0) 938 usec = 1; 939 if (bootverbose) 940 printf("%s bandwidth = %u kBps\n", funcname, 941 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 942 free(buf, M_TEMP); 943 return (usec); 944} 945#endif /* I586_CPU */ 946 947static device_method_t npx_methods[] = { 948 /* Device interface */ 949 DEVMETHOD(device_identify, npx_identify), 950 DEVMETHOD(device_probe, npx_probe), 951 DEVMETHOD(device_attach, npx_attach), 952 DEVMETHOD(device_detach, bus_generic_detach), 953 DEVMETHOD(device_shutdown, bus_generic_shutdown), 954 DEVMETHOD(device_suspend, bus_generic_suspend), 955 DEVMETHOD(device_resume, bus_generic_resume), 956 957 { 0, 0 } 958}; 959 960static driver_t npx_driver = { 961 "npx", 962 npx_methods, 963 1, /* no softc */ 964}; 965 966static devclass_t npx_devclass; 967 968#ifdef DEV_ISA 969/* 970 * We prefer to attach to the root nexus so that the usual case (exception 16) 971 * doesn't describe the processor as being `on isa'. 972 */ 973DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 974 975/* 976 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 977 */ 978static struct isa_pnp_id npxisa_ids[] = { 979 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 980 { 0 } 981}; 982 983static int 984npxisa_probe(device_t dev) 985{ 986 int result; 987 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 988 device_quiet(dev); 989 } 990 return(result); 991} 992 993static int 994npxisa_attach(device_t dev) 995{ 996 return (0); 997} 998 999static device_method_t npxisa_methods[] = { 1000 /* Device interface */ 1001 DEVMETHOD(device_probe, npxisa_probe), 1002 DEVMETHOD(device_attach, npxisa_attach), 1003 DEVMETHOD(device_detach, bus_generic_detach), 1004 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1005 DEVMETHOD(device_suspend, bus_generic_suspend), 1006 DEVMETHOD(device_resume, bus_generic_resume), 1007 1008 { 0, 0 } 1009}; 1010 1011static driver_t npxisa_driver = { 1012 "npxisa", 1013 npxisa_methods, 1014 1, /* no softc */ 1015}; 1016 1017static devclass_t npxisa_devclass; 1018 1019DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1020#ifndef PC98 1021DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1022#endif 1023#endif /* DEV_ISA */ 1024