1262197Srwatson/*- 2262197Srwatson * Copyright (c) 2011 Robert N. M. Watson 3262197Srwatson * All rights reserved. 4262197Srwatson * 5262197Srwatson * This software was developed by SRI International and the University of 6262197Srwatson * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7262197Srwatson * ("CTSRD"), as part of the DARPA CRASH research programme. 8262197Srwatson * 9262197Srwatson * Redistribution and use in source and binary forms, with or without 10262197Srwatson * modification, are permitted provided that the following conditions 11262197Srwatson * are met: 12262197Srwatson * 1. Redistributions of source code must retain the above copyright 13262197Srwatson * notice, this list of conditions and the following disclaimer. 14262197Srwatson * 2. Redistributions in binary form must reproduce the above copyright 15262197Srwatson * notice, this list of conditions and the following disclaimer in the 16262197Srwatson * documentation and/or other materials provided with the distribution. 17262197Srwatson * 18262197Srwatson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19262197Srwatson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20262197Srwatson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21262197Srwatson * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22262197Srwatson * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23262197Srwatson * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24262197Srwatson * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25262197Srwatson * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26262197Srwatson * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27262197Srwatson * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28262197Srwatson * SUCH DAMAGE. 29262197Srwatson * 30262197Srwatson * $FreeBSD: stable/11/stand/mips/beri/common/mips.h 262197 2014-02-18 23:18:32Z rwatson $ 31262197Srwatson */ 32262197Srwatson 33262197Srwatson#ifndef _MIPS_H_ 34262197Srwatson#define _MIPS_H_ 35262197Srwatson 36262197Srwatson/* 37262197Srwatson * 64-bit MIPS types. 38262197Srwatson */ 39262197Srwatson#if 0 40262197Srwatsontypedef unsigned long register_t; /* 64-bit MIPS register */ 41262197Srwatson#endif 42262197Srwatsontypedef unsigned long paddr_t; /* Physical address */ 43262197Srwatsontypedef unsigned long vaddr_t; /* Virtual address */ 44262197Srwatson 45262197Srwatson#if 0 46262197Srwatsontypedef unsigned char uint8_t; 47262197Srwatsontypedef unsigned short uint16_t; 48262197Srwatsontypedef unsigned int uint32_t; 49262197Srwatsontypedef unsigned long uint64_t; 50262197Srwatson#endif 51262197Srwatson 52262197Srwatson/* 53262197Srwatson * MIPS address space layout. 54262197Srwatson */ 55262197Srwatson#define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000 56262197Srwatson#define MIPS_XKPHYS_CACHED_NC_BASE 0x9800000000000000 57262197Srwatson 58262197Srwatsonstatic inline vaddr_t 59262197Srwatsonmips_phys_to_cached(paddr_t phys) 60262197Srwatson{ 61262197Srwatson 62262197Srwatson return (phys | MIPS_XKPHYS_CACHED_NC_BASE); 63262197Srwatson} 64262197Srwatson 65262197Srwatsonstatic inline vaddr_t 66262197Srwatsonmips_phys_to_uncached(paddr_t phys) 67262197Srwatson{ 68262197Srwatson 69262197Srwatson return (phys | MIPS_XKPHYS_UNCACHED_BASE); 70262197Srwatson} 71262197Srwatson 72262197Srwatson/* 73262197Srwatson * Endian conversion routines for use in I/O -- most Altera devices are little 74262197Srwatson * endian, but our processor is big endian. 75262197Srwatson */ 76262197Srwatsonstatic inline uint16_t 77262197Srwatsonbyteswap16(uint16_t v) 78262197Srwatson{ 79262197Srwatson 80262197Srwatson return ((v & 0xff00) >> 8 | (v & 0xff) << 8); 81262197Srwatson} 82262197Srwatson 83262197Srwatsonstatic inline uint32_t 84262197Srwatsonbyteswap32(uint32_t v) 85262197Srwatson{ 86262197Srwatson 87262197Srwatson return ((v & 0xff000000) >> 24 | (v & 0x00ff0000) >> 8 | 88262197Srwatson (v & 0x0000ff00) << 8 | (v & 0x000000ff) << 24); 89262197Srwatson} 90262197Srwatson 91262197Srwatson/* 92262197Srwatson * MIPS simple I/O routines -- arguments are virtual addresses so that the 93262197Srwatson * caller can determine required caching properties. 94262197Srwatson */ 95262197Srwatsonstatic inline uint8_t 96262197Srwatsonmips_ioread_uint8(vaddr_t vaddr) 97262197Srwatson{ 98262197Srwatson uint8_t v; 99262197Srwatson 100262197Srwatson __asm__ __volatile__ ("lb %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 101262197Srwatson return (v); 102262197Srwatson} 103262197Srwatson 104262197Srwatsonstatic inline void 105262197Srwatsonmips_iowrite_uint8(vaddr_t vaddr, uint8_t v) 106262197Srwatson{ 107262197Srwatson 108262197Srwatson __asm__ __volatile__ ("sb %0, 0(%1)" : : "r" (v), "r" (vaddr)); 109262197Srwatson} 110262197Srwatson 111262197Srwatsonstatic inline uint32_t 112262197Srwatsonmips_ioread_uint32(vaddr_t vaddr) 113262197Srwatson{ 114262197Srwatson uint32_t v; 115262197Srwatson 116262197Srwatson __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 117262197Srwatson return (v); 118262197Srwatson} 119262197Srwatson 120262197Srwatsonstatic inline void 121262197Srwatsonmips_iowrite_uint32(vaddr_t vaddr, uint32_t v) 122262197Srwatson{ 123262197Srwatson 124262197Srwatson __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr)); 125262197Srwatson} 126262197Srwatson 127262197Srwatson/* 128262197Srwatson * Little-endian versions of 32-bit I/O routines. 129262197Srwatson */ 130262197Srwatsonstatic inline uint32_t 131262197Srwatsonmips_ioread_uint32le(vaddr_t vaddr) 132262197Srwatson{ 133262197Srwatson 134262197Srwatson return (byteswap32(mips_ioread_uint32(vaddr))); 135262197Srwatson} 136262197Srwatson 137262197Srwatsonstatic inline void 138262197Srwatsonmips_iowrite_uint32le(vaddr_t vaddr, uint32_t v) 139262197Srwatson{ 140262197Srwatson 141262197Srwatson mips_iowrite_uint32(vaddr, byteswap32(v)); 142262197Srwatson} 143262197Srwatson 144262197Srwatson/* 145262197Srwatson * Coprocessor 0 interfaces. 146262197Srwatson */ 147262197Srwatsonstatic inline register_t 148262197Srwatsoncp0_count_get(void) 149262197Srwatson{ 150262197Srwatson register_t count; 151262197Srwatson 152262197Srwatson __asm__ __volatile__ ("dmfc0 %0, $9" : "=r" (count)); 153262197Srwatson return (count); 154262197Srwatson} 155262197Srwatson 156262197Srwatson#endif 157