fwohci.h revision 302408 
1/*
2 * Copyright (c) 2007 Hidetoshi Shimokawa
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the acknowledgement as bellow:
15 *
16 *    This product includes software developed by K. Kobayashi and H. Shimokawa
17 *
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: stable/11/sys/boot/i386/libfirewire/fwohci.h 258780 2013-11-30 22:17:27Z eadler $
34 *
35 */
36
37#define MAX_OHCI 5
38#define CROMSIZE 0x400
39
40struct fw_eui64 {
41        uint32_t hi, lo;
42};
43
44struct fwohci_softc {
45	uint32_t locator;
46	uint32_t devid;
47	uint32_t base_addr;
48	uint32_t bus_id;
49	uint32_t handle;
50	int32_t state;
51	struct crom_src_buf *crom_src_buf;
52	struct crom_src *crom_src;
53	struct crom_chunk *crom_root;
54	struct fw_eui64 eui;
55	int	speed;
56	int	maxrec;
57	uint32_t *config_rom;
58	char config_rom_buf[CROMSIZE*2]; /* double size for alignment */
59};
60
61int fwohci_init(struct fwohci_softc *, int);
62void fwohci_ibr(struct fwohci_softc *);
63void fwohci_poll(struct fwohci_softc *);
64
65#define FWOHCI_STATE_DEAD	(-1)
66#define FWOHCI_STATE_INIT	0
67#define FWOHCI_STATE_ENABLED	1
68#define FWOHCI_STATE_BUSRESET	2
69#define FWOHCI_STATE_NORMAL	3
70
71#define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o)))
72#define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v))
73
74#define	OHCI_VERSION		0x00
75#define	OHCI_ATRETRY		0x08
76#define	OHCI_CROMHDR		0x18
77#define OHCI_BUS_ID		0x1c
78#define	OHCI_BUS_OPT		0x20
79#define	OHCI_BUSIRMC		(1U << 31)
80#define	OHCI_BUSCMC		(1 << 30)
81#define	OHCI_BUSISC		(1 << 29)
82#define	OHCI_BUSBMC		(1 << 28)
83#define	OHCI_BUSPMC		(1 << 27)
84#define OHCI_BUSFNC		OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
85				OHCI_BUSBMC | OHCI_BUSPMC
86
87#define	OHCI_EUID_HI		0x24
88#define	OHCI_EUID_LO		0x28
89
90#define	OHCI_CROMPTR		0x34
91#define	OHCI_HCCCTL		0x50
92#define	OHCI_HCCCTLCLR		0x54
93#define	OHCI_AREQHI		0x100
94#define	OHCI_AREQHICLR		0x104
95#define	OHCI_AREQLO		0x108
96#define	OHCI_AREQLOCLR		0x10c
97#define	OHCI_PREQHI		0x110
98#define	OHCI_PREQHICLR		0x114
99#define	OHCI_PREQLO		0x118
100#define	OHCI_PREQLOCLR		0x11c
101#define	OHCI_PREQUPPER		0x120
102
103#define	OHCI_SID_BUF		0x64
104#define	OHCI_SID_CNT		0x68
105#define OHCI_SID_ERR		(1U << 31)
106#define OHCI_SID_CNT_MASK	0xffc
107
108#define	OHCI_IT_STAT		0x90
109#define	OHCI_IT_STATCLR		0x94
110#define	OHCI_IT_MASK		0x98
111#define	OHCI_IT_MASKCLR		0x9c
112
113#define	OHCI_IR_STAT		0xa0
114#define	OHCI_IR_STATCLR		0xa4
115#define	OHCI_IR_MASK		0xa8
116#define	OHCI_IR_MASKCLR		0xac
117
118#define	OHCI_LNKCTL		0xe0
119#define	OHCI_LNKCTLCLR		0xe4
120
121#define	OHCI_PHYACCESS		0xec
122#define	OHCI_CYCLETIMER		0xf0
123
124#define	OHCI_DMACTL(off)	(off)
125#define	OHCI_DMACTLCLR(off)	(off + 4)
126#define	OHCI_DMACMD(off)	(off + 0xc)
127#define	OHCI_DMAMATCH(off)	(off + 0x10)
128
129#define OHCI_ATQOFF		0x180
130#define OHCI_ATQCTL		OHCI_ATQOFF
131#define OHCI_ATQCTLCLR		(OHCI_ATQOFF + 4)
132#define OHCI_ATQCMD		(OHCI_ATQOFF + 0xc)
133#define OHCI_ATQMATCH		(OHCI_ATQOFF + 0x10)
134
135#define OHCI_ATSOFF		0x1a0
136#define OHCI_ATSCTL		OHCI_ATSOFF
137#define OHCI_ATSCTLCLR		(OHCI_ATSOFF + 4)
138#define OHCI_ATSCMD		(OHCI_ATSOFF + 0xc)
139#define OHCI_ATSMATCH		(OHCI_ATSOFF + 0x10)
140
141#define OHCI_ARQOFF		0x1c0
142#define OHCI_ARQCTL		OHCI_ARQOFF
143#define OHCI_ARQCTLCLR		(OHCI_ARQOFF + 4)
144#define OHCI_ARQCMD		(OHCI_ARQOFF + 0xc)
145#define OHCI_ARQMATCH		(OHCI_ARQOFF + 0x10)
146
147#define OHCI_ARSOFF		0x1e0
148#define OHCI_ARSCTL		OHCI_ARSOFF
149#define OHCI_ARSCTLCLR		(OHCI_ARSOFF + 4)
150#define OHCI_ARSCMD		(OHCI_ARSOFF + 0xc)
151#define OHCI_ARSMATCH		(OHCI_ARSOFF + 0x10)
152
153#define OHCI_ITOFF(CH)		(0x200 + 0x10 * (CH))
154#define OHCI_ITCTL(CH)		(OHCI_ITOFF(CH))
155#define OHCI_ITCTLCLR(CH)	(OHCI_ITOFF(CH) + 4)
156#define OHCI_ITCMD(CH)		(OHCI_ITOFF(CH) + 0xc)
157
158#define OHCI_IROFF(CH)		(0x400 + 0x20 * (CH))
159#define OHCI_IRCTL(CH)		(OHCI_IROFF(CH))
160#define OHCI_IRCTLCLR(CH)	(OHCI_IROFF(CH) + 4)
161#define OHCI_IRCMD(CH)		(OHCI_IROFF(CH) + 0xc)
162#define OHCI_IRMATCH(CH)	(OHCI_IROFF(CH) + 0x10)
163