1130146Sdas/*- 2143708Sdas * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3130146Sdas * All rights reserved. 4130146Sdas * 5130146Sdas * Redistribution and use in source and binary forms, with or without 6130146Sdas * modification, are permitted provided that the following conditions 7130146Sdas * are met: 8130146Sdas * 1. Redistributions of source code must retain the above copyright 9130146Sdas * notice, this list of conditions and the following disclaimer. 10130146Sdas * 2. Redistributions in binary form must reproduce the above copyright 11130146Sdas * notice, this list of conditions and the following disclaimer in the 12130146Sdas * documentation and/or other materials provided with the distribution. 13130146Sdas * 14130146Sdas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15130146Sdas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16130146Sdas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17130146Sdas * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18130146Sdas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19130146Sdas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20130146Sdas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21130146Sdas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22130146Sdas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23130146Sdas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24130146Sdas * SUCH DAMAGE. 25130146Sdas * 26130146Sdas * $FreeBSD$ 27130146Sdas */ 28130146Sdas 29130146Sdas#ifndef _FENV_H_ 30130146Sdas#define _FENV_H_ 31130146Sdas 32130146Sdas#include <sys/_types.h> 33130146Sdas 34226218Sdas#ifndef __fenv_static 35226218Sdas#define __fenv_static static 36226218Sdas#endif 37226218Sdas 38130146Sdastypedef __uint32_t fenv_t; 39130146Sdastypedef __uint32_t fexcept_t; 40130146Sdas 41130146Sdas/* Exception flags */ 42130146Sdas#define FE_INEXACT 0x02000000 43130146Sdas#define FE_DIVBYZERO 0x04000000 44130146Sdas#define FE_UNDERFLOW 0x08000000 45130146Sdas#define FE_OVERFLOW 0x10000000 46130146Sdas#define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 47130146Sdas 48130146Sdas/* 49130146Sdas * The PowerPC architecture has extra invalid flags that indicate the 50130146Sdas * specific type of invalid operation occurred. These flags may be 51130146Sdas * tested, set, and cleared---but not masked---separately. All of 52130146Sdas * these bits are cleared when FE_INVALID is cleared, but only 53130146Sdas * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 54130146Sdas */ 55130146Sdas#define FE_VXCVI 0x00000100 /* invalid integer convert */ 56130146Sdas#define FE_VXSQRT 0x00000200 /* square root of a negative */ 57130146Sdas#define FE_VXSOFT 0x00000400 /* software-requested exception */ 58130146Sdas#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 59130146Sdas#define FE_VXIMZ 0x00100000 /* inf * 0 */ 60130146Sdas#define FE_VXZDZ 0x00200000 /* 0 / 0 */ 61130146Sdas#define FE_VXIDI 0x00400000 /* inf / inf */ 62130146Sdas#define FE_VXISI 0x00800000 /* inf - inf */ 63130146Sdas#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 64130146Sdas#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 65130146Sdas FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 66130146Sdas FE_VXSNAN | FE_INVALID) 67130146Sdas#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 68130146Sdas FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 69130146Sdas 70130146Sdas/* Rounding modes */ 71130146Sdas#define FE_TONEAREST 0x0000 72130146Sdas#define FE_TOWARDZERO 0x0001 73130146Sdas#define FE_UPWARD 0x0002 74130146Sdas#define FE_DOWNWARD 0x0003 75130146Sdas#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 76130146Sdas FE_UPWARD | FE_TOWARDZERO) 77130146Sdas 78130146Sdas__BEGIN_DECLS 79130146Sdas 80130146Sdas/* Default floating-point environment */ 81130146Sdasextern const fenv_t __fe_dfl_env; 82130146Sdas#define FE_DFL_ENV (&__fe_dfl_env) 83130146Sdas 84130146Sdas/* We need to be able to map status flag positions to mask flag positions */ 85130146Sdas#define _FPUSW_SHIFT 22 86130146Sdas#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 87130146Sdas FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 88130146Sdas 89176530Sraj#ifndef _SOFT_FLOAT 90140219Sdas#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 91130146Sdas#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 92176530Sraj#else 93176530Sraj#define __mffs(__env) 94176530Sraj#define __mtfsf(__env) 95176530Sraj#endif 96130146Sdas 97130146Sdasunion __fpscr { 98130146Sdas double __d; 99130146Sdas struct { 100296111Snwhitehorn#if _BYTE_ORDER == _LITTLE_ENDIAN 101296111Snwhitehorn fenv_t __reg; 102130146Sdas __uint32_t __junk; 103296111Snwhitehorn#else 104296111Snwhitehorn __uint32_t __junk; 105130146Sdas fenv_t __reg; 106296111Snwhitehorn#endif 107130146Sdas } __bits; 108130146Sdas}; 109130146Sdas 110226218Sdas__fenv_static inline int 111130146Sdasfeclearexcept(int __excepts) 112130146Sdas{ 113130146Sdas union __fpscr __r; 114130146Sdas 115130146Sdas if (__excepts & FE_INVALID) 116130146Sdas __excepts |= FE_ALL_INVALID; 117130146Sdas __mffs(&__r.__d); 118130146Sdas __r.__bits.__reg &= ~__excepts; 119130146Sdas __mtfsf(__r.__d); 120130146Sdas return (0); 121130146Sdas} 122130146Sdas 123226218Sdas__fenv_static inline int 124130146Sdasfegetexceptflag(fexcept_t *__flagp, int __excepts) 125130146Sdas{ 126130146Sdas union __fpscr __r; 127130146Sdas 128130146Sdas __mffs(&__r.__d); 129130146Sdas *__flagp = __r.__bits.__reg & __excepts; 130130146Sdas return (0); 131130146Sdas} 132130146Sdas 133226218Sdas__fenv_static inline int 134130146Sdasfesetexceptflag(const fexcept_t *__flagp, int __excepts) 135130146Sdas{ 136130146Sdas union __fpscr __r; 137130146Sdas 138130146Sdas if (__excepts & FE_INVALID) 139130146Sdas __excepts |= FE_ALL_EXCEPT; 140130146Sdas __mffs(&__r.__d); 141130146Sdas __r.__bits.__reg &= ~__excepts; 142130146Sdas __r.__bits.__reg |= *__flagp & __excepts; 143130146Sdas __mtfsf(__r.__d); 144130146Sdas return (0); 145130146Sdas} 146130146Sdas 147226218Sdas__fenv_static inline int 148130146Sdasferaiseexcept(int __excepts) 149130146Sdas{ 150130146Sdas union __fpscr __r; 151130146Sdas 152130146Sdas if (__excepts & FE_INVALID) 153130146Sdas __excepts |= FE_VXSOFT; 154130146Sdas __mffs(&__r.__d); 155130146Sdas __r.__bits.__reg |= __excepts; 156130146Sdas __mtfsf(__r.__d); 157130146Sdas return (0); 158130146Sdas} 159130146Sdas 160226218Sdas__fenv_static inline int 161130146Sdasfetestexcept(int __excepts) 162130146Sdas{ 163130146Sdas union __fpscr __r; 164130146Sdas 165130146Sdas __mffs(&__r.__d); 166130146Sdas return (__r.__bits.__reg & __excepts); 167130146Sdas} 168130146Sdas 169226218Sdas__fenv_static inline int 170130146Sdasfegetround(void) 171130146Sdas{ 172130146Sdas union __fpscr __r; 173130146Sdas 174130146Sdas __mffs(&__r.__d); 175130146Sdas return (__r.__bits.__reg & _ROUND_MASK); 176130146Sdas} 177130146Sdas 178226218Sdas__fenv_static inline int 179130146Sdasfesetround(int __round) 180130146Sdas{ 181130146Sdas union __fpscr __r; 182130146Sdas 183130146Sdas if (__round & ~_ROUND_MASK) 184130146Sdas return (-1); 185130146Sdas __mffs(&__r.__d); 186130146Sdas __r.__bits.__reg &= ~_ROUND_MASK; 187130146Sdas __r.__bits.__reg |= __round; 188130146Sdas __mtfsf(__r.__d); 189130146Sdas return (0); 190130146Sdas} 191130146Sdas 192226218Sdas__fenv_static inline int 193130146Sdasfegetenv(fenv_t *__envp) 194130146Sdas{ 195130146Sdas union __fpscr __r; 196130146Sdas 197130146Sdas __mffs(&__r.__d); 198130146Sdas *__envp = __r.__bits.__reg; 199130146Sdas return (0); 200130146Sdas} 201130146Sdas 202226218Sdas__fenv_static inline int 203130146Sdasfeholdexcept(fenv_t *__envp) 204130146Sdas{ 205130146Sdas union __fpscr __r; 206130146Sdas 207130146Sdas __mffs(&__r.__d); 208130146Sdas *__envp = __r.__d; 209130146Sdas __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 210130146Sdas __mtfsf(__r.__d); 211130146Sdas return (0); 212130146Sdas} 213130146Sdas 214226218Sdas__fenv_static inline int 215130146Sdasfesetenv(const fenv_t *__envp) 216130146Sdas{ 217130146Sdas union __fpscr __r; 218130146Sdas 219130146Sdas __r.__bits.__reg = *__envp; 220130146Sdas __mtfsf(__r.__d); 221130146Sdas return (0); 222130146Sdas} 223130146Sdas 224226218Sdas__fenv_static inline int 225130146Sdasfeupdateenv(const fenv_t *__envp) 226130146Sdas{ 227130146Sdas union __fpscr __r; 228130146Sdas 229130146Sdas __mffs(&__r.__d); 230130146Sdas __r.__bits.__reg &= FE_ALL_EXCEPT; 231130146Sdas __r.__bits.__reg |= *__envp; 232130146Sdas __mtfsf(__r.__d); 233130146Sdas return (0); 234130146Sdas} 235130146Sdas 236130146Sdas#if __BSD_VISIBLE 237130146Sdas 238226218Sdas/* We currently provide no external definitions of the functions below. */ 239226218Sdas 240226218Sdasstatic inline int 241143708Sdasfeenableexcept(int __mask) 242130146Sdas{ 243130146Sdas union __fpscr __r; 244130146Sdas fenv_t __oldmask; 245130146Sdas 246130146Sdas __mffs(&__r.__d); 247130146Sdas __oldmask = __r.__bits.__reg; 248143708Sdas __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 249130146Sdas __mtfsf(__r.__d); 250130146Sdas return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 251130146Sdas} 252130146Sdas 253226218Sdasstatic inline int 254143708Sdasfedisableexcept(int __mask) 255130146Sdas{ 256130146Sdas union __fpscr __r; 257143708Sdas fenv_t __oldmask; 258130146Sdas 259130146Sdas __mffs(&__r.__d); 260143708Sdas __oldmask = __r.__bits.__reg; 261143708Sdas __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 262143708Sdas __mtfsf(__r.__d); 263143708Sdas return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 264143708Sdas} 265143708Sdas 266226218Sdasstatic inline int 267143708Sdasfegetexcept(void) 268143708Sdas{ 269143708Sdas union __fpscr __r; 270143708Sdas 271143708Sdas __mffs(&__r.__d); 272130146Sdas return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 273130146Sdas} 274130146Sdas 275130146Sdas#endif /* __BSD_VISIBLE */ 276130146Sdas 277130146Sdas__END_DECLS 278130146Sdas 279130146Sdas#endif /* !_FENV_H_ */ 280