libpmc.c revision 283112
1/*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 283112 2015-05-19 15:25:47Z br $"); 29 30#include <sys/types.h> 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/pmc.h> 34#include <sys/syscall.h> 35 36#include <ctype.h> 37#include <errno.h> 38#include <fcntl.h> 39#include <pmc.h> 40#include <stdio.h> 41#include <stdlib.h> 42#include <string.h> 43#include <strings.h> 44#include <unistd.h> 45 46#include "libpmcinternal.h" 47 48/* Function prototypes */ 49#if defined(__i386__) 50static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52#endif 53#if defined(__amd64__) || defined(__i386__) 54static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66#endif 67#if defined(__i386__) 68static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72#endif 73#if defined(__amd64__) || defined(__i386__) 74static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76#endif 77#if defined(__arm__) 78#if defined(__XSCALE__) 79static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 80 struct pmc_op_pmcallocate *_pmc_config); 81#endif 82static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84#endif 85#if defined(__aarch64__) 86static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 87 struct pmc_op_pmcallocate *_pmc_config); 88#endif 89#if defined(__mips__) 90static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 91 struct pmc_op_pmcallocate *_pmc_config); 92#endif /* __mips__ */ 93static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 94 struct pmc_op_pmcallocate *_pmc_config); 95 96#if defined(__powerpc__) 97static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 98 struct pmc_op_pmcallocate *_pmc_config); 99#endif /* __powerpc__ */ 100 101#define PMC_CALL(cmd, params) \ 102 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 103 104/* 105 * Event aliases provide a way for the user to ask for generic events 106 * like "cache-misses", or "instructions-retired". These aliases are 107 * mapped to the appropriate canonical event descriptions using a 108 * lookup table. 109 */ 110struct pmc_event_alias { 111 const char *pm_alias; 112 const char *pm_spec; 113}; 114 115static const struct pmc_event_alias *pmc_mdep_event_aliases; 116 117/* 118 * The pmc_event_descr structure maps symbolic names known to the user 119 * to integer codes used by the PMC KLD. 120 */ 121struct pmc_event_descr { 122 const char *pm_ev_name; 123 enum pmc_event pm_ev_code; 124}; 125 126/* 127 * The pmc_class_descr structure maps class name prefixes for 128 * event names to event tables and other PMC class data. 129 */ 130struct pmc_class_descr { 131 const char *pm_evc_name; 132 size_t pm_evc_name_size; 133 enum pmc_class pm_evc_class; 134 const struct pmc_event_descr *pm_evc_event_table; 135 size_t pm_evc_event_table_size; 136 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 137 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 138}; 139 140#define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 141#define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 142 143#undef __PMC_EV 144#define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 145 146/* 147 * PMC_CLASSDEP_TABLE(NAME, CLASS) 148 * 149 * Define a table mapping event names and aliases to HWPMC event IDs. 150 */ 151#define PMC_CLASSDEP_TABLE(N, C) \ 152 static const struct pmc_event_descr N##_event_table[] = \ 153 { \ 154 __PMC_EV_##C() \ 155 } 156 157PMC_CLASSDEP_TABLE(iaf, IAF); 158PMC_CLASSDEP_TABLE(k7, K7); 159PMC_CLASSDEP_TABLE(k8, K8); 160PMC_CLASSDEP_TABLE(p4, P4); 161PMC_CLASSDEP_TABLE(p5, P5); 162PMC_CLASSDEP_TABLE(p6, P6); 163PMC_CLASSDEP_TABLE(xscale, XSCALE); 164PMC_CLASSDEP_TABLE(armv7, ARMV7); 165PMC_CLASSDEP_TABLE(armv8, ARMV8); 166PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 167PMC_CLASSDEP_TABLE(mips74k, MIPS74K); 168PMC_CLASSDEP_TABLE(octeon, OCTEON); 169PMC_CLASSDEP_TABLE(ucf, UCF); 170PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 171PMC_CLASSDEP_TABLE(ppc970, PPC970); 172PMC_CLASSDEP_TABLE(e500, E500); 173 174static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 175 176#undef __PMC_EV_ALIAS 177#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 178 179static const struct pmc_event_descr atom_event_table[] = 180{ 181 __PMC_EV_ALIAS_ATOM() 182}; 183 184static const struct pmc_event_descr atom_silvermont_event_table[] = 185{ 186 __PMC_EV_ALIAS_ATOM_SILVERMONT() 187}; 188 189static const struct pmc_event_descr core_event_table[] = 190{ 191 __PMC_EV_ALIAS_CORE() 192}; 193 194 195static const struct pmc_event_descr core2_event_table[] = 196{ 197 __PMC_EV_ALIAS_CORE2() 198}; 199 200static const struct pmc_event_descr corei7_event_table[] = 201{ 202 __PMC_EV_ALIAS_COREI7() 203}; 204 205static const struct pmc_event_descr nehalem_ex_event_table[] = 206{ 207 __PMC_EV_ALIAS_COREI7() 208}; 209 210static const struct pmc_event_descr haswell_event_table[] = 211{ 212 __PMC_EV_ALIAS_HASWELL() 213}; 214 215static const struct pmc_event_descr haswell_xeon_event_table[] = 216{ 217 __PMC_EV_ALIAS_HASWELL_XEON() 218}; 219 220 221static const struct pmc_event_descr ivybridge_event_table[] = 222{ 223 __PMC_EV_ALIAS_IVYBRIDGE() 224}; 225 226static const struct pmc_event_descr ivybridge_xeon_event_table[] = 227{ 228 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 229}; 230 231static const struct pmc_event_descr sandybridge_event_table[] = 232{ 233 __PMC_EV_ALIAS_SANDYBRIDGE() 234}; 235 236static const struct pmc_event_descr sandybridge_xeon_event_table[] = 237{ 238 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 239}; 240 241static const struct pmc_event_descr westmere_event_table[] = 242{ 243 __PMC_EV_ALIAS_WESTMERE() 244}; 245 246static const struct pmc_event_descr westmere_ex_event_table[] = 247{ 248 __PMC_EV_ALIAS_WESTMERE() 249}; 250 251static const struct pmc_event_descr corei7uc_event_table[] = 252{ 253 __PMC_EV_ALIAS_COREI7UC() 254}; 255 256static const struct pmc_event_descr haswelluc_event_table[] = 257{ 258 __PMC_EV_ALIAS_HASWELLUC() 259}; 260 261static const struct pmc_event_descr sandybridgeuc_event_table[] = 262{ 263 __PMC_EV_ALIAS_SANDYBRIDGEUC() 264}; 265 266static const struct pmc_event_descr westmereuc_event_table[] = 267{ 268 __PMC_EV_ALIAS_WESTMEREUC() 269}; 270 271static const struct pmc_event_descr cortex_a53_event_table[] = 272{ 273 __PMC_EV_ALIAS_ARMV8_CORTEX_A53() 274}; 275 276static const struct pmc_event_descr cortex_a57_event_table[] = 277{ 278 __PMC_EV_ALIAS_ARMV8_CORTEX_A57() 279}; 280 281/* 282 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 283 * 284 * Map a CPU to the PMC classes it supports. 285 */ 286#define PMC_MDEP_TABLE(N,C,...) \ 287 static const enum pmc_class N##_pmc_classes[] = { \ 288 PMC_CLASS_##C, __VA_ARGS__ \ 289 } 290 291PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 292PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 293PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 294PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 295PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 296PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 297PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 298PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 299PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 300PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 301PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 302PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 303PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 304PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 305PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 306PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 307PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 308PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 309PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 310PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 311PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); 312PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 313PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); 314PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 315PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); 316PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 317PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); 318PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); 319PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); 320PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 321 322static const struct pmc_event_descr tsc_event_table[] = 323{ 324 __PMC_EV_TSC() 325}; 326 327#undef PMC_CLASS_TABLE_DESC 328#define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 329static const struct pmc_class_descr NAME##_class_table_descr = \ 330 { \ 331 .pm_evc_name = #CLASS "-", \ 332 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 333 .pm_evc_class = PMC_CLASS_##CLASS , \ 334 .pm_evc_event_table = EVENTS##_event_table , \ 335 .pm_evc_event_table_size = \ 336 PMC_EVENT_TABLE_SIZE(EVENTS), \ 337 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 338 } 339 340#if defined(__i386__) || defined(__amd64__) 341PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 342PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 343PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 344PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 345PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 346PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 347PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap); 348PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 349PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap); 350PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 351PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 352PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 353PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 354PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 355PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap); 356PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 357PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 358PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 359PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 360PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 361#endif 362#if defined(__i386__) 363PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 364#endif 365#if defined(__i386__) || defined(__amd64__) 366PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 367PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 368#endif 369#if defined(__i386__) 370PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 371PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 372#endif 373#if defined(__i386__) || defined(__amd64__) 374PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 375#endif 376#if defined(__arm__) 377#if defined(__XSCALE__) 378PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 379#endif 380PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); 381#endif 382#if defined(__aarch64__) 383PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); 384PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); 385#endif 386#if defined(__mips__) 387PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 388PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); 389PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 390#endif /* __mips__ */ 391#if defined(__powerpc__) 392PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 393PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 394PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc); 395#endif 396 397static struct pmc_class_descr soft_class_table_descr = 398{ 399 .pm_evc_name = "SOFT-", 400 .pm_evc_name_size = sizeof("SOFT-") - 1, 401 .pm_evc_class = PMC_CLASS_SOFT, 402 .pm_evc_event_table = NULL, 403 .pm_evc_event_table_size = 0, 404 .pm_evc_allocate_pmc = soft_allocate_pmc 405}; 406 407#undef PMC_CLASS_TABLE_DESC 408 409static const struct pmc_class_descr **pmc_class_table; 410#define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 411 412static const enum pmc_class *pmc_mdep_class_list; 413static size_t pmc_mdep_class_list_size; 414 415/* 416 * Mapping tables, mapping enumeration values to human readable 417 * strings. 418 */ 419 420static const char * pmc_capability_names[] = { 421#undef __PMC_CAP 422#define __PMC_CAP(N,V,D) #N , 423 __PMC_CAPS() 424}; 425 426static const char * pmc_class_names[] = { 427#undef __PMC_CLASS 428#define __PMC_CLASS(C) #C , 429 __PMC_CLASSES() 430}; 431 432struct pmc_cputype_map { 433 enum pmc_cputype pm_cputype; 434 const char *pm_name; 435}; 436 437static const struct pmc_cputype_map pmc_cputype_names[] = { 438#undef __PMC_CPU 439#define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 440 __PMC_CPUS() 441}; 442 443static const char * pmc_disposition_names[] = { 444#undef __PMC_DISP 445#define __PMC_DISP(D) #D , 446 __PMC_DISPOSITIONS() 447}; 448 449static const char * pmc_mode_names[] = { 450#undef __PMC_MODE 451#define __PMC_MODE(M,N) #M , 452 __PMC_MODES() 453}; 454 455static const char * pmc_state_names[] = { 456#undef __PMC_STATE 457#define __PMC_STATE(S) #S , 458 __PMC_STATES() 459}; 460 461/* 462 * Filled in by pmc_init(). 463 */ 464static int pmc_syscall = -1; 465static struct pmc_cpuinfo cpu_info; 466static struct pmc_op_getdyneventinfo soft_event_info; 467 468/* Event masks for events */ 469struct pmc_masks { 470 const char *pm_name; 471 const uint64_t pm_value; 472}; 473#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 474#define NULLMASK { .pm_name = NULL } 475 476#if defined(__amd64__) || defined(__i386__) 477static int 478pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 479{ 480 const struct pmc_masks *pm; 481 char *q, *r; 482 int c; 483 484 if (pmask == NULL) /* no mask keywords */ 485 return (-1); 486 q = strchr(p, '='); /* skip '=' */ 487 if (*++q == '\0') /* no more data */ 488 return (-1); 489 c = 0; /* count of mask keywords seen */ 490 while ((r = strsep(&q, "+")) != NULL) { 491 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 492 pm++) 493 ; 494 if (pm->pm_name == NULL) /* not found */ 495 return (-1); 496 *evmask |= pm->pm_value; 497 c++; 498 } 499 return (c); 500} 501#endif 502 503#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 504#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 505#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 506 507#if defined(__i386__) 508 509/* 510 * AMD K7 (Athlon) CPUs. 511 */ 512 513static struct pmc_event_alias k7_aliases[] = { 514 EV_ALIAS("branches", "k7-retired-branches"), 515 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 516 EV_ALIAS("cycles", "tsc"), 517 EV_ALIAS("dc-misses", "k7-dc-misses"), 518 EV_ALIAS("ic-misses", "k7-ic-misses"), 519 EV_ALIAS("instructions", "k7-retired-instructions"), 520 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 521 EV_ALIAS(NULL, NULL) 522}; 523 524#define K7_KW_COUNT "count" 525#define K7_KW_EDGE "edge" 526#define K7_KW_INV "inv" 527#define K7_KW_OS "os" 528#define K7_KW_UNITMASK "unitmask" 529#define K7_KW_USR "usr" 530 531static int 532k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 533 struct pmc_op_pmcallocate *pmc_config) 534{ 535 char *e, *p, *q; 536 int c, has_unitmask; 537 uint32_t count, unitmask; 538 539 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 540 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 541 542 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 543 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 544 pe == PMC_EV_K7_DC_WRITEBACKS) { 545 has_unitmask = 1; 546 unitmask = AMD_PMC_UNITMASK_MOESI; 547 } else 548 unitmask = has_unitmask = 0; 549 550 while ((p = strsep(&ctrspec, ",")) != NULL) { 551 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 552 q = strchr(p, '='); 553 if (*++q == '\0') /* skip '=' */ 554 return (-1); 555 556 count = strtol(q, &e, 0); 557 if (e == q || *e != '\0') 558 return (-1); 559 560 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 561 pmc_config->pm_md.pm_amd.pm_amd_config |= 562 AMD_PMC_TO_COUNTER(count); 563 564 } else if (KWMATCH(p, K7_KW_EDGE)) { 565 pmc_config->pm_caps |= PMC_CAP_EDGE; 566 } else if (KWMATCH(p, K7_KW_INV)) { 567 pmc_config->pm_caps |= PMC_CAP_INVERT; 568 } else if (KWMATCH(p, K7_KW_OS)) { 569 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 570 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 571 if (has_unitmask == 0) 572 return (-1); 573 unitmask = 0; 574 q = strchr(p, '='); 575 if (*++q == '\0') /* skip '=' */ 576 return (-1); 577 578 while ((c = tolower(*q++)) != 0) 579 if (c == 'm') 580 unitmask |= AMD_PMC_UNITMASK_M; 581 else if (c == 'o') 582 unitmask |= AMD_PMC_UNITMASK_O; 583 else if (c == 'e') 584 unitmask |= AMD_PMC_UNITMASK_E; 585 else if (c == 's') 586 unitmask |= AMD_PMC_UNITMASK_S; 587 else if (c == 'i') 588 unitmask |= AMD_PMC_UNITMASK_I; 589 else if (c == '+') 590 continue; 591 else 592 return (-1); 593 594 if (unitmask == 0) 595 return (-1); 596 597 } else if (KWMATCH(p, K7_KW_USR)) { 598 pmc_config->pm_caps |= PMC_CAP_USER; 599 } else 600 return (-1); 601 } 602 603 if (has_unitmask) { 604 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 605 pmc_config->pm_md.pm_amd.pm_amd_config |= 606 AMD_PMC_TO_UNITMASK(unitmask); 607 } 608 609 return (0); 610 611} 612 613#endif 614 615#if defined(__amd64__) || defined(__i386__) 616 617/* 618 * Intel Core (Family 6, Model E) PMCs. 619 */ 620 621static struct pmc_event_alias core_aliases[] = { 622 EV_ALIAS("branches", "iap-br-instr-ret"), 623 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 624 EV_ALIAS("cycles", "tsc-tsc"), 625 EV_ALIAS("ic-misses", "iap-icache-misses"), 626 EV_ALIAS("instructions", "iap-instr-ret"), 627 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 628 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 629 EV_ALIAS(NULL, NULL) 630}; 631 632/* 633 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 634 * and Atom (Family 6, model 1CH) PMCs. 635 * 636 * We map aliases to events on the fixed-function counters if these 637 * are present. Note that not all CPUs in this family contain fixed-function 638 * counters. 639 */ 640 641static struct pmc_event_alias core2_aliases[] = { 642 EV_ALIAS("branches", "iap-br-inst-retired.any"), 643 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 644 EV_ALIAS("cycles", "tsc-tsc"), 645 EV_ALIAS("ic-misses", "iap-l1i-misses"), 646 EV_ALIAS("instructions", "iaf-instr-retired.any"), 647 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 648 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 649 EV_ALIAS(NULL, NULL) 650}; 651 652static struct pmc_event_alias core2_aliases_without_iaf[] = { 653 EV_ALIAS("branches", "iap-br-inst-retired.any"), 654 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 655 EV_ALIAS("cycles", "tsc-tsc"), 656 EV_ALIAS("ic-misses", "iap-l1i-misses"), 657 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 658 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 659 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 660 EV_ALIAS(NULL, NULL) 661}; 662 663#define atom_aliases core2_aliases 664#define atom_aliases_without_iaf core2_aliases_without_iaf 665#define atom_silvermont_aliases core2_aliases 666#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 667#define corei7_aliases core2_aliases 668#define corei7_aliases_without_iaf core2_aliases_without_iaf 669#define nehalem_ex_aliases core2_aliases 670#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf 671#define haswell_aliases core2_aliases 672#define haswell_aliases_without_iaf core2_aliases_without_iaf 673#define haswell_xeon_aliases core2_aliases 674#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf 675#define ivybridge_aliases core2_aliases 676#define ivybridge_aliases_without_iaf core2_aliases_without_iaf 677#define ivybridge_xeon_aliases core2_aliases 678#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 679#define sandybridge_aliases core2_aliases 680#define sandybridge_aliases_without_iaf core2_aliases_without_iaf 681#define sandybridge_xeon_aliases core2_aliases 682#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 683#define westmere_aliases core2_aliases 684#define westmere_aliases_without_iaf core2_aliases_without_iaf 685#define westmere_ex_aliases core2_aliases 686#define westmere_ex_aliases_without_iaf core2_aliases_without_iaf 687 688#define IAF_KW_OS "os" 689#define IAF_KW_USR "usr" 690#define IAF_KW_ANYTHREAD "anythread" 691 692/* 693 * Parse an event specifier for Intel fixed function counters. 694 */ 695static int 696iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 697 struct pmc_op_pmcallocate *pmc_config) 698{ 699 char *p; 700 701 (void) pe; 702 703 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 704 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 705 706 while ((p = strsep(&ctrspec, ",")) != NULL) { 707 if (KWMATCH(p, IAF_KW_OS)) 708 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 709 else if (KWMATCH(p, IAF_KW_USR)) 710 pmc_config->pm_caps |= PMC_CAP_USER; 711 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 712 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 713 else 714 return (-1); 715 } 716 717 return (0); 718} 719 720/* 721 * Core/Core2 support. 722 */ 723 724#define IAP_KW_AGENT "agent" 725#define IAP_KW_ANYTHREAD "anythread" 726#define IAP_KW_CACHESTATE "cachestate" 727#define IAP_KW_CMASK "cmask" 728#define IAP_KW_CORE "core" 729#define IAP_KW_EDGE "edge" 730#define IAP_KW_INV "inv" 731#define IAP_KW_OS "os" 732#define IAP_KW_PREFETCH "prefetch" 733#define IAP_KW_SNOOPRESPONSE "snoopresponse" 734#define IAP_KW_SNOOPTYPE "snooptype" 735#define IAP_KW_TRANSITION "trans" 736#define IAP_KW_USR "usr" 737#define IAP_KW_RSP "rsp" 738 739static struct pmc_masks iap_core_mask[] = { 740 PMCMASK(all, (0x3 << 14)), 741 PMCMASK(this, (0x1 << 14)), 742 NULLMASK 743}; 744 745static struct pmc_masks iap_agent_mask[] = { 746 PMCMASK(this, 0), 747 PMCMASK(any, (0x1 << 13)), 748 NULLMASK 749}; 750 751static struct pmc_masks iap_prefetch_mask[] = { 752 PMCMASK(both, (0x3 << 12)), 753 PMCMASK(only, (0x1 << 12)), 754 PMCMASK(exclude, 0), 755 NULLMASK 756}; 757 758static struct pmc_masks iap_cachestate_mask[] = { 759 PMCMASK(i, (1 << 8)), 760 PMCMASK(s, (1 << 9)), 761 PMCMASK(e, (1 << 10)), 762 PMCMASK(m, (1 << 11)), 763 NULLMASK 764}; 765 766static struct pmc_masks iap_snoopresponse_mask[] = { 767 PMCMASK(clean, (1 << 8)), 768 PMCMASK(hit, (1 << 9)), 769 PMCMASK(hitm, (1 << 11)), 770 NULLMASK 771}; 772 773static struct pmc_masks iap_snooptype_mask[] = { 774 PMCMASK(cmp2s, (1 << 8)), 775 PMCMASK(cmp2i, (1 << 9)), 776 NULLMASK 777}; 778 779static struct pmc_masks iap_transition_mask[] = { 780 PMCMASK(any, 0x00), 781 PMCMASK(frequency, 0x10), 782 NULLMASK 783}; 784 785static struct pmc_masks iap_rsp_mask_i7_wm[] = { 786 PMCMASK(DMND_DATA_RD, (1 << 0)), 787 PMCMASK(DMND_RFO, (1 << 1)), 788 PMCMASK(DMND_IFETCH, (1 << 2)), 789 PMCMASK(WB, (1 << 3)), 790 PMCMASK(PF_DATA_RD, (1 << 4)), 791 PMCMASK(PF_RFO, (1 << 5)), 792 PMCMASK(PF_IFETCH, (1 << 6)), 793 PMCMASK(OTHER, (1 << 7)), 794 PMCMASK(UNCORE_HIT, (1 << 8)), 795 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 796 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 797 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 798 PMCMASK(REMOTE_DRAM, (1 << 13)), 799 PMCMASK(LOCAL_DRAM, (1 << 14)), 800 PMCMASK(NON_DRAM, (1 << 15)), 801 NULLMASK 802}; 803 804static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 805 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 806 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 807 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 808 PMCMASK(REQ_WB, (1ULL << 3)), 809 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 810 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 811 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 812 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 813 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 814 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 815 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 816 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 817 PMCMASK(REQ_OTHER, (1ULL << 15)), 818 PMCMASK(RES_ANY, (1ULL << 16)), 819 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 820 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 821 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 822 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 823 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 824 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 825 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 826 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 827 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 828 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 829 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 830 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 831 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 832 NULLMASK 833}; 834 835static struct pmc_masks iap_rsp_mask_haswell[] = { 836 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 837 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 838 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 839 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 840 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 841 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 842 PMCMASK(REQ_OTHER, (1ULL << 15)), 843 PMCMASK(RES_ANY, (1ULL << 16)), 844 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 845 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 846 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 847 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 848 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 849 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 850 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 851 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 852 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 853 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 854 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 855 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 856 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 857 NULLMASK 858}; 859 860static int 861iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 862 struct pmc_op_pmcallocate *pmc_config) 863{ 864 char *e, *p, *q; 865 uint64_t cachestate, evmask, rsp; 866 int count, n; 867 868 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 869 PMC_CAP_QUALIFIER); 870 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 871 872 cachestate = evmask = rsp = 0; 873 874 /* Parse additional modifiers if present */ 875 while ((p = strsep(&ctrspec, ",")) != NULL) { 876 877 n = 0; 878 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 879 q = strchr(p, '='); 880 if (*++q == '\0') /* skip '=' */ 881 return (-1); 882 count = strtol(q, &e, 0); 883 if (e == q || *e != '\0') 884 return (-1); 885 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 886 pmc_config->pm_md.pm_iap.pm_iap_config |= 887 IAP_CMASK(count); 888 } else if (KWMATCH(p, IAP_KW_EDGE)) { 889 pmc_config->pm_caps |= PMC_CAP_EDGE; 890 } else if (KWMATCH(p, IAP_KW_INV)) { 891 pmc_config->pm_caps |= PMC_CAP_INVERT; 892 } else if (KWMATCH(p, IAP_KW_OS)) { 893 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 894 } else if (KWMATCH(p, IAP_KW_USR)) { 895 pmc_config->pm_caps |= PMC_CAP_USER; 896 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 897 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 898 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 899 n = pmc_parse_mask(iap_core_mask, p, &evmask); 900 if (n != 1) 901 return (-1); 902 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 903 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 904 if (n != 1) 905 return (-1); 906 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 907 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 908 if (n != 1) 909 return (-1); 910 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 911 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 912 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 913 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 914 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 915 if (n != 1) 916 return (-1); 917 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 918 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 919 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 920 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 921 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 922 n = pmc_parse_mask(iap_snoopresponse_mask, p, 923 &evmask); 924 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 925 n = pmc_parse_mask(iap_snooptype_mask, p, 926 &evmask); 927 } else 928 return (-1); 929 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 930 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE || 931 cpu_info.pm_cputype == PMC_CPU_INTEL_NEHALEM_EX || 932 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE_EX) { 933 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 934 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 935 } else 936 return (-1); 937 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 938 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 939 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 940 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 941 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 942 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 943 } else 944 return (-1); 945 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL || 946 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) { 947 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 948 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 949 } else 950 return (-1); 951 } else 952 return (-1); 953 954 if (n < 0) /* Parsing failed. */ 955 return (-1); 956 } 957 958 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 959 960 /* 961 * If the event requires a 'cachestate' qualifier but was not 962 * specified by the user, use a sensible default. 963 */ 964 switch (pe) { 965 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 966 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 967 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 968 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 969 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 970 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 971 case PMC_EV_IAP_EVENT_32H: /* Core */ 972 case PMC_EV_IAP_EVENT_40H: /* Core */ 973 case PMC_EV_IAP_EVENT_41H: /* Core */ 974 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 975 if (cachestate == 0) 976 cachestate = (0xF << 8); 977 break; 978 case PMC_EV_IAP_EVENT_77H: /* Atom */ 979 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 980 * Atom processor 981 */ 982 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 983 cachestate = (0xF << 8); 984 break; 985 default: 986 break; 987 } 988 989 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 990 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 991 992 return (0); 993} 994 995/* 996 * Intel Uncore. 997 */ 998 999static int 1000ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 1001 struct pmc_op_pmcallocate *pmc_config) 1002{ 1003 (void) pe; 1004 (void) ctrspec; 1005 1006 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1007 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 1008 1009 return (0); 1010} 1011 1012#define UCP_KW_CMASK "cmask" 1013#define UCP_KW_EDGE "edge" 1014#define UCP_KW_INV "inv" 1015 1016static int 1017ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 1018 struct pmc_op_pmcallocate *pmc_config) 1019{ 1020 char *e, *p, *q; 1021 int count, n; 1022 1023 (void) pe; 1024 1025 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 1026 PMC_CAP_QUALIFIER); 1027 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 1028 1029 /* Parse additional modifiers if present */ 1030 while ((p = strsep(&ctrspec, ",")) != NULL) { 1031 1032 n = 0; 1033 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 1034 q = strchr(p, '='); 1035 if (*++q == '\0') /* skip '=' */ 1036 return (-1); 1037 count = strtol(q, &e, 0); 1038 if (e == q || *e != '\0') 1039 return (-1); 1040 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1041 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 1042 UCP_CMASK(count); 1043 } else if (KWMATCH(p, UCP_KW_EDGE)) { 1044 pmc_config->pm_caps |= PMC_CAP_EDGE; 1045 } else if (KWMATCH(p, UCP_KW_INV)) { 1046 pmc_config->pm_caps |= PMC_CAP_INVERT; 1047 } else 1048 return (-1); 1049 1050 if (n < 0) /* Parsing failed. */ 1051 return (-1); 1052 } 1053 1054 return (0); 1055} 1056 1057/* 1058 * AMD K8 PMCs. 1059 * 1060 * These are very similar to AMD K7 PMCs, but support more kinds of 1061 * events. 1062 */ 1063 1064static struct pmc_event_alias k8_aliases[] = { 1065 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 1066 EV_ALIAS("branch-mispredicts", 1067 "k8-fr-retired-taken-branches-mispredicted"), 1068 EV_ALIAS("cycles", "tsc"), 1069 EV_ALIAS("dc-misses", "k8-dc-miss"), 1070 EV_ALIAS("ic-misses", "k8-ic-miss"), 1071 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1072 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1073 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1074 EV_ALIAS(NULL, NULL) 1075}; 1076 1077#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1078 1079/* 1080 * Parsing tables 1081 */ 1082 1083/* fp dispatched fpu ops */ 1084static const struct pmc_masks k8_mask_fdfo[] = { 1085 __K8MASK(add-pipe-excluding-junk-ops, 0), 1086 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1087 __K8MASK(store-pipe-excluding-junk-ops, 2), 1088 __K8MASK(add-pipe-junk-ops, 3), 1089 __K8MASK(multiply-pipe-junk-ops, 4), 1090 __K8MASK(store-pipe-junk-ops, 5), 1091 NULLMASK 1092}; 1093 1094/* ls segment register loads */ 1095static const struct pmc_masks k8_mask_lsrl[] = { 1096 __K8MASK(es, 0), 1097 __K8MASK(cs, 1), 1098 __K8MASK(ss, 2), 1099 __K8MASK(ds, 3), 1100 __K8MASK(fs, 4), 1101 __K8MASK(gs, 5), 1102 __K8MASK(hs, 6), 1103 NULLMASK 1104}; 1105 1106/* ls locked operation */ 1107static const struct pmc_masks k8_mask_llo[] = { 1108 __K8MASK(locked-instructions, 0), 1109 __K8MASK(cycles-in-request, 1), 1110 __K8MASK(cycles-to-complete, 2), 1111 NULLMASK 1112}; 1113 1114/* dc refill from {l2,system} and dc copyback */ 1115static const struct pmc_masks k8_mask_dc[] = { 1116 __K8MASK(invalid, 0), 1117 __K8MASK(shared, 1), 1118 __K8MASK(exclusive, 2), 1119 __K8MASK(owner, 3), 1120 __K8MASK(modified, 4), 1121 NULLMASK 1122}; 1123 1124/* dc one bit ecc error */ 1125static const struct pmc_masks k8_mask_dobee[] = { 1126 __K8MASK(scrubber, 0), 1127 __K8MASK(piggyback, 1), 1128 NULLMASK 1129}; 1130 1131/* dc dispatched prefetch instructions */ 1132static const struct pmc_masks k8_mask_ddpi[] = { 1133 __K8MASK(load, 0), 1134 __K8MASK(store, 1), 1135 __K8MASK(nta, 2), 1136 NULLMASK 1137}; 1138 1139/* dc dcache accesses by locks */ 1140static const struct pmc_masks k8_mask_dabl[] = { 1141 __K8MASK(accesses, 0), 1142 __K8MASK(misses, 1), 1143 NULLMASK 1144}; 1145 1146/* bu internal l2 request */ 1147static const struct pmc_masks k8_mask_bilr[] = { 1148 __K8MASK(ic-fill, 0), 1149 __K8MASK(dc-fill, 1), 1150 __K8MASK(tlb-reload, 2), 1151 __K8MASK(tag-snoop, 3), 1152 __K8MASK(cancelled, 4), 1153 NULLMASK 1154}; 1155 1156/* bu fill request l2 miss */ 1157static const struct pmc_masks k8_mask_bfrlm[] = { 1158 __K8MASK(ic-fill, 0), 1159 __K8MASK(dc-fill, 1), 1160 __K8MASK(tlb-reload, 2), 1161 NULLMASK 1162}; 1163 1164/* bu fill into l2 */ 1165static const struct pmc_masks k8_mask_bfil[] = { 1166 __K8MASK(dirty-l2-victim, 0), 1167 __K8MASK(victim-from-l2, 1), 1168 NULLMASK 1169}; 1170 1171/* fr retired fpu instructions */ 1172static const struct pmc_masks k8_mask_frfi[] = { 1173 __K8MASK(x87, 0), 1174 __K8MASK(mmx-3dnow, 1), 1175 __K8MASK(packed-sse-sse2, 2), 1176 __K8MASK(scalar-sse-sse2, 3), 1177 NULLMASK 1178}; 1179 1180/* fr retired fastpath double op instructions */ 1181static const struct pmc_masks k8_mask_frfdoi[] = { 1182 __K8MASK(low-op-pos-0, 0), 1183 __K8MASK(low-op-pos-1, 1), 1184 __K8MASK(low-op-pos-2, 2), 1185 NULLMASK 1186}; 1187 1188/* fr fpu exceptions */ 1189static const struct pmc_masks k8_mask_ffe[] = { 1190 __K8MASK(x87-reclass-microfaults, 0), 1191 __K8MASK(sse-retype-microfaults, 1), 1192 __K8MASK(sse-reclass-microfaults, 2), 1193 __K8MASK(sse-and-x87-microtraps, 3), 1194 NULLMASK 1195}; 1196 1197/* nb memory controller page access event */ 1198static const struct pmc_masks k8_mask_nmcpae[] = { 1199 __K8MASK(page-hit, 0), 1200 __K8MASK(page-miss, 1), 1201 __K8MASK(page-conflict, 2), 1202 NULLMASK 1203}; 1204 1205/* nb memory controller turnaround */ 1206static const struct pmc_masks k8_mask_nmct[] = { 1207 __K8MASK(dimm-turnaround, 0), 1208 __K8MASK(read-to-write-turnaround, 1), 1209 __K8MASK(write-to-read-turnaround, 2), 1210 NULLMASK 1211}; 1212 1213/* nb memory controller bypass saturation */ 1214static const struct pmc_masks k8_mask_nmcbs[] = { 1215 __K8MASK(memory-controller-hi-pri-bypass, 0), 1216 __K8MASK(memory-controller-lo-pri-bypass, 1), 1217 __K8MASK(dram-controller-interface-bypass, 2), 1218 __K8MASK(dram-controller-queue-bypass, 3), 1219 NULLMASK 1220}; 1221 1222/* nb sized commands */ 1223static const struct pmc_masks k8_mask_nsc[] = { 1224 __K8MASK(nonpostwrszbyte, 0), 1225 __K8MASK(nonpostwrszdword, 1), 1226 __K8MASK(postwrszbyte, 2), 1227 __K8MASK(postwrszdword, 3), 1228 __K8MASK(rdszbyte, 4), 1229 __K8MASK(rdszdword, 5), 1230 __K8MASK(rdmodwr, 6), 1231 NULLMASK 1232}; 1233 1234/* nb probe result */ 1235static const struct pmc_masks k8_mask_npr[] = { 1236 __K8MASK(probe-miss, 0), 1237 __K8MASK(probe-hit, 1), 1238 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1239 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1240 NULLMASK 1241}; 1242 1243/* nb hypertransport bus bandwidth */ 1244static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1245 __K8MASK(command, 0), 1246 __K8MASK(data, 1), 1247 __K8MASK(buffer-release, 2), 1248 __K8MASK(nop, 3), 1249 NULLMASK 1250}; 1251 1252#undef __K8MASK 1253 1254#define K8_KW_COUNT "count" 1255#define K8_KW_EDGE "edge" 1256#define K8_KW_INV "inv" 1257#define K8_KW_MASK "mask" 1258#define K8_KW_OS "os" 1259#define K8_KW_USR "usr" 1260 1261static int 1262k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1263 struct pmc_op_pmcallocate *pmc_config) 1264{ 1265 char *e, *p, *q; 1266 int n; 1267 uint32_t count; 1268 uint64_t evmask; 1269 const struct pmc_masks *pm, *pmask; 1270 1271 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1272 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1273 1274 pmask = NULL; 1275 evmask = 0; 1276 1277#define __K8SETMASK(M) pmask = k8_mask_##M 1278 1279 /* setup parsing tables */ 1280 switch (pe) { 1281 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1282 __K8SETMASK(fdfo); 1283 break; 1284 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1285 __K8SETMASK(lsrl); 1286 break; 1287 case PMC_EV_K8_LS_LOCKED_OPERATION: 1288 __K8SETMASK(llo); 1289 break; 1290 case PMC_EV_K8_DC_REFILL_FROM_L2: 1291 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1292 case PMC_EV_K8_DC_COPYBACK: 1293 __K8SETMASK(dc); 1294 break; 1295 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1296 __K8SETMASK(dobee); 1297 break; 1298 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1299 __K8SETMASK(ddpi); 1300 break; 1301 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1302 __K8SETMASK(dabl); 1303 break; 1304 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1305 __K8SETMASK(bilr); 1306 break; 1307 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1308 __K8SETMASK(bfrlm); 1309 break; 1310 case PMC_EV_K8_BU_FILL_INTO_L2: 1311 __K8SETMASK(bfil); 1312 break; 1313 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1314 __K8SETMASK(frfi); 1315 break; 1316 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1317 __K8SETMASK(frfdoi); 1318 break; 1319 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1320 __K8SETMASK(ffe); 1321 break; 1322 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1323 __K8SETMASK(nmcpae); 1324 break; 1325 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1326 __K8SETMASK(nmct); 1327 break; 1328 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1329 __K8SETMASK(nmcbs); 1330 break; 1331 case PMC_EV_K8_NB_SIZED_COMMANDS: 1332 __K8SETMASK(nsc); 1333 break; 1334 case PMC_EV_K8_NB_PROBE_RESULT: 1335 __K8SETMASK(npr); 1336 break; 1337 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1338 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1339 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1340 __K8SETMASK(nhbb); 1341 break; 1342 1343 default: 1344 break; /* no options defined */ 1345 } 1346 1347 while ((p = strsep(&ctrspec, ",")) != NULL) { 1348 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1349 q = strchr(p, '='); 1350 if (*++q == '\0') /* skip '=' */ 1351 return (-1); 1352 1353 count = strtol(q, &e, 0); 1354 if (e == q || *e != '\0') 1355 return (-1); 1356 1357 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1358 pmc_config->pm_md.pm_amd.pm_amd_config |= 1359 AMD_PMC_TO_COUNTER(count); 1360 1361 } else if (KWMATCH(p, K8_KW_EDGE)) { 1362 pmc_config->pm_caps |= PMC_CAP_EDGE; 1363 } else if (KWMATCH(p, K8_KW_INV)) { 1364 pmc_config->pm_caps |= PMC_CAP_INVERT; 1365 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1366 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1367 return (-1); 1368 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1369 } else if (KWMATCH(p, K8_KW_OS)) { 1370 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1371 } else if (KWMATCH(p, K8_KW_USR)) { 1372 pmc_config->pm_caps |= PMC_CAP_USER; 1373 } else 1374 return (-1); 1375 } 1376 1377 /* other post processing */ 1378 switch (pe) { 1379 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1380 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1381 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1382 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1383 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1384 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1385 /* XXX only available in rev B and later */ 1386 break; 1387 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1388 /* XXX only available in rev C and later */ 1389 break; 1390 case PMC_EV_K8_LS_LOCKED_OPERATION: 1391 /* XXX CPU Rev A,B evmask is to be zero */ 1392 if (evmask & (evmask - 1)) /* > 1 bit set */ 1393 return (-1); 1394 if (evmask == 0) { 1395 evmask = 0x01; /* Rev C and later: #instrs */ 1396 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1397 } 1398 break; 1399 default: 1400 if (evmask == 0 && pmask != NULL) { 1401 for (pm = pmask; pm->pm_name; pm++) 1402 evmask |= pm->pm_value; 1403 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1404 } 1405 } 1406 1407 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1408 pmc_config->pm_md.pm_amd.pm_amd_config = 1409 AMD_PMC_TO_UNITMASK(evmask); 1410 1411 return (0); 1412} 1413 1414#endif 1415 1416#if defined(__amd64__) || defined(__i386__) 1417 1418/* 1419 * Intel P4 PMCs 1420 */ 1421 1422static struct pmc_event_alias p4_aliases[] = { 1423 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1424 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1425 EV_ALIAS("cycles", "tsc"), 1426 EV_ALIAS("instructions", 1427 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1428 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1429 EV_ALIAS(NULL, NULL) 1430}; 1431 1432#define P4_KW_ACTIVE "active" 1433#define P4_KW_ACTIVE_ANY "any" 1434#define P4_KW_ACTIVE_BOTH "both" 1435#define P4_KW_ACTIVE_NONE "none" 1436#define P4_KW_ACTIVE_SINGLE "single" 1437#define P4_KW_BUSREQTYPE "busreqtype" 1438#define P4_KW_CASCADE "cascade" 1439#define P4_KW_EDGE "edge" 1440#define P4_KW_INV "complement" 1441#define P4_KW_OS "os" 1442#define P4_KW_MASK "mask" 1443#define P4_KW_PRECISE "precise" 1444#define P4_KW_TAG "tag" 1445#define P4_KW_THRESHOLD "threshold" 1446#define P4_KW_USR "usr" 1447 1448#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1449 1450static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1451 __P4MASK(dd, 0), 1452 __P4MASK(db, 1), 1453 __P4MASK(di, 2), 1454 __P4MASK(bd, 3), 1455 __P4MASK(bb, 4), 1456 __P4MASK(bi, 5), 1457 __P4MASK(id, 6), 1458 __P4MASK(ib, 7), 1459 NULLMASK 1460}; 1461 1462static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1463 __P4MASK(tcmiss, 0), 1464 NULLMASK, 1465}; 1466 1467static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1468 __P4MASK(hit, 0), 1469 __P4MASK(miss, 1), 1470 __P4MASK(hit-uc, 2), 1471 NULLMASK 1472}; 1473 1474static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1475 __P4MASK(st-rb-full, 2), 1476 __P4MASK(64k-conf, 3), 1477 NULLMASK 1478}; 1479 1480static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1481 __P4MASK(lsc, 0), 1482 __P4MASK(ssc, 1), 1483 NULLMASK 1484}; 1485 1486static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1487 __P4MASK(split-ld, 1), 1488 NULLMASK 1489}; 1490 1491static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1492 __P4MASK(split-st, 1), 1493 NULLMASK 1494}; 1495 1496static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1497 __P4MASK(no-sta, 1), 1498 __P4MASK(no-std, 3), 1499 __P4MASK(partial-data, 4), 1500 __P4MASK(unalgn-addr, 5), 1501 NULLMASK 1502}; 1503 1504static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1505 __P4MASK(dtmiss, 0), 1506 __P4MASK(itmiss, 1), 1507 NULLMASK 1508}; 1509 1510static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1511 __P4MASK(rd-2ndl-hits, 0), 1512 __P4MASK(rd-2ndl-hite, 1), 1513 __P4MASK(rd-2ndl-hitm, 2), 1514 __P4MASK(rd-3rdl-hits, 3), 1515 __P4MASK(rd-3rdl-hite, 4), 1516 __P4MASK(rd-3rdl-hitm, 5), 1517 __P4MASK(rd-2ndl-miss, 8), 1518 __P4MASK(rd-3rdl-miss, 9), 1519 __P4MASK(wr-2ndl-miss, 10), 1520 NULLMASK 1521}; 1522 1523static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1524 __P4MASK(all-read, 5), 1525 __P4MASK(all-write, 6), 1526 __P4MASK(mem-uc, 7), 1527 __P4MASK(mem-wc, 8), 1528 __P4MASK(mem-wt, 9), 1529 __P4MASK(mem-wp, 10), 1530 __P4MASK(mem-wb, 11), 1531 __P4MASK(own, 13), 1532 __P4MASK(other, 14), 1533 __P4MASK(prefetch, 15), 1534 NULLMASK 1535}; 1536 1537static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1538 __P4MASK(all-read, 5), 1539 __P4MASK(all-write, 6), 1540 __P4MASK(mem-uc, 7), 1541 __P4MASK(mem-wc, 8), 1542 __P4MASK(mem-wt, 9), 1543 __P4MASK(mem-wp, 10), 1544 __P4MASK(mem-wb, 11), 1545 __P4MASK(own, 13), 1546 __P4MASK(other, 14), 1547 __P4MASK(prefetch, 15), 1548 NULLMASK 1549}; 1550 1551static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1552 __P4MASK(drdy-drv, 0), 1553 __P4MASK(drdy-own, 1), 1554 __P4MASK(drdy-other, 2), 1555 __P4MASK(dbsy-drv, 3), 1556 __P4MASK(dbsy-own, 4), 1557 __P4MASK(dbsy-other, 5), 1558 NULLMASK 1559}; 1560 1561static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1562 __P4MASK(req-type0, 0), 1563 __P4MASK(req-type1, 1), 1564 __P4MASK(req-len0, 2), 1565 __P4MASK(req-len1, 3), 1566 __P4MASK(req-io-type, 5), 1567 __P4MASK(req-lock-type, 6), 1568 __P4MASK(req-cache-type, 7), 1569 __P4MASK(req-split-type, 8), 1570 __P4MASK(req-dem-type, 9), 1571 __P4MASK(req-ord-type, 10), 1572 __P4MASK(mem-type0, 11), 1573 __P4MASK(mem-type1, 12), 1574 __P4MASK(mem-type2, 13), 1575 NULLMASK 1576}; 1577 1578static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1579 __P4MASK(all, 15), 1580 NULLMASK 1581}; 1582 1583static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1584 __P4MASK(all, 15), 1585 NULLMASK 1586}; 1587 1588static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1589 __P4MASK(all, 15), 1590 NULLMASK 1591}; 1592 1593static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1594 __P4MASK(all, 15), 1595 NULLMASK 1596}; 1597 1598static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1599 __P4MASK(all, 15), 1600 NULLMASK 1601}; 1602 1603static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1604 __P4MASK(all, 15), 1605 NULLMASK 1606}; 1607 1608static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1609 __P4MASK(all, 15), 1610 NULLMASK 1611}; 1612 1613static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1614 __P4MASK(all, 15), 1615 NULLMASK 1616}; 1617 1618static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1619 __P4MASK(allp0, 3), 1620 __P4MASK(allp2, 4), 1621 NULLMASK 1622}; 1623 1624static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1625 __P4MASK(running, 0), 1626 NULLMASK 1627}; 1628 1629static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1630 __P4MASK(cisc, 0), 1631 NULLMASK 1632}; 1633 1634static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1635 __P4MASK(from-tc-build, 0), 1636 __P4MASK(from-tc-deliver, 1), 1637 __P4MASK(from-rom, 2), 1638 NULLMASK 1639}; 1640 1641static const struct pmc_masks p4_mask_rmbt[] = { 1642 /* retired mispred branch type */ 1643 __P4MASK(conditional, 1), 1644 __P4MASK(call, 2), 1645 __P4MASK(return, 3), 1646 __P4MASK(indirect, 4), 1647 NULLMASK 1648}; 1649 1650static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1651 __P4MASK(conditional, 1), 1652 __P4MASK(call, 2), 1653 __P4MASK(retired, 3), 1654 __P4MASK(indirect, 4), 1655 NULLMASK 1656}; 1657 1658static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1659 __P4MASK(sbfull, 5), 1660 NULLMASK 1661}; 1662 1663static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1664 __P4MASK(wcb-evicts, 0), 1665 __P4MASK(wcb-full-evict, 1), 1666 NULLMASK 1667}; 1668 1669static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1670 __P4MASK(nbogus, 0), 1671 __P4MASK(bogus, 1), 1672 NULLMASK 1673}; 1674 1675static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1676 __P4MASK(nbogus0, 0), 1677 __P4MASK(nbogus1, 1), 1678 __P4MASK(nbogus2, 2), 1679 __P4MASK(nbogus3, 3), 1680 __P4MASK(bogus0, 4), 1681 __P4MASK(bogus1, 5), 1682 __P4MASK(bogus2, 6), 1683 __P4MASK(bogus3, 7), 1684 NULLMASK 1685}; 1686 1687static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1688 __P4MASK(nbogus, 0), 1689 __P4MASK(bogus, 1), 1690 NULLMASK 1691}; 1692 1693static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1694 __P4MASK(nbogusntag, 0), 1695 __P4MASK(nbogustag, 1), 1696 __P4MASK(bogusntag, 2), 1697 __P4MASK(bogustag, 3), 1698 NULLMASK 1699}; 1700 1701static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1702 __P4MASK(nbogus, 0), 1703 __P4MASK(bogus, 1), 1704 NULLMASK 1705}; 1706 1707static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1708 __P4MASK(tagloads, 1), 1709 __P4MASK(tagstores, 2), 1710 NULLMASK 1711}; 1712 1713static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1714 __P4MASK(mmnp, 0), 1715 __P4MASK(mmnm, 1), 1716 __P4MASK(mmtp, 2), 1717 __P4MASK(mmtm, 3), 1718 NULLMASK 1719}; 1720 1721static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1722 __P4MASK(nbogus, 0), 1723 NULLMASK 1724}; 1725 1726static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1727 __P4MASK(fpsu, 0), 1728 __P4MASK(fpso, 1), 1729 __P4MASK(poao, 2), 1730 __P4MASK(poau, 3), 1731 __P4MASK(prea, 4), 1732 NULLMASK 1733}; 1734 1735static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1736 __P4MASK(clear, 0), 1737 __P4MASK(moclear, 2), 1738 __P4MASK(smclear, 3), 1739 NULLMASK 1740}; 1741 1742/* P4 event parser */ 1743static int 1744p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1745 struct pmc_op_pmcallocate *pmc_config) 1746{ 1747 1748 char *e, *p, *q; 1749 int count, has_tag, has_busreqtype, n; 1750 uint32_t cccractivemask; 1751 uint64_t evmask; 1752 const struct pmc_masks *pm, *pmask; 1753 1754 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1755 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1756 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1757 1758 pmask = NULL; 1759 evmask = 0; 1760 cccractivemask = 0x3; 1761 has_tag = has_busreqtype = 0; 1762 1763#define __P4SETMASK(M) do { \ 1764 pmask = p4_mask_##M; \ 1765} while (0) 1766 1767 switch (pe) { 1768 case PMC_EV_P4_TC_DELIVER_MODE: 1769 __P4SETMASK(tcdm); 1770 break; 1771 case PMC_EV_P4_BPU_FETCH_REQUEST: 1772 __P4SETMASK(bfr); 1773 break; 1774 case PMC_EV_P4_ITLB_REFERENCE: 1775 __P4SETMASK(ir); 1776 break; 1777 case PMC_EV_P4_MEMORY_CANCEL: 1778 __P4SETMASK(memcan); 1779 break; 1780 case PMC_EV_P4_MEMORY_COMPLETE: 1781 __P4SETMASK(memcomp); 1782 break; 1783 case PMC_EV_P4_LOAD_PORT_REPLAY: 1784 __P4SETMASK(lpr); 1785 break; 1786 case PMC_EV_P4_STORE_PORT_REPLAY: 1787 __P4SETMASK(spr); 1788 break; 1789 case PMC_EV_P4_MOB_LOAD_REPLAY: 1790 __P4SETMASK(mlr); 1791 break; 1792 case PMC_EV_P4_PAGE_WALK_TYPE: 1793 __P4SETMASK(pwt); 1794 break; 1795 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1796 __P4SETMASK(bcr); 1797 break; 1798 case PMC_EV_P4_IOQ_ALLOCATION: 1799 __P4SETMASK(ia); 1800 has_busreqtype = 1; 1801 break; 1802 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1803 __P4SETMASK(iae); 1804 has_busreqtype = 1; 1805 break; 1806 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1807 __P4SETMASK(fda); 1808 break; 1809 case PMC_EV_P4_BSQ_ALLOCATION: 1810 __P4SETMASK(ba); 1811 break; 1812 case PMC_EV_P4_SSE_INPUT_ASSIST: 1813 __P4SETMASK(sia); 1814 break; 1815 case PMC_EV_P4_PACKED_SP_UOP: 1816 __P4SETMASK(psu); 1817 break; 1818 case PMC_EV_P4_PACKED_DP_UOP: 1819 __P4SETMASK(pdu); 1820 break; 1821 case PMC_EV_P4_SCALAR_SP_UOP: 1822 __P4SETMASK(ssu); 1823 break; 1824 case PMC_EV_P4_SCALAR_DP_UOP: 1825 __P4SETMASK(sdu); 1826 break; 1827 case PMC_EV_P4_64BIT_MMX_UOP: 1828 __P4SETMASK(64bmu); 1829 break; 1830 case PMC_EV_P4_128BIT_MMX_UOP: 1831 __P4SETMASK(128bmu); 1832 break; 1833 case PMC_EV_P4_X87_FP_UOP: 1834 __P4SETMASK(xfu); 1835 break; 1836 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1837 __P4SETMASK(xsmu); 1838 break; 1839 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1840 __P4SETMASK(gpe); 1841 break; 1842 case PMC_EV_P4_TC_MS_XFER: 1843 __P4SETMASK(tmx); 1844 break; 1845 case PMC_EV_P4_UOP_QUEUE_WRITES: 1846 __P4SETMASK(uqw); 1847 break; 1848 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1849 __P4SETMASK(rmbt); 1850 break; 1851 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1852 __P4SETMASK(rbt); 1853 break; 1854 case PMC_EV_P4_RESOURCE_STALL: 1855 __P4SETMASK(rs); 1856 break; 1857 case PMC_EV_P4_WC_BUFFER: 1858 __P4SETMASK(wb); 1859 break; 1860 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1861 case PMC_EV_P4_B2B_CYCLES: 1862 case PMC_EV_P4_BNR: 1863 case PMC_EV_P4_SNOOP: 1864 case PMC_EV_P4_RESPONSE: 1865 break; 1866 case PMC_EV_P4_FRONT_END_EVENT: 1867 __P4SETMASK(fee); 1868 break; 1869 case PMC_EV_P4_EXECUTION_EVENT: 1870 __P4SETMASK(ee); 1871 break; 1872 case PMC_EV_P4_REPLAY_EVENT: 1873 __P4SETMASK(re); 1874 break; 1875 case PMC_EV_P4_INSTR_RETIRED: 1876 __P4SETMASK(insret); 1877 break; 1878 case PMC_EV_P4_UOPS_RETIRED: 1879 __P4SETMASK(ur); 1880 break; 1881 case PMC_EV_P4_UOP_TYPE: 1882 __P4SETMASK(ut); 1883 break; 1884 case PMC_EV_P4_BRANCH_RETIRED: 1885 __P4SETMASK(br); 1886 break; 1887 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1888 __P4SETMASK(mbr); 1889 break; 1890 case PMC_EV_P4_X87_ASSIST: 1891 __P4SETMASK(xa); 1892 break; 1893 case PMC_EV_P4_MACHINE_CLEAR: 1894 __P4SETMASK(machclr); 1895 break; 1896 default: 1897 return (-1); 1898 } 1899 1900 /* process additional flags */ 1901 while ((p = strsep(&ctrspec, ",")) != NULL) { 1902 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1903 q = strchr(p, '='); 1904 if (*++q == '\0') /* skip '=' */ 1905 return (-1); 1906 1907 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1908 cccractivemask = 0x0; 1909 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1910 cccractivemask = 0x1; 1911 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1912 cccractivemask = 0x2; 1913 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1914 cccractivemask = 0x3; 1915 else 1916 return (-1); 1917 1918 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1919 if (has_busreqtype == 0) 1920 return (-1); 1921 1922 q = strchr(p, '='); 1923 if (*++q == '\0') /* skip '=' */ 1924 return (-1); 1925 1926 count = strtol(q, &e, 0); 1927 if (e == q || *e != '\0') 1928 return (-1); 1929 evmask = (evmask & ~0x1F) | (count & 0x1F); 1930 } else if (KWMATCH(p, P4_KW_CASCADE)) 1931 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1932 else if (KWMATCH(p, P4_KW_EDGE)) 1933 pmc_config->pm_caps |= PMC_CAP_EDGE; 1934 else if (KWMATCH(p, P4_KW_INV)) 1935 pmc_config->pm_caps |= PMC_CAP_INVERT; 1936 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1937 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1938 return (-1); 1939 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1940 } else if (KWMATCH(p, P4_KW_OS)) 1941 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1942 else if (KWMATCH(p, P4_KW_PRECISE)) 1943 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1944 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1945 if (has_tag == 0) 1946 return (-1); 1947 1948 q = strchr(p, '='); 1949 if (*++q == '\0') /* skip '=' */ 1950 return (-1); 1951 1952 count = strtol(q, &e, 0); 1953 if (e == q || *e != '\0') 1954 return (-1); 1955 1956 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1957 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1958 P4_ESCR_TO_TAG_VALUE(count); 1959 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1960 q = strchr(p, '='); 1961 if (*++q == '\0') /* skip '=' */ 1962 return (-1); 1963 1964 count = strtol(q, &e, 0); 1965 if (e == q || *e != '\0') 1966 return (-1); 1967 1968 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1969 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1970 ~P4_CCCR_THRESHOLD_MASK; 1971 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1972 P4_CCCR_TO_THRESHOLD(count); 1973 } else if (KWMATCH(p, P4_KW_USR)) 1974 pmc_config->pm_caps |= PMC_CAP_USER; 1975 else 1976 return (-1); 1977 } 1978 1979 /* other post processing */ 1980 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1981 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1982 pe == PMC_EV_P4_BSQ_ALLOCATION) 1983 pmc_config->pm_caps |= PMC_CAP_EDGE; 1984 1985 /* fill in thread activity mask */ 1986 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1987 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1988 1989 if (evmask) 1990 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1991 1992 switch (pe) { 1993 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1994 if ((evmask & 0x06) == 0x06 || 1995 (evmask & 0x18) == 0x18) 1996 return (-1); /* can't have own+other bits together */ 1997 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1998 evmask = 0x1D; 1999 break; 2000 case PMC_EV_P4_MACHINE_CLEAR: 2001 /* only one bit is allowed to be set */ 2002 if ((evmask & (evmask - 1)) != 0) 2003 return (-1); 2004 if (evmask == 0) { 2005 evmask = 0x1; /* 'CLEAR' */ 2006 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2007 } 2008 break; 2009 default: 2010 if (evmask == 0 && pmask) { 2011 for (pm = pmask; pm->pm_name; pm++) 2012 evmask |= pm->pm_value; 2013 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2014 } 2015 } 2016 2017 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 2018 P4_ESCR_TO_EVENT_MASK(evmask); 2019 2020 return (0); 2021} 2022 2023#endif 2024 2025#if defined(__i386__) 2026 2027/* 2028 * Pentium style PMCs 2029 */ 2030 2031static struct pmc_event_alias p5_aliases[] = { 2032 EV_ALIAS("branches", "p5-taken-branches"), 2033 EV_ALIAS("cycles", "tsc"), 2034 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 2035 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 2036 EV_ALIAS("instructions", "p5-instructions-executed"), 2037 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 2038 EV_ALIAS("unhalted-cycles", 2039 "p5-number-of-cycles-not-in-halt-state"), 2040 EV_ALIAS(NULL, NULL) 2041}; 2042 2043static int 2044p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 2045 struct pmc_op_pmcallocate *pmc_config) 2046{ 2047 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 2048} 2049 2050/* 2051 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 2052 * and Pentium M CPUs. 2053 */ 2054 2055static struct pmc_event_alias p6_aliases[] = { 2056 EV_ALIAS("branches", "p6-br-inst-retired"), 2057 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 2058 EV_ALIAS("cycles", "tsc"), 2059 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 2060 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 2061 EV_ALIAS("instructions", "p6-inst-retired"), 2062 EV_ALIAS("interrupts", "p6-hw-int-rx"), 2063 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 2064 EV_ALIAS(NULL, NULL) 2065}; 2066 2067#define P6_KW_CMASK "cmask" 2068#define P6_KW_EDGE "edge" 2069#define P6_KW_INV "inv" 2070#define P6_KW_OS "os" 2071#define P6_KW_UMASK "umask" 2072#define P6_KW_USR "usr" 2073 2074static struct pmc_masks p6_mask_mesi[] = { 2075 PMCMASK(m, 0x01), 2076 PMCMASK(e, 0x02), 2077 PMCMASK(s, 0x04), 2078 PMCMASK(i, 0x08), 2079 NULLMASK 2080}; 2081 2082static struct pmc_masks p6_mask_mesihw[] = { 2083 PMCMASK(m, 0x01), 2084 PMCMASK(e, 0x02), 2085 PMCMASK(s, 0x04), 2086 PMCMASK(i, 0x08), 2087 PMCMASK(nonhw, 0x00), 2088 PMCMASK(hw, 0x10), 2089 PMCMASK(both, 0x30), 2090 NULLMASK 2091}; 2092 2093static struct pmc_masks p6_mask_hw[] = { 2094 PMCMASK(nonhw, 0x00), 2095 PMCMASK(hw, 0x10), 2096 PMCMASK(both, 0x30), 2097 NULLMASK 2098}; 2099 2100static struct pmc_masks p6_mask_any[] = { 2101 PMCMASK(self, 0x00), 2102 PMCMASK(any, 0x20), 2103 NULLMASK 2104}; 2105 2106static struct pmc_masks p6_mask_ekp[] = { 2107 PMCMASK(nta, 0x00), 2108 PMCMASK(t1, 0x01), 2109 PMCMASK(t2, 0x02), 2110 PMCMASK(wos, 0x03), 2111 NULLMASK 2112}; 2113 2114static struct pmc_masks p6_mask_pps[] = { 2115 PMCMASK(packed-and-scalar, 0x00), 2116 PMCMASK(scalar, 0x01), 2117 NULLMASK 2118}; 2119 2120static struct pmc_masks p6_mask_mite[] = { 2121 PMCMASK(packed-multiply, 0x01), 2122 PMCMASK(packed-shift, 0x02), 2123 PMCMASK(pack, 0x04), 2124 PMCMASK(unpack, 0x08), 2125 PMCMASK(packed-logical, 0x10), 2126 PMCMASK(packed-arithmetic, 0x20), 2127 NULLMASK 2128}; 2129 2130static struct pmc_masks p6_mask_fmt[] = { 2131 PMCMASK(mmxtofp, 0x00), 2132 PMCMASK(fptommx, 0x01), 2133 NULLMASK 2134}; 2135 2136static struct pmc_masks p6_mask_sr[] = { 2137 PMCMASK(es, 0x01), 2138 PMCMASK(ds, 0x02), 2139 PMCMASK(fs, 0x04), 2140 PMCMASK(gs, 0x08), 2141 NULLMASK 2142}; 2143 2144static struct pmc_masks p6_mask_eet[] = { 2145 PMCMASK(all, 0x00), 2146 PMCMASK(freq, 0x02), 2147 NULLMASK 2148}; 2149 2150static struct pmc_masks p6_mask_efur[] = { 2151 PMCMASK(all, 0x00), 2152 PMCMASK(loadop, 0x01), 2153 PMCMASK(stdsta, 0x02), 2154 NULLMASK 2155}; 2156 2157static struct pmc_masks p6_mask_essir[] = { 2158 PMCMASK(sse-packed-single, 0x00), 2159 PMCMASK(sse-packed-single-scalar-single, 0x01), 2160 PMCMASK(sse2-packed-double, 0x02), 2161 PMCMASK(sse2-scalar-double, 0x03), 2162 NULLMASK 2163}; 2164 2165static struct pmc_masks p6_mask_esscir[] = { 2166 PMCMASK(sse-packed-single, 0x00), 2167 PMCMASK(sse-scalar-single, 0x01), 2168 PMCMASK(sse2-packed-double, 0x02), 2169 PMCMASK(sse2-scalar-double, 0x03), 2170 NULLMASK 2171}; 2172 2173/* P6 event parser */ 2174static int 2175p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2176 struct pmc_op_pmcallocate *pmc_config) 2177{ 2178 char *e, *p, *q; 2179 uint64_t evmask; 2180 int count, n; 2181 const struct pmc_masks *pm, *pmask; 2182 2183 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2184 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2185 2186 evmask = 0; 2187 2188#define P6MASKSET(M) pmask = p6_mask_ ## M 2189 2190 switch(pe) { 2191 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2192 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2193 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2194 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2195 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2196 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2197 case PMC_EV_P6_BUS_TRAN_BRD: 2198 case PMC_EV_P6_BUS_TRAN_RFO: 2199 case PMC_EV_P6_BUS_TRANS_WB: 2200 case PMC_EV_P6_BUS_TRAN_IFETCH: 2201 case PMC_EV_P6_BUS_TRAN_INVAL: 2202 case PMC_EV_P6_BUS_TRAN_PWR: 2203 case PMC_EV_P6_BUS_TRANS_P: 2204 case PMC_EV_P6_BUS_TRANS_IO: 2205 case PMC_EV_P6_BUS_TRAN_DEF: 2206 case PMC_EV_P6_BUS_TRAN_BURST: 2207 case PMC_EV_P6_BUS_TRAN_ANY: 2208 case PMC_EV_P6_BUS_TRAN_MEM: 2209 P6MASKSET(any); break; 2210 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2211 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2212 P6MASKSET(ekp); break; 2213 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2214 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2215 P6MASKSET(pps); break; 2216 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2217 P6MASKSET(mite); break; 2218 case PMC_EV_P6_FP_MMX_TRANS: 2219 P6MASKSET(fmt); break; 2220 case PMC_EV_P6_SEG_RENAME_STALLS: 2221 case PMC_EV_P6_SEG_REG_RENAMES: 2222 P6MASKSET(sr); break; 2223 case PMC_EV_P6_EMON_EST_TRANS: 2224 P6MASKSET(eet); break; 2225 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2226 P6MASKSET(efur); break; 2227 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2228 P6MASKSET(essir); break; 2229 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2230 P6MASKSET(esscir); break; 2231 default: 2232 pmask = NULL; 2233 break; 2234 } 2235 2236 /* Pentium M PMCs have a few events with different semantics */ 2237 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2238 if (pe == PMC_EV_P6_L2_LD || 2239 pe == PMC_EV_P6_L2_LINES_IN || 2240 pe == PMC_EV_P6_L2_LINES_OUT) 2241 P6MASKSET(mesihw); 2242 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2243 P6MASKSET(hw); 2244 } 2245 2246 /* Parse additional modifiers if present */ 2247 while ((p = strsep(&ctrspec, ",")) != NULL) { 2248 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2249 q = strchr(p, '='); 2250 if (*++q == '\0') /* skip '=' */ 2251 return (-1); 2252 count = strtol(q, &e, 0); 2253 if (e == q || *e != '\0') 2254 return (-1); 2255 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2256 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2257 P6_EVSEL_TO_CMASK(count); 2258 } else if (KWMATCH(p, P6_KW_EDGE)) { 2259 pmc_config->pm_caps |= PMC_CAP_EDGE; 2260 } else if (KWMATCH(p, P6_KW_INV)) { 2261 pmc_config->pm_caps |= PMC_CAP_INVERT; 2262 } else if (KWMATCH(p, P6_KW_OS)) { 2263 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2264 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2265 evmask = 0; 2266 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2267 return (-1); 2268 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2269 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2270 pe == PMC_EV_P6_BUS_TRAN_BRD || 2271 pe == PMC_EV_P6_BUS_TRAN_RFO || 2272 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2273 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2274 pe == PMC_EV_P6_BUS_TRAN_PWR || 2275 pe == PMC_EV_P6_BUS_TRAN_DEF || 2276 pe == PMC_EV_P6_BUS_TRAN_BURST || 2277 pe == PMC_EV_P6_BUS_TRAN_ANY || 2278 pe == PMC_EV_P6_BUS_TRAN_MEM || 2279 pe == PMC_EV_P6_BUS_TRANS_IO || 2280 pe == PMC_EV_P6_BUS_TRANS_P || 2281 pe == PMC_EV_P6_BUS_TRANS_WB || 2282 pe == PMC_EV_P6_EMON_EST_TRANS || 2283 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2284 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2285 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2286 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2287 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2288 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2289 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2290 pe == PMC_EV_P6_FP_MMX_TRANS) 2291 && (n > 1)) /* Only one mask keyword is allowed. */ 2292 return (-1); 2293 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2294 } else if (KWMATCH(p, P6_KW_USR)) { 2295 pmc_config->pm_caps |= PMC_CAP_USER; 2296 } else 2297 return (-1); 2298 } 2299 2300 /* post processing */ 2301 switch (pe) { 2302 2303 /* 2304 * The following events default to an evmask of 0 2305 */ 2306 2307 /* default => 'self' */ 2308 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2309 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2310 case PMC_EV_P6_BUS_TRAN_BRD: 2311 case PMC_EV_P6_BUS_TRAN_RFO: 2312 case PMC_EV_P6_BUS_TRANS_WB: 2313 case PMC_EV_P6_BUS_TRAN_IFETCH: 2314 case PMC_EV_P6_BUS_TRAN_INVAL: 2315 case PMC_EV_P6_BUS_TRAN_PWR: 2316 case PMC_EV_P6_BUS_TRANS_P: 2317 case PMC_EV_P6_BUS_TRANS_IO: 2318 case PMC_EV_P6_BUS_TRAN_DEF: 2319 case PMC_EV_P6_BUS_TRAN_BURST: 2320 case PMC_EV_P6_BUS_TRAN_ANY: 2321 case PMC_EV_P6_BUS_TRAN_MEM: 2322 2323 /* default => 'nta' */ 2324 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2325 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2326 2327 /* default => 'packed and scalar' */ 2328 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2329 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2330 2331 /* default => 'mmx to fp transitions' */ 2332 case PMC_EV_P6_FP_MMX_TRANS: 2333 2334 /* default => 'SSE Packed Single' */ 2335 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2336 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2337 2338 /* default => 'all fused micro-ops' */ 2339 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2340 2341 /* default => 'all transitions' */ 2342 case PMC_EV_P6_EMON_EST_TRANS: 2343 break; 2344 2345 case PMC_EV_P6_MMX_UOPS_EXEC: 2346 evmask = 0x0F; /* only value allowed */ 2347 break; 2348 2349 default: 2350 /* 2351 * For all other events, set the default event mask 2352 * to a logical OR of all the allowed event mask bits. 2353 */ 2354 if (evmask == 0 && pmask) { 2355 for (pm = pmask; pm->pm_name; pm++) 2356 evmask |= pm->pm_value; 2357 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2358 } 2359 2360 break; 2361 } 2362 2363 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2364 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2365 P6_EVSEL_TO_UMASK(evmask); 2366 2367 return (0); 2368} 2369 2370#endif 2371 2372#if defined(__i386__) || defined(__amd64__) 2373static int 2374tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2375 struct pmc_op_pmcallocate *pmc_config) 2376{ 2377 if (pe != PMC_EV_TSC_TSC) 2378 return (-1); 2379 2380 /* TSC events must be unqualified. */ 2381 if (ctrspec && *ctrspec != '\0') 2382 return (-1); 2383 2384 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2385 pmc_config->pm_caps |= PMC_CAP_READ; 2386 2387 return (0); 2388} 2389#endif 2390 2391static struct pmc_event_alias generic_aliases[] = { 2392 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2393 EV_ALIAS(NULL, NULL) 2394}; 2395 2396static int 2397soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2398 struct pmc_op_pmcallocate *pmc_config) 2399{ 2400 (void)ctrspec; 2401 (void)pmc_config; 2402 2403 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2404 return (-1); 2405 2406 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2407 return (0); 2408} 2409 2410#if defined(__arm__) 2411#if defined(__XSCALE__) 2412 2413static struct pmc_event_alias xscale_aliases[] = { 2414 EV_ALIAS("branches", "BRANCH_RETIRED"), 2415 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2416 EV_ALIAS("dc-misses", "DC_MISS"), 2417 EV_ALIAS("ic-misses", "IC_MISS"), 2418 EV_ALIAS("instructions", "INSTR_RETIRED"), 2419 EV_ALIAS(NULL, NULL) 2420}; 2421static int 2422xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2423 struct pmc_op_pmcallocate *pmc_config __unused) 2424{ 2425 switch (pe) { 2426 default: 2427 break; 2428 } 2429 2430 return (0); 2431} 2432#endif 2433 2434static struct pmc_event_alias armv7_aliases[] = { 2435 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), 2436 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), 2437 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2438 EV_ALIAS(NULL, NULL) 2439}; 2440static int 2441armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2442 struct pmc_op_pmcallocate *pmc_config __unused) 2443{ 2444 switch (pe) { 2445 default: 2446 break; 2447 } 2448 2449 return (0); 2450} 2451#endif 2452 2453#if defined(__aarch64__) 2454static struct pmc_event_alias cortex_a53_aliases[] = { 2455 EV_ALIAS(NULL, NULL) 2456}; 2457static struct pmc_event_alias cortex_a57_aliases[] = { 2458 EV_ALIAS(NULL, NULL) 2459}; 2460static int 2461arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2462 struct pmc_op_pmcallocate *pmc_config __unused) 2463{ 2464 switch (pe) { 2465 default: 2466 break; 2467 } 2468 2469 return (0); 2470} 2471#endif 2472 2473#if defined(__mips__) 2474 2475static struct pmc_event_alias mips24k_aliases[] = { 2476 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2477 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2478 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2479 EV_ALIAS(NULL, NULL) 2480}; 2481 2482static struct pmc_event_alias mips74k_aliases[] = { 2483 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2484 EV_ALIAS("branches", "BRANCH_INSNS"), 2485 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), 2486 EV_ALIAS(NULL, NULL) 2487}; 2488 2489static struct pmc_event_alias octeon_aliases[] = { 2490 EV_ALIAS("instructions", "RET"), 2491 EV_ALIAS("branches", "BR"), 2492 EV_ALIAS("branch-mispredicts", "BRMIS"), 2493 EV_ALIAS(NULL, NULL) 2494}; 2495 2496#define MIPS_KW_OS "os" 2497#define MIPS_KW_USR "usr" 2498#define MIPS_KW_ANYTHREAD "anythread" 2499 2500static int 2501mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2502 struct pmc_op_pmcallocate *pmc_config __unused) 2503{ 2504 char *p; 2505 2506 (void) pe; 2507 2508 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2509 2510 while ((p = strsep(&ctrspec, ",")) != NULL) { 2511 if (KWMATCH(p, MIPS_KW_OS)) 2512 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2513 else if (KWMATCH(p, MIPS_KW_USR)) 2514 pmc_config->pm_caps |= PMC_CAP_USER; 2515 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2516 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2517 else 2518 return (-1); 2519 } 2520 2521 return (0); 2522} 2523 2524#endif /* __mips__ */ 2525 2526#if defined(__powerpc__) 2527 2528static struct pmc_event_alias ppc7450_aliases[] = { 2529 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2530 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2531 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2532 EV_ALIAS(NULL, NULL) 2533}; 2534 2535static struct pmc_event_alias ppc970_aliases[] = { 2536 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2537 EV_ALIAS("cycles", "CYCLES"), 2538 EV_ALIAS(NULL, NULL) 2539}; 2540 2541static struct pmc_event_alias e500_aliases[] = { 2542 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2543 EV_ALIAS("cycles", "CYCLES"), 2544 EV_ALIAS(NULL, NULL) 2545}; 2546 2547#define POWERPC_KW_OS "os" 2548#define POWERPC_KW_USR "usr" 2549#define POWERPC_KW_ANYTHREAD "anythread" 2550 2551static int 2552powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2553 struct pmc_op_pmcallocate *pmc_config __unused) 2554{ 2555 char *p; 2556 2557 (void) pe; 2558 2559 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2560 2561 while ((p = strsep(&ctrspec, ",")) != NULL) { 2562 if (KWMATCH(p, POWERPC_KW_OS)) 2563 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2564 else if (KWMATCH(p, POWERPC_KW_USR)) 2565 pmc_config->pm_caps |= PMC_CAP_USER; 2566 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2567 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2568 else 2569 return (-1); 2570 } 2571 2572 return (0); 2573} 2574 2575#endif /* __powerpc__ */ 2576 2577 2578/* 2579 * Match an event name `name' with its canonical form. 2580 * 2581 * Matches are case insensitive and spaces, periods, underscores and 2582 * hyphen characters are considered to match each other. 2583 * 2584 * Returns 1 for a match, 0 otherwise. 2585 */ 2586 2587static int 2588pmc_match_event_name(const char *name, const char *canonicalname) 2589{ 2590 int cc, nc; 2591 const unsigned char *c, *n; 2592 2593 c = (const unsigned char *) canonicalname; 2594 n = (const unsigned char *) name; 2595 2596 for (; (nc = *n) && (cc = *c); n++, c++) { 2597 2598 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2599 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2600 continue; 2601 2602 if (toupper(nc) == toupper(cc)) 2603 continue; 2604 2605 2606 return (0); 2607 } 2608 2609 if (*n == '\0' && *c == '\0') 2610 return (1); 2611 2612 return (0); 2613} 2614 2615/* 2616 * Match an event name against all the event named supported by a 2617 * PMC class. 2618 * 2619 * Returns an event descriptor pointer on match or NULL otherwise. 2620 */ 2621static const struct pmc_event_descr * 2622pmc_match_event_class(const char *name, 2623 const struct pmc_class_descr *pcd) 2624{ 2625 size_t n; 2626 const struct pmc_event_descr *ev; 2627 2628 ev = pcd->pm_evc_event_table; 2629 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2630 if (pmc_match_event_name(name, ev->pm_ev_name)) 2631 return (ev); 2632 2633 return (NULL); 2634} 2635 2636static int 2637pmc_mdep_is_compatible_class(enum pmc_class pc) 2638{ 2639 size_t n; 2640 2641 for (n = 0; n < pmc_mdep_class_list_size; n++) 2642 if (pmc_mdep_class_list[n] == pc) 2643 return (1); 2644 return (0); 2645} 2646 2647/* 2648 * API entry points 2649 */ 2650 2651int 2652pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2653 uint32_t flags, int cpu, pmc_id_t *pmcid) 2654{ 2655 size_t n; 2656 int retval; 2657 char *r, *spec_copy; 2658 const char *ctrname; 2659 const struct pmc_event_descr *ev; 2660 const struct pmc_event_alias *alias; 2661 struct pmc_op_pmcallocate pmc_config; 2662 const struct pmc_class_descr *pcd; 2663 2664 spec_copy = NULL; 2665 retval = -1; 2666 2667 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2668 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2669 errno = EINVAL; 2670 goto out; 2671 } 2672 2673 /* replace an event alias with the canonical event specifier */ 2674 if (pmc_mdep_event_aliases) 2675 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2676 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2677 spec_copy = strdup(alias->pm_spec); 2678 break; 2679 } 2680 2681 if (spec_copy == NULL) 2682 spec_copy = strdup(ctrspec); 2683 2684 r = spec_copy; 2685 ctrname = strsep(&r, ","); 2686 2687 /* 2688 * If a explicit class prefix was given by the user, restrict the 2689 * search for the event to the specified PMC class. 2690 */ 2691 ev = NULL; 2692 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2693 pcd = pmc_class_table[n]; 2694 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2695 strncasecmp(ctrname, pcd->pm_evc_name, 2696 pcd->pm_evc_name_size) == 0) { 2697 if ((ev = pmc_match_event_class(ctrname + 2698 pcd->pm_evc_name_size, pcd)) == NULL) { 2699 errno = EINVAL; 2700 goto out; 2701 } 2702 break; 2703 } 2704 } 2705 2706 /* 2707 * Otherwise, search for this event in all compatible PMC 2708 * classes. 2709 */ 2710 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2711 pcd = pmc_class_table[n]; 2712 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2713 ev = pmc_match_event_class(ctrname, pcd); 2714 } 2715 2716 if (ev == NULL) { 2717 errno = EINVAL; 2718 goto out; 2719 } 2720 2721 bzero(&pmc_config, sizeof(pmc_config)); 2722 pmc_config.pm_ev = ev->pm_ev_code; 2723 pmc_config.pm_class = pcd->pm_evc_class; 2724 pmc_config.pm_cpu = cpu; 2725 pmc_config.pm_mode = mode; 2726 pmc_config.pm_flags = flags; 2727 2728 if (PMC_IS_SAMPLING_MODE(mode)) 2729 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2730 2731 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2732 errno = EINVAL; 2733 goto out; 2734 } 2735 2736 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2737 goto out; 2738 2739 *pmcid = pmc_config.pm_pmcid; 2740 2741 retval = 0; 2742 2743 out: 2744 if (spec_copy) 2745 free(spec_copy); 2746 2747 return (retval); 2748} 2749 2750int 2751pmc_attach(pmc_id_t pmc, pid_t pid) 2752{ 2753 struct pmc_op_pmcattach pmc_attach_args; 2754 2755 pmc_attach_args.pm_pmc = pmc; 2756 pmc_attach_args.pm_pid = pid; 2757 2758 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2759} 2760 2761int 2762pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2763{ 2764 unsigned int i; 2765 enum pmc_class cl; 2766 2767 cl = PMC_ID_TO_CLASS(pmcid); 2768 for (i = 0; i < cpu_info.pm_nclass; i++) 2769 if (cpu_info.pm_classes[i].pm_class == cl) { 2770 *caps = cpu_info.pm_classes[i].pm_caps; 2771 return (0); 2772 } 2773 errno = EINVAL; 2774 return (-1); 2775} 2776 2777int 2778pmc_configure_logfile(int fd) 2779{ 2780 struct pmc_op_configurelog cla; 2781 2782 cla.pm_logfd = fd; 2783 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2784 return (-1); 2785 return (0); 2786} 2787 2788int 2789pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2790{ 2791 if (pmc_syscall == -1) { 2792 errno = ENXIO; 2793 return (-1); 2794 } 2795 2796 *pci = &cpu_info; 2797 return (0); 2798} 2799 2800int 2801pmc_detach(pmc_id_t pmc, pid_t pid) 2802{ 2803 struct pmc_op_pmcattach pmc_detach_args; 2804 2805 pmc_detach_args.pm_pmc = pmc; 2806 pmc_detach_args.pm_pid = pid; 2807 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2808} 2809 2810int 2811pmc_disable(int cpu, int pmc) 2812{ 2813 struct pmc_op_pmcadmin ssa; 2814 2815 ssa.pm_cpu = cpu; 2816 ssa.pm_pmc = pmc; 2817 ssa.pm_state = PMC_STATE_DISABLED; 2818 return (PMC_CALL(PMCADMIN, &ssa)); 2819} 2820 2821int 2822pmc_enable(int cpu, int pmc) 2823{ 2824 struct pmc_op_pmcadmin ssa; 2825 2826 ssa.pm_cpu = cpu; 2827 ssa.pm_pmc = pmc; 2828 ssa.pm_state = PMC_STATE_FREE; 2829 return (PMC_CALL(PMCADMIN, &ssa)); 2830} 2831 2832/* 2833 * Return a list of events known to a given PMC class. 'cl' is the 2834 * PMC class identifier, 'eventnames' is the returned list of 'const 2835 * char *' pointers pointing to the names of the events. 'nevents' is 2836 * the number of event name pointers returned. 2837 * 2838 * The space for 'eventnames' is allocated using malloc(3). The caller 2839 * is responsible for freeing this space when done. 2840 */ 2841int 2842pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2843 int *nevents) 2844{ 2845 int count; 2846 const char **names; 2847 const struct pmc_event_descr *ev; 2848 2849 switch (cl) 2850 { 2851 case PMC_CLASS_IAF: 2852 ev = iaf_event_table; 2853 count = PMC_EVENT_TABLE_SIZE(iaf); 2854 break; 2855 case PMC_CLASS_IAP: 2856 /* 2857 * Return the most appropriate set of event name 2858 * spellings for the current CPU. 2859 */ 2860 switch (cpu_info.pm_cputype) { 2861 default: 2862 case PMC_CPU_INTEL_ATOM: 2863 ev = atom_event_table; 2864 count = PMC_EVENT_TABLE_SIZE(atom); 2865 break; 2866 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2867 ev = atom_silvermont_event_table; 2868 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2869 break; 2870 case PMC_CPU_INTEL_CORE: 2871 ev = core_event_table; 2872 count = PMC_EVENT_TABLE_SIZE(core); 2873 break; 2874 case PMC_CPU_INTEL_CORE2: 2875 case PMC_CPU_INTEL_CORE2EXTREME: 2876 ev = core2_event_table; 2877 count = PMC_EVENT_TABLE_SIZE(core2); 2878 break; 2879 case PMC_CPU_INTEL_COREI7: 2880 ev = corei7_event_table; 2881 count = PMC_EVENT_TABLE_SIZE(corei7); 2882 break; 2883 case PMC_CPU_INTEL_NEHALEM_EX: 2884 ev = nehalem_ex_event_table; 2885 count = PMC_EVENT_TABLE_SIZE(nehalem_ex); 2886 break; 2887 case PMC_CPU_INTEL_HASWELL: 2888 ev = haswell_event_table; 2889 count = PMC_EVENT_TABLE_SIZE(haswell); 2890 break; 2891 case PMC_CPU_INTEL_HASWELL_XEON: 2892 ev = haswell_xeon_event_table; 2893 count = PMC_EVENT_TABLE_SIZE(haswell_xeon); 2894 break; 2895 case PMC_CPU_INTEL_IVYBRIDGE: 2896 ev = ivybridge_event_table; 2897 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2898 break; 2899 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2900 ev = ivybridge_xeon_event_table; 2901 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2902 break; 2903 case PMC_CPU_INTEL_SANDYBRIDGE: 2904 ev = sandybridge_event_table; 2905 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2906 break; 2907 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2908 ev = sandybridge_xeon_event_table; 2909 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2910 break; 2911 case PMC_CPU_INTEL_WESTMERE: 2912 ev = westmere_event_table; 2913 count = PMC_EVENT_TABLE_SIZE(westmere); 2914 break; 2915 case PMC_CPU_INTEL_WESTMERE_EX: 2916 ev = westmere_ex_event_table; 2917 count = PMC_EVENT_TABLE_SIZE(westmere_ex); 2918 break; 2919 } 2920 break; 2921 case PMC_CLASS_UCF: 2922 ev = ucf_event_table; 2923 count = PMC_EVENT_TABLE_SIZE(ucf); 2924 break; 2925 case PMC_CLASS_UCP: 2926 /* 2927 * Return the most appropriate set of event name 2928 * spellings for the current CPU. 2929 */ 2930 switch (cpu_info.pm_cputype) { 2931 default: 2932 case PMC_CPU_INTEL_COREI7: 2933 ev = corei7uc_event_table; 2934 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2935 break; 2936 case PMC_CPU_INTEL_HASWELL: 2937 ev = haswelluc_event_table; 2938 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2939 break; 2940 case PMC_CPU_INTEL_SANDYBRIDGE: 2941 ev = sandybridgeuc_event_table; 2942 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2943 break; 2944 case PMC_CPU_INTEL_WESTMERE: 2945 ev = westmereuc_event_table; 2946 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2947 break; 2948 } 2949 break; 2950 case PMC_CLASS_TSC: 2951 ev = tsc_event_table; 2952 count = PMC_EVENT_TABLE_SIZE(tsc); 2953 break; 2954 case PMC_CLASS_K7: 2955 ev = k7_event_table; 2956 count = PMC_EVENT_TABLE_SIZE(k7); 2957 break; 2958 case PMC_CLASS_K8: 2959 ev = k8_event_table; 2960 count = PMC_EVENT_TABLE_SIZE(k8); 2961 break; 2962 case PMC_CLASS_P4: 2963 ev = p4_event_table; 2964 count = PMC_EVENT_TABLE_SIZE(p4); 2965 break; 2966 case PMC_CLASS_P5: 2967 ev = p5_event_table; 2968 count = PMC_EVENT_TABLE_SIZE(p5); 2969 break; 2970 case PMC_CLASS_P6: 2971 ev = p6_event_table; 2972 count = PMC_EVENT_TABLE_SIZE(p6); 2973 break; 2974 case PMC_CLASS_XSCALE: 2975 ev = xscale_event_table; 2976 count = PMC_EVENT_TABLE_SIZE(xscale); 2977 break; 2978 case PMC_CLASS_ARMV7: 2979 ev = armv7_event_table; 2980 count = PMC_EVENT_TABLE_SIZE(armv7); 2981 break; 2982 case PMC_CLASS_ARMV8: 2983 switch (cpu_info.pm_cputype) { 2984 default: 2985 case PMC_CPU_ARMV8_CORTEX_A53: 2986 ev = cortex_a53_event_table; 2987 count = PMC_EVENT_TABLE_SIZE(cortex_a53); 2988 break; 2989 case PMC_CPU_ARMV8_CORTEX_A57: 2990 ev = cortex_a57_event_table; 2991 count = PMC_EVENT_TABLE_SIZE(cortex_a57); 2992 break; 2993 } 2994 break; 2995 case PMC_CLASS_MIPS24K: 2996 ev = mips24k_event_table; 2997 count = PMC_EVENT_TABLE_SIZE(mips24k); 2998 break; 2999 case PMC_CLASS_MIPS74K: 3000 ev = mips74k_event_table; 3001 count = PMC_EVENT_TABLE_SIZE(mips74k); 3002 break; 3003 case PMC_CLASS_OCTEON: 3004 ev = octeon_event_table; 3005 count = PMC_EVENT_TABLE_SIZE(octeon); 3006 break; 3007 case PMC_CLASS_PPC7450: 3008 ev = ppc7450_event_table; 3009 count = PMC_EVENT_TABLE_SIZE(ppc7450); 3010 break; 3011 case PMC_CLASS_PPC970: 3012 ev = ppc970_event_table; 3013 count = PMC_EVENT_TABLE_SIZE(ppc970); 3014 break; 3015 case PMC_CLASS_E500: 3016 ev = e500_event_table; 3017 count = PMC_EVENT_TABLE_SIZE(e500); 3018 break; 3019 case PMC_CLASS_SOFT: 3020 ev = soft_event_table; 3021 count = soft_event_info.pm_nevent; 3022 break; 3023 default: 3024 errno = EINVAL; 3025 return (-1); 3026 } 3027 3028 if ((names = malloc(count * sizeof(const char *))) == NULL) 3029 return (-1); 3030 3031 *eventnames = names; 3032 *nevents = count; 3033 3034 for (;count--; ev++, names++) 3035 *names = ev->pm_ev_name; 3036 3037 return (0); 3038} 3039 3040int 3041pmc_flush_logfile(void) 3042{ 3043 return (PMC_CALL(FLUSHLOG,0)); 3044} 3045 3046int 3047pmc_close_logfile(void) 3048{ 3049 return (PMC_CALL(CLOSELOG,0)); 3050} 3051 3052int 3053pmc_get_driver_stats(struct pmc_driverstats *ds) 3054{ 3055 struct pmc_op_getdriverstats gms; 3056 3057 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 3058 return (-1); 3059 3060 /* copy out fields in the current userland<->library interface */ 3061 ds->pm_intr_ignored = gms.pm_intr_ignored; 3062 ds->pm_intr_processed = gms.pm_intr_processed; 3063 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 3064 ds->pm_syscalls = gms.pm_syscalls; 3065 ds->pm_syscall_errors = gms.pm_syscall_errors; 3066 ds->pm_buffer_requests = gms.pm_buffer_requests; 3067 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 3068 ds->pm_log_sweeps = gms.pm_log_sweeps; 3069 return (0); 3070} 3071 3072int 3073pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 3074{ 3075 struct pmc_op_getmsr gm; 3076 3077 gm.pm_pmcid = pmc; 3078 if (PMC_CALL(PMCGETMSR, &gm) < 0) 3079 return (-1); 3080 *msr = gm.pm_msr; 3081 return (0); 3082} 3083 3084int 3085pmc_init(void) 3086{ 3087 int error, pmc_mod_id; 3088 unsigned int n; 3089 uint32_t abi_version; 3090 struct module_stat pmc_modstat; 3091 struct pmc_op_getcpuinfo op_cpu_info; 3092#if defined(__amd64__) || defined(__i386__) 3093 int cpu_has_iaf_counters; 3094 unsigned int t; 3095#endif 3096 3097 if (pmc_syscall != -1) /* already inited */ 3098 return (0); 3099 3100 /* retrieve the system call number from the KLD */ 3101 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 3102 return (-1); 3103 3104 pmc_modstat.version = sizeof(struct module_stat); 3105 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 3106 return (-1); 3107 3108 pmc_syscall = pmc_modstat.data.intval; 3109 3110 /* check the kernel module's ABI against our compiled-in version */ 3111 abi_version = PMC_VERSION; 3112 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 3113 return (pmc_syscall = -1); 3114 3115 /* ignore patch & minor numbers for the comparision */ 3116 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 3117 errno = EPROGMISMATCH; 3118 return (pmc_syscall = -1); 3119 } 3120 3121 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 3122 return (pmc_syscall = -1); 3123 3124 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 3125 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 3126 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 3127 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 3128 for (n = 0; n < cpu_info.pm_nclass; n++) 3129 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 3130 3131 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 3132 sizeof(struct pmc_class_descr *)); 3133 3134 if (pmc_class_table == NULL) 3135 return (-1); 3136 3137 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 3138 pmc_class_table[n] = NULL; 3139 3140 /* 3141 * Get soft events list. 3142 */ 3143 soft_event_info.pm_class = PMC_CLASS_SOFT; 3144 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 3145 return (pmc_syscall = -1); 3146 3147 /* Map soft events to static list. */ 3148 for (n = 0; n < soft_event_info.pm_nevent; n++) { 3149 soft_event_table[n].pm_ev_name = 3150 soft_event_info.pm_events[n].pm_ev_name; 3151 soft_event_table[n].pm_ev_code = 3152 soft_event_info.pm_events[n].pm_ev_code; 3153 } 3154 soft_class_table_descr.pm_evc_event_table_size = \ 3155 soft_event_info.pm_nevent; 3156 soft_class_table_descr.pm_evc_event_table = \ 3157 soft_event_table; 3158 3159 /* 3160 * Fill in the class table. 3161 */ 3162 n = 0; 3163 3164 /* Fill soft events information. */ 3165 pmc_class_table[n++] = &soft_class_table_descr; 3166#if defined(__amd64__) || defined(__i386__) 3167 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3168 pmc_class_table[n++] = &tsc_class_table_descr; 3169 3170 /* 3171 * Check if this CPU has fixed function counters. 3172 */ 3173 cpu_has_iaf_counters = 0; 3174 for (t = 0; t < cpu_info.pm_nclass; t++) 3175 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3176 cpu_info.pm_classes[t].pm_num > 0) 3177 cpu_has_iaf_counters = 1; 3178#endif 3179 3180#define PMC_MDEP_INIT(C) do { \ 3181 pmc_mdep_event_aliases = C##_aliases; \ 3182 pmc_mdep_class_list = C##_pmc_classes; \ 3183 pmc_mdep_class_list_size = \ 3184 PMC_TABLE_SIZE(C##_pmc_classes); \ 3185 } while (0) 3186 3187#define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3188 PMC_MDEP_INIT(C); \ 3189 pmc_class_table[n++] = &iaf_class_table_descr; \ 3190 if (!cpu_has_iaf_counters) \ 3191 pmc_mdep_event_aliases = \ 3192 C##_aliases_without_iaf; \ 3193 pmc_class_table[n] = &C##_class_table_descr; \ 3194 } while (0) 3195 3196 /* Configure the event name parser. */ 3197 switch (cpu_info.pm_cputype) { 3198#if defined(__i386__) 3199 case PMC_CPU_AMD_K7: 3200 PMC_MDEP_INIT(k7); 3201 pmc_class_table[n] = &k7_class_table_descr; 3202 break; 3203 case PMC_CPU_INTEL_P5: 3204 PMC_MDEP_INIT(p5); 3205 pmc_class_table[n] = &p5_class_table_descr; 3206 break; 3207 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3208 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3209 case PMC_CPU_INTEL_PIII: 3210 case PMC_CPU_INTEL_PM: 3211 PMC_MDEP_INIT(p6); 3212 pmc_class_table[n] = &p6_class_table_descr; 3213 break; 3214#endif 3215#if defined(__amd64__) || defined(__i386__) 3216 case PMC_CPU_AMD_K8: 3217 PMC_MDEP_INIT(k8); 3218 pmc_class_table[n] = &k8_class_table_descr; 3219 break; 3220 case PMC_CPU_INTEL_ATOM: 3221 PMC_MDEP_INIT_INTEL_V2(atom); 3222 break; 3223 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3224 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3225 break; 3226 case PMC_CPU_INTEL_CORE: 3227 PMC_MDEP_INIT(core); 3228 pmc_class_table[n] = &core_class_table_descr; 3229 break; 3230 case PMC_CPU_INTEL_CORE2: 3231 case PMC_CPU_INTEL_CORE2EXTREME: 3232 PMC_MDEP_INIT_INTEL_V2(core2); 3233 break; 3234 case PMC_CPU_INTEL_COREI7: 3235 pmc_class_table[n++] = &ucf_class_table_descr; 3236 pmc_class_table[n++] = &corei7uc_class_table_descr; 3237 PMC_MDEP_INIT_INTEL_V2(corei7); 3238 break; 3239 case PMC_CPU_INTEL_NEHALEM_EX: 3240 PMC_MDEP_INIT_INTEL_V2(nehalem_ex); 3241 break; 3242 case PMC_CPU_INTEL_HASWELL: 3243 pmc_class_table[n++] = &ucf_class_table_descr; 3244 pmc_class_table[n++] = &haswelluc_class_table_descr; 3245 PMC_MDEP_INIT_INTEL_V2(haswell); 3246 break; 3247 case PMC_CPU_INTEL_HASWELL_XEON: 3248 PMC_MDEP_INIT_INTEL_V2(haswell_xeon); 3249 break; 3250 case PMC_CPU_INTEL_IVYBRIDGE: 3251 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3252 break; 3253 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3254 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3255 break; 3256 case PMC_CPU_INTEL_SANDYBRIDGE: 3257 pmc_class_table[n++] = &ucf_class_table_descr; 3258 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3259 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3260 break; 3261 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3262 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3263 break; 3264 case PMC_CPU_INTEL_WESTMERE: 3265 pmc_class_table[n++] = &ucf_class_table_descr; 3266 pmc_class_table[n++] = &westmereuc_class_table_descr; 3267 PMC_MDEP_INIT_INTEL_V2(westmere); 3268 break; 3269 case PMC_CPU_INTEL_WESTMERE_EX: 3270 PMC_MDEP_INIT_INTEL_V2(westmere_ex); 3271 break; 3272 case PMC_CPU_INTEL_PIV: 3273 PMC_MDEP_INIT(p4); 3274 pmc_class_table[n] = &p4_class_table_descr; 3275 break; 3276#endif 3277 case PMC_CPU_GENERIC: 3278 PMC_MDEP_INIT(generic); 3279 break; 3280#if defined(__arm__) 3281#if defined(__XSCALE__) 3282 case PMC_CPU_INTEL_XSCALE: 3283 PMC_MDEP_INIT(xscale); 3284 pmc_class_table[n] = &xscale_class_table_descr; 3285 break; 3286#endif 3287 case PMC_CPU_ARMV7: 3288 PMC_MDEP_INIT(armv7); 3289 pmc_class_table[n] = &armv7_class_table_descr; 3290 break; 3291#endif 3292#if defined(__aarch64__) 3293 case PMC_CPU_ARMV8_CORTEX_A53: 3294 PMC_MDEP_INIT(cortex_a53); 3295 pmc_class_table[n] = &cortex_a53_class_table_descr; 3296 break; 3297 case PMC_CPU_ARMV8_CORTEX_A57: 3298 PMC_MDEP_INIT(cortex_a57); 3299 pmc_class_table[n] = &cortex_a57_class_table_descr; 3300 break; 3301#endif 3302#if defined(__mips__) 3303 case PMC_CPU_MIPS_24K: 3304 PMC_MDEP_INIT(mips24k); 3305 pmc_class_table[n] = &mips24k_class_table_descr; 3306 break; 3307 case PMC_CPU_MIPS_74K: 3308 PMC_MDEP_INIT(mips74k); 3309 pmc_class_table[n] = &mips74k_class_table_descr; 3310 break; 3311 case PMC_CPU_MIPS_OCTEON: 3312 PMC_MDEP_INIT(octeon); 3313 pmc_class_table[n] = &octeon_class_table_descr; 3314 break; 3315#endif /* __mips__ */ 3316#if defined(__powerpc__) 3317 case PMC_CPU_PPC_7450: 3318 PMC_MDEP_INIT(ppc7450); 3319 pmc_class_table[n] = &ppc7450_class_table_descr; 3320 break; 3321 case PMC_CPU_PPC_970: 3322 PMC_MDEP_INIT(ppc970); 3323 pmc_class_table[n] = &ppc970_class_table_descr; 3324 break; 3325 case PMC_CPU_PPC_E500: 3326 PMC_MDEP_INIT(e500); 3327 pmc_class_table[n] = &e500_class_table_descr; 3328 break; 3329#endif 3330 default: 3331 /* 3332 * Some kind of CPU this version of the library knows nothing 3333 * about. This shouldn't happen since the abi version check 3334 * should have caught this. 3335 */ 3336 errno = ENXIO; 3337 return (pmc_syscall = -1); 3338 } 3339 3340 return (0); 3341} 3342 3343const char * 3344pmc_name_of_capability(enum pmc_caps cap) 3345{ 3346 int i; 3347 3348 /* 3349 * 'cap' should have a single bit set and should be in 3350 * range. 3351 */ 3352 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3353 cap > PMC_CAP_LAST) { 3354 errno = EINVAL; 3355 return (NULL); 3356 } 3357 3358 i = ffs(cap); 3359 return (pmc_capability_names[i - 1]); 3360} 3361 3362const char * 3363pmc_name_of_class(enum pmc_class pc) 3364{ 3365 if ((int) pc >= PMC_CLASS_FIRST && 3366 pc <= PMC_CLASS_LAST) 3367 return (pmc_class_names[pc]); 3368 3369 errno = EINVAL; 3370 return (NULL); 3371} 3372 3373const char * 3374pmc_name_of_cputype(enum pmc_cputype cp) 3375{ 3376 size_t n; 3377 3378 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3379 if (cp == pmc_cputype_names[n].pm_cputype) 3380 return (pmc_cputype_names[n].pm_name); 3381 3382 errno = EINVAL; 3383 return (NULL); 3384} 3385 3386const char * 3387pmc_name_of_disposition(enum pmc_disp pd) 3388{ 3389 if ((int) pd >= PMC_DISP_FIRST && 3390 pd <= PMC_DISP_LAST) 3391 return (pmc_disposition_names[pd]); 3392 3393 errno = EINVAL; 3394 return (NULL); 3395} 3396 3397const char * 3398_pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3399{ 3400 const struct pmc_event_descr *ev, *evfence; 3401 3402 ev = evfence = NULL; 3403 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3404 ev = iaf_event_table; 3405 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3406 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3407 switch (cpu) { 3408 case PMC_CPU_INTEL_ATOM: 3409 ev = atom_event_table; 3410 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3411 break; 3412 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3413 ev = atom_silvermont_event_table; 3414 evfence = atom_silvermont_event_table + 3415 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3416 break; 3417 case PMC_CPU_INTEL_CORE: 3418 ev = core_event_table; 3419 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3420 break; 3421 case PMC_CPU_INTEL_CORE2: 3422 case PMC_CPU_INTEL_CORE2EXTREME: 3423 ev = core2_event_table; 3424 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3425 break; 3426 case PMC_CPU_INTEL_COREI7: 3427 ev = corei7_event_table; 3428 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3429 break; 3430 case PMC_CPU_INTEL_NEHALEM_EX: 3431 ev = nehalem_ex_event_table; 3432 evfence = nehalem_ex_event_table + 3433 PMC_EVENT_TABLE_SIZE(nehalem_ex); 3434 break; 3435 case PMC_CPU_INTEL_HASWELL: 3436 ev = haswell_event_table; 3437 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3438 break; 3439 case PMC_CPU_INTEL_HASWELL_XEON: 3440 ev = haswell_xeon_event_table; 3441 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon); 3442 break; 3443 3444 case PMC_CPU_INTEL_IVYBRIDGE: 3445 ev = ivybridge_event_table; 3446 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3447 break; 3448 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3449 ev = ivybridge_xeon_event_table; 3450 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3451 break; 3452 case PMC_CPU_INTEL_SANDYBRIDGE: 3453 ev = sandybridge_event_table; 3454 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3455 break; 3456 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3457 ev = sandybridge_xeon_event_table; 3458 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3459 break; 3460 case PMC_CPU_INTEL_WESTMERE: 3461 ev = westmere_event_table; 3462 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3463 break; 3464 case PMC_CPU_INTEL_WESTMERE_EX: 3465 ev = westmere_ex_event_table; 3466 evfence = westmere_ex_event_table + 3467 PMC_EVENT_TABLE_SIZE(westmere_ex); 3468 break; 3469 default: /* Unknown CPU type. */ 3470 break; 3471 } 3472 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3473 ev = ucf_event_table; 3474 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3475 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3476 switch (cpu) { 3477 case PMC_CPU_INTEL_COREI7: 3478 ev = corei7uc_event_table; 3479 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3480 break; 3481 case PMC_CPU_INTEL_SANDYBRIDGE: 3482 ev = sandybridgeuc_event_table; 3483 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3484 break; 3485 case PMC_CPU_INTEL_WESTMERE: 3486 ev = westmereuc_event_table; 3487 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3488 break; 3489 default: /* Unknown CPU type. */ 3490 break; 3491 } 3492 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3493 ev = k7_event_table; 3494 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3495 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3496 ev = k8_event_table; 3497 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3498 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3499 ev = p4_event_table; 3500 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3501 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3502 ev = p5_event_table; 3503 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3504 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3505 ev = p6_event_table; 3506 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3507 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3508 ev = xscale_event_table; 3509 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3510 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { 3511 ev = armv7_event_table; 3512 evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); 3513 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { 3514 switch (cpu) { 3515 case PMC_CPU_ARMV8_CORTEX_A53: 3516 ev = cortex_a53_event_table; 3517 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); 3518 break; 3519 case PMC_CPU_ARMV8_CORTEX_A57: 3520 ev = cortex_a57_event_table; 3521 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); 3522 break; 3523 default: /* Unknown CPU type. */ 3524 break; 3525 } 3526 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3527 ev = mips24k_event_table; 3528 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3529 } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { 3530 ev = mips74k_event_table; 3531 evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); 3532 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3533 ev = octeon_event_table; 3534 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3535 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3536 ev = ppc7450_event_table; 3537 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3538 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3539 ev = ppc970_event_table; 3540 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3541 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) { 3542 ev = e500_event_table; 3543 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500); 3544 } else if (pe == PMC_EV_TSC_TSC) { 3545 ev = tsc_event_table; 3546 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3547 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3548 ev = soft_event_table; 3549 evfence = soft_event_table + soft_event_info.pm_nevent; 3550 } 3551 3552 for (; ev != evfence; ev++) 3553 if (pe == ev->pm_ev_code) 3554 return (ev->pm_ev_name); 3555 3556 return (NULL); 3557} 3558 3559const char * 3560pmc_name_of_event(enum pmc_event pe) 3561{ 3562 const char *n; 3563 3564 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3565 return (n); 3566 3567 errno = EINVAL; 3568 return (NULL); 3569} 3570 3571const char * 3572pmc_name_of_mode(enum pmc_mode pm) 3573{ 3574 if ((int) pm >= PMC_MODE_FIRST && 3575 pm <= PMC_MODE_LAST) 3576 return (pmc_mode_names[pm]); 3577 3578 errno = EINVAL; 3579 return (NULL); 3580} 3581 3582const char * 3583pmc_name_of_state(enum pmc_state ps) 3584{ 3585 if ((int) ps >= PMC_STATE_FIRST && 3586 ps <= PMC_STATE_LAST) 3587 return (pmc_state_names[ps]); 3588 3589 errno = EINVAL; 3590 return (NULL); 3591} 3592 3593int 3594pmc_ncpu(void) 3595{ 3596 if (pmc_syscall == -1) { 3597 errno = ENXIO; 3598 return (-1); 3599 } 3600 3601 return (cpu_info.pm_ncpu); 3602} 3603 3604int 3605pmc_npmc(int cpu) 3606{ 3607 if (pmc_syscall == -1) { 3608 errno = ENXIO; 3609 return (-1); 3610 } 3611 3612 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3613 errno = EINVAL; 3614 return (-1); 3615 } 3616 3617 return (cpu_info.pm_npmc); 3618} 3619 3620int 3621pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3622{ 3623 int nbytes, npmc; 3624 struct pmc_op_getpmcinfo *pmci; 3625 3626 if ((npmc = pmc_npmc(cpu)) < 0) 3627 return (-1); 3628 3629 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3630 npmc * sizeof(struct pmc_info); 3631 3632 if ((pmci = calloc(1, nbytes)) == NULL) 3633 return (-1); 3634 3635 pmci->pm_cpu = cpu; 3636 3637 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3638 free(pmci); 3639 return (-1); 3640 } 3641 3642 /* kernel<->library, library<->userland interfaces are identical */ 3643 *ppmci = (struct pmc_pmcinfo *) pmci; 3644 return (0); 3645} 3646 3647int 3648pmc_read(pmc_id_t pmc, pmc_value_t *value) 3649{ 3650 struct pmc_op_pmcrw pmc_read_op; 3651 3652 pmc_read_op.pm_pmcid = pmc; 3653 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3654 pmc_read_op.pm_value = -1; 3655 3656 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3657 return (-1); 3658 3659 *value = pmc_read_op.pm_value; 3660 return (0); 3661} 3662 3663int 3664pmc_release(pmc_id_t pmc) 3665{ 3666 struct pmc_op_simple pmc_release_args; 3667 3668 pmc_release_args.pm_pmcid = pmc; 3669 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3670} 3671 3672int 3673pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3674{ 3675 struct pmc_op_pmcrw pmc_rw_op; 3676 3677 pmc_rw_op.pm_pmcid = pmc; 3678 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3679 pmc_rw_op.pm_value = newvalue; 3680 3681 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3682 return (-1); 3683 3684 *oldvaluep = pmc_rw_op.pm_value; 3685 return (0); 3686} 3687 3688int 3689pmc_set(pmc_id_t pmc, pmc_value_t value) 3690{ 3691 struct pmc_op_pmcsetcount sc; 3692 3693 sc.pm_pmcid = pmc; 3694 sc.pm_count = value; 3695 3696 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3697 return (-1); 3698 return (0); 3699} 3700 3701int 3702pmc_start(pmc_id_t pmc) 3703{ 3704 struct pmc_op_simple pmc_start_args; 3705 3706 pmc_start_args.pm_pmcid = pmc; 3707 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3708} 3709 3710int 3711pmc_stop(pmc_id_t pmc) 3712{ 3713 struct pmc_op_simple pmc_stop_args; 3714 3715 pmc_stop_args.pm_pmcid = pmc; 3716 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3717} 3718 3719int 3720pmc_width(pmc_id_t pmcid, uint32_t *width) 3721{ 3722 unsigned int i; 3723 enum pmc_class cl; 3724 3725 cl = PMC_ID_TO_CLASS(pmcid); 3726 for (i = 0; i < cpu_info.pm_nclass; i++) 3727 if (cpu_info.pm_classes[i].pm_class == cl) { 3728 *width = cpu_info.pm_classes[i].pm_width; 3729 return (0); 3730 } 3731 errno = EINVAL; 3732 return (-1); 3733} 3734 3735int 3736pmc_write(pmc_id_t pmc, pmc_value_t value) 3737{ 3738 struct pmc_op_pmcrw pmc_write_op; 3739 3740 pmc_write_op.pm_pmcid = pmc; 3741 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3742 pmc_write_op.pm_value = value; 3743 return (PMC_CALL(PMCRW, &pmc_write_op)); 3744} 3745 3746int 3747pmc_writelog(uint32_t userdata) 3748{ 3749 struct pmc_op_writelog wl; 3750 3751 wl.pm_userdata = userdata; 3752 return (PMC_CALL(WRITELOG, &wl)); 3753} 3754