libpmc.c revision 263446
1/*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 263446 2014-03-20 20:51:08Z hiren $"); 29 30#include <sys/types.h> 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/pmc.h> 34#include <sys/syscall.h> 35 36#include <ctype.h> 37#include <errno.h> 38#include <fcntl.h> 39#include <pmc.h> 40#include <stdio.h> 41#include <stdlib.h> 42#include <string.h> 43#include <strings.h> 44#include <unistd.h> 45 46#include "libpmcinternal.h" 47 48/* Function prototypes */ 49#if defined(__i386__) 50static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 51 struct pmc_op_pmcallocate *_pmc_config); 52#endif 53#if defined(__amd64__) || defined(__i386__) 54static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 55 struct pmc_op_pmcallocate *_pmc_config); 56static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 57 struct pmc_op_pmcallocate *_pmc_config); 58static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 59 struct pmc_op_pmcallocate *_pmc_config); 60static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 61 struct pmc_op_pmcallocate *_pmc_config); 62static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 63 struct pmc_op_pmcallocate *_pmc_config); 64static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 65 struct pmc_op_pmcallocate *_pmc_config); 66#endif 67#if defined(__i386__) 68static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 69 struct pmc_op_pmcallocate *_pmc_config); 70static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 71 struct pmc_op_pmcallocate *_pmc_config); 72#endif 73#if defined(__amd64__) || defined(__i386__) 74static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 75 struct pmc_op_pmcallocate *_pmc_config); 76#endif 77#if defined(__XSCALE__) 78static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 79 struct pmc_op_pmcallocate *_pmc_config); 80#endif 81#if defined(__mips__) 82static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84#endif /* __mips__ */ 85static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 86 struct pmc_op_pmcallocate *_pmc_config); 87 88#if defined(__powerpc__) 89static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec, 90 struct pmc_op_pmcallocate *_pmc_config); 91#endif /* __powerpc__ */ 92 93#define PMC_CALL(cmd, params) \ 94 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 95 96/* 97 * Event aliases provide a way for the user to ask for generic events 98 * like "cache-misses", or "instructions-retired". These aliases are 99 * mapped to the appropriate canonical event descriptions using a 100 * lookup table. 101 */ 102struct pmc_event_alias { 103 const char *pm_alias; 104 const char *pm_spec; 105}; 106 107static const struct pmc_event_alias *pmc_mdep_event_aliases; 108 109/* 110 * The pmc_event_descr structure maps symbolic names known to the user 111 * to integer codes used by the PMC KLD. 112 */ 113struct pmc_event_descr { 114 const char *pm_ev_name; 115 enum pmc_event pm_ev_code; 116}; 117 118/* 119 * The pmc_class_descr structure maps class name prefixes for 120 * event names to event tables and other PMC class data. 121 */ 122struct pmc_class_descr { 123 const char *pm_evc_name; 124 size_t pm_evc_name_size; 125 enum pmc_class pm_evc_class; 126 const struct pmc_event_descr *pm_evc_event_table; 127 size_t pm_evc_event_table_size; 128 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 129 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 130}; 131 132#define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 133#define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 134 135#undef __PMC_EV 136#define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 137 138/* 139 * PMC_CLASSDEP_TABLE(NAME, CLASS) 140 * 141 * Define a table mapping event names and aliases to HWPMC event IDs. 142 */ 143#define PMC_CLASSDEP_TABLE(N, C) \ 144 static const struct pmc_event_descr N##_event_table[] = \ 145 { \ 146 __PMC_EV_##C() \ 147 } 148 149PMC_CLASSDEP_TABLE(iaf, IAF); 150PMC_CLASSDEP_TABLE(k7, K7); 151PMC_CLASSDEP_TABLE(k8, K8); 152PMC_CLASSDEP_TABLE(p4, P4); 153PMC_CLASSDEP_TABLE(p5, P5); 154PMC_CLASSDEP_TABLE(p6, P6); 155PMC_CLASSDEP_TABLE(xscale, XSCALE); 156PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 157PMC_CLASSDEP_TABLE(octeon, OCTEON); 158PMC_CLASSDEP_TABLE(ucf, UCF); 159PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 160PMC_CLASSDEP_TABLE(ppc970, PPC970); 161 162static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 163 164#undef __PMC_EV_ALIAS 165#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 166 167static const struct pmc_event_descr atom_event_table[] = 168{ 169 __PMC_EV_ALIAS_ATOM() 170}; 171 172static const struct pmc_event_descr atom_silvermont_event_table[] = 173{ 174 __PMC_EV_ALIAS_ATOM_SILVERMONT() 175}; 176 177static const struct pmc_event_descr core_event_table[] = 178{ 179 __PMC_EV_ALIAS_CORE() 180}; 181 182 183static const struct pmc_event_descr core2_event_table[] = 184{ 185 __PMC_EV_ALIAS_CORE2() 186}; 187 188static const struct pmc_event_descr corei7_event_table[] = 189{ 190 __PMC_EV_ALIAS_COREI7() 191}; 192 193static const struct pmc_event_descr haswell_event_table[] = 194{ 195 __PMC_EV_ALIAS_HASWELL() 196}; 197 198static const struct pmc_event_descr ivybridge_event_table[] = 199{ 200 __PMC_EV_ALIAS_IVYBRIDGE() 201}; 202 203static const struct pmc_event_descr ivybridge_xeon_event_table[] = 204{ 205 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 206}; 207 208static const struct pmc_event_descr sandybridge_event_table[] = 209{ 210 __PMC_EV_ALIAS_SANDYBRIDGE() 211}; 212 213static const struct pmc_event_descr sandybridge_xeon_event_table[] = 214{ 215 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 216}; 217 218static const struct pmc_event_descr westmere_event_table[] = 219{ 220 __PMC_EV_ALIAS_WESTMERE() 221}; 222 223static const struct pmc_event_descr corei7uc_event_table[] = 224{ 225 __PMC_EV_ALIAS_COREI7UC() 226}; 227 228static const struct pmc_event_descr haswelluc_event_table[] = 229{ 230 __PMC_EV_ALIAS_HASWELLUC() 231}; 232 233static const struct pmc_event_descr sandybridgeuc_event_table[] = 234{ 235 __PMC_EV_ALIAS_SANDYBRIDGEUC() 236}; 237 238static const struct pmc_event_descr westmereuc_event_table[] = 239{ 240 __PMC_EV_ALIAS_WESTMEREUC() 241}; 242 243/* 244 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 245 * 246 * Map a CPU to the PMC classes it supports. 247 */ 248#define PMC_MDEP_TABLE(N,C,...) \ 249 static const enum pmc_class N##_pmc_classes[] = { \ 250 PMC_CLASS_##C, __VA_ARGS__ \ 251 } 252 253PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 254PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 255PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 256PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 257PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 258PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 259PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 260PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 261PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 262PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 263PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 264PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 265PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 266PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 267PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 268PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 269PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 270PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 271PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 272PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); 273PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970); 274PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 275 276static const struct pmc_event_descr tsc_event_table[] = 277{ 278 __PMC_EV_TSC() 279}; 280 281#undef PMC_CLASS_TABLE_DESC 282#define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 283static const struct pmc_class_descr NAME##_class_table_descr = \ 284 { \ 285 .pm_evc_name = #CLASS "-", \ 286 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 287 .pm_evc_class = PMC_CLASS_##CLASS , \ 288 .pm_evc_event_table = EVENTS##_event_table , \ 289 .pm_evc_event_table_size = \ 290 PMC_EVENT_TABLE_SIZE(EVENTS), \ 291 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 292 } 293 294#if defined(__i386__) || defined(__amd64__) 295PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 296PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 297PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap); 298PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 299PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 300PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 301PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); 302PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 303PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 304PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 305PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 306PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 307PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 308PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 309PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); 310PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 311PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 312#endif 313#if defined(__i386__) 314PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 315#endif 316#if defined(__i386__) || defined(__amd64__) 317PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 318PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 319#endif 320#if defined(__i386__) 321PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 322PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 323#endif 324#if defined(__i386__) || defined(__amd64__) 325PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 326#endif 327#if defined(__XSCALE__) 328PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 329#endif 330#if defined(__mips__) 331PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 332PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 333#endif /* __mips__ */ 334#if defined(__powerpc__) 335PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); 336PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); 337#endif 338 339static struct pmc_class_descr soft_class_table_descr = 340{ 341 .pm_evc_name = "SOFT-", 342 .pm_evc_name_size = sizeof("SOFT-") - 1, 343 .pm_evc_class = PMC_CLASS_SOFT, 344 .pm_evc_event_table = NULL, 345 .pm_evc_event_table_size = 0, 346 .pm_evc_allocate_pmc = soft_allocate_pmc 347}; 348 349#undef PMC_CLASS_TABLE_DESC 350 351static const struct pmc_class_descr **pmc_class_table; 352#define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 353 354static const enum pmc_class *pmc_mdep_class_list; 355static size_t pmc_mdep_class_list_size; 356 357/* 358 * Mapping tables, mapping enumeration values to human readable 359 * strings. 360 */ 361 362static const char * pmc_capability_names[] = { 363#undef __PMC_CAP 364#define __PMC_CAP(N,V,D) #N , 365 __PMC_CAPS() 366}; 367 368static const char * pmc_class_names[] = { 369#undef __PMC_CLASS 370#define __PMC_CLASS(C) #C , 371 __PMC_CLASSES() 372}; 373 374struct pmc_cputype_map { 375 enum pmc_cputype pm_cputype; 376 const char *pm_name; 377}; 378 379static const struct pmc_cputype_map pmc_cputype_names[] = { 380#undef __PMC_CPU 381#define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 382 __PMC_CPUS() 383}; 384 385static const char * pmc_disposition_names[] = { 386#undef __PMC_DISP 387#define __PMC_DISP(D) #D , 388 __PMC_DISPOSITIONS() 389}; 390 391static const char * pmc_mode_names[] = { 392#undef __PMC_MODE 393#define __PMC_MODE(M,N) #M , 394 __PMC_MODES() 395}; 396 397static const char * pmc_state_names[] = { 398#undef __PMC_STATE 399#define __PMC_STATE(S) #S , 400 __PMC_STATES() 401}; 402 403/* 404 * Filled in by pmc_init(). 405 */ 406static int pmc_syscall = -1; 407static struct pmc_cpuinfo cpu_info; 408static struct pmc_op_getdyneventinfo soft_event_info; 409 410/* Event masks for events */ 411struct pmc_masks { 412 const char *pm_name; 413 const uint64_t pm_value; 414}; 415#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 416#define NULLMASK { .pm_name = NULL } 417 418#if defined(__amd64__) || defined(__i386__) 419static int 420pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 421{ 422 const struct pmc_masks *pm; 423 char *q, *r; 424 int c; 425 426 if (pmask == NULL) /* no mask keywords */ 427 return (-1); 428 q = strchr(p, '='); /* skip '=' */ 429 if (*++q == '\0') /* no more data */ 430 return (-1); 431 c = 0; /* count of mask keywords seen */ 432 while ((r = strsep(&q, "+")) != NULL) { 433 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 434 pm++) 435 ; 436 if (pm->pm_name == NULL) /* not found */ 437 return (-1); 438 *evmask |= pm->pm_value; 439 c++; 440 } 441 return (c); 442} 443#endif 444 445#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 446#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 447#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 448 449#if defined(__i386__) 450 451/* 452 * AMD K7 (Athlon) CPUs. 453 */ 454 455static struct pmc_event_alias k7_aliases[] = { 456 EV_ALIAS("branches", "k7-retired-branches"), 457 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 458 EV_ALIAS("cycles", "tsc"), 459 EV_ALIAS("dc-misses", "k7-dc-misses"), 460 EV_ALIAS("ic-misses", "k7-ic-misses"), 461 EV_ALIAS("instructions", "k7-retired-instructions"), 462 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 463 EV_ALIAS(NULL, NULL) 464}; 465 466#define K7_KW_COUNT "count" 467#define K7_KW_EDGE "edge" 468#define K7_KW_INV "inv" 469#define K7_KW_OS "os" 470#define K7_KW_UNITMASK "unitmask" 471#define K7_KW_USR "usr" 472 473static int 474k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 475 struct pmc_op_pmcallocate *pmc_config) 476{ 477 char *e, *p, *q; 478 int c, has_unitmask; 479 uint32_t count, unitmask; 480 481 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 482 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 483 484 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 485 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 486 pe == PMC_EV_K7_DC_WRITEBACKS) { 487 has_unitmask = 1; 488 unitmask = AMD_PMC_UNITMASK_MOESI; 489 } else 490 unitmask = has_unitmask = 0; 491 492 while ((p = strsep(&ctrspec, ",")) != NULL) { 493 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 494 q = strchr(p, '='); 495 if (*++q == '\0') /* skip '=' */ 496 return (-1); 497 498 count = strtol(q, &e, 0); 499 if (e == q || *e != '\0') 500 return (-1); 501 502 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 503 pmc_config->pm_md.pm_amd.pm_amd_config |= 504 AMD_PMC_TO_COUNTER(count); 505 506 } else if (KWMATCH(p, K7_KW_EDGE)) { 507 pmc_config->pm_caps |= PMC_CAP_EDGE; 508 } else if (KWMATCH(p, K7_KW_INV)) { 509 pmc_config->pm_caps |= PMC_CAP_INVERT; 510 } else if (KWMATCH(p, K7_KW_OS)) { 511 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 512 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 513 if (has_unitmask == 0) 514 return (-1); 515 unitmask = 0; 516 q = strchr(p, '='); 517 if (*++q == '\0') /* skip '=' */ 518 return (-1); 519 520 while ((c = tolower(*q++)) != 0) 521 if (c == 'm') 522 unitmask |= AMD_PMC_UNITMASK_M; 523 else if (c == 'o') 524 unitmask |= AMD_PMC_UNITMASK_O; 525 else if (c == 'e') 526 unitmask |= AMD_PMC_UNITMASK_E; 527 else if (c == 's') 528 unitmask |= AMD_PMC_UNITMASK_S; 529 else if (c == 'i') 530 unitmask |= AMD_PMC_UNITMASK_I; 531 else if (c == '+') 532 continue; 533 else 534 return (-1); 535 536 if (unitmask == 0) 537 return (-1); 538 539 } else if (KWMATCH(p, K7_KW_USR)) { 540 pmc_config->pm_caps |= PMC_CAP_USER; 541 } else 542 return (-1); 543 } 544 545 if (has_unitmask) { 546 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 547 pmc_config->pm_md.pm_amd.pm_amd_config |= 548 AMD_PMC_TO_UNITMASK(unitmask); 549 } 550 551 return (0); 552 553} 554 555#endif 556 557#if defined(__amd64__) || defined(__i386__) 558 559/* 560 * Intel Core (Family 6, Model E) PMCs. 561 */ 562 563static struct pmc_event_alias core_aliases[] = { 564 EV_ALIAS("branches", "iap-br-instr-ret"), 565 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 566 EV_ALIAS("cycles", "tsc-tsc"), 567 EV_ALIAS("ic-misses", "iap-icache-misses"), 568 EV_ALIAS("instructions", "iap-instr-ret"), 569 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 570 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 571 EV_ALIAS(NULL, NULL) 572}; 573 574/* 575 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 576 * and Atom (Family 6, model 1CH) PMCs. 577 * 578 * We map aliases to events on the fixed-function counters if these 579 * are present. Note that not all CPUs in this family contain fixed-function 580 * counters. 581 */ 582 583static struct pmc_event_alias core2_aliases[] = { 584 EV_ALIAS("branches", "iap-br-inst-retired.any"), 585 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 586 EV_ALIAS("cycles", "tsc-tsc"), 587 EV_ALIAS("ic-misses", "iap-l1i-misses"), 588 EV_ALIAS("instructions", "iaf-instr-retired.any"), 589 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 590 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 591 EV_ALIAS(NULL, NULL) 592}; 593 594static struct pmc_event_alias core2_aliases_without_iaf[] = { 595 EV_ALIAS("branches", "iap-br-inst-retired.any"), 596 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 597 EV_ALIAS("cycles", "tsc-tsc"), 598 EV_ALIAS("ic-misses", "iap-l1i-misses"), 599 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 600 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 601 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 602 EV_ALIAS(NULL, NULL) 603}; 604 605#define atom_aliases core2_aliases 606#define atom_aliases_without_iaf core2_aliases_without_iaf 607#define atom_silvermont_aliases core2_aliases 608#define atom_silvermont_aliases_without_iaf core2_aliases_without_iaf 609#define corei7_aliases core2_aliases 610#define corei7_aliases_without_iaf core2_aliases_without_iaf 611#define haswell_aliases core2_aliases 612#define haswell_aliases_without_iaf core2_aliases_without_iaf 613#define ivybridge_aliases core2_aliases 614#define ivybridge_aliases_without_iaf core2_aliases_without_iaf 615#define ivybridge_xeon_aliases core2_aliases 616#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 617#define sandybridge_aliases core2_aliases 618#define sandybridge_aliases_without_iaf core2_aliases_without_iaf 619#define sandybridge_xeon_aliases core2_aliases 620#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 621#define westmere_aliases core2_aliases 622#define westmere_aliases_without_iaf core2_aliases_without_iaf 623 624#define IAF_KW_OS "os" 625#define IAF_KW_USR "usr" 626#define IAF_KW_ANYTHREAD "anythread" 627 628/* 629 * Parse an event specifier for Intel fixed function counters. 630 */ 631static int 632iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 633 struct pmc_op_pmcallocate *pmc_config) 634{ 635 char *p; 636 637 (void) pe; 638 639 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 640 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 641 642 while ((p = strsep(&ctrspec, ",")) != NULL) { 643 if (KWMATCH(p, IAF_KW_OS)) 644 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 645 else if (KWMATCH(p, IAF_KW_USR)) 646 pmc_config->pm_caps |= PMC_CAP_USER; 647 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 648 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 649 else 650 return (-1); 651 } 652 653 return (0); 654} 655 656/* 657 * Core/Core2 support. 658 */ 659 660#define IAP_KW_AGENT "agent" 661#define IAP_KW_ANYTHREAD "anythread" 662#define IAP_KW_CACHESTATE "cachestate" 663#define IAP_KW_CMASK "cmask" 664#define IAP_KW_CORE "core" 665#define IAP_KW_EDGE "edge" 666#define IAP_KW_INV "inv" 667#define IAP_KW_OS "os" 668#define IAP_KW_PREFETCH "prefetch" 669#define IAP_KW_SNOOPRESPONSE "snoopresponse" 670#define IAP_KW_SNOOPTYPE "snooptype" 671#define IAP_KW_TRANSITION "trans" 672#define IAP_KW_USR "usr" 673#define IAP_KW_RSP "rsp" 674 675static struct pmc_masks iap_core_mask[] = { 676 PMCMASK(all, (0x3 << 14)), 677 PMCMASK(this, (0x1 << 14)), 678 NULLMASK 679}; 680 681static struct pmc_masks iap_agent_mask[] = { 682 PMCMASK(this, 0), 683 PMCMASK(any, (0x1 << 13)), 684 NULLMASK 685}; 686 687static struct pmc_masks iap_prefetch_mask[] = { 688 PMCMASK(both, (0x3 << 12)), 689 PMCMASK(only, (0x1 << 12)), 690 PMCMASK(exclude, 0), 691 NULLMASK 692}; 693 694static struct pmc_masks iap_cachestate_mask[] = { 695 PMCMASK(i, (1 << 8)), 696 PMCMASK(s, (1 << 9)), 697 PMCMASK(e, (1 << 10)), 698 PMCMASK(m, (1 << 11)), 699 NULLMASK 700}; 701 702static struct pmc_masks iap_snoopresponse_mask[] = { 703 PMCMASK(clean, (1 << 8)), 704 PMCMASK(hit, (1 << 9)), 705 PMCMASK(hitm, (1 << 11)), 706 NULLMASK 707}; 708 709static struct pmc_masks iap_snooptype_mask[] = { 710 PMCMASK(cmp2s, (1 << 8)), 711 PMCMASK(cmp2i, (1 << 9)), 712 NULLMASK 713}; 714 715static struct pmc_masks iap_transition_mask[] = { 716 PMCMASK(any, 0x00), 717 PMCMASK(frequency, 0x10), 718 NULLMASK 719}; 720 721static struct pmc_masks iap_rsp_mask_i7_wm[] = { 722 PMCMASK(DMND_DATA_RD, (1 << 0)), 723 PMCMASK(DMND_RFO, (1 << 1)), 724 PMCMASK(DMND_IFETCH, (1 << 2)), 725 PMCMASK(WB, (1 << 3)), 726 PMCMASK(PF_DATA_RD, (1 << 4)), 727 PMCMASK(PF_RFO, (1 << 5)), 728 PMCMASK(PF_IFETCH, (1 << 6)), 729 PMCMASK(OTHER, (1 << 7)), 730 PMCMASK(UNCORE_HIT, (1 << 8)), 731 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 732 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 733 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 734 PMCMASK(REMOTE_DRAM, (1 << 13)), 735 PMCMASK(LOCAL_DRAM, (1 << 14)), 736 PMCMASK(NON_DRAM, (1 << 15)), 737 NULLMASK 738}; 739 740static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 741 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 742 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 743 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 744 PMCMASK(REQ_WB, (1ULL << 3)), 745 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 746 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 747 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 748 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 749 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 750 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 751 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 752 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 753 PMCMASK(REQ_OTHER, (1ULL << 15)), 754 PMCMASK(RES_ANY, (1ULL << 16)), 755 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 756 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 757 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 758 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 759 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 760 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 761 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 762 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 763 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 764 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 765 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 766 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 767 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 768 NULLMASK 769}; 770 771static struct pmc_masks iap_rsp_mask_haswell[] = { 772 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 773 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 774 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 775 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 776 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 777 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 778 PMCMASK(REQ_OTHER, (1ULL << 15)), 779 PMCMASK(RES_ANY, (1ULL << 16)), 780 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 781 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 782 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 783 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 784 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 785 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 786 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 787 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 788 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 789 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 790 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 791 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 792 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 793 NULLMASK 794}; 795 796static int 797iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 798 struct pmc_op_pmcallocate *pmc_config) 799{ 800 char *e, *p, *q; 801 uint64_t cachestate, evmask, rsp; 802 int count, n; 803 804 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 805 PMC_CAP_QUALIFIER); 806 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 807 808 cachestate = evmask = rsp = 0; 809 810 /* Parse additional modifiers if present */ 811 while ((p = strsep(&ctrspec, ",")) != NULL) { 812 813 n = 0; 814 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 815 q = strchr(p, '='); 816 if (*++q == '\0') /* skip '=' */ 817 return (-1); 818 count = strtol(q, &e, 0); 819 if (e == q || *e != '\0') 820 return (-1); 821 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 822 pmc_config->pm_md.pm_iap.pm_iap_config |= 823 IAP_CMASK(count); 824 } else if (KWMATCH(p, IAP_KW_EDGE)) { 825 pmc_config->pm_caps |= PMC_CAP_EDGE; 826 } else if (KWMATCH(p, IAP_KW_INV)) { 827 pmc_config->pm_caps |= PMC_CAP_INVERT; 828 } else if (KWMATCH(p, IAP_KW_OS)) { 829 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 830 } else if (KWMATCH(p, IAP_KW_USR)) { 831 pmc_config->pm_caps |= PMC_CAP_USER; 832 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 833 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 834 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 835 n = pmc_parse_mask(iap_core_mask, p, &evmask); 836 if (n != 1) 837 return (-1); 838 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 839 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 840 if (n != 1) 841 return (-1); 842 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 843 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 844 if (n != 1) 845 return (-1); 846 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 847 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 848 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 849 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 850 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 851 if (n != 1) 852 return (-1); 853 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 854 cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 855 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 856 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 857 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 858 n = pmc_parse_mask(iap_snoopresponse_mask, p, 859 &evmask); 860 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 861 n = pmc_parse_mask(iap_snooptype_mask, p, 862 &evmask); 863 } else 864 return (-1); 865 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 866 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { 867 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 868 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 869 } else 870 return (-1); 871 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 872 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 873 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 874 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 875 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 876 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 877 } else 878 return (-1); 879 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) { 880 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 881 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); 882 } else 883 return (-1); 884 } else 885 return (-1); 886 887 if (n < 0) /* Parsing failed. */ 888 return (-1); 889 } 890 891 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 892 893 /* 894 * If the event requires a 'cachestate' qualifier but was not 895 * specified by the user, use a sensible default. 896 */ 897 switch (pe) { 898 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 899 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 900 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 901 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 902 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 903 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 904 case PMC_EV_IAP_EVENT_32H: /* Core */ 905 case PMC_EV_IAP_EVENT_40H: /* Core */ 906 case PMC_EV_IAP_EVENT_41H: /* Core */ 907 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 908 if (cachestate == 0) 909 cachestate = (0xF << 8); 910 break; 911 case PMC_EV_IAP_EVENT_77H: /* Atom */ 912 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 913 * Atom processor 914 */ 915 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 916 cachestate = (0xF << 8); 917 break; 918 default: 919 break; 920 } 921 922 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 923 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 924 925 return (0); 926} 927 928/* 929 * Intel Uncore. 930 */ 931 932static int 933ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 934 struct pmc_op_pmcallocate *pmc_config) 935{ 936 (void) pe; 937 (void) ctrspec; 938 939 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 940 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 941 942 return (0); 943} 944 945#define UCP_KW_CMASK "cmask" 946#define UCP_KW_EDGE "edge" 947#define UCP_KW_INV "inv" 948 949static int 950ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 951 struct pmc_op_pmcallocate *pmc_config) 952{ 953 char *e, *p, *q; 954 int count, n; 955 956 (void) pe; 957 958 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 959 PMC_CAP_QUALIFIER); 960 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 961 962 /* Parse additional modifiers if present */ 963 while ((p = strsep(&ctrspec, ",")) != NULL) { 964 965 n = 0; 966 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 967 q = strchr(p, '='); 968 if (*++q == '\0') /* skip '=' */ 969 return (-1); 970 count = strtol(q, &e, 0); 971 if (e == q || *e != '\0') 972 return (-1); 973 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 974 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 975 UCP_CMASK(count); 976 } else if (KWMATCH(p, UCP_KW_EDGE)) { 977 pmc_config->pm_caps |= PMC_CAP_EDGE; 978 } else if (KWMATCH(p, UCP_KW_INV)) { 979 pmc_config->pm_caps |= PMC_CAP_INVERT; 980 } else 981 return (-1); 982 983 if (n < 0) /* Parsing failed. */ 984 return (-1); 985 } 986 987 return (0); 988} 989 990/* 991 * AMD K8 PMCs. 992 * 993 * These are very similar to AMD K7 PMCs, but support more kinds of 994 * events. 995 */ 996 997static struct pmc_event_alias k8_aliases[] = { 998 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 999 EV_ALIAS("branch-mispredicts", 1000 "k8-fr-retired-taken-branches-mispredicted"), 1001 EV_ALIAS("cycles", "tsc"), 1002 EV_ALIAS("dc-misses", "k8-dc-miss"), 1003 EV_ALIAS("ic-misses", "k8-ic-miss"), 1004 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 1005 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 1006 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 1007 EV_ALIAS(NULL, NULL) 1008}; 1009 1010#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 1011 1012/* 1013 * Parsing tables 1014 */ 1015 1016/* fp dispatched fpu ops */ 1017static const struct pmc_masks k8_mask_fdfo[] = { 1018 __K8MASK(add-pipe-excluding-junk-ops, 0), 1019 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 1020 __K8MASK(store-pipe-excluding-junk-ops, 2), 1021 __K8MASK(add-pipe-junk-ops, 3), 1022 __K8MASK(multiply-pipe-junk-ops, 4), 1023 __K8MASK(store-pipe-junk-ops, 5), 1024 NULLMASK 1025}; 1026 1027/* ls segment register loads */ 1028static const struct pmc_masks k8_mask_lsrl[] = { 1029 __K8MASK(es, 0), 1030 __K8MASK(cs, 1), 1031 __K8MASK(ss, 2), 1032 __K8MASK(ds, 3), 1033 __K8MASK(fs, 4), 1034 __K8MASK(gs, 5), 1035 __K8MASK(hs, 6), 1036 NULLMASK 1037}; 1038 1039/* ls locked operation */ 1040static const struct pmc_masks k8_mask_llo[] = { 1041 __K8MASK(locked-instructions, 0), 1042 __K8MASK(cycles-in-request, 1), 1043 __K8MASK(cycles-to-complete, 2), 1044 NULLMASK 1045}; 1046 1047/* dc refill from {l2,system} and dc copyback */ 1048static const struct pmc_masks k8_mask_dc[] = { 1049 __K8MASK(invalid, 0), 1050 __K8MASK(shared, 1), 1051 __K8MASK(exclusive, 2), 1052 __K8MASK(owner, 3), 1053 __K8MASK(modified, 4), 1054 NULLMASK 1055}; 1056 1057/* dc one bit ecc error */ 1058static const struct pmc_masks k8_mask_dobee[] = { 1059 __K8MASK(scrubber, 0), 1060 __K8MASK(piggyback, 1), 1061 NULLMASK 1062}; 1063 1064/* dc dispatched prefetch instructions */ 1065static const struct pmc_masks k8_mask_ddpi[] = { 1066 __K8MASK(load, 0), 1067 __K8MASK(store, 1), 1068 __K8MASK(nta, 2), 1069 NULLMASK 1070}; 1071 1072/* dc dcache accesses by locks */ 1073static const struct pmc_masks k8_mask_dabl[] = { 1074 __K8MASK(accesses, 0), 1075 __K8MASK(misses, 1), 1076 NULLMASK 1077}; 1078 1079/* bu internal l2 request */ 1080static const struct pmc_masks k8_mask_bilr[] = { 1081 __K8MASK(ic-fill, 0), 1082 __K8MASK(dc-fill, 1), 1083 __K8MASK(tlb-reload, 2), 1084 __K8MASK(tag-snoop, 3), 1085 __K8MASK(cancelled, 4), 1086 NULLMASK 1087}; 1088 1089/* bu fill request l2 miss */ 1090static const struct pmc_masks k8_mask_bfrlm[] = { 1091 __K8MASK(ic-fill, 0), 1092 __K8MASK(dc-fill, 1), 1093 __K8MASK(tlb-reload, 2), 1094 NULLMASK 1095}; 1096 1097/* bu fill into l2 */ 1098static const struct pmc_masks k8_mask_bfil[] = { 1099 __K8MASK(dirty-l2-victim, 0), 1100 __K8MASK(victim-from-l2, 1), 1101 NULLMASK 1102}; 1103 1104/* fr retired fpu instructions */ 1105static const struct pmc_masks k8_mask_frfi[] = { 1106 __K8MASK(x87, 0), 1107 __K8MASK(mmx-3dnow, 1), 1108 __K8MASK(packed-sse-sse2, 2), 1109 __K8MASK(scalar-sse-sse2, 3), 1110 NULLMASK 1111}; 1112 1113/* fr retired fastpath double op instructions */ 1114static const struct pmc_masks k8_mask_frfdoi[] = { 1115 __K8MASK(low-op-pos-0, 0), 1116 __K8MASK(low-op-pos-1, 1), 1117 __K8MASK(low-op-pos-2, 2), 1118 NULLMASK 1119}; 1120 1121/* fr fpu exceptions */ 1122static const struct pmc_masks k8_mask_ffe[] = { 1123 __K8MASK(x87-reclass-microfaults, 0), 1124 __K8MASK(sse-retype-microfaults, 1), 1125 __K8MASK(sse-reclass-microfaults, 2), 1126 __K8MASK(sse-and-x87-microtraps, 3), 1127 NULLMASK 1128}; 1129 1130/* nb memory controller page access event */ 1131static const struct pmc_masks k8_mask_nmcpae[] = { 1132 __K8MASK(page-hit, 0), 1133 __K8MASK(page-miss, 1), 1134 __K8MASK(page-conflict, 2), 1135 NULLMASK 1136}; 1137 1138/* nb memory controller turnaround */ 1139static const struct pmc_masks k8_mask_nmct[] = { 1140 __K8MASK(dimm-turnaround, 0), 1141 __K8MASK(read-to-write-turnaround, 1), 1142 __K8MASK(write-to-read-turnaround, 2), 1143 NULLMASK 1144}; 1145 1146/* nb memory controller bypass saturation */ 1147static const struct pmc_masks k8_mask_nmcbs[] = { 1148 __K8MASK(memory-controller-hi-pri-bypass, 0), 1149 __K8MASK(memory-controller-lo-pri-bypass, 1), 1150 __K8MASK(dram-controller-interface-bypass, 2), 1151 __K8MASK(dram-controller-queue-bypass, 3), 1152 NULLMASK 1153}; 1154 1155/* nb sized commands */ 1156static const struct pmc_masks k8_mask_nsc[] = { 1157 __K8MASK(nonpostwrszbyte, 0), 1158 __K8MASK(nonpostwrszdword, 1), 1159 __K8MASK(postwrszbyte, 2), 1160 __K8MASK(postwrszdword, 3), 1161 __K8MASK(rdszbyte, 4), 1162 __K8MASK(rdszdword, 5), 1163 __K8MASK(rdmodwr, 6), 1164 NULLMASK 1165}; 1166 1167/* nb probe result */ 1168static const struct pmc_masks k8_mask_npr[] = { 1169 __K8MASK(probe-miss, 0), 1170 __K8MASK(probe-hit, 1), 1171 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1172 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1173 NULLMASK 1174}; 1175 1176/* nb hypertransport bus bandwidth */ 1177static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1178 __K8MASK(command, 0), 1179 __K8MASK(data, 1), 1180 __K8MASK(buffer-release, 2), 1181 __K8MASK(nop, 3), 1182 NULLMASK 1183}; 1184 1185#undef __K8MASK 1186 1187#define K8_KW_COUNT "count" 1188#define K8_KW_EDGE "edge" 1189#define K8_KW_INV "inv" 1190#define K8_KW_MASK "mask" 1191#define K8_KW_OS "os" 1192#define K8_KW_USR "usr" 1193 1194static int 1195k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1196 struct pmc_op_pmcallocate *pmc_config) 1197{ 1198 char *e, *p, *q; 1199 int n; 1200 uint32_t count; 1201 uint64_t evmask; 1202 const struct pmc_masks *pm, *pmask; 1203 1204 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1205 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1206 1207 pmask = NULL; 1208 evmask = 0; 1209 1210#define __K8SETMASK(M) pmask = k8_mask_##M 1211 1212 /* setup parsing tables */ 1213 switch (pe) { 1214 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1215 __K8SETMASK(fdfo); 1216 break; 1217 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1218 __K8SETMASK(lsrl); 1219 break; 1220 case PMC_EV_K8_LS_LOCKED_OPERATION: 1221 __K8SETMASK(llo); 1222 break; 1223 case PMC_EV_K8_DC_REFILL_FROM_L2: 1224 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1225 case PMC_EV_K8_DC_COPYBACK: 1226 __K8SETMASK(dc); 1227 break; 1228 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1229 __K8SETMASK(dobee); 1230 break; 1231 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1232 __K8SETMASK(ddpi); 1233 break; 1234 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1235 __K8SETMASK(dabl); 1236 break; 1237 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1238 __K8SETMASK(bilr); 1239 break; 1240 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1241 __K8SETMASK(bfrlm); 1242 break; 1243 case PMC_EV_K8_BU_FILL_INTO_L2: 1244 __K8SETMASK(bfil); 1245 break; 1246 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1247 __K8SETMASK(frfi); 1248 break; 1249 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1250 __K8SETMASK(frfdoi); 1251 break; 1252 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1253 __K8SETMASK(ffe); 1254 break; 1255 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1256 __K8SETMASK(nmcpae); 1257 break; 1258 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1259 __K8SETMASK(nmct); 1260 break; 1261 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1262 __K8SETMASK(nmcbs); 1263 break; 1264 case PMC_EV_K8_NB_SIZED_COMMANDS: 1265 __K8SETMASK(nsc); 1266 break; 1267 case PMC_EV_K8_NB_PROBE_RESULT: 1268 __K8SETMASK(npr); 1269 break; 1270 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1271 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1272 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1273 __K8SETMASK(nhbb); 1274 break; 1275 1276 default: 1277 break; /* no options defined */ 1278 } 1279 1280 while ((p = strsep(&ctrspec, ",")) != NULL) { 1281 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1282 q = strchr(p, '='); 1283 if (*++q == '\0') /* skip '=' */ 1284 return (-1); 1285 1286 count = strtol(q, &e, 0); 1287 if (e == q || *e != '\0') 1288 return (-1); 1289 1290 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1291 pmc_config->pm_md.pm_amd.pm_amd_config |= 1292 AMD_PMC_TO_COUNTER(count); 1293 1294 } else if (KWMATCH(p, K8_KW_EDGE)) { 1295 pmc_config->pm_caps |= PMC_CAP_EDGE; 1296 } else if (KWMATCH(p, K8_KW_INV)) { 1297 pmc_config->pm_caps |= PMC_CAP_INVERT; 1298 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1299 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1300 return (-1); 1301 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1302 } else if (KWMATCH(p, K8_KW_OS)) { 1303 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1304 } else if (KWMATCH(p, K8_KW_USR)) { 1305 pmc_config->pm_caps |= PMC_CAP_USER; 1306 } else 1307 return (-1); 1308 } 1309 1310 /* other post processing */ 1311 switch (pe) { 1312 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1313 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1314 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1315 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1316 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1317 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1318 /* XXX only available in rev B and later */ 1319 break; 1320 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1321 /* XXX only available in rev C and later */ 1322 break; 1323 case PMC_EV_K8_LS_LOCKED_OPERATION: 1324 /* XXX CPU Rev A,B evmask is to be zero */ 1325 if (evmask & (evmask - 1)) /* > 1 bit set */ 1326 return (-1); 1327 if (evmask == 0) { 1328 evmask = 0x01; /* Rev C and later: #instrs */ 1329 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1330 } 1331 break; 1332 default: 1333 if (evmask == 0 && pmask != NULL) { 1334 for (pm = pmask; pm->pm_name; pm++) 1335 evmask |= pm->pm_value; 1336 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1337 } 1338 } 1339 1340 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1341 pmc_config->pm_md.pm_amd.pm_amd_config = 1342 AMD_PMC_TO_UNITMASK(evmask); 1343 1344 return (0); 1345} 1346 1347#endif 1348 1349#if defined(__amd64__) || defined(__i386__) 1350 1351/* 1352 * Intel P4 PMCs 1353 */ 1354 1355static struct pmc_event_alias p4_aliases[] = { 1356 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1357 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1358 EV_ALIAS("cycles", "tsc"), 1359 EV_ALIAS("instructions", 1360 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1361 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1362 EV_ALIAS(NULL, NULL) 1363}; 1364 1365#define P4_KW_ACTIVE "active" 1366#define P4_KW_ACTIVE_ANY "any" 1367#define P4_KW_ACTIVE_BOTH "both" 1368#define P4_KW_ACTIVE_NONE "none" 1369#define P4_KW_ACTIVE_SINGLE "single" 1370#define P4_KW_BUSREQTYPE "busreqtype" 1371#define P4_KW_CASCADE "cascade" 1372#define P4_KW_EDGE "edge" 1373#define P4_KW_INV "complement" 1374#define P4_KW_OS "os" 1375#define P4_KW_MASK "mask" 1376#define P4_KW_PRECISE "precise" 1377#define P4_KW_TAG "tag" 1378#define P4_KW_THRESHOLD "threshold" 1379#define P4_KW_USR "usr" 1380 1381#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1382 1383static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1384 __P4MASK(dd, 0), 1385 __P4MASK(db, 1), 1386 __P4MASK(di, 2), 1387 __P4MASK(bd, 3), 1388 __P4MASK(bb, 4), 1389 __P4MASK(bi, 5), 1390 __P4MASK(id, 6), 1391 __P4MASK(ib, 7), 1392 NULLMASK 1393}; 1394 1395static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1396 __P4MASK(tcmiss, 0), 1397 NULLMASK, 1398}; 1399 1400static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1401 __P4MASK(hit, 0), 1402 __P4MASK(miss, 1), 1403 __P4MASK(hit-uc, 2), 1404 NULLMASK 1405}; 1406 1407static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1408 __P4MASK(st-rb-full, 2), 1409 __P4MASK(64k-conf, 3), 1410 NULLMASK 1411}; 1412 1413static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1414 __P4MASK(lsc, 0), 1415 __P4MASK(ssc, 1), 1416 NULLMASK 1417}; 1418 1419static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1420 __P4MASK(split-ld, 1), 1421 NULLMASK 1422}; 1423 1424static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1425 __P4MASK(split-st, 1), 1426 NULLMASK 1427}; 1428 1429static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1430 __P4MASK(no-sta, 1), 1431 __P4MASK(no-std, 3), 1432 __P4MASK(partial-data, 4), 1433 __P4MASK(unalgn-addr, 5), 1434 NULLMASK 1435}; 1436 1437static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1438 __P4MASK(dtmiss, 0), 1439 __P4MASK(itmiss, 1), 1440 NULLMASK 1441}; 1442 1443static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1444 __P4MASK(rd-2ndl-hits, 0), 1445 __P4MASK(rd-2ndl-hite, 1), 1446 __P4MASK(rd-2ndl-hitm, 2), 1447 __P4MASK(rd-3rdl-hits, 3), 1448 __P4MASK(rd-3rdl-hite, 4), 1449 __P4MASK(rd-3rdl-hitm, 5), 1450 __P4MASK(rd-2ndl-miss, 8), 1451 __P4MASK(rd-3rdl-miss, 9), 1452 __P4MASK(wr-2ndl-miss, 10), 1453 NULLMASK 1454}; 1455 1456static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1457 __P4MASK(all-read, 5), 1458 __P4MASK(all-write, 6), 1459 __P4MASK(mem-uc, 7), 1460 __P4MASK(mem-wc, 8), 1461 __P4MASK(mem-wt, 9), 1462 __P4MASK(mem-wp, 10), 1463 __P4MASK(mem-wb, 11), 1464 __P4MASK(own, 13), 1465 __P4MASK(other, 14), 1466 __P4MASK(prefetch, 15), 1467 NULLMASK 1468}; 1469 1470static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1471 __P4MASK(all-read, 5), 1472 __P4MASK(all-write, 6), 1473 __P4MASK(mem-uc, 7), 1474 __P4MASK(mem-wc, 8), 1475 __P4MASK(mem-wt, 9), 1476 __P4MASK(mem-wp, 10), 1477 __P4MASK(mem-wb, 11), 1478 __P4MASK(own, 13), 1479 __P4MASK(other, 14), 1480 __P4MASK(prefetch, 15), 1481 NULLMASK 1482}; 1483 1484static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1485 __P4MASK(drdy-drv, 0), 1486 __P4MASK(drdy-own, 1), 1487 __P4MASK(drdy-other, 2), 1488 __P4MASK(dbsy-drv, 3), 1489 __P4MASK(dbsy-own, 4), 1490 __P4MASK(dbsy-other, 5), 1491 NULLMASK 1492}; 1493 1494static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1495 __P4MASK(req-type0, 0), 1496 __P4MASK(req-type1, 1), 1497 __P4MASK(req-len0, 2), 1498 __P4MASK(req-len1, 3), 1499 __P4MASK(req-io-type, 5), 1500 __P4MASK(req-lock-type, 6), 1501 __P4MASK(req-cache-type, 7), 1502 __P4MASK(req-split-type, 8), 1503 __P4MASK(req-dem-type, 9), 1504 __P4MASK(req-ord-type, 10), 1505 __P4MASK(mem-type0, 11), 1506 __P4MASK(mem-type1, 12), 1507 __P4MASK(mem-type2, 13), 1508 NULLMASK 1509}; 1510 1511static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1512 __P4MASK(all, 15), 1513 NULLMASK 1514}; 1515 1516static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1517 __P4MASK(all, 15), 1518 NULLMASK 1519}; 1520 1521static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1522 __P4MASK(all, 15), 1523 NULLMASK 1524}; 1525 1526static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1527 __P4MASK(all, 15), 1528 NULLMASK 1529}; 1530 1531static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1532 __P4MASK(all, 15), 1533 NULLMASK 1534}; 1535 1536static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1537 __P4MASK(all, 15), 1538 NULLMASK 1539}; 1540 1541static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1542 __P4MASK(all, 15), 1543 NULLMASK 1544}; 1545 1546static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1547 __P4MASK(all, 15), 1548 NULLMASK 1549}; 1550 1551static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1552 __P4MASK(allp0, 3), 1553 __P4MASK(allp2, 4), 1554 NULLMASK 1555}; 1556 1557static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1558 __P4MASK(running, 0), 1559 NULLMASK 1560}; 1561 1562static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1563 __P4MASK(cisc, 0), 1564 NULLMASK 1565}; 1566 1567static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1568 __P4MASK(from-tc-build, 0), 1569 __P4MASK(from-tc-deliver, 1), 1570 __P4MASK(from-rom, 2), 1571 NULLMASK 1572}; 1573 1574static const struct pmc_masks p4_mask_rmbt[] = { 1575 /* retired mispred branch type */ 1576 __P4MASK(conditional, 1), 1577 __P4MASK(call, 2), 1578 __P4MASK(return, 3), 1579 __P4MASK(indirect, 4), 1580 NULLMASK 1581}; 1582 1583static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1584 __P4MASK(conditional, 1), 1585 __P4MASK(call, 2), 1586 __P4MASK(retired, 3), 1587 __P4MASK(indirect, 4), 1588 NULLMASK 1589}; 1590 1591static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1592 __P4MASK(sbfull, 5), 1593 NULLMASK 1594}; 1595 1596static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1597 __P4MASK(wcb-evicts, 0), 1598 __P4MASK(wcb-full-evict, 1), 1599 NULLMASK 1600}; 1601 1602static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1603 __P4MASK(nbogus, 0), 1604 __P4MASK(bogus, 1), 1605 NULLMASK 1606}; 1607 1608static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1609 __P4MASK(nbogus0, 0), 1610 __P4MASK(nbogus1, 1), 1611 __P4MASK(nbogus2, 2), 1612 __P4MASK(nbogus3, 3), 1613 __P4MASK(bogus0, 4), 1614 __P4MASK(bogus1, 5), 1615 __P4MASK(bogus2, 6), 1616 __P4MASK(bogus3, 7), 1617 NULLMASK 1618}; 1619 1620static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1621 __P4MASK(nbogus, 0), 1622 __P4MASK(bogus, 1), 1623 NULLMASK 1624}; 1625 1626static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1627 __P4MASK(nbogusntag, 0), 1628 __P4MASK(nbogustag, 1), 1629 __P4MASK(bogusntag, 2), 1630 __P4MASK(bogustag, 3), 1631 NULLMASK 1632}; 1633 1634static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1635 __P4MASK(nbogus, 0), 1636 __P4MASK(bogus, 1), 1637 NULLMASK 1638}; 1639 1640static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1641 __P4MASK(tagloads, 1), 1642 __P4MASK(tagstores, 2), 1643 NULLMASK 1644}; 1645 1646static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1647 __P4MASK(mmnp, 0), 1648 __P4MASK(mmnm, 1), 1649 __P4MASK(mmtp, 2), 1650 __P4MASK(mmtm, 3), 1651 NULLMASK 1652}; 1653 1654static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1655 __P4MASK(nbogus, 0), 1656 NULLMASK 1657}; 1658 1659static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1660 __P4MASK(fpsu, 0), 1661 __P4MASK(fpso, 1), 1662 __P4MASK(poao, 2), 1663 __P4MASK(poau, 3), 1664 __P4MASK(prea, 4), 1665 NULLMASK 1666}; 1667 1668static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1669 __P4MASK(clear, 0), 1670 __P4MASK(moclear, 2), 1671 __P4MASK(smclear, 3), 1672 NULLMASK 1673}; 1674 1675/* P4 event parser */ 1676static int 1677p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1678 struct pmc_op_pmcallocate *pmc_config) 1679{ 1680 1681 char *e, *p, *q; 1682 int count, has_tag, has_busreqtype, n; 1683 uint32_t cccractivemask; 1684 uint64_t evmask; 1685 const struct pmc_masks *pm, *pmask; 1686 1687 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1688 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1689 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1690 1691 pmask = NULL; 1692 evmask = 0; 1693 cccractivemask = 0x3; 1694 has_tag = has_busreqtype = 0; 1695 1696#define __P4SETMASK(M) do { \ 1697 pmask = p4_mask_##M; \ 1698} while (0) 1699 1700 switch (pe) { 1701 case PMC_EV_P4_TC_DELIVER_MODE: 1702 __P4SETMASK(tcdm); 1703 break; 1704 case PMC_EV_P4_BPU_FETCH_REQUEST: 1705 __P4SETMASK(bfr); 1706 break; 1707 case PMC_EV_P4_ITLB_REFERENCE: 1708 __P4SETMASK(ir); 1709 break; 1710 case PMC_EV_P4_MEMORY_CANCEL: 1711 __P4SETMASK(memcan); 1712 break; 1713 case PMC_EV_P4_MEMORY_COMPLETE: 1714 __P4SETMASK(memcomp); 1715 break; 1716 case PMC_EV_P4_LOAD_PORT_REPLAY: 1717 __P4SETMASK(lpr); 1718 break; 1719 case PMC_EV_P4_STORE_PORT_REPLAY: 1720 __P4SETMASK(spr); 1721 break; 1722 case PMC_EV_P4_MOB_LOAD_REPLAY: 1723 __P4SETMASK(mlr); 1724 break; 1725 case PMC_EV_P4_PAGE_WALK_TYPE: 1726 __P4SETMASK(pwt); 1727 break; 1728 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1729 __P4SETMASK(bcr); 1730 break; 1731 case PMC_EV_P4_IOQ_ALLOCATION: 1732 __P4SETMASK(ia); 1733 has_busreqtype = 1; 1734 break; 1735 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1736 __P4SETMASK(iae); 1737 has_busreqtype = 1; 1738 break; 1739 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1740 __P4SETMASK(fda); 1741 break; 1742 case PMC_EV_P4_BSQ_ALLOCATION: 1743 __P4SETMASK(ba); 1744 break; 1745 case PMC_EV_P4_SSE_INPUT_ASSIST: 1746 __P4SETMASK(sia); 1747 break; 1748 case PMC_EV_P4_PACKED_SP_UOP: 1749 __P4SETMASK(psu); 1750 break; 1751 case PMC_EV_P4_PACKED_DP_UOP: 1752 __P4SETMASK(pdu); 1753 break; 1754 case PMC_EV_P4_SCALAR_SP_UOP: 1755 __P4SETMASK(ssu); 1756 break; 1757 case PMC_EV_P4_SCALAR_DP_UOP: 1758 __P4SETMASK(sdu); 1759 break; 1760 case PMC_EV_P4_64BIT_MMX_UOP: 1761 __P4SETMASK(64bmu); 1762 break; 1763 case PMC_EV_P4_128BIT_MMX_UOP: 1764 __P4SETMASK(128bmu); 1765 break; 1766 case PMC_EV_P4_X87_FP_UOP: 1767 __P4SETMASK(xfu); 1768 break; 1769 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1770 __P4SETMASK(xsmu); 1771 break; 1772 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1773 __P4SETMASK(gpe); 1774 break; 1775 case PMC_EV_P4_TC_MS_XFER: 1776 __P4SETMASK(tmx); 1777 break; 1778 case PMC_EV_P4_UOP_QUEUE_WRITES: 1779 __P4SETMASK(uqw); 1780 break; 1781 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1782 __P4SETMASK(rmbt); 1783 break; 1784 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1785 __P4SETMASK(rbt); 1786 break; 1787 case PMC_EV_P4_RESOURCE_STALL: 1788 __P4SETMASK(rs); 1789 break; 1790 case PMC_EV_P4_WC_BUFFER: 1791 __P4SETMASK(wb); 1792 break; 1793 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1794 case PMC_EV_P4_B2B_CYCLES: 1795 case PMC_EV_P4_BNR: 1796 case PMC_EV_P4_SNOOP: 1797 case PMC_EV_P4_RESPONSE: 1798 break; 1799 case PMC_EV_P4_FRONT_END_EVENT: 1800 __P4SETMASK(fee); 1801 break; 1802 case PMC_EV_P4_EXECUTION_EVENT: 1803 __P4SETMASK(ee); 1804 break; 1805 case PMC_EV_P4_REPLAY_EVENT: 1806 __P4SETMASK(re); 1807 break; 1808 case PMC_EV_P4_INSTR_RETIRED: 1809 __P4SETMASK(insret); 1810 break; 1811 case PMC_EV_P4_UOPS_RETIRED: 1812 __P4SETMASK(ur); 1813 break; 1814 case PMC_EV_P4_UOP_TYPE: 1815 __P4SETMASK(ut); 1816 break; 1817 case PMC_EV_P4_BRANCH_RETIRED: 1818 __P4SETMASK(br); 1819 break; 1820 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1821 __P4SETMASK(mbr); 1822 break; 1823 case PMC_EV_P4_X87_ASSIST: 1824 __P4SETMASK(xa); 1825 break; 1826 case PMC_EV_P4_MACHINE_CLEAR: 1827 __P4SETMASK(machclr); 1828 break; 1829 default: 1830 return (-1); 1831 } 1832 1833 /* process additional flags */ 1834 while ((p = strsep(&ctrspec, ",")) != NULL) { 1835 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1836 q = strchr(p, '='); 1837 if (*++q == '\0') /* skip '=' */ 1838 return (-1); 1839 1840 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1841 cccractivemask = 0x0; 1842 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1843 cccractivemask = 0x1; 1844 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1845 cccractivemask = 0x2; 1846 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1847 cccractivemask = 0x3; 1848 else 1849 return (-1); 1850 1851 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1852 if (has_busreqtype == 0) 1853 return (-1); 1854 1855 q = strchr(p, '='); 1856 if (*++q == '\0') /* skip '=' */ 1857 return (-1); 1858 1859 count = strtol(q, &e, 0); 1860 if (e == q || *e != '\0') 1861 return (-1); 1862 evmask = (evmask & ~0x1F) | (count & 0x1F); 1863 } else if (KWMATCH(p, P4_KW_CASCADE)) 1864 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1865 else if (KWMATCH(p, P4_KW_EDGE)) 1866 pmc_config->pm_caps |= PMC_CAP_EDGE; 1867 else if (KWMATCH(p, P4_KW_INV)) 1868 pmc_config->pm_caps |= PMC_CAP_INVERT; 1869 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1870 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1871 return (-1); 1872 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1873 } else if (KWMATCH(p, P4_KW_OS)) 1874 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1875 else if (KWMATCH(p, P4_KW_PRECISE)) 1876 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1877 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1878 if (has_tag == 0) 1879 return (-1); 1880 1881 q = strchr(p, '='); 1882 if (*++q == '\0') /* skip '=' */ 1883 return (-1); 1884 1885 count = strtol(q, &e, 0); 1886 if (e == q || *e != '\0') 1887 return (-1); 1888 1889 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1890 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1891 P4_ESCR_TO_TAG_VALUE(count); 1892 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1893 q = strchr(p, '='); 1894 if (*++q == '\0') /* skip '=' */ 1895 return (-1); 1896 1897 count = strtol(q, &e, 0); 1898 if (e == q || *e != '\0') 1899 return (-1); 1900 1901 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1902 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1903 ~P4_CCCR_THRESHOLD_MASK; 1904 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1905 P4_CCCR_TO_THRESHOLD(count); 1906 } else if (KWMATCH(p, P4_KW_USR)) 1907 pmc_config->pm_caps |= PMC_CAP_USER; 1908 else 1909 return (-1); 1910 } 1911 1912 /* other post processing */ 1913 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1914 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1915 pe == PMC_EV_P4_BSQ_ALLOCATION) 1916 pmc_config->pm_caps |= PMC_CAP_EDGE; 1917 1918 /* fill in thread activity mask */ 1919 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1920 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1921 1922 if (evmask) 1923 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1924 1925 switch (pe) { 1926 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1927 if ((evmask & 0x06) == 0x06 || 1928 (evmask & 0x18) == 0x18) 1929 return (-1); /* can't have own+other bits together */ 1930 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1931 evmask = 0x1D; 1932 break; 1933 case PMC_EV_P4_MACHINE_CLEAR: 1934 /* only one bit is allowed to be set */ 1935 if ((evmask & (evmask - 1)) != 0) 1936 return (-1); 1937 if (evmask == 0) { 1938 evmask = 0x1; /* 'CLEAR' */ 1939 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1940 } 1941 break; 1942 default: 1943 if (evmask == 0 && pmask) { 1944 for (pm = pmask; pm->pm_name; pm++) 1945 evmask |= pm->pm_value; 1946 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1947 } 1948 } 1949 1950 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1951 P4_ESCR_TO_EVENT_MASK(evmask); 1952 1953 return (0); 1954} 1955 1956#endif 1957 1958#if defined(__i386__) 1959 1960/* 1961 * Pentium style PMCs 1962 */ 1963 1964static struct pmc_event_alias p5_aliases[] = { 1965 EV_ALIAS("branches", "p5-taken-branches"), 1966 EV_ALIAS("cycles", "tsc"), 1967 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1968 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1969 EV_ALIAS("instructions", "p5-instructions-executed"), 1970 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1971 EV_ALIAS("unhalted-cycles", 1972 "p5-number-of-cycles-not-in-halt-state"), 1973 EV_ALIAS(NULL, NULL) 1974}; 1975 1976static int 1977p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1978 struct pmc_op_pmcallocate *pmc_config) 1979{ 1980 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 1981} 1982 1983/* 1984 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 1985 * and Pentium M CPUs. 1986 */ 1987 1988static struct pmc_event_alias p6_aliases[] = { 1989 EV_ALIAS("branches", "p6-br-inst-retired"), 1990 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 1991 EV_ALIAS("cycles", "tsc"), 1992 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 1993 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 1994 EV_ALIAS("instructions", "p6-inst-retired"), 1995 EV_ALIAS("interrupts", "p6-hw-int-rx"), 1996 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 1997 EV_ALIAS(NULL, NULL) 1998}; 1999 2000#define P6_KW_CMASK "cmask" 2001#define P6_KW_EDGE "edge" 2002#define P6_KW_INV "inv" 2003#define P6_KW_OS "os" 2004#define P6_KW_UMASK "umask" 2005#define P6_KW_USR "usr" 2006 2007static struct pmc_masks p6_mask_mesi[] = { 2008 PMCMASK(m, 0x01), 2009 PMCMASK(e, 0x02), 2010 PMCMASK(s, 0x04), 2011 PMCMASK(i, 0x08), 2012 NULLMASK 2013}; 2014 2015static struct pmc_masks p6_mask_mesihw[] = { 2016 PMCMASK(m, 0x01), 2017 PMCMASK(e, 0x02), 2018 PMCMASK(s, 0x04), 2019 PMCMASK(i, 0x08), 2020 PMCMASK(nonhw, 0x00), 2021 PMCMASK(hw, 0x10), 2022 PMCMASK(both, 0x30), 2023 NULLMASK 2024}; 2025 2026static struct pmc_masks p6_mask_hw[] = { 2027 PMCMASK(nonhw, 0x00), 2028 PMCMASK(hw, 0x10), 2029 PMCMASK(both, 0x30), 2030 NULLMASK 2031}; 2032 2033static struct pmc_masks p6_mask_any[] = { 2034 PMCMASK(self, 0x00), 2035 PMCMASK(any, 0x20), 2036 NULLMASK 2037}; 2038 2039static struct pmc_masks p6_mask_ekp[] = { 2040 PMCMASK(nta, 0x00), 2041 PMCMASK(t1, 0x01), 2042 PMCMASK(t2, 0x02), 2043 PMCMASK(wos, 0x03), 2044 NULLMASK 2045}; 2046 2047static struct pmc_masks p6_mask_pps[] = { 2048 PMCMASK(packed-and-scalar, 0x00), 2049 PMCMASK(scalar, 0x01), 2050 NULLMASK 2051}; 2052 2053static struct pmc_masks p6_mask_mite[] = { 2054 PMCMASK(packed-multiply, 0x01), 2055 PMCMASK(packed-shift, 0x02), 2056 PMCMASK(pack, 0x04), 2057 PMCMASK(unpack, 0x08), 2058 PMCMASK(packed-logical, 0x10), 2059 PMCMASK(packed-arithmetic, 0x20), 2060 NULLMASK 2061}; 2062 2063static struct pmc_masks p6_mask_fmt[] = { 2064 PMCMASK(mmxtofp, 0x00), 2065 PMCMASK(fptommx, 0x01), 2066 NULLMASK 2067}; 2068 2069static struct pmc_masks p6_mask_sr[] = { 2070 PMCMASK(es, 0x01), 2071 PMCMASK(ds, 0x02), 2072 PMCMASK(fs, 0x04), 2073 PMCMASK(gs, 0x08), 2074 NULLMASK 2075}; 2076 2077static struct pmc_masks p6_mask_eet[] = { 2078 PMCMASK(all, 0x00), 2079 PMCMASK(freq, 0x02), 2080 NULLMASK 2081}; 2082 2083static struct pmc_masks p6_mask_efur[] = { 2084 PMCMASK(all, 0x00), 2085 PMCMASK(loadop, 0x01), 2086 PMCMASK(stdsta, 0x02), 2087 NULLMASK 2088}; 2089 2090static struct pmc_masks p6_mask_essir[] = { 2091 PMCMASK(sse-packed-single, 0x00), 2092 PMCMASK(sse-packed-single-scalar-single, 0x01), 2093 PMCMASK(sse2-packed-double, 0x02), 2094 PMCMASK(sse2-scalar-double, 0x03), 2095 NULLMASK 2096}; 2097 2098static struct pmc_masks p6_mask_esscir[] = { 2099 PMCMASK(sse-packed-single, 0x00), 2100 PMCMASK(sse-scalar-single, 0x01), 2101 PMCMASK(sse2-packed-double, 0x02), 2102 PMCMASK(sse2-scalar-double, 0x03), 2103 NULLMASK 2104}; 2105 2106/* P6 event parser */ 2107static int 2108p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2109 struct pmc_op_pmcallocate *pmc_config) 2110{ 2111 char *e, *p, *q; 2112 uint64_t evmask; 2113 int count, n; 2114 const struct pmc_masks *pm, *pmask; 2115 2116 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2117 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2118 2119 evmask = 0; 2120 2121#define P6MASKSET(M) pmask = p6_mask_ ## M 2122 2123 switch(pe) { 2124 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2125 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2126 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2127 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2128 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2129 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2130 case PMC_EV_P6_BUS_TRAN_BRD: 2131 case PMC_EV_P6_BUS_TRAN_RFO: 2132 case PMC_EV_P6_BUS_TRANS_WB: 2133 case PMC_EV_P6_BUS_TRAN_IFETCH: 2134 case PMC_EV_P6_BUS_TRAN_INVAL: 2135 case PMC_EV_P6_BUS_TRAN_PWR: 2136 case PMC_EV_P6_BUS_TRANS_P: 2137 case PMC_EV_P6_BUS_TRANS_IO: 2138 case PMC_EV_P6_BUS_TRAN_DEF: 2139 case PMC_EV_P6_BUS_TRAN_BURST: 2140 case PMC_EV_P6_BUS_TRAN_ANY: 2141 case PMC_EV_P6_BUS_TRAN_MEM: 2142 P6MASKSET(any); break; 2143 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2144 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2145 P6MASKSET(ekp); break; 2146 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2147 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2148 P6MASKSET(pps); break; 2149 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2150 P6MASKSET(mite); break; 2151 case PMC_EV_P6_FP_MMX_TRANS: 2152 P6MASKSET(fmt); break; 2153 case PMC_EV_P6_SEG_RENAME_STALLS: 2154 case PMC_EV_P6_SEG_REG_RENAMES: 2155 P6MASKSET(sr); break; 2156 case PMC_EV_P6_EMON_EST_TRANS: 2157 P6MASKSET(eet); break; 2158 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2159 P6MASKSET(efur); break; 2160 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2161 P6MASKSET(essir); break; 2162 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2163 P6MASKSET(esscir); break; 2164 default: 2165 pmask = NULL; 2166 break; 2167 } 2168 2169 /* Pentium M PMCs have a few events with different semantics */ 2170 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2171 if (pe == PMC_EV_P6_L2_LD || 2172 pe == PMC_EV_P6_L2_LINES_IN || 2173 pe == PMC_EV_P6_L2_LINES_OUT) 2174 P6MASKSET(mesihw); 2175 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2176 P6MASKSET(hw); 2177 } 2178 2179 /* Parse additional modifiers if present */ 2180 while ((p = strsep(&ctrspec, ",")) != NULL) { 2181 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2182 q = strchr(p, '='); 2183 if (*++q == '\0') /* skip '=' */ 2184 return (-1); 2185 count = strtol(q, &e, 0); 2186 if (e == q || *e != '\0') 2187 return (-1); 2188 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2189 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2190 P6_EVSEL_TO_CMASK(count); 2191 } else if (KWMATCH(p, P6_KW_EDGE)) { 2192 pmc_config->pm_caps |= PMC_CAP_EDGE; 2193 } else if (KWMATCH(p, P6_KW_INV)) { 2194 pmc_config->pm_caps |= PMC_CAP_INVERT; 2195 } else if (KWMATCH(p, P6_KW_OS)) { 2196 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2197 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2198 evmask = 0; 2199 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2200 return (-1); 2201 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2202 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2203 pe == PMC_EV_P6_BUS_TRAN_BRD || 2204 pe == PMC_EV_P6_BUS_TRAN_RFO || 2205 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2206 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2207 pe == PMC_EV_P6_BUS_TRAN_PWR || 2208 pe == PMC_EV_P6_BUS_TRAN_DEF || 2209 pe == PMC_EV_P6_BUS_TRAN_BURST || 2210 pe == PMC_EV_P6_BUS_TRAN_ANY || 2211 pe == PMC_EV_P6_BUS_TRAN_MEM || 2212 pe == PMC_EV_P6_BUS_TRANS_IO || 2213 pe == PMC_EV_P6_BUS_TRANS_P || 2214 pe == PMC_EV_P6_BUS_TRANS_WB || 2215 pe == PMC_EV_P6_EMON_EST_TRANS || 2216 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2217 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2218 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2219 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2220 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2221 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2222 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2223 pe == PMC_EV_P6_FP_MMX_TRANS) 2224 && (n > 1)) /* Only one mask keyword is allowed. */ 2225 return (-1); 2226 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2227 } else if (KWMATCH(p, P6_KW_USR)) { 2228 pmc_config->pm_caps |= PMC_CAP_USER; 2229 } else 2230 return (-1); 2231 } 2232 2233 /* post processing */ 2234 switch (pe) { 2235 2236 /* 2237 * The following events default to an evmask of 0 2238 */ 2239 2240 /* default => 'self' */ 2241 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2242 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2243 case PMC_EV_P6_BUS_TRAN_BRD: 2244 case PMC_EV_P6_BUS_TRAN_RFO: 2245 case PMC_EV_P6_BUS_TRANS_WB: 2246 case PMC_EV_P6_BUS_TRAN_IFETCH: 2247 case PMC_EV_P6_BUS_TRAN_INVAL: 2248 case PMC_EV_P6_BUS_TRAN_PWR: 2249 case PMC_EV_P6_BUS_TRANS_P: 2250 case PMC_EV_P6_BUS_TRANS_IO: 2251 case PMC_EV_P6_BUS_TRAN_DEF: 2252 case PMC_EV_P6_BUS_TRAN_BURST: 2253 case PMC_EV_P6_BUS_TRAN_ANY: 2254 case PMC_EV_P6_BUS_TRAN_MEM: 2255 2256 /* default => 'nta' */ 2257 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2258 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2259 2260 /* default => 'packed and scalar' */ 2261 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2262 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2263 2264 /* default => 'mmx to fp transitions' */ 2265 case PMC_EV_P6_FP_MMX_TRANS: 2266 2267 /* default => 'SSE Packed Single' */ 2268 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2269 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2270 2271 /* default => 'all fused micro-ops' */ 2272 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2273 2274 /* default => 'all transitions' */ 2275 case PMC_EV_P6_EMON_EST_TRANS: 2276 break; 2277 2278 case PMC_EV_P6_MMX_UOPS_EXEC: 2279 evmask = 0x0F; /* only value allowed */ 2280 break; 2281 2282 default: 2283 /* 2284 * For all other events, set the default event mask 2285 * to a logical OR of all the allowed event mask bits. 2286 */ 2287 if (evmask == 0 && pmask) { 2288 for (pm = pmask; pm->pm_name; pm++) 2289 evmask |= pm->pm_value; 2290 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2291 } 2292 2293 break; 2294 } 2295 2296 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2297 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2298 P6_EVSEL_TO_UMASK(evmask); 2299 2300 return (0); 2301} 2302 2303#endif 2304 2305#if defined(__i386__) || defined(__amd64__) 2306static int 2307tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2308 struct pmc_op_pmcallocate *pmc_config) 2309{ 2310 if (pe != PMC_EV_TSC_TSC) 2311 return (-1); 2312 2313 /* TSC events must be unqualified. */ 2314 if (ctrspec && *ctrspec != '\0') 2315 return (-1); 2316 2317 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2318 pmc_config->pm_caps |= PMC_CAP_READ; 2319 2320 return (0); 2321} 2322#endif 2323 2324static struct pmc_event_alias generic_aliases[] = { 2325 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2326 EV_ALIAS(NULL, NULL) 2327}; 2328 2329static int 2330soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2331 struct pmc_op_pmcallocate *pmc_config) 2332{ 2333 (void)ctrspec; 2334 (void)pmc_config; 2335 2336 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2337 return (-1); 2338 2339 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2340 return (0); 2341} 2342 2343#if defined(__XSCALE__) 2344 2345static struct pmc_event_alias xscale_aliases[] = { 2346 EV_ALIAS("branches", "BRANCH_RETIRED"), 2347 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2348 EV_ALIAS("dc-misses", "DC_MISS"), 2349 EV_ALIAS("ic-misses", "IC_MISS"), 2350 EV_ALIAS("instructions", "INSTR_RETIRED"), 2351 EV_ALIAS(NULL, NULL) 2352}; 2353static int 2354xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2355 struct pmc_op_pmcallocate *pmc_config __unused) 2356{ 2357 switch (pe) { 2358 default: 2359 break; 2360 } 2361 2362 return (0); 2363} 2364#endif 2365 2366#if defined(__mips__) 2367 2368static struct pmc_event_alias mips24k_aliases[] = { 2369 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2370 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2371 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2372 EV_ALIAS(NULL, NULL) 2373}; 2374 2375static struct pmc_event_alias octeon_aliases[] = { 2376 EV_ALIAS("instructions", "RET"), 2377 EV_ALIAS("branches", "BR"), 2378 EV_ALIAS("branch-mispredicts", "BRMIS"), 2379 EV_ALIAS(NULL, NULL) 2380}; 2381 2382#define MIPS_KW_OS "os" 2383#define MIPS_KW_USR "usr" 2384#define MIPS_KW_ANYTHREAD "anythread" 2385 2386static int 2387mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2388 struct pmc_op_pmcallocate *pmc_config __unused) 2389{ 2390 char *p; 2391 2392 (void) pe; 2393 2394 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2395 2396 while ((p = strsep(&ctrspec, ",")) != NULL) { 2397 if (KWMATCH(p, MIPS_KW_OS)) 2398 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2399 else if (KWMATCH(p, MIPS_KW_USR)) 2400 pmc_config->pm_caps |= PMC_CAP_USER; 2401 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2402 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2403 else 2404 return (-1); 2405 } 2406 2407 return (0); 2408} 2409 2410#endif /* __mips__ */ 2411 2412#if defined(__powerpc__) 2413 2414static struct pmc_event_alias ppc7450_aliases[] = { 2415 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2416 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2417 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2418 EV_ALIAS(NULL, NULL) 2419}; 2420 2421static struct pmc_event_alias ppc970_aliases[] = { 2422 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2423 EV_ALIAS("cycles", "CYCLES"), 2424 EV_ALIAS(NULL, NULL) 2425}; 2426 2427#define POWERPC_KW_OS "os" 2428#define POWERPC_KW_USR "usr" 2429#define POWERPC_KW_ANYTHREAD "anythread" 2430 2431static int 2432powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2433 struct pmc_op_pmcallocate *pmc_config __unused) 2434{ 2435 char *p; 2436 2437 (void) pe; 2438 2439 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2440 2441 while ((p = strsep(&ctrspec, ",")) != NULL) { 2442 if (KWMATCH(p, POWERPC_KW_OS)) 2443 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2444 else if (KWMATCH(p, POWERPC_KW_USR)) 2445 pmc_config->pm_caps |= PMC_CAP_USER; 2446 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD)) 2447 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2448 else 2449 return (-1); 2450 } 2451 2452 return (0); 2453} 2454 2455#endif /* __powerpc__ */ 2456 2457 2458/* 2459 * Match an event name `name' with its canonical form. 2460 * 2461 * Matches are case insensitive and spaces, periods, underscores and 2462 * hyphen characters are considered to match each other. 2463 * 2464 * Returns 1 for a match, 0 otherwise. 2465 */ 2466 2467static int 2468pmc_match_event_name(const char *name, const char *canonicalname) 2469{ 2470 int cc, nc; 2471 const unsigned char *c, *n; 2472 2473 c = (const unsigned char *) canonicalname; 2474 n = (const unsigned char *) name; 2475 2476 for (; (nc = *n) && (cc = *c); n++, c++) { 2477 2478 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2479 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2480 continue; 2481 2482 if (toupper(nc) == toupper(cc)) 2483 continue; 2484 2485 2486 return (0); 2487 } 2488 2489 if (*n == '\0' && *c == '\0') 2490 return (1); 2491 2492 return (0); 2493} 2494 2495/* 2496 * Match an event name against all the event named supported by a 2497 * PMC class. 2498 * 2499 * Returns an event descriptor pointer on match or NULL otherwise. 2500 */ 2501static const struct pmc_event_descr * 2502pmc_match_event_class(const char *name, 2503 const struct pmc_class_descr *pcd) 2504{ 2505 size_t n; 2506 const struct pmc_event_descr *ev; 2507 2508 ev = pcd->pm_evc_event_table; 2509 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2510 if (pmc_match_event_name(name, ev->pm_ev_name)) 2511 return (ev); 2512 2513 return (NULL); 2514} 2515 2516static int 2517pmc_mdep_is_compatible_class(enum pmc_class pc) 2518{ 2519 size_t n; 2520 2521 for (n = 0; n < pmc_mdep_class_list_size; n++) 2522 if (pmc_mdep_class_list[n] == pc) 2523 return (1); 2524 return (0); 2525} 2526 2527/* 2528 * API entry points 2529 */ 2530 2531int 2532pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2533 uint32_t flags, int cpu, pmc_id_t *pmcid) 2534{ 2535 size_t n; 2536 int retval; 2537 char *r, *spec_copy; 2538 const char *ctrname; 2539 const struct pmc_event_descr *ev; 2540 const struct pmc_event_alias *alias; 2541 struct pmc_op_pmcallocate pmc_config; 2542 const struct pmc_class_descr *pcd; 2543 2544 spec_copy = NULL; 2545 retval = -1; 2546 2547 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2548 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2549 errno = EINVAL; 2550 goto out; 2551 } 2552 2553 /* replace an event alias with the canonical event specifier */ 2554 if (pmc_mdep_event_aliases) 2555 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2556 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2557 spec_copy = strdup(alias->pm_spec); 2558 break; 2559 } 2560 2561 if (spec_copy == NULL) 2562 spec_copy = strdup(ctrspec); 2563 2564 r = spec_copy; 2565 ctrname = strsep(&r, ","); 2566 2567 /* 2568 * If a explicit class prefix was given by the user, restrict the 2569 * search for the event to the specified PMC class. 2570 */ 2571 ev = NULL; 2572 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2573 pcd = pmc_class_table[n]; 2574 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2575 strncasecmp(ctrname, pcd->pm_evc_name, 2576 pcd->pm_evc_name_size) == 0) { 2577 if ((ev = pmc_match_event_class(ctrname + 2578 pcd->pm_evc_name_size, pcd)) == NULL) { 2579 errno = EINVAL; 2580 goto out; 2581 } 2582 break; 2583 } 2584 } 2585 2586 /* 2587 * Otherwise, search for this event in all compatible PMC 2588 * classes. 2589 */ 2590 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2591 pcd = pmc_class_table[n]; 2592 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2593 ev = pmc_match_event_class(ctrname, pcd); 2594 } 2595 2596 if (ev == NULL) { 2597 errno = EINVAL; 2598 goto out; 2599 } 2600 2601 bzero(&pmc_config, sizeof(pmc_config)); 2602 pmc_config.pm_ev = ev->pm_ev_code; 2603 pmc_config.pm_class = pcd->pm_evc_class; 2604 pmc_config.pm_cpu = cpu; 2605 pmc_config.pm_mode = mode; 2606 pmc_config.pm_flags = flags; 2607 2608 if (PMC_IS_SAMPLING_MODE(mode)) 2609 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2610 2611 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2612 errno = EINVAL; 2613 goto out; 2614 } 2615 2616 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2617 goto out; 2618 2619 *pmcid = pmc_config.pm_pmcid; 2620 2621 retval = 0; 2622 2623 out: 2624 if (spec_copy) 2625 free(spec_copy); 2626 2627 return (retval); 2628} 2629 2630int 2631pmc_attach(pmc_id_t pmc, pid_t pid) 2632{ 2633 struct pmc_op_pmcattach pmc_attach_args; 2634 2635 pmc_attach_args.pm_pmc = pmc; 2636 pmc_attach_args.pm_pid = pid; 2637 2638 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2639} 2640 2641int 2642pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2643{ 2644 unsigned int i; 2645 enum pmc_class cl; 2646 2647 cl = PMC_ID_TO_CLASS(pmcid); 2648 for (i = 0; i < cpu_info.pm_nclass; i++) 2649 if (cpu_info.pm_classes[i].pm_class == cl) { 2650 *caps = cpu_info.pm_classes[i].pm_caps; 2651 return (0); 2652 } 2653 errno = EINVAL; 2654 return (-1); 2655} 2656 2657int 2658pmc_configure_logfile(int fd) 2659{ 2660 struct pmc_op_configurelog cla; 2661 2662 cla.pm_logfd = fd; 2663 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2664 return (-1); 2665 return (0); 2666} 2667 2668int 2669pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2670{ 2671 if (pmc_syscall == -1) { 2672 errno = ENXIO; 2673 return (-1); 2674 } 2675 2676 *pci = &cpu_info; 2677 return (0); 2678} 2679 2680int 2681pmc_detach(pmc_id_t pmc, pid_t pid) 2682{ 2683 struct pmc_op_pmcattach pmc_detach_args; 2684 2685 pmc_detach_args.pm_pmc = pmc; 2686 pmc_detach_args.pm_pid = pid; 2687 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2688} 2689 2690int 2691pmc_disable(int cpu, int pmc) 2692{ 2693 struct pmc_op_pmcadmin ssa; 2694 2695 ssa.pm_cpu = cpu; 2696 ssa.pm_pmc = pmc; 2697 ssa.pm_state = PMC_STATE_DISABLED; 2698 return (PMC_CALL(PMCADMIN, &ssa)); 2699} 2700 2701int 2702pmc_enable(int cpu, int pmc) 2703{ 2704 struct pmc_op_pmcadmin ssa; 2705 2706 ssa.pm_cpu = cpu; 2707 ssa.pm_pmc = pmc; 2708 ssa.pm_state = PMC_STATE_FREE; 2709 return (PMC_CALL(PMCADMIN, &ssa)); 2710} 2711 2712/* 2713 * Return a list of events known to a given PMC class. 'cl' is the 2714 * PMC class identifier, 'eventnames' is the returned list of 'const 2715 * char *' pointers pointing to the names of the events. 'nevents' is 2716 * the number of event name pointers returned. 2717 * 2718 * The space for 'eventnames' is allocated using malloc(3). The caller 2719 * is responsible for freeing this space when done. 2720 */ 2721int 2722pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2723 int *nevents) 2724{ 2725 int count; 2726 const char **names; 2727 const struct pmc_event_descr *ev; 2728 2729 switch (cl) 2730 { 2731 case PMC_CLASS_IAF: 2732 ev = iaf_event_table; 2733 count = PMC_EVENT_TABLE_SIZE(iaf); 2734 break; 2735 case PMC_CLASS_IAP: 2736 /* 2737 * Return the most appropriate set of event name 2738 * spellings for the current CPU. 2739 */ 2740 switch (cpu_info.pm_cputype) { 2741 default: 2742 case PMC_CPU_INTEL_ATOM: 2743 ev = atom_event_table; 2744 count = PMC_EVENT_TABLE_SIZE(atom); 2745 break; 2746 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2747 ev = atom_silvermont_event_table; 2748 count = PMC_EVENT_TABLE_SIZE(atom_silvermont); 2749 break; 2750 case PMC_CPU_INTEL_CORE: 2751 ev = core_event_table; 2752 count = PMC_EVENT_TABLE_SIZE(core); 2753 break; 2754 case PMC_CPU_INTEL_CORE2: 2755 case PMC_CPU_INTEL_CORE2EXTREME: 2756 ev = core2_event_table; 2757 count = PMC_EVENT_TABLE_SIZE(core2); 2758 break; 2759 case PMC_CPU_INTEL_COREI7: 2760 ev = corei7_event_table; 2761 count = PMC_EVENT_TABLE_SIZE(corei7); 2762 break; 2763 case PMC_CPU_INTEL_HASWELL: 2764 ev = haswell_event_table; 2765 count = PMC_EVENT_TABLE_SIZE(haswell); 2766 break; 2767 case PMC_CPU_INTEL_IVYBRIDGE: 2768 ev = ivybridge_event_table; 2769 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2770 break; 2771 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2772 ev = ivybridge_xeon_event_table; 2773 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2774 break; 2775 case PMC_CPU_INTEL_SANDYBRIDGE: 2776 ev = sandybridge_event_table; 2777 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2778 break; 2779 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2780 ev = sandybridge_xeon_event_table; 2781 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2782 break; 2783 case PMC_CPU_INTEL_WESTMERE: 2784 ev = westmere_event_table; 2785 count = PMC_EVENT_TABLE_SIZE(westmere); 2786 break; 2787 } 2788 break; 2789 case PMC_CLASS_UCF: 2790 ev = ucf_event_table; 2791 count = PMC_EVENT_TABLE_SIZE(ucf); 2792 break; 2793 case PMC_CLASS_UCP: 2794 /* 2795 * Return the most appropriate set of event name 2796 * spellings for the current CPU. 2797 */ 2798 switch (cpu_info.pm_cputype) { 2799 default: 2800 case PMC_CPU_INTEL_COREI7: 2801 ev = corei7uc_event_table; 2802 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2803 break; 2804 case PMC_CPU_INTEL_HASWELL: 2805 ev = haswelluc_event_table; 2806 count = PMC_EVENT_TABLE_SIZE(haswelluc); 2807 break; 2808 case PMC_CPU_INTEL_SANDYBRIDGE: 2809 ev = sandybridgeuc_event_table; 2810 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2811 break; 2812 case PMC_CPU_INTEL_WESTMERE: 2813 ev = westmereuc_event_table; 2814 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2815 break; 2816 } 2817 break; 2818 case PMC_CLASS_TSC: 2819 ev = tsc_event_table; 2820 count = PMC_EVENT_TABLE_SIZE(tsc); 2821 break; 2822 case PMC_CLASS_K7: 2823 ev = k7_event_table; 2824 count = PMC_EVENT_TABLE_SIZE(k7); 2825 break; 2826 case PMC_CLASS_K8: 2827 ev = k8_event_table; 2828 count = PMC_EVENT_TABLE_SIZE(k8); 2829 break; 2830 case PMC_CLASS_P4: 2831 ev = p4_event_table; 2832 count = PMC_EVENT_TABLE_SIZE(p4); 2833 break; 2834 case PMC_CLASS_P5: 2835 ev = p5_event_table; 2836 count = PMC_EVENT_TABLE_SIZE(p5); 2837 break; 2838 case PMC_CLASS_P6: 2839 ev = p6_event_table; 2840 count = PMC_EVENT_TABLE_SIZE(p6); 2841 break; 2842 case PMC_CLASS_XSCALE: 2843 ev = xscale_event_table; 2844 count = PMC_EVENT_TABLE_SIZE(xscale); 2845 break; 2846 case PMC_CLASS_MIPS24K: 2847 ev = mips24k_event_table; 2848 count = PMC_EVENT_TABLE_SIZE(mips24k); 2849 break; 2850 case PMC_CLASS_OCTEON: 2851 ev = octeon_event_table; 2852 count = PMC_EVENT_TABLE_SIZE(octeon); 2853 break; 2854 case PMC_CLASS_PPC7450: 2855 ev = ppc7450_event_table; 2856 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2857 break; 2858 case PMC_CLASS_PPC970: 2859 ev = ppc970_event_table; 2860 count = PMC_EVENT_TABLE_SIZE(ppc970); 2861 break; 2862 case PMC_CLASS_SOFT: 2863 ev = soft_event_table; 2864 count = soft_event_info.pm_nevent; 2865 break; 2866 default: 2867 errno = EINVAL; 2868 return (-1); 2869 } 2870 2871 if ((names = malloc(count * sizeof(const char *))) == NULL) 2872 return (-1); 2873 2874 *eventnames = names; 2875 *nevents = count; 2876 2877 for (;count--; ev++, names++) 2878 *names = ev->pm_ev_name; 2879 2880 return (0); 2881} 2882 2883int 2884pmc_flush_logfile(void) 2885{ 2886 return (PMC_CALL(FLUSHLOG,0)); 2887} 2888 2889int 2890pmc_close_logfile(void) 2891{ 2892 return (PMC_CALL(CLOSELOG,0)); 2893} 2894 2895int 2896pmc_get_driver_stats(struct pmc_driverstats *ds) 2897{ 2898 struct pmc_op_getdriverstats gms; 2899 2900 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2901 return (-1); 2902 2903 /* copy out fields in the current userland<->library interface */ 2904 ds->pm_intr_ignored = gms.pm_intr_ignored; 2905 ds->pm_intr_processed = gms.pm_intr_processed; 2906 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2907 ds->pm_syscalls = gms.pm_syscalls; 2908 ds->pm_syscall_errors = gms.pm_syscall_errors; 2909 ds->pm_buffer_requests = gms.pm_buffer_requests; 2910 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2911 ds->pm_log_sweeps = gms.pm_log_sweeps; 2912 return (0); 2913} 2914 2915int 2916pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2917{ 2918 struct pmc_op_getmsr gm; 2919 2920 gm.pm_pmcid = pmc; 2921 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2922 return (-1); 2923 *msr = gm.pm_msr; 2924 return (0); 2925} 2926 2927int 2928pmc_init(void) 2929{ 2930 int error, pmc_mod_id; 2931 unsigned int n; 2932 uint32_t abi_version; 2933 struct module_stat pmc_modstat; 2934 struct pmc_op_getcpuinfo op_cpu_info; 2935#if defined(__amd64__) || defined(__i386__) 2936 int cpu_has_iaf_counters; 2937 unsigned int t; 2938#endif 2939 2940 if (pmc_syscall != -1) /* already inited */ 2941 return (0); 2942 2943 /* retrieve the system call number from the KLD */ 2944 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2945 return (-1); 2946 2947 pmc_modstat.version = sizeof(struct module_stat); 2948 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2949 return (-1); 2950 2951 pmc_syscall = pmc_modstat.data.intval; 2952 2953 /* check the kernel module's ABI against our compiled-in version */ 2954 abi_version = PMC_VERSION; 2955 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2956 return (pmc_syscall = -1); 2957 2958 /* ignore patch & minor numbers for the comparision */ 2959 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2960 errno = EPROGMISMATCH; 2961 return (pmc_syscall = -1); 2962 } 2963 2964 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2965 return (pmc_syscall = -1); 2966 2967 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2968 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2969 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2970 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2971 for (n = 0; n < cpu_info.pm_nclass; n++) 2972 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 2973 2974 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 2975 sizeof(struct pmc_class_descr *)); 2976 2977 if (pmc_class_table == NULL) 2978 return (-1); 2979 2980 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 2981 pmc_class_table[n] = NULL; 2982 2983 /* 2984 * Get soft events list. 2985 */ 2986 soft_event_info.pm_class = PMC_CLASS_SOFT; 2987 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 2988 return (pmc_syscall = -1); 2989 2990 /* Map soft events to static list. */ 2991 for (n = 0; n < soft_event_info.pm_nevent; n++) { 2992 soft_event_table[n].pm_ev_name = 2993 soft_event_info.pm_events[n].pm_ev_name; 2994 soft_event_table[n].pm_ev_code = 2995 soft_event_info.pm_events[n].pm_ev_code; 2996 } 2997 soft_class_table_descr.pm_evc_event_table_size = \ 2998 soft_event_info.pm_nevent; 2999 soft_class_table_descr.pm_evc_event_table = \ 3000 soft_event_table; 3001 3002 /* 3003 * Fill in the class table. 3004 */ 3005 n = 0; 3006 3007 /* Fill soft events information. */ 3008 pmc_class_table[n++] = &soft_class_table_descr; 3009#if defined(__amd64__) || defined(__i386__) 3010 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 3011 pmc_class_table[n++] = &tsc_class_table_descr; 3012 3013 /* 3014 * Check if this CPU has fixed function counters. 3015 */ 3016 cpu_has_iaf_counters = 0; 3017 for (t = 0; t < cpu_info.pm_nclass; t++) 3018 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 3019 cpu_info.pm_classes[t].pm_num > 0) 3020 cpu_has_iaf_counters = 1; 3021#endif 3022 3023#define PMC_MDEP_INIT(C) do { \ 3024 pmc_mdep_event_aliases = C##_aliases; \ 3025 pmc_mdep_class_list = C##_pmc_classes; \ 3026 pmc_mdep_class_list_size = \ 3027 PMC_TABLE_SIZE(C##_pmc_classes); \ 3028 } while (0) 3029 3030#define PMC_MDEP_INIT_INTEL_V2(C) do { \ 3031 PMC_MDEP_INIT(C); \ 3032 pmc_class_table[n++] = &iaf_class_table_descr; \ 3033 if (!cpu_has_iaf_counters) \ 3034 pmc_mdep_event_aliases = \ 3035 C##_aliases_without_iaf; \ 3036 pmc_class_table[n] = &C##_class_table_descr; \ 3037 } while (0) 3038 3039 /* Configure the event name parser. */ 3040 switch (cpu_info.pm_cputype) { 3041#if defined(__i386__) 3042 case PMC_CPU_AMD_K7: 3043 PMC_MDEP_INIT(k7); 3044 pmc_class_table[n] = &k7_class_table_descr; 3045 break; 3046 case PMC_CPU_INTEL_P5: 3047 PMC_MDEP_INIT(p5); 3048 pmc_class_table[n] = &p5_class_table_descr; 3049 break; 3050 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 3051 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 3052 case PMC_CPU_INTEL_PIII: 3053 case PMC_CPU_INTEL_PM: 3054 PMC_MDEP_INIT(p6); 3055 pmc_class_table[n] = &p6_class_table_descr; 3056 break; 3057#endif 3058#if defined(__amd64__) || defined(__i386__) 3059 case PMC_CPU_AMD_K8: 3060 PMC_MDEP_INIT(k8); 3061 pmc_class_table[n] = &k8_class_table_descr; 3062 break; 3063 case PMC_CPU_INTEL_ATOM: 3064 PMC_MDEP_INIT_INTEL_V2(atom); 3065 break; 3066 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3067 PMC_MDEP_INIT_INTEL_V2(atom_silvermont); 3068 break; 3069 case PMC_CPU_INTEL_CORE: 3070 PMC_MDEP_INIT(core); 3071 pmc_class_table[n] = &core_class_table_descr; 3072 break; 3073 case PMC_CPU_INTEL_CORE2: 3074 case PMC_CPU_INTEL_CORE2EXTREME: 3075 PMC_MDEP_INIT_INTEL_V2(core2); 3076 break; 3077 case PMC_CPU_INTEL_COREI7: 3078 pmc_class_table[n++] = &ucf_class_table_descr; 3079 pmc_class_table[n++] = &corei7uc_class_table_descr; 3080 PMC_MDEP_INIT_INTEL_V2(corei7); 3081 break; 3082 case PMC_CPU_INTEL_HASWELL: 3083 pmc_class_table[n++] = &ucf_class_table_descr; 3084 pmc_class_table[n++] = &haswelluc_class_table_descr; 3085 PMC_MDEP_INIT_INTEL_V2(haswell); 3086 break; 3087 case PMC_CPU_INTEL_IVYBRIDGE: 3088 PMC_MDEP_INIT_INTEL_V2(ivybridge); 3089 break; 3090 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3091 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3092 break; 3093 case PMC_CPU_INTEL_SANDYBRIDGE: 3094 pmc_class_table[n++] = &ucf_class_table_descr; 3095 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3096 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3097 break; 3098 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3099 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3100 break; 3101 case PMC_CPU_INTEL_WESTMERE: 3102 pmc_class_table[n++] = &ucf_class_table_descr; 3103 pmc_class_table[n++] = &westmereuc_class_table_descr; 3104 PMC_MDEP_INIT_INTEL_V2(westmere); 3105 break; 3106 case PMC_CPU_INTEL_PIV: 3107 PMC_MDEP_INIT(p4); 3108 pmc_class_table[n] = &p4_class_table_descr; 3109 break; 3110#endif 3111 case PMC_CPU_GENERIC: 3112 PMC_MDEP_INIT(generic); 3113 break; 3114#if defined(__XSCALE__) 3115 case PMC_CPU_INTEL_XSCALE: 3116 PMC_MDEP_INIT(xscale); 3117 pmc_class_table[n] = &xscale_class_table_descr; 3118 break; 3119#endif 3120#if defined(__mips__) 3121 case PMC_CPU_MIPS_24K: 3122 PMC_MDEP_INIT(mips24k); 3123 pmc_class_table[n] = &mips24k_class_table_descr; 3124 break; 3125 case PMC_CPU_MIPS_OCTEON: 3126 PMC_MDEP_INIT(octeon); 3127 pmc_class_table[n] = &octeon_class_table_descr; 3128 break; 3129#endif /* __mips__ */ 3130#if defined(__powerpc__) 3131 case PMC_CPU_PPC_7450: 3132 PMC_MDEP_INIT(ppc7450); 3133 pmc_class_table[n] = &ppc7450_class_table_descr; 3134 break; 3135 case PMC_CPU_PPC_970: 3136 PMC_MDEP_INIT(ppc970); 3137 pmc_class_table[n] = &ppc970_class_table_descr; 3138 break; 3139#endif 3140 default: 3141 /* 3142 * Some kind of CPU this version of the library knows nothing 3143 * about. This shouldn't happen since the abi version check 3144 * should have caught this. 3145 */ 3146 errno = ENXIO; 3147 return (pmc_syscall = -1); 3148 } 3149 3150 return (0); 3151} 3152 3153const char * 3154pmc_name_of_capability(enum pmc_caps cap) 3155{ 3156 int i; 3157 3158 /* 3159 * 'cap' should have a single bit set and should be in 3160 * range. 3161 */ 3162 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3163 cap > PMC_CAP_LAST) { 3164 errno = EINVAL; 3165 return (NULL); 3166 } 3167 3168 i = ffs(cap); 3169 return (pmc_capability_names[i - 1]); 3170} 3171 3172const char * 3173pmc_name_of_class(enum pmc_class pc) 3174{ 3175 if ((int) pc >= PMC_CLASS_FIRST && 3176 pc <= PMC_CLASS_LAST) 3177 return (pmc_class_names[pc]); 3178 3179 errno = EINVAL; 3180 return (NULL); 3181} 3182 3183const char * 3184pmc_name_of_cputype(enum pmc_cputype cp) 3185{ 3186 size_t n; 3187 3188 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3189 if (cp == pmc_cputype_names[n].pm_cputype) 3190 return (pmc_cputype_names[n].pm_name); 3191 3192 errno = EINVAL; 3193 return (NULL); 3194} 3195 3196const char * 3197pmc_name_of_disposition(enum pmc_disp pd) 3198{ 3199 if ((int) pd >= PMC_DISP_FIRST && 3200 pd <= PMC_DISP_LAST) 3201 return (pmc_disposition_names[pd]); 3202 3203 errno = EINVAL; 3204 return (NULL); 3205} 3206 3207const char * 3208_pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3209{ 3210 const struct pmc_event_descr *ev, *evfence; 3211 3212 ev = evfence = NULL; 3213 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3214 ev = iaf_event_table; 3215 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3216 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3217 switch (cpu) { 3218 case PMC_CPU_INTEL_ATOM: 3219 ev = atom_event_table; 3220 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3221 break; 3222 case PMC_CPU_INTEL_ATOM_SILVERMONT: 3223 ev = atom_silvermont_event_table; 3224 evfence = atom_silvermont_event_table + 3225 PMC_EVENT_TABLE_SIZE(atom_silvermont); 3226 break; 3227 case PMC_CPU_INTEL_CORE: 3228 ev = core_event_table; 3229 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3230 break; 3231 case PMC_CPU_INTEL_CORE2: 3232 case PMC_CPU_INTEL_CORE2EXTREME: 3233 ev = core2_event_table; 3234 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3235 break; 3236 case PMC_CPU_INTEL_COREI7: 3237 ev = corei7_event_table; 3238 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3239 break; 3240 case PMC_CPU_INTEL_HASWELL: 3241 ev = haswell_event_table; 3242 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); 3243 break; 3244 case PMC_CPU_INTEL_IVYBRIDGE: 3245 ev = ivybridge_event_table; 3246 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3247 break; 3248 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3249 ev = ivybridge_xeon_event_table; 3250 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3251 break; 3252 case PMC_CPU_INTEL_SANDYBRIDGE: 3253 ev = sandybridge_event_table; 3254 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3255 break; 3256 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3257 ev = sandybridge_xeon_event_table; 3258 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3259 break; 3260 case PMC_CPU_INTEL_WESTMERE: 3261 ev = westmere_event_table; 3262 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3263 break; 3264 default: /* Unknown CPU type. */ 3265 break; 3266 } 3267 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3268 ev = ucf_event_table; 3269 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3270 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3271 switch (cpu) { 3272 case PMC_CPU_INTEL_COREI7: 3273 ev = corei7uc_event_table; 3274 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3275 break; 3276 case PMC_CPU_INTEL_SANDYBRIDGE: 3277 ev = sandybridgeuc_event_table; 3278 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3279 break; 3280 case PMC_CPU_INTEL_WESTMERE: 3281 ev = westmereuc_event_table; 3282 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3283 break; 3284 default: /* Unknown CPU type. */ 3285 break; 3286 } 3287 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3288 ev = k7_event_table; 3289 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3290 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3291 ev = k8_event_table; 3292 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3293 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3294 ev = p4_event_table; 3295 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3296 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3297 ev = p5_event_table; 3298 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3299 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3300 ev = p6_event_table; 3301 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3302 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3303 ev = xscale_event_table; 3304 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3305 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3306 ev = mips24k_event_table; 3307 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3308 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3309 ev = octeon_event_table; 3310 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3311 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3312 ev = ppc7450_event_table; 3313 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3314 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) { 3315 ev = ppc970_event_table; 3316 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970); 3317 } else if (pe == PMC_EV_TSC_TSC) { 3318 ev = tsc_event_table; 3319 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3320 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3321 ev = soft_event_table; 3322 evfence = soft_event_table + soft_event_info.pm_nevent; 3323 } 3324 3325 for (; ev != evfence; ev++) 3326 if (pe == ev->pm_ev_code) 3327 return (ev->pm_ev_name); 3328 3329 return (NULL); 3330} 3331 3332const char * 3333pmc_name_of_event(enum pmc_event pe) 3334{ 3335 const char *n; 3336 3337 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3338 return (n); 3339 3340 errno = EINVAL; 3341 return (NULL); 3342} 3343 3344const char * 3345pmc_name_of_mode(enum pmc_mode pm) 3346{ 3347 if ((int) pm >= PMC_MODE_FIRST && 3348 pm <= PMC_MODE_LAST) 3349 return (pmc_mode_names[pm]); 3350 3351 errno = EINVAL; 3352 return (NULL); 3353} 3354 3355const char * 3356pmc_name_of_state(enum pmc_state ps) 3357{ 3358 if ((int) ps >= PMC_STATE_FIRST && 3359 ps <= PMC_STATE_LAST) 3360 return (pmc_state_names[ps]); 3361 3362 errno = EINVAL; 3363 return (NULL); 3364} 3365 3366int 3367pmc_ncpu(void) 3368{ 3369 if (pmc_syscall == -1) { 3370 errno = ENXIO; 3371 return (-1); 3372 } 3373 3374 return (cpu_info.pm_ncpu); 3375} 3376 3377int 3378pmc_npmc(int cpu) 3379{ 3380 if (pmc_syscall == -1) { 3381 errno = ENXIO; 3382 return (-1); 3383 } 3384 3385 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3386 errno = EINVAL; 3387 return (-1); 3388 } 3389 3390 return (cpu_info.pm_npmc); 3391} 3392 3393int 3394pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3395{ 3396 int nbytes, npmc; 3397 struct pmc_op_getpmcinfo *pmci; 3398 3399 if ((npmc = pmc_npmc(cpu)) < 0) 3400 return (-1); 3401 3402 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3403 npmc * sizeof(struct pmc_info); 3404 3405 if ((pmci = calloc(1, nbytes)) == NULL) 3406 return (-1); 3407 3408 pmci->pm_cpu = cpu; 3409 3410 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3411 free(pmci); 3412 return (-1); 3413 } 3414 3415 /* kernel<->library, library<->userland interfaces are identical */ 3416 *ppmci = (struct pmc_pmcinfo *) pmci; 3417 return (0); 3418} 3419 3420int 3421pmc_read(pmc_id_t pmc, pmc_value_t *value) 3422{ 3423 struct pmc_op_pmcrw pmc_read_op; 3424 3425 pmc_read_op.pm_pmcid = pmc; 3426 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3427 pmc_read_op.pm_value = -1; 3428 3429 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3430 return (-1); 3431 3432 *value = pmc_read_op.pm_value; 3433 return (0); 3434} 3435 3436int 3437pmc_release(pmc_id_t pmc) 3438{ 3439 struct pmc_op_simple pmc_release_args; 3440 3441 pmc_release_args.pm_pmcid = pmc; 3442 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3443} 3444 3445int 3446pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3447{ 3448 struct pmc_op_pmcrw pmc_rw_op; 3449 3450 pmc_rw_op.pm_pmcid = pmc; 3451 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3452 pmc_rw_op.pm_value = newvalue; 3453 3454 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3455 return (-1); 3456 3457 *oldvaluep = pmc_rw_op.pm_value; 3458 return (0); 3459} 3460 3461int 3462pmc_set(pmc_id_t pmc, pmc_value_t value) 3463{ 3464 struct pmc_op_pmcsetcount sc; 3465 3466 sc.pm_pmcid = pmc; 3467 sc.pm_count = value; 3468 3469 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3470 return (-1); 3471 return (0); 3472} 3473 3474int 3475pmc_start(pmc_id_t pmc) 3476{ 3477 struct pmc_op_simple pmc_start_args; 3478 3479 pmc_start_args.pm_pmcid = pmc; 3480 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3481} 3482 3483int 3484pmc_stop(pmc_id_t pmc) 3485{ 3486 struct pmc_op_simple pmc_stop_args; 3487 3488 pmc_stop_args.pm_pmcid = pmc; 3489 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3490} 3491 3492int 3493pmc_width(pmc_id_t pmcid, uint32_t *width) 3494{ 3495 unsigned int i; 3496 enum pmc_class cl; 3497 3498 cl = PMC_ID_TO_CLASS(pmcid); 3499 for (i = 0; i < cpu_info.pm_nclass; i++) 3500 if (cpu_info.pm_classes[i].pm_class == cl) { 3501 *width = cpu_info.pm_classes[i].pm_width; 3502 return (0); 3503 } 3504 errno = EINVAL; 3505 return (-1); 3506} 3507 3508int 3509pmc_write(pmc_id_t pmc, pmc_value_t value) 3510{ 3511 struct pmc_op_pmcrw pmc_write_op; 3512 3513 pmc_write_op.pm_pmcid = pmc; 3514 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3515 pmc_write_op.pm_value = value; 3516 return (PMC_CALL(PMCRW, &pmc_write_op)); 3517} 3518 3519int 3520pmc_writelog(uint32_t userdata) 3521{ 3522 struct pmc_op_writelog wl; 3523 3524 wl.pm_userdata = userdata; 3525 return (PMC_CALL(WRITELOG, &wl)); 3526} 3527