libpmc.c revision 246166
1/*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 246166 2013-01-31 22:09:53Z sbruno $"); 29 30#include <sys/types.h> 31#include <sys/module.h> 32#include <sys/pmc.h> 33#include <sys/syscall.h> 34 35#include <ctype.h> 36#include <errno.h> 37#include <fcntl.h> 38#include <pmc.h> 39#include <stdio.h> 40#include <stdlib.h> 41#include <string.h> 42#include <strings.h> 43#include <unistd.h> 44 45#include "libpmcinternal.h" 46 47/* Function prototypes */ 48#if defined(__i386__) 49static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 50 struct pmc_op_pmcallocate *_pmc_config); 51#endif 52#if defined(__amd64__) || defined(__i386__) 53static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 54 struct pmc_op_pmcallocate *_pmc_config); 55static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 62 struct pmc_op_pmcallocate *_pmc_config); 63static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65#endif 66#if defined(__i386__) 67static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 70 struct pmc_op_pmcallocate *_pmc_config); 71#endif 72#if defined(__amd64__) || defined(__i386__) 73static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 74 struct pmc_op_pmcallocate *_pmc_config); 75#endif 76#if defined(__XSCALE__) 77static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79#endif 80#if defined(__mips__) 81static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, 82 struct pmc_op_pmcallocate *_pmc_config); 83#endif /* __mips__ */ 84static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 85 struct pmc_op_pmcallocate *_pmc_config); 86 87#if defined(__powerpc__) 88static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec, 89 struct pmc_op_pmcallocate *_pmc_config); 90#endif /* __powerpc__ */ 91 92#define PMC_CALL(cmd, params) \ 93 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 94 95/* 96 * Event aliases provide a way for the user to ask for generic events 97 * like "cache-misses", or "instructions-retired". These aliases are 98 * mapped to the appropriate canonical event descriptions using a 99 * lookup table. 100 */ 101struct pmc_event_alias { 102 const char *pm_alias; 103 const char *pm_spec; 104}; 105 106static const struct pmc_event_alias *pmc_mdep_event_aliases; 107 108/* 109 * The pmc_event_descr structure maps symbolic names known to the user 110 * to integer codes used by the PMC KLD. 111 */ 112struct pmc_event_descr { 113 const char *pm_ev_name; 114 enum pmc_event pm_ev_code; 115}; 116 117/* 118 * The pmc_class_descr structure maps class name prefixes for 119 * event names to event tables and other PMC class data. 120 */ 121struct pmc_class_descr { 122 const char *pm_evc_name; 123 size_t pm_evc_name_size; 124 enum pmc_class pm_evc_class; 125 const struct pmc_event_descr *pm_evc_event_table; 126 size_t pm_evc_event_table_size; 127 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 128 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 129}; 130 131#define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 132#define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 133 134#undef __PMC_EV 135#define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 136 137/* 138 * PMC_CLASSDEP_TABLE(NAME, CLASS) 139 * 140 * Define a table mapping event names and aliases to HWPMC event IDs. 141 */ 142#define PMC_CLASSDEP_TABLE(N, C) \ 143 static const struct pmc_event_descr N##_event_table[] = \ 144 { \ 145 __PMC_EV_##C() \ 146 } 147 148PMC_CLASSDEP_TABLE(iaf, IAF); 149PMC_CLASSDEP_TABLE(k7, K7); 150PMC_CLASSDEP_TABLE(k8, K8); 151PMC_CLASSDEP_TABLE(p4, P4); 152PMC_CLASSDEP_TABLE(p5, P5); 153PMC_CLASSDEP_TABLE(p6, P6); 154PMC_CLASSDEP_TABLE(xscale, XSCALE); 155PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 156PMC_CLASSDEP_TABLE(octeon, OCTEON); 157PMC_CLASSDEP_TABLE(ucf, UCF); 158PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 159 160static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; 161 162#undef __PMC_EV_ALIAS 163#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 164 165static const struct pmc_event_descr atom_event_table[] = 166{ 167 __PMC_EV_ALIAS_ATOM() 168}; 169 170static const struct pmc_event_descr core_event_table[] = 171{ 172 __PMC_EV_ALIAS_CORE() 173}; 174 175 176static const struct pmc_event_descr core2_event_table[] = 177{ 178 __PMC_EV_ALIAS_CORE2() 179}; 180 181static const struct pmc_event_descr corei7_event_table[] = 182{ 183 __PMC_EV_ALIAS_COREI7() 184}; 185 186static const struct pmc_event_descr ivybridge_event_table[] = 187{ 188 __PMC_EV_ALIAS_IVYBRIDGE() 189}; 190 191static const struct pmc_event_descr ivybridge_xeon_event_table[] = 192{ 193 __PMC_EV_ALIAS_IVYBRIDGE_XEON() 194}; 195 196static const struct pmc_event_descr sandybridge_event_table[] = 197{ 198 __PMC_EV_ALIAS_SANDYBRIDGE() 199}; 200 201static const struct pmc_event_descr sandybridge_xeon_event_table[] = 202{ 203 __PMC_EV_ALIAS_SANDYBRIDGE_XEON() 204}; 205 206static const struct pmc_event_descr westmere_event_table[] = 207{ 208 __PMC_EV_ALIAS_WESTMERE() 209}; 210 211static const struct pmc_event_descr corei7uc_event_table[] = 212{ 213 __PMC_EV_ALIAS_COREI7UC() 214}; 215 216static const struct pmc_event_descr sandybridgeuc_event_table[] = 217{ 218 __PMC_EV_ALIAS_SANDYBRIDGEUC() 219}; 220 221static const struct pmc_event_descr westmereuc_event_table[] = 222{ 223 __PMC_EV_ALIAS_WESTMEREUC() 224}; 225 226/* 227 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 228 * 229 * Map a CPU to the PMC classes it supports. 230 */ 231#define PMC_MDEP_TABLE(N,C,...) \ 232 static const enum pmc_class N##_pmc_classes[] = { \ 233 PMC_CLASS_##C, __VA_ARGS__ \ 234 } 235 236PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 237PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); 238PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 239PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 240PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 241PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 242PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 243PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); 244PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 245PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); 246PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); 247PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); 248PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); 249PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); 250PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); 251PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); 252PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); 253PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); 254PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); 255 256static const struct pmc_event_descr tsc_event_table[] = 257{ 258 __PMC_EV_TSC() 259}; 260 261#undef PMC_CLASS_TABLE_DESC 262#define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 263static const struct pmc_class_descr NAME##_class_table_descr = \ 264 { \ 265 .pm_evc_name = #CLASS "-", \ 266 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 267 .pm_evc_class = PMC_CLASS_##CLASS , \ 268 .pm_evc_event_table = EVENTS##_event_table , \ 269 .pm_evc_event_table_size = \ 270 PMC_EVENT_TABLE_SIZE(EVENTS), \ 271 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 272 } 273 274#if defined(__i386__) || defined(__amd64__) 275PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 276PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 277PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 278PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 279PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 280PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); 281PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); 282PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); 283PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); 284PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 285PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 286PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 287PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); 288PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 289#endif 290#if defined(__i386__) 291PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 292#endif 293#if defined(__i386__) || defined(__amd64__) 294PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 295PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 296#endif 297#if defined(__i386__) 298PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 299PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 300#endif 301#if defined(__i386__) || defined(__amd64__) 302PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 303#endif 304#if defined(__XSCALE__) 305PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 306#endif 307#if defined(__mips__) 308PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); 309PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); 310#endif /* __mips__ */ 311#if defined(__powerpc__) 312PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450); 313#endif 314 315static struct pmc_class_descr soft_class_table_descr = 316{ 317 .pm_evc_name = "SOFT-", 318 .pm_evc_name_size = sizeof("SOFT-") - 1, 319 .pm_evc_class = PMC_CLASS_SOFT, 320 .pm_evc_event_table = NULL, 321 .pm_evc_event_table_size = 0, 322 .pm_evc_allocate_pmc = soft_allocate_pmc 323}; 324 325#undef PMC_CLASS_TABLE_DESC 326 327static const struct pmc_class_descr **pmc_class_table; 328#define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 329 330static const enum pmc_class *pmc_mdep_class_list; 331static size_t pmc_mdep_class_list_size; 332 333/* 334 * Mapping tables, mapping enumeration values to human readable 335 * strings. 336 */ 337 338static const char * pmc_capability_names[] = { 339#undef __PMC_CAP 340#define __PMC_CAP(N,V,D) #N , 341 __PMC_CAPS() 342}; 343 344static const char * pmc_class_names[] = { 345#undef __PMC_CLASS 346#define __PMC_CLASS(C) #C , 347 __PMC_CLASSES() 348}; 349 350struct pmc_cputype_map { 351 enum pmc_cputype pm_cputype; 352 const char *pm_name; 353}; 354 355static const struct pmc_cputype_map pmc_cputype_names[] = { 356#undef __PMC_CPU 357#define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 358 __PMC_CPUS() 359}; 360 361static const char * pmc_disposition_names[] = { 362#undef __PMC_DISP 363#define __PMC_DISP(D) #D , 364 __PMC_DISPOSITIONS() 365}; 366 367static const char * pmc_mode_names[] = { 368#undef __PMC_MODE 369#define __PMC_MODE(M,N) #M , 370 __PMC_MODES() 371}; 372 373static const char * pmc_state_names[] = { 374#undef __PMC_STATE 375#define __PMC_STATE(S) #S , 376 __PMC_STATES() 377}; 378 379/* 380 * Filled in by pmc_init(). 381 */ 382static int pmc_syscall = -1; 383static struct pmc_cpuinfo cpu_info; 384static struct pmc_op_getdyneventinfo soft_event_info; 385 386/* Event masks for events */ 387struct pmc_masks { 388 const char *pm_name; 389 const uint64_t pm_value; 390}; 391#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 392#define NULLMASK { .pm_name = NULL } 393 394#if defined(__amd64__) || defined(__i386__) 395static int 396pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) 397{ 398 const struct pmc_masks *pm; 399 char *q, *r; 400 int c; 401 402 if (pmask == NULL) /* no mask keywords */ 403 return (-1); 404 q = strchr(p, '='); /* skip '=' */ 405 if (*++q == '\0') /* no more data */ 406 return (-1); 407 c = 0; /* count of mask keywords seen */ 408 while ((r = strsep(&q, "+")) != NULL) { 409 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 410 pm++) 411 ; 412 if (pm->pm_name == NULL) /* not found */ 413 return (-1); 414 *evmask |= pm->pm_value; 415 c++; 416 } 417 return (c); 418} 419#endif 420 421#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 422#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 423#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 424 425#if defined(__i386__) 426 427/* 428 * AMD K7 (Athlon) CPUs. 429 */ 430 431static struct pmc_event_alias k7_aliases[] = { 432 EV_ALIAS("branches", "k7-retired-branches"), 433 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 434 EV_ALIAS("cycles", "tsc"), 435 EV_ALIAS("dc-misses", "k7-dc-misses"), 436 EV_ALIAS("ic-misses", "k7-ic-misses"), 437 EV_ALIAS("instructions", "k7-retired-instructions"), 438 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 439 EV_ALIAS(NULL, NULL) 440}; 441 442#define K7_KW_COUNT "count" 443#define K7_KW_EDGE "edge" 444#define K7_KW_INV "inv" 445#define K7_KW_OS "os" 446#define K7_KW_UNITMASK "unitmask" 447#define K7_KW_USR "usr" 448 449static int 450k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 451 struct pmc_op_pmcallocate *pmc_config) 452{ 453 char *e, *p, *q; 454 int c, has_unitmask; 455 uint32_t count, unitmask; 456 457 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 458 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 459 460 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 461 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 462 pe == PMC_EV_K7_DC_WRITEBACKS) { 463 has_unitmask = 1; 464 unitmask = AMD_PMC_UNITMASK_MOESI; 465 } else 466 unitmask = has_unitmask = 0; 467 468 while ((p = strsep(&ctrspec, ",")) != NULL) { 469 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 470 q = strchr(p, '='); 471 if (*++q == '\0') /* skip '=' */ 472 return (-1); 473 474 count = strtol(q, &e, 0); 475 if (e == q || *e != '\0') 476 return (-1); 477 478 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 479 pmc_config->pm_md.pm_amd.pm_amd_config |= 480 AMD_PMC_TO_COUNTER(count); 481 482 } else if (KWMATCH(p, K7_KW_EDGE)) { 483 pmc_config->pm_caps |= PMC_CAP_EDGE; 484 } else if (KWMATCH(p, K7_KW_INV)) { 485 pmc_config->pm_caps |= PMC_CAP_INVERT; 486 } else if (KWMATCH(p, K7_KW_OS)) { 487 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 488 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 489 if (has_unitmask == 0) 490 return (-1); 491 unitmask = 0; 492 q = strchr(p, '='); 493 if (*++q == '\0') /* skip '=' */ 494 return (-1); 495 496 while ((c = tolower(*q++)) != 0) 497 if (c == 'm') 498 unitmask |= AMD_PMC_UNITMASK_M; 499 else if (c == 'o') 500 unitmask |= AMD_PMC_UNITMASK_O; 501 else if (c == 'e') 502 unitmask |= AMD_PMC_UNITMASK_E; 503 else if (c == 's') 504 unitmask |= AMD_PMC_UNITMASK_S; 505 else if (c == 'i') 506 unitmask |= AMD_PMC_UNITMASK_I; 507 else if (c == '+') 508 continue; 509 else 510 return (-1); 511 512 if (unitmask == 0) 513 return (-1); 514 515 } else if (KWMATCH(p, K7_KW_USR)) { 516 pmc_config->pm_caps |= PMC_CAP_USER; 517 } else 518 return (-1); 519 } 520 521 if (has_unitmask) { 522 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 523 pmc_config->pm_md.pm_amd.pm_amd_config |= 524 AMD_PMC_TO_UNITMASK(unitmask); 525 } 526 527 return (0); 528 529} 530 531#endif 532 533#if defined(__amd64__) || defined(__i386__) 534 535/* 536 * Intel Core (Family 6, Model E) PMCs. 537 */ 538 539static struct pmc_event_alias core_aliases[] = { 540 EV_ALIAS("branches", "iap-br-instr-ret"), 541 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 542 EV_ALIAS("cycles", "tsc-tsc"), 543 EV_ALIAS("ic-misses", "iap-icache-misses"), 544 EV_ALIAS("instructions", "iap-instr-ret"), 545 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 546 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 547 EV_ALIAS(NULL, NULL) 548}; 549 550/* 551 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 552 * and Atom (Family 6, model 1CH) PMCs. 553 * 554 * We map aliases to events on the fixed-function counters if these 555 * are present. Note that not all CPUs in this family contain fixed-function 556 * counters. 557 */ 558 559static struct pmc_event_alias core2_aliases[] = { 560 EV_ALIAS("branches", "iap-br-inst-retired.any"), 561 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 562 EV_ALIAS("cycles", "tsc-tsc"), 563 EV_ALIAS("ic-misses", "iap-l1i-misses"), 564 EV_ALIAS("instructions", "iaf-instr-retired.any"), 565 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 566 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 567 EV_ALIAS(NULL, NULL) 568}; 569 570static struct pmc_event_alias core2_aliases_without_iaf[] = { 571 EV_ALIAS("branches", "iap-br-inst-retired.any"), 572 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 573 EV_ALIAS("cycles", "tsc-tsc"), 574 EV_ALIAS("ic-misses", "iap-l1i-misses"), 575 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 576 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 577 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 578 EV_ALIAS(NULL, NULL) 579}; 580 581#define atom_aliases core2_aliases 582#define atom_aliases_without_iaf core2_aliases_without_iaf 583#define corei7_aliases core2_aliases 584#define corei7_aliases_without_iaf core2_aliases_without_iaf 585#define ivybridge_aliases core2_aliases 586#define ivybridge_aliases_without_iaf core2_aliases_without_iaf 587#define ivybridge_xeon_aliases core2_aliases 588#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 589#define sandybridge_aliases core2_aliases 590#define sandybridge_aliases_without_iaf core2_aliases_without_iaf 591#define sandybridge_xeon_aliases core2_aliases 592#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf 593#define westmere_aliases core2_aliases 594#define westmere_aliases_without_iaf core2_aliases_without_iaf 595 596#define IAF_KW_OS "os" 597#define IAF_KW_USR "usr" 598#define IAF_KW_ANYTHREAD "anythread" 599 600/* 601 * Parse an event specifier for Intel fixed function counters. 602 */ 603static int 604iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 605 struct pmc_op_pmcallocate *pmc_config) 606{ 607 char *p; 608 609 (void) pe; 610 611 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 612 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 613 614 while ((p = strsep(&ctrspec, ",")) != NULL) { 615 if (KWMATCH(p, IAF_KW_OS)) 616 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 617 else if (KWMATCH(p, IAF_KW_USR)) 618 pmc_config->pm_caps |= PMC_CAP_USER; 619 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 620 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 621 else 622 return (-1); 623 } 624 625 return (0); 626} 627 628/* 629 * Core/Core2 support. 630 */ 631 632#define IAP_KW_AGENT "agent" 633#define IAP_KW_ANYTHREAD "anythread" 634#define IAP_KW_CACHESTATE "cachestate" 635#define IAP_KW_CMASK "cmask" 636#define IAP_KW_CORE "core" 637#define IAP_KW_EDGE "edge" 638#define IAP_KW_INV "inv" 639#define IAP_KW_OS "os" 640#define IAP_KW_PREFETCH "prefetch" 641#define IAP_KW_SNOOPRESPONSE "snoopresponse" 642#define IAP_KW_SNOOPTYPE "snooptype" 643#define IAP_KW_TRANSITION "trans" 644#define IAP_KW_USR "usr" 645#define IAP_KW_RSP "rsp" 646 647static struct pmc_masks iap_core_mask[] = { 648 PMCMASK(all, (0x3 << 14)), 649 PMCMASK(this, (0x1 << 14)), 650 NULLMASK 651}; 652 653static struct pmc_masks iap_agent_mask[] = { 654 PMCMASK(this, 0), 655 PMCMASK(any, (0x1 << 13)), 656 NULLMASK 657}; 658 659static struct pmc_masks iap_prefetch_mask[] = { 660 PMCMASK(both, (0x3 << 12)), 661 PMCMASK(only, (0x1 << 12)), 662 PMCMASK(exclude, 0), 663 NULLMASK 664}; 665 666static struct pmc_masks iap_cachestate_mask[] = { 667 PMCMASK(i, (1 << 8)), 668 PMCMASK(s, (1 << 9)), 669 PMCMASK(e, (1 << 10)), 670 PMCMASK(m, (1 << 11)), 671 NULLMASK 672}; 673 674static struct pmc_masks iap_snoopresponse_mask[] = { 675 PMCMASK(clean, (1 << 8)), 676 PMCMASK(hit, (1 << 9)), 677 PMCMASK(hitm, (1 << 11)), 678 NULLMASK 679}; 680 681static struct pmc_masks iap_snooptype_mask[] = { 682 PMCMASK(cmp2s, (1 << 8)), 683 PMCMASK(cmp2i, (1 << 9)), 684 NULLMASK 685}; 686 687static struct pmc_masks iap_transition_mask[] = { 688 PMCMASK(any, 0x00), 689 PMCMASK(frequency, 0x10), 690 NULLMASK 691}; 692 693static struct pmc_masks iap_rsp_mask_i7_wm[] = { 694 PMCMASK(DMND_DATA_RD, (1 << 0)), 695 PMCMASK(DMND_RFO, (1 << 1)), 696 PMCMASK(DMND_IFETCH, (1 << 2)), 697 PMCMASK(WB, (1 << 3)), 698 PMCMASK(PF_DATA_RD, (1 << 4)), 699 PMCMASK(PF_RFO, (1 << 5)), 700 PMCMASK(PF_IFETCH, (1 << 6)), 701 PMCMASK(OTHER, (1 << 7)), 702 PMCMASK(UNCORE_HIT, (1 << 8)), 703 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 704 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 705 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 706 PMCMASK(REMOTE_DRAM, (1 << 13)), 707 PMCMASK(LOCAL_DRAM, (1 << 14)), 708 PMCMASK(NON_DRAM, (1 << 15)), 709 NULLMASK 710}; 711 712static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { 713 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), 714 PMCMASK(REQ_DMND_RFO, (1ULL << 1)), 715 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), 716 PMCMASK(REQ_WB, (1ULL << 3)), 717 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), 718 PMCMASK(REQ_PF_RFO, (1ULL << 5)), 719 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), 720 PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), 721 PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), 722 PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), 723 PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), 724 PMCMASK(REQ_STRM_ST, (1ULL << 11)), 725 PMCMASK(REQ_OTHER, (1ULL << 15)), 726 PMCMASK(RES_ANY, (1ULL << 16)), 727 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), 728 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), 729 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), 730 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), 731 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), 732 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), 733 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), 734 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), 735 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), 736 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), 737 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), 738 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), 739 PMCMASK(RES_NON_DRAM, (1ULL << 37)), 740 NULLMASK 741}; 742 743static int 744iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 745 struct pmc_op_pmcallocate *pmc_config) 746{ 747 char *e, *p, *q; 748 uint64_t cachestate, evmask, rsp; 749 int count, n; 750 751 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 752 PMC_CAP_QUALIFIER); 753 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 754 755 cachestate = evmask = rsp = 0; 756 757 /* Parse additional modifiers if present */ 758 while ((p = strsep(&ctrspec, ",")) != NULL) { 759 760 n = 0; 761 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 762 q = strchr(p, '='); 763 if (*++q == '\0') /* skip '=' */ 764 return (-1); 765 count = strtol(q, &e, 0); 766 if (e == q || *e != '\0') 767 return (-1); 768 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 769 pmc_config->pm_md.pm_iap.pm_iap_config |= 770 IAP_CMASK(count); 771 } else if (KWMATCH(p, IAP_KW_EDGE)) { 772 pmc_config->pm_caps |= PMC_CAP_EDGE; 773 } else if (KWMATCH(p, IAP_KW_INV)) { 774 pmc_config->pm_caps |= PMC_CAP_INVERT; 775 } else if (KWMATCH(p, IAP_KW_OS)) { 776 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 777 } else if (KWMATCH(p, IAP_KW_USR)) { 778 pmc_config->pm_caps |= PMC_CAP_USER; 779 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 780 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 781 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 782 n = pmc_parse_mask(iap_core_mask, p, &evmask); 783 if (n != 1) 784 return (-1); 785 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 786 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 787 if (n != 1) 788 return (-1); 789 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 790 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 791 if (n != 1) 792 return (-1); 793 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 794 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 795 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 796 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 797 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 798 if (n != 1) 799 return (-1); 800 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 801 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 802 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 803 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 804 n = pmc_parse_mask(iap_snoopresponse_mask, p, 805 &evmask); 806 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 807 n = pmc_parse_mask(iap_snooptype_mask, p, 808 &evmask); 809 } else 810 return (-1); 811 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 812 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { 813 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 814 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); 815 } else 816 return (-1); 817 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 818 cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 819 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE || 820 cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) { 821 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 822 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); 823 } else 824 return (-1); 825 } else 826 return (-1); 827 828 if (n < 0) /* Parsing failed. */ 829 return (-1); 830 } 831 832 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 833 834 /* 835 * If the event requires a 'cachestate' qualifier but was not 836 * specified by the user, use a sensible default. 837 */ 838 switch (pe) { 839 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 840 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 841 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 842 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 843 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 844 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 845 case PMC_EV_IAP_EVENT_32H: /* Core */ 846 case PMC_EV_IAP_EVENT_40H: /* Core */ 847 case PMC_EV_IAP_EVENT_41H: /* Core */ 848 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 849 if (cachestate == 0) 850 cachestate = (0xF << 8); 851 break; 852 case PMC_EV_IAP_EVENT_77H: /* Atom */ 853 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 854 * Atom processor 855 */ 856 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 857 cachestate = (0xF << 8); 858 break; 859 default: 860 break; 861 } 862 863 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 864 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 865 866 return (0); 867} 868 869/* 870 * Intel Uncore. 871 */ 872 873static int 874ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 875 struct pmc_op_pmcallocate *pmc_config) 876{ 877 (void) pe; 878 (void) ctrspec; 879 880 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 881 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 882 883 return (0); 884} 885 886#define UCP_KW_CMASK "cmask" 887#define UCP_KW_EDGE "edge" 888#define UCP_KW_INV "inv" 889 890static int 891ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 892 struct pmc_op_pmcallocate *pmc_config) 893{ 894 char *e, *p, *q; 895 int count, n; 896 897 (void) pe; 898 899 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 900 PMC_CAP_QUALIFIER); 901 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 902 903 /* Parse additional modifiers if present */ 904 while ((p = strsep(&ctrspec, ",")) != NULL) { 905 906 n = 0; 907 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 908 q = strchr(p, '='); 909 if (*++q == '\0') /* skip '=' */ 910 return (-1); 911 count = strtol(q, &e, 0); 912 if (e == q || *e != '\0') 913 return (-1); 914 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 915 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 916 UCP_CMASK(count); 917 } else if (KWMATCH(p, UCP_KW_EDGE)) { 918 pmc_config->pm_caps |= PMC_CAP_EDGE; 919 } else if (KWMATCH(p, UCP_KW_INV)) { 920 pmc_config->pm_caps |= PMC_CAP_INVERT; 921 } else 922 return (-1); 923 924 if (n < 0) /* Parsing failed. */ 925 return (-1); 926 } 927 928 return (0); 929} 930 931/* 932 * AMD K8 PMCs. 933 * 934 * These are very similar to AMD K7 PMCs, but support more kinds of 935 * events. 936 */ 937 938static struct pmc_event_alias k8_aliases[] = { 939 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 940 EV_ALIAS("branch-mispredicts", 941 "k8-fr-retired-taken-branches-mispredicted"), 942 EV_ALIAS("cycles", "tsc"), 943 EV_ALIAS("dc-misses", "k8-dc-miss"), 944 EV_ALIAS("ic-misses", "k8-ic-miss"), 945 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 946 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 947 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 948 EV_ALIAS(NULL, NULL) 949}; 950 951#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 952 953/* 954 * Parsing tables 955 */ 956 957/* fp dispatched fpu ops */ 958static const struct pmc_masks k8_mask_fdfo[] = { 959 __K8MASK(add-pipe-excluding-junk-ops, 0), 960 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 961 __K8MASK(store-pipe-excluding-junk-ops, 2), 962 __K8MASK(add-pipe-junk-ops, 3), 963 __K8MASK(multiply-pipe-junk-ops, 4), 964 __K8MASK(store-pipe-junk-ops, 5), 965 NULLMASK 966}; 967 968/* ls segment register loads */ 969static const struct pmc_masks k8_mask_lsrl[] = { 970 __K8MASK(es, 0), 971 __K8MASK(cs, 1), 972 __K8MASK(ss, 2), 973 __K8MASK(ds, 3), 974 __K8MASK(fs, 4), 975 __K8MASK(gs, 5), 976 __K8MASK(hs, 6), 977 NULLMASK 978}; 979 980/* ls locked operation */ 981static const struct pmc_masks k8_mask_llo[] = { 982 __K8MASK(locked-instructions, 0), 983 __K8MASK(cycles-in-request, 1), 984 __K8MASK(cycles-to-complete, 2), 985 NULLMASK 986}; 987 988/* dc refill from {l2,system} and dc copyback */ 989static const struct pmc_masks k8_mask_dc[] = { 990 __K8MASK(invalid, 0), 991 __K8MASK(shared, 1), 992 __K8MASK(exclusive, 2), 993 __K8MASK(owner, 3), 994 __K8MASK(modified, 4), 995 NULLMASK 996}; 997 998/* dc one bit ecc error */ 999static const struct pmc_masks k8_mask_dobee[] = { 1000 __K8MASK(scrubber, 0), 1001 __K8MASK(piggyback, 1), 1002 NULLMASK 1003}; 1004 1005/* dc dispatched prefetch instructions */ 1006static const struct pmc_masks k8_mask_ddpi[] = { 1007 __K8MASK(load, 0), 1008 __K8MASK(store, 1), 1009 __K8MASK(nta, 2), 1010 NULLMASK 1011}; 1012 1013/* dc dcache accesses by locks */ 1014static const struct pmc_masks k8_mask_dabl[] = { 1015 __K8MASK(accesses, 0), 1016 __K8MASK(misses, 1), 1017 NULLMASK 1018}; 1019 1020/* bu internal l2 request */ 1021static const struct pmc_masks k8_mask_bilr[] = { 1022 __K8MASK(ic-fill, 0), 1023 __K8MASK(dc-fill, 1), 1024 __K8MASK(tlb-reload, 2), 1025 __K8MASK(tag-snoop, 3), 1026 __K8MASK(cancelled, 4), 1027 NULLMASK 1028}; 1029 1030/* bu fill request l2 miss */ 1031static const struct pmc_masks k8_mask_bfrlm[] = { 1032 __K8MASK(ic-fill, 0), 1033 __K8MASK(dc-fill, 1), 1034 __K8MASK(tlb-reload, 2), 1035 NULLMASK 1036}; 1037 1038/* bu fill into l2 */ 1039static const struct pmc_masks k8_mask_bfil[] = { 1040 __K8MASK(dirty-l2-victim, 0), 1041 __K8MASK(victim-from-l2, 1), 1042 NULLMASK 1043}; 1044 1045/* fr retired fpu instructions */ 1046static const struct pmc_masks k8_mask_frfi[] = { 1047 __K8MASK(x87, 0), 1048 __K8MASK(mmx-3dnow, 1), 1049 __K8MASK(packed-sse-sse2, 2), 1050 __K8MASK(scalar-sse-sse2, 3), 1051 NULLMASK 1052}; 1053 1054/* fr retired fastpath double op instructions */ 1055static const struct pmc_masks k8_mask_frfdoi[] = { 1056 __K8MASK(low-op-pos-0, 0), 1057 __K8MASK(low-op-pos-1, 1), 1058 __K8MASK(low-op-pos-2, 2), 1059 NULLMASK 1060}; 1061 1062/* fr fpu exceptions */ 1063static const struct pmc_masks k8_mask_ffe[] = { 1064 __K8MASK(x87-reclass-microfaults, 0), 1065 __K8MASK(sse-retype-microfaults, 1), 1066 __K8MASK(sse-reclass-microfaults, 2), 1067 __K8MASK(sse-and-x87-microtraps, 3), 1068 NULLMASK 1069}; 1070 1071/* nb memory controller page access event */ 1072static const struct pmc_masks k8_mask_nmcpae[] = { 1073 __K8MASK(page-hit, 0), 1074 __K8MASK(page-miss, 1), 1075 __K8MASK(page-conflict, 2), 1076 NULLMASK 1077}; 1078 1079/* nb memory controller turnaround */ 1080static const struct pmc_masks k8_mask_nmct[] = { 1081 __K8MASK(dimm-turnaround, 0), 1082 __K8MASK(read-to-write-turnaround, 1), 1083 __K8MASK(write-to-read-turnaround, 2), 1084 NULLMASK 1085}; 1086 1087/* nb memory controller bypass saturation */ 1088static const struct pmc_masks k8_mask_nmcbs[] = { 1089 __K8MASK(memory-controller-hi-pri-bypass, 0), 1090 __K8MASK(memory-controller-lo-pri-bypass, 1), 1091 __K8MASK(dram-controller-interface-bypass, 2), 1092 __K8MASK(dram-controller-queue-bypass, 3), 1093 NULLMASK 1094}; 1095 1096/* nb sized commands */ 1097static const struct pmc_masks k8_mask_nsc[] = { 1098 __K8MASK(nonpostwrszbyte, 0), 1099 __K8MASK(nonpostwrszdword, 1), 1100 __K8MASK(postwrszbyte, 2), 1101 __K8MASK(postwrszdword, 3), 1102 __K8MASK(rdszbyte, 4), 1103 __K8MASK(rdszdword, 5), 1104 __K8MASK(rdmodwr, 6), 1105 NULLMASK 1106}; 1107 1108/* nb probe result */ 1109static const struct pmc_masks k8_mask_npr[] = { 1110 __K8MASK(probe-miss, 0), 1111 __K8MASK(probe-hit, 1), 1112 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1113 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1114 NULLMASK 1115}; 1116 1117/* nb hypertransport bus bandwidth */ 1118static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1119 __K8MASK(command, 0), 1120 __K8MASK(data, 1), 1121 __K8MASK(buffer-release, 2), 1122 __K8MASK(nop, 3), 1123 NULLMASK 1124}; 1125 1126#undef __K8MASK 1127 1128#define K8_KW_COUNT "count" 1129#define K8_KW_EDGE "edge" 1130#define K8_KW_INV "inv" 1131#define K8_KW_MASK "mask" 1132#define K8_KW_OS "os" 1133#define K8_KW_USR "usr" 1134 1135static int 1136k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1137 struct pmc_op_pmcallocate *pmc_config) 1138{ 1139 char *e, *p, *q; 1140 int n; 1141 uint32_t count; 1142 uint64_t evmask; 1143 const struct pmc_masks *pm, *pmask; 1144 1145 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1146 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1147 1148 pmask = NULL; 1149 evmask = 0; 1150 1151#define __K8SETMASK(M) pmask = k8_mask_##M 1152 1153 /* setup parsing tables */ 1154 switch (pe) { 1155 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1156 __K8SETMASK(fdfo); 1157 break; 1158 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1159 __K8SETMASK(lsrl); 1160 break; 1161 case PMC_EV_K8_LS_LOCKED_OPERATION: 1162 __K8SETMASK(llo); 1163 break; 1164 case PMC_EV_K8_DC_REFILL_FROM_L2: 1165 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1166 case PMC_EV_K8_DC_COPYBACK: 1167 __K8SETMASK(dc); 1168 break; 1169 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1170 __K8SETMASK(dobee); 1171 break; 1172 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1173 __K8SETMASK(ddpi); 1174 break; 1175 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1176 __K8SETMASK(dabl); 1177 break; 1178 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1179 __K8SETMASK(bilr); 1180 break; 1181 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1182 __K8SETMASK(bfrlm); 1183 break; 1184 case PMC_EV_K8_BU_FILL_INTO_L2: 1185 __K8SETMASK(bfil); 1186 break; 1187 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1188 __K8SETMASK(frfi); 1189 break; 1190 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1191 __K8SETMASK(frfdoi); 1192 break; 1193 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1194 __K8SETMASK(ffe); 1195 break; 1196 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1197 __K8SETMASK(nmcpae); 1198 break; 1199 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1200 __K8SETMASK(nmct); 1201 break; 1202 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1203 __K8SETMASK(nmcbs); 1204 break; 1205 case PMC_EV_K8_NB_SIZED_COMMANDS: 1206 __K8SETMASK(nsc); 1207 break; 1208 case PMC_EV_K8_NB_PROBE_RESULT: 1209 __K8SETMASK(npr); 1210 break; 1211 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1212 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1213 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1214 __K8SETMASK(nhbb); 1215 break; 1216 1217 default: 1218 break; /* no options defined */ 1219 } 1220 1221 while ((p = strsep(&ctrspec, ",")) != NULL) { 1222 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1223 q = strchr(p, '='); 1224 if (*++q == '\0') /* skip '=' */ 1225 return (-1); 1226 1227 count = strtol(q, &e, 0); 1228 if (e == q || *e != '\0') 1229 return (-1); 1230 1231 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1232 pmc_config->pm_md.pm_amd.pm_amd_config |= 1233 AMD_PMC_TO_COUNTER(count); 1234 1235 } else if (KWMATCH(p, K8_KW_EDGE)) { 1236 pmc_config->pm_caps |= PMC_CAP_EDGE; 1237 } else if (KWMATCH(p, K8_KW_INV)) { 1238 pmc_config->pm_caps |= PMC_CAP_INVERT; 1239 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1240 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1241 return (-1); 1242 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1243 } else if (KWMATCH(p, K8_KW_OS)) { 1244 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1245 } else if (KWMATCH(p, K8_KW_USR)) { 1246 pmc_config->pm_caps |= PMC_CAP_USER; 1247 } else 1248 return (-1); 1249 } 1250 1251 /* other post processing */ 1252 switch (pe) { 1253 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1254 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1255 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1256 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1257 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1258 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1259 /* XXX only available in rev B and later */ 1260 break; 1261 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1262 /* XXX only available in rev C and later */ 1263 break; 1264 case PMC_EV_K8_LS_LOCKED_OPERATION: 1265 /* XXX CPU Rev A,B evmask is to be zero */ 1266 if (evmask & (evmask - 1)) /* > 1 bit set */ 1267 return (-1); 1268 if (evmask == 0) { 1269 evmask = 0x01; /* Rev C and later: #instrs */ 1270 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1271 } 1272 break; 1273 default: 1274 if (evmask == 0 && pmask != NULL) { 1275 for (pm = pmask; pm->pm_name; pm++) 1276 evmask |= pm->pm_value; 1277 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1278 } 1279 } 1280 1281 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1282 pmc_config->pm_md.pm_amd.pm_amd_config = 1283 AMD_PMC_TO_UNITMASK(evmask); 1284 1285 return (0); 1286} 1287 1288#endif 1289 1290#if defined(__amd64__) || defined(__i386__) 1291 1292/* 1293 * Intel P4 PMCs 1294 */ 1295 1296static struct pmc_event_alias p4_aliases[] = { 1297 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1298 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1299 EV_ALIAS("cycles", "tsc"), 1300 EV_ALIAS("instructions", 1301 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1302 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1303 EV_ALIAS(NULL, NULL) 1304}; 1305 1306#define P4_KW_ACTIVE "active" 1307#define P4_KW_ACTIVE_ANY "any" 1308#define P4_KW_ACTIVE_BOTH "both" 1309#define P4_KW_ACTIVE_NONE "none" 1310#define P4_KW_ACTIVE_SINGLE "single" 1311#define P4_KW_BUSREQTYPE "busreqtype" 1312#define P4_KW_CASCADE "cascade" 1313#define P4_KW_EDGE "edge" 1314#define P4_KW_INV "complement" 1315#define P4_KW_OS "os" 1316#define P4_KW_MASK "mask" 1317#define P4_KW_PRECISE "precise" 1318#define P4_KW_TAG "tag" 1319#define P4_KW_THRESHOLD "threshold" 1320#define P4_KW_USR "usr" 1321 1322#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1323 1324static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1325 __P4MASK(dd, 0), 1326 __P4MASK(db, 1), 1327 __P4MASK(di, 2), 1328 __P4MASK(bd, 3), 1329 __P4MASK(bb, 4), 1330 __P4MASK(bi, 5), 1331 __P4MASK(id, 6), 1332 __P4MASK(ib, 7), 1333 NULLMASK 1334}; 1335 1336static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1337 __P4MASK(tcmiss, 0), 1338 NULLMASK, 1339}; 1340 1341static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1342 __P4MASK(hit, 0), 1343 __P4MASK(miss, 1), 1344 __P4MASK(hit-uc, 2), 1345 NULLMASK 1346}; 1347 1348static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1349 __P4MASK(st-rb-full, 2), 1350 __P4MASK(64k-conf, 3), 1351 NULLMASK 1352}; 1353 1354static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1355 __P4MASK(lsc, 0), 1356 __P4MASK(ssc, 1), 1357 NULLMASK 1358}; 1359 1360static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1361 __P4MASK(split-ld, 1), 1362 NULLMASK 1363}; 1364 1365static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1366 __P4MASK(split-st, 1), 1367 NULLMASK 1368}; 1369 1370static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1371 __P4MASK(no-sta, 1), 1372 __P4MASK(no-std, 3), 1373 __P4MASK(partial-data, 4), 1374 __P4MASK(unalgn-addr, 5), 1375 NULLMASK 1376}; 1377 1378static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1379 __P4MASK(dtmiss, 0), 1380 __P4MASK(itmiss, 1), 1381 NULLMASK 1382}; 1383 1384static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1385 __P4MASK(rd-2ndl-hits, 0), 1386 __P4MASK(rd-2ndl-hite, 1), 1387 __P4MASK(rd-2ndl-hitm, 2), 1388 __P4MASK(rd-3rdl-hits, 3), 1389 __P4MASK(rd-3rdl-hite, 4), 1390 __P4MASK(rd-3rdl-hitm, 5), 1391 __P4MASK(rd-2ndl-miss, 8), 1392 __P4MASK(rd-3rdl-miss, 9), 1393 __P4MASK(wr-2ndl-miss, 10), 1394 NULLMASK 1395}; 1396 1397static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1398 __P4MASK(all-read, 5), 1399 __P4MASK(all-write, 6), 1400 __P4MASK(mem-uc, 7), 1401 __P4MASK(mem-wc, 8), 1402 __P4MASK(mem-wt, 9), 1403 __P4MASK(mem-wp, 10), 1404 __P4MASK(mem-wb, 11), 1405 __P4MASK(own, 13), 1406 __P4MASK(other, 14), 1407 __P4MASK(prefetch, 15), 1408 NULLMASK 1409}; 1410 1411static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1412 __P4MASK(all-read, 5), 1413 __P4MASK(all-write, 6), 1414 __P4MASK(mem-uc, 7), 1415 __P4MASK(mem-wc, 8), 1416 __P4MASK(mem-wt, 9), 1417 __P4MASK(mem-wp, 10), 1418 __P4MASK(mem-wb, 11), 1419 __P4MASK(own, 13), 1420 __P4MASK(other, 14), 1421 __P4MASK(prefetch, 15), 1422 NULLMASK 1423}; 1424 1425static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1426 __P4MASK(drdy-drv, 0), 1427 __P4MASK(drdy-own, 1), 1428 __P4MASK(drdy-other, 2), 1429 __P4MASK(dbsy-drv, 3), 1430 __P4MASK(dbsy-own, 4), 1431 __P4MASK(dbsy-other, 5), 1432 NULLMASK 1433}; 1434 1435static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1436 __P4MASK(req-type0, 0), 1437 __P4MASK(req-type1, 1), 1438 __P4MASK(req-len0, 2), 1439 __P4MASK(req-len1, 3), 1440 __P4MASK(req-io-type, 5), 1441 __P4MASK(req-lock-type, 6), 1442 __P4MASK(req-cache-type, 7), 1443 __P4MASK(req-split-type, 8), 1444 __P4MASK(req-dem-type, 9), 1445 __P4MASK(req-ord-type, 10), 1446 __P4MASK(mem-type0, 11), 1447 __P4MASK(mem-type1, 12), 1448 __P4MASK(mem-type2, 13), 1449 NULLMASK 1450}; 1451 1452static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1453 __P4MASK(all, 15), 1454 NULLMASK 1455}; 1456 1457static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1458 __P4MASK(all, 15), 1459 NULLMASK 1460}; 1461 1462static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1463 __P4MASK(all, 15), 1464 NULLMASK 1465}; 1466 1467static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1468 __P4MASK(all, 15), 1469 NULLMASK 1470}; 1471 1472static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1473 __P4MASK(all, 15), 1474 NULLMASK 1475}; 1476 1477static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1478 __P4MASK(all, 15), 1479 NULLMASK 1480}; 1481 1482static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1483 __P4MASK(all, 15), 1484 NULLMASK 1485}; 1486 1487static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1488 __P4MASK(all, 15), 1489 NULLMASK 1490}; 1491 1492static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1493 __P4MASK(allp0, 3), 1494 __P4MASK(allp2, 4), 1495 NULLMASK 1496}; 1497 1498static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1499 __P4MASK(running, 0), 1500 NULLMASK 1501}; 1502 1503static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1504 __P4MASK(cisc, 0), 1505 NULLMASK 1506}; 1507 1508static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1509 __P4MASK(from-tc-build, 0), 1510 __P4MASK(from-tc-deliver, 1), 1511 __P4MASK(from-rom, 2), 1512 NULLMASK 1513}; 1514 1515static const struct pmc_masks p4_mask_rmbt[] = { 1516 /* retired mispred branch type */ 1517 __P4MASK(conditional, 1), 1518 __P4MASK(call, 2), 1519 __P4MASK(return, 3), 1520 __P4MASK(indirect, 4), 1521 NULLMASK 1522}; 1523 1524static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1525 __P4MASK(conditional, 1), 1526 __P4MASK(call, 2), 1527 __P4MASK(retired, 3), 1528 __P4MASK(indirect, 4), 1529 NULLMASK 1530}; 1531 1532static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1533 __P4MASK(sbfull, 5), 1534 NULLMASK 1535}; 1536 1537static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1538 __P4MASK(wcb-evicts, 0), 1539 __P4MASK(wcb-full-evict, 1), 1540 NULLMASK 1541}; 1542 1543static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1544 __P4MASK(nbogus, 0), 1545 __P4MASK(bogus, 1), 1546 NULLMASK 1547}; 1548 1549static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1550 __P4MASK(nbogus0, 0), 1551 __P4MASK(nbogus1, 1), 1552 __P4MASK(nbogus2, 2), 1553 __P4MASK(nbogus3, 3), 1554 __P4MASK(bogus0, 4), 1555 __P4MASK(bogus1, 5), 1556 __P4MASK(bogus2, 6), 1557 __P4MASK(bogus3, 7), 1558 NULLMASK 1559}; 1560 1561static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1562 __P4MASK(nbogus, 0), 1563 __P4MASK(bogus, 1), 1564 NULLMASK 1565}; 1566 1567static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1568 __P4MASK(nbogusntag, 0), 1569 __P4MASK(nbogustag, 1), 1570 __P4MASK(bogusntag, 2), 1571 __P4MASK(bogustag, 3), 1572 NULLMASK 1573}; 1574 1575static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1576 __P4MASK(nbogus, 0), 1577 __P4MASK(bogus, 1), 1578 NULLMASK 1579}; 1580 1581static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1582 __P4MASK(tagloads, 1), 1583 __P4MASK(tagstores, 2), 1584 NULLMASK 1585}; 1586 1587static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1588 __P4MASK(mmnp, 0), 1589 __P4MASK(mmnm, 1), 1590 __P4MASK(mmtp, 2), 1591 __P4MASK(mmtm, 3), 1592 NULLMASK 1593}; 1594 1595static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1596 __P4MASK(nbogus, 0), 1597 NULLMASK 1598}; 1599 1600static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1601 __P4MASK(fpsu, 0), 1602 __P4MASK(fpso, 1), 1603 __P4MASK(poao, 2), 1604 __P4MASK(poau, 3), 1605 __P4MASK(prea, 4), 1606 NULLMASK 1607}; 1608 1609static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1610 __P4MASK(clear, 0), 1611 __P4MASK(moclear, 2), 1612 __P4MASK(smclear, 3), 1613 NULLMASK 1614}; 1615 1616/* P4 event parser */ 1617static int 1618p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1619 struct pmc_op_pmcallocate *pmc_config) 1620{ 1621 1622 char *e, *p, *q; 1623 int count, has_tag, has_busreqtype, n; 1624 uint32_t cccractivemask; 1625 uint64_t evmask; 1626 const struct pmc_masks *pm, *pmask; 1627 1628 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1629 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1630 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1631 1632 pmask = NULL; 1633 evmask = 0; 1634 cccractivemask = 0x3; 1635 has_tag = has_busreqtype = 0; 1636 1637#define __P4SETMASK(M) do { \ 1638 pmask = p4_mask_##M; \ 1639} while (0) 1640 1641 switch (pe) { 1642 case PMC_EV_P4_TC_DELIVER_MODE: 1643 __P4SETMASK(tcdm); 1644 break; 1645 case PMC_EV_P4_BPU_FETCH_REQUEST: 1646 __P4SETMASK(bfr); 1647 break; 1648 case PMC_EV_P4_ITLB_REFERENCE: 1649 __P4SETMASK(ir); 1650 break; 1651 case PMC_EV_P4_MEMORY_CANCEL: 1652 __P4SETMASK(memcan); 1653 break; 1654 case PMC_EV_P4_MEMORY_COMPLETE: 1655 __P4SETMASK(memcomp); 1656 break; 1657 case PMC_EV_P4_LOAD_PORT_REPLAY: 1658 __P4SETMASK(lpr); 1659 break; 1660 case PMC_EV_P4_STORE_PORT_REPLAY: 1661 __P4SETMASK(spr); 1662 break; 1663 case PMC_EV_P4_MOB_LOAD_REPLAY: 1664 __P4SETMASK(mlr); 1665 break; 1666 case PMC_EV_P4_PAGE_WALK_TYPE: 1667 __P4SETMASK(pwt); 1668 break; 1669 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1670 __P4SETMASK(bcr); 1671 break; 1672 case PMC_EV_P4_IOQ_ALLOCATION: 1673 __P4SETMASK(ia); 1674 has_busreqtype = 1; 1675 break; 1676 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1677 __P4SETMASK(iae); 1678 has_busreqtype = 1; 1679 break; 1680 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1681 __P4SETMASK(fda); 1682 break; 1683 case PMC_EV_P4_BSQ_ALLOCATION: 1684 __P4SETMASK(ba); 1685 break; 1686 case PMC_EV_P4_SSE_INPUT_ASSIST: 1687 __P4SETMASK(sia); 1688 break; 1689 case PMC_EV_P4_PACKED_SP_UOP: 1690 __P4SETMASK(psu); 1691 break; 1692 case PMC_EV_P4_PACKED_DP_UOP: 1693 __P4SETMASK(pdu); 1694 break; 1695 case PMC_EV_P4_SCALAR_SP_UOP: 1696 __P4SETMASK(ssu); 1697 break; 1698 case PMC_EV_P4_SCALAR_DP_UOP: 1699 __P4SETMASK(sdu); 1700 break; 1701 case PMC_EV_P4_64BIT_MMX_UOP: 1702 __P4SETMASK(64bmu); 1703 break; 1704 case PMC_EV_P4_128BIT_MMX_UOP: 1705 __P4SETMASK(128bmu); 1706 break; 1707 case PMC_EV_P4_X87_FP_UOP: 1708 __P4SETMASK(xfu); 1709 break; 1710 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1711 __P4SETMASK(xsmu); 1712 break; 1713 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1714 __P4SETMASK(gpe); 1715 break; 1716 case PMC_EV_P4_TC_MS_XFER: 1717 __P4SETMASK(tmx); 1718 break; 1719 case PMC_EV_P4_UOP_QUEUE_WRITES: 1720 __P4SETMASK(uqw); 1721 break; 1722 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1723 __P4SETMASK(rmbt); 1724 break; 1725 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1726 __P4SETMASK(rbt); 1727 break; 1728 case PMC_EV_P4_RESOURCE_STALL: 1729 __P4SETMASK(rs); 1730 break; 1731 case PMC_EV_P4_WC_BUFFER: 1732 __P4SETMASK(wb); 1733 break; 1734 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1735 case PMC_EV_P4_B2B_CYCLES: 1736 case PMC_EV_P4_BNR: 1737 case PMC_EV_P4_SNOOP: 1738 case PMC_EV_P4_RESPONSE: 1739 break; 1740 case PMC_EV_P4_FRONT_END_EVENT: 1741 __P4SETMASK(fee); 1742 break; 1743 case PMC_EV_P4_EXECUTION_EVENT: 1744 __P4SETMASK(ee); 1745 break; 1746 case PMC_EV_P4_REPLAY_EVENT: 1747 __P4SETMASK(re); 1748 break; 1749 case PMC_EV_P4_INSTR_RETIRED: 1750 __P4SETMASK(insret); 1751 break; 1752 case PMC_EV_P4_UOPS_RETIRED: 1753 __P4SETMASK(ur); 1754 break; 1755 case PMC_EV_P4_UOP_TYPE: 1756 __P4SETMASK(ut); 1757 break; 1758 case PMC_EV_P4_BRANCH_RETIRED: 1759 __P4SETMASK(br); 1760 break; 1761 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1762 __P4SETMASK(mbr); 1763 break; 1764 case PMC_EV_P4_X87_ASSIST: 1765 __P4SETMASK(xa); 1766 break; 1767 case PMC_EV_P4_MACHINE_CLEAR: 1768 __P4SETMASK(machclr); 1769 break; 1770 default: 1771 return (-1); 1772 } 1773 1774 /* process additional flags */ 1775 while ((p = strsep(&ctrspec, ",")) != NULL) { 1776 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1777 q = strchr(p, '='); 1778 if (*++q == '\0') /* skip '=' */ 1779 return (-1); 1780 1781 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1782 cccractivemask = 0x0; 1783 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1784 cccractivemask = 0x1; 1785 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1786 cccractivemask = 0x2; 1787 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1788 cccractivemask = 0x3; 1789 else 1790 return (-1); 1791 1792 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1793 if (has_busreqtype == 0) 1794 return (-1); 1795 1796 q = strchr(p, '='); 1797 if (*++q == '\0') /* skip '=' */ 1798 return (-1); 1799 1800 count = strtol(q, &e, 0); 1801 if (e == q || *e != '\0') 1802 return (-1); 1803 evmask = (evmask & ~0x1F) | (count & 0x1F); 1804 } else if (KWMATCH(p, P4_KW_CASCADE)) 1805 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1806 else if (KWMATCH(p, P4_KW_EDGE)) 1807 pmc_config->pm_caps |= PMC_CAP_EDGE; 1808 else if (KWMATCH(p, P4_KW_INV)) 1809 pmc_config->pm_caps |= PMC_CAP_INVERT; 1810 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1811 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1812 return (-1); 1813 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1814 } else if (KWMATCH(p, P4_KW_OS)) 1815 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1816 else if (KWMATCH(p, P4_KW_PRECISE)) 1817 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1818 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1819 if (has_tag == 0) 1820 return (-1); 1821 1822 q = strchr(p, '='); 1823 if (*++q == '\0') /* skip '=' */ 1824 return (-1); 1825 1826 count = strtol(q, &e, 0); 1827 if (e == q || *e != '\0') 1828 return (-1); 1829 1830 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1831 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1832 P4_ESCR_TO_TAG_VALUE(count); 1833 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1834 q = strchr(p, '='); 1835 if (*++q == '\0') /* skip '=' */ 1836 return (-1); 1837 1838 count = strtol(q, &e, 0); 1839 if (e == q || *e != '\0') 1840 return (-1); 1841 1842 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1843 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1844 ~P4_CCCR_THRESHOLD_MASK; 1845 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1846 P4_CCCR_TO_THRESHOLD(count); 1847 } else if (KWMATCH(p, P4_KW_USR)) 1848 pmc_config->pm_caps |= PMC_CAP_USER; 1849 else 1850 return (-1); 1851 } 1852 1853 /* other post processing */ 1854 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1855 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1856 pe == PMC_EV_P4_BSQ_ALLOCATION) 1857 pmc_config->pm_caps |= PMC_CAP_EDGE; 1858 1859 /* fill in thread activity mask */ 1860 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1861 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1862 1863 if (evmask) 1864 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1865 1866 switch (pe) { 1867 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1868 if ((evmask & 0x06) == 0x06 || 1869 (evmask & 0x18) == 0x18) 1870 return (-1); /* can't have own+other bits together */ 1871 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1872 evmask = 0x1D; 1873 break; 1874 case PMC_EV_P4_MACHINE_CLEAR: 1875 /* only one bit is allowed to be set */ 1876 if ((evmask & (evmask - 1)) != 0) 1877 return (-1); 1878 if (evmask == 0) { 1879 evmask = 0x1; /* 'CLEAR' */ 1880 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1881 } 1882 break; 1883 default: 1884 if (evmask == 0 && pmask) { 1885 for (pm = pmask; pm->pm_name; pm++) 1886 evmask |= pm->pm_value; 1887 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1888 } 1889 } 1890 1891 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1892 P4_ESCR_TO_EVENT_MASK(evmask); 1893 1894 return (0); 1895} 1896 1897#endif 1898 1899#if defined(__i386__) 1900 1901/* 1902 * Pentium style PMCs 1903 */ 1904 1905static struct pmc_event_alias p5_aliases[] = { 1906 EV_ALIAS("branches", "p5-taken-branches"), 1907 EV_ALIAS("cycles", "tsc"), 1908 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1909 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1910 EV_ALIAS("instructions", "p5-instructions-executed"), 1911 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1912 EV_ALIAS("unhalted-cycles", 1913 "p5-number-of-cycles-not-in-halt-state"), 1914 EV_ALIAS(NULL, NULL) 1915}; 1916 1917static int 1918p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1919 struct pmc_op_pmcallocate *pmc_config) 1920{ 1921 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 1922} 1923 1924/* 1925 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 1926 * and Pentium M CPUs. 1927 */ 1928 1929static struct pmc_event_alias p6_aliases[] = { 1930 EV_ALIAS("branches", "p6-br-inst-retired"), 1931 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 1932 EV_ALIAS("cycles", "tsc"), 1933 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 1934 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 1935 EV_ALIAS("instructions", "p6-inst-retired"), 1936 EV_ALIAS("interrupts", "p6-hw-int-rx"), 1937 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 1938 EV_ALIAS(NULL, NULL) 1939}; 1940 1941#define P6_KW_CMASK "cmask" 1942#define P6_KW_EDGE "edge" 1943#define P6_KW_INV "inv" 1944#define P6_KW_OS "os" 1945#define P6_KW_UMASK "umask" 1946#define P6_KW_USR "usr" 1947 1948static struct pmc_masks p6_mask_mesi[] = { 1949 PMCMASK(m, 0x01), 1950 PMCMASK(e, 0x02), 1951 PMCMASK(s, 0x04), 1952 PMCMASK(i, 0x08), 1953 NULLMASK 1954}; 1955 1956static struct pmc_masks p6_mask_mesihw[] = { 1957 PMCMASK(m, 0x01), 1958 PMCMASK(e, 0x02), 1959 PMCMASK(s, 0x04), 1960 PMCMASK(i, 0x08), 1961 PMCMASK(nonhw, 0x00), 1962 PMCMASK(hw, 0x10), 1963 PMCMASK(both, 0x30), 1964 NULLMASK 1965}; 1966 1967static struct pmc_masks p6_mask_hw[] = { 1968 PMCMASK(nonhw, 0x00), 1969 PMCMASK(hw, 0x10), 1970 PMCMASK(both, 0x30), 1971 NULLMASK 1972}; 1973 1974static struct pmc_masks p6_mask_any[] = { 1975 PMCMASK(self, 0x00), 1976 PMCMASK(any, 0x20), 1977 NULLMASK 1978}; 1979 1980static struct pmc_masks p6_mask_ekp[] = { 1981 PMCMASK(nta, 0x00), 1982 PMCMASK(t1, 0x01), 1983 PMCMASK(t2, 0x02), 1984 PMCMASK(wos, 0x03), 1985 NULLMASK 1986}; 1987 1988static struct pmc_masks p6_mask_pps[] = { 1989 PMCMASK(packed-and-scalar, 0x00), 1990 PMCMASK(scalar, 0x01), 1991 NULLMASK 1992}; 1993 1994static struct pmc_masks p6_mask_mite[] = { 1995 PMCMASK(packed-multiply, 0x01), 1996 PMCMASK(packed-shift, 0x02), 1997 PMCMASK(pack, 0x04), 1998 PMCMASK(unpack, 0x08), 1999 PMCMASK(packed-logical, 0x10), 2000 PMCMASK(packed-arithmetic, 0x20), 2001 NULLMASK 2002}; 2003 2004static struct pmc_masks p6_mask_fmt[] = { 2005 PMCMASK(mmxtofp, 0x00), 2006 PMCMASK(fptommx, 0x01), 2007 NULLMASK 2008}; 2009 2010static struct pmc_masks p6_mask_sr[] = { 2011 PMCMASK(es, 0x01), 2012 PMCMASK(ds, 0x02), 2013 PMCMASK(fs, 0x04), 2014 PMCMASK(gs, 0x08), 2015 NULLMASK 2016}; 2017 2018static struct pmc_masks p6_mask_eet[] = { 2019 PMCMASK(all, 0x00), 2020 PMCMASK(freq, 0x02), 2021 NULLMASK 2022}; 2023 2024static struct pmc_masks p6_mask_efur[] = { 2025 PMCMASK(all, 0x00), 2026 PMCMASK(loadop, 0x01), 2027 PMCMASK(stdsta, 0x02), 2028 NULLMASK 2029}; 2030 2031static struct pmc_masks p6_mask_essir[] = { 2032 PMCMASK(sse-packed-single, 0x00), 2033 PMCMASK(sse-packed-single-scalar-single, 0x01), 2034 PMCMASK(sse2-packed-double, 0x02), 2035 PMCMASK(sse2-scalar-double, 0x03), 2036 NULLMASK 2037}; 2038 2039static struct pmc_masks p6_mask_esscir[] = { 2040 PMCMASK(sse-packed-single, 0x00), 2041 PMCMASK(sse-scalar-single, 0x01), 2042 PMCMASK(sse2-packed-double, 0x02), 2043 PMCMASK(sse2-scalar-double, 0x03), 2044 NULLMASK 2045}; 2046 2047/* P6 event parser */ 2048static int 2049p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 2050 struct pmc_op_pmcallocate *pmc_config) 2051{ 2052 char *e, *p, *q; 2053 uint64_t evmask; 2054 int count, n; 2055 const struct pmc_masks *pm, *pmask; 2056 2057 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2058 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 2059 2060 evmask = 0; 2061 2062#define P6MASKSET(M) pmask = p6_mask_ ## M 2063 2064 switch(pe) { 2065 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 2066 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 2067 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 2068 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 2069 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2070 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2071 case PMC_EV_P6_BUS_TRAN_BRD: 2072 case PMC_EV_P6_BUS_TRAN_RFO: 2073 case PMC_EV_P6_BUS_TRANS_WB: 2074 case PMC_EV_P6_BUS_TRAN_IFETCH: 2075 case PMC_EV_P6_BUS_TRAN_INVAL: 2076 case PMC_EV_P6_BUS_TRAN_PWR: 2077 case PMC_EV_P6_BUS_TRANS_P: 2078 case PMC_EV_P6_BUS_TRANS_IO: 2079 case PMC_EV_P6_BUS_TRAN_DEF: 2080 case PMC_EV_P6_BUS_TRAN_BURST: 2081 case PMC_EV_P6_BUS_TRAN_ANY: 2082 case PMC_EV_P6_BUS_TRAN_MEM: 2083 P6MASKSET(any); break; 2084 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2085 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2086 P6MASKSET(ekp); break; 2087 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2088 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2089 P6MASKSET(pps); break; 2090 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 2091 P6MASKSET(mite); break; 2092 case PMC_EV_P6_FP_MMX_TRANS: 2093 P6MASKSET(fmt); break; 2094 case PMC_EV_P6_SEG_RENAME_STALLS: 2095 case PMC_EV_P6_SEG_REG_RENAMES: 2096 P6MASKSET(sr); break; 2097 case PMC_EV_P6_EMON_EST_TRANS: 2098 P6MASKSET(eet); break; 2099 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2100 P6MASKSET(efur); break; 2101 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2102 P6MASKSET(essir); break; 2103 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2104 P6MASKSET(esscir); break; 2105 default: 2106 pmask = NULL; 2107 break; 2108 } 2109 2110 /* Pentium M PMCs have a few events with different semantics */ 2111 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2112 if (pe == PMC_EV_P6_L2_LD || 2113 pe == PMC_EV_P6_L2_LINES_IN || 2114 pe == PMC_EV_P6_L2_LINES_OUT) 2115 P6MASKSET(mesihw); 2116 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2117 P6MASKSET(hw); 2118 } 2119 2120 /* Parse additional modifiers if present */ 2121 while ((p = strsep(&ctrspec, ",")) != NULL) { 2122 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2123 q = strchr(p, '='); 2124 if (*++q == '\0') /* skip '=' */ 2125 return (-1); 2126 count = strtol(q, &e, 0); 2127 if (e == q || *e != '\0') 2128 return (-1); 2129 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2130 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2131 P6_EVSEL_TO_CMASK(count); 2132 } else if (KWMATCH(p, P6_KW_EDGE)) { 2133 pmc_config->pm_caps |= PMC_CAP_EDGE; 2134 } else if (KWMATCH(p, P6_KW_INV)) { 2135 pmc_config->pm_caps |= PMC_CAP_INVERT; 2136 } else if (KWMATCH(p, P6_KW_OS)) { 2137 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2138 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2139 evmask = 0; 2140 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2141 return (-1); 2142 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2143 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2144 pe == PMC_EV_P6_BUS_TRAN_BRD || 2145 pe == PMC_EV_P6_BUS_TRAN_RFO || 2146 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2147 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2148 pe == PMC_EV_P6_BUS_TRAN_PWR || 2149 pe == PMC_EV_P6_BUS_TRAN_DEF || 2150 pe == PMC_EV_P6_BUS_TRAN_BURST || 2151 pe == PMC_EV_P6_BUS_TRAN_ANY || 2152 pe == PMC_EV_P6_BUS_TRAN_MEM || 2153 pe == PMC_EV_P6_BUS_TRANS_IO || 2154 pe == PMC_EV_P6_BUS_TRANS_P || 2155 pe == PMC_EV_P6_BUS_TRANS_WB || 2156 pe == PMC_EV_P6_EMON_EST_TRANS || 2157 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2158 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2159 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2160 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2161 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2162 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2163 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2164 pe == PMC_EV_P6_FP_MMX_TRANS) 2165 && (n > 1)) /* Only one mask keyword is allowed. */ 2166 return (-1); 2167 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2168 } else if (KWMATCH(p, P6_KW_USR)) { 2169 pmc_config->pm_caps |= PMC_CAP_USER; 2170 } else 2171 return (-1); 2172 } 2173 2174 /* post processing */ 2175 switch (pe) { 2176 2177 /* 2178 * The following events default to an evmask of 0 2179 */ 2180 2181 /* default => 'self' */ 2182 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2183 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2184 case PMC_EV_P6_BUS_TRAN_BRD: 2185 case PMC_EV_P6_BUS_TRAN_RFO: 2186 case PMC_EV_P6_BUS_TRANS_WB: 2187 case PMC_EV_P6_BUS_TRAN_IFETCH: 2188 case PMC_EV_P6_BUS_TRAN_INVAL: 2189 case PMC_EV_P6_BUS_TRAN_PWR: 2190 case PMC_EV_P6_BUS_TRANS_P: 2191 case PMC_EV_P6_BUS_TRANS_IO: 2192 case PMC_EV_P6_BUS_TRAN_DEF: 2193 case PMC_EV_P6_BUS_TRAN_BURST: 2194 case PMC_EV_P6_BUS_TRAN_ANY: 2195 case PMC_EV_P6_BUS_TRAN_MEM: 2196 2197 /* default => 'nta' */ 2198 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2199 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2200 2201 /* default => 'packed and scalar' */ 2202 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2203 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2204 2205 /* default => 'mmx to fp transitions' */ 2206 case PMC_EV_P6_FP_MMX_TRANS: 2207 2208 /* default => 'SSE Packed Single' */ 2209 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2210 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2211 2212 /* default => 'all fused micro-ops' */ 2213 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2214 2215 /* default => 'all transitions' */ 2216 case PMC_EV_P6_EMON_EST_TRANS: 2217 break; 2218 2219 case PMC_EV_P6_MMX_UOPS_EXEC: 2220 evmask = 0x0F; /* only value allowed */ 2221 break; 2222 2223 default: 2224 /* 2225 * For all other events, set the default event mask 2226 * to a logical OR of all the allowed event mask bits. 2227 */ 2228 if (evmask == 0 && pmask) { 2229 for (pm = pmask; pm->pm_name; pm++) 2230 evmask |= pm->pm_value; 2231 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2232 } 2233 2234 break; 2235 } 2236 2237 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2238 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2239 P6_EVSEL_TO_UMASK(evmask); 2240 2241 return (0); 2242} 2243 2244#endif 2245 2246#if defined(__i386__) || defined(__amd64__) 2247static int 2248tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2249 struct pmc_op_pmcallocate *pmc_config) 2250{ 2251 if (pe != PMC_EV_TSC_TSC) 2252 return (-1); 2253 2254 /* TSC events must be unqualified. */ 2255 if (ctrspec && *ctrspec != '\0') 2256 return (-1); 2257 2258 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2259 pmc_config->pm_caps |= PMC_CAP_READ; 2260 2261 return (0); 2262} 2263#endif 2264 2265static struct pmc_event_alias generic_aliases[] = { 2266 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), 2267 EV_ALIAS(NULL, NULL) 2268}; 2269 2270static int 2271soft_allocate_pmc(enum pmc_event pe, char *ctrspec, 2272 struct pmc_op_pmcallocate *pmc_config) 2273{ 2274 (void)ctrspec; 2275 (void)pmc_config; 2276 2277 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST) 2278 return (-1); 2279 2280 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2281 return (0); 2282} 2283 2284#if defined(__XSCALE__) 2285 2286static struct pmc_event_alias xscale_aliases[] = { 2287 EV_ALIAS("branches", "BRANCH_RETIRED"), 2288 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2289 EV_ALIAS("dc-misses", "DC_MISS"), 2290 EV_ALIAS("ic-misses", "IC_MISS"), 2291 EV_ALIAS("instructions", "INSTR_RETIRED"), 2292 EV_ALIAS(NULL, NULL) 2293}; 2294static int 2295xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2296 struct pmc_op_pmcallocate *pmc_config __unused) 2297{ 2298 switch (pe) { 2299 default: 2300 break; 2301 } 2302 2303 return (0); 2304} 2305#endif 2306 2307#if defined(__mips__) 2308 2309static struct pmc_event_alias mips24k_aliases[] = { 2310 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2311 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2312 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2313 EV_ALIAS(NULL, NULL) 2314}; 2315 2316static struct pmc_event_alias octeon_aliases[] = { 2317 EV_ALIAS("instructions", "RET"), 2318 EV_ALIAS("branches", "BR"), 2319 EV_ALIAS("branch-mispredicts", "BRMIS"), 2320 EV_ALIAS(NULL, NULL) 2321}; 2322 2323#define MIPS_KW_OS "os" 2324#define MIPS_KW_USR "usr" 2325#define MIPS_KW_ANYTHREAD "anythread" 2326 2327static int 2328mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2329 struct pmc_op_pmcallocate *pmc_config __unused) 2330{ 2331 char *p; 2332 2333 (void) pe; 2334 2335 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2336 2337 while ((p = strsep(&ctrspec, ",")) != NULL) { 2338 if (KWMATCH(p, MIPS_KW_OS)) 2339 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2340 else if (KWMATCH(p, MIPS_KW_USR)) 2341 pmc_config->pm_caps |= PMC_CAP_USER; 2342 else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) 2343 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2344 else 2345 return (-1); 2346 } 2347 2348 return (0); 2349} 2350 2351#endif /* __mips__ */ 2352 2353#if defined(__powerpc__) 2354 2355static struct pmc_event_alias ppc7450_aliases[] = { 2356 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2357 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2358 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2359 EV_ALIAS(NULL, NULL) 2360}; 2361 2362#define PPC7450_KW_OS "os" 2363#define PPC7450_KW_USR "usr" 2364#define PPC7450_KW_ANYTHREAD "anythread" 2365 2366static int 2367ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2368 struct pmc_op_pmcallocate *pmc_config __unused) 2369{ 2370 char *p; 2371 2372 (void) pe; 2373 2374 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2375 2376 while ((p = strsep(&ctrspec, ",")) != NULL) { 2377 if (KWMATCH(p, PPC7450_KW_OS)) 2378 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2379 else if (KWMATCH(p, PPC7450_KW_USR)) 2380 pmc_config->pm_caps |= PMC_CAP_USER; 2381 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD)) 2382 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2383 else 2384 return (-1); 2385 } 2386 2387 return (0); 2388} 2389#endif /* __powerpc__ */ 2390 2391 2392/* 2393 * Match an event name `name' with its canonical form. 2394 * 2395 * Matches are case insensitive and spaces, periods, underscores and 2396 * hyphen characters are considered to match each other. 2397 * 2398 * Returns 1 for a match, 0 otherwise. 2399 */ 2400 2401static int 2402pmc_match_event_name(const char *name, const char *canonicalname) 2403{ 2404 int cc, nc; 2405 const unsigned char *c, *n; 2406 2407 c = (const unsigned char *) canonicalname; 2408 n = (const unsigned char *) name; 2409 2410 for (; (nc = *n) && (cc = *c); n++, c++) { 2411 2412 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2413 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2414 continue; 2415 2416 if (toupper(nc) == toupper(cc)) 2417 continue; 2418 2419 2420 return (0); 2421 } 2422 2423 if (*n == '\0' && *c == '\0') 2424 return (1); 2425 2426 return (0); 2427} 2428 2429/* 2430 * Match an event name against all the event named supported by a 2431 * PMC class. 2432 * 2433 * Returns an event descriptor pointer on match or NULL otherwise. 2434 */ 2435static const struct pmc_event_descr * 2436pmc_match_event_class(const char *name, 2437 const struct pmc_class_descr *pcd) 2438{ 2439 size_t n; 2440 const struct pmc_event_descr *ev; 2441 2442 ev = pcd->pm_evc_event_table; 2443 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2444 if (pmc_match_event_name(name, ev->pm_ev_name)) 2445 return (ev); 2446 2447 return (NULL); 2448} 2449 2450static int 2451pmc_mdep_is_compatible_class(enum pmc_class pc) 2452{ 2453 size_t n; 2454 2455 for (n = 0; n < pmc_mdep_class_list_size; n++) 2456 if (pmc_mdep_class_list[n] == pc) 2457 return (1); 2458 return (0); 2459} 2460 2461/* 2462 * API entry points 2463 */ 2464 2465int 2466pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2467 uint32_t flags, int cpu, pmc_id_t *pmcid) 2468{ 2469 size_t n; 2470 int retval; 2471 char *r, *spec_copy; 2472 const char *ctrname; 2473 const struct pmc_event_descr *ev; 2474 const struct pmc_event_alias *alias; 2475 struct pmc_op_pmcallocate pmc_config; 2476 const struct pmc_class_descr *pcd; 2477 2478 spec_copy = NULL; 2479 retval = -1; 2480 2481 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2482 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2483 errno = EINVAL; 2484 goto out; 2485 } 2486 2487 /* replace an event alias with the canonical event specifier */ 2488 if (pmc_mdep_event_aliases) 2489 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2490 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2491 spec_copy = strdup(alias->pm_spec); 2492 break; 2493 } 2494 2495 if (spec_copy == NULL) 2496 spec_copy = strdup(ctrspec); 2497 2498 r = spec_copy; 2499 ctrname = strsep(&r, ","); 2500 2501 /* 2502 * If a explicit class prefix was given by the user, restrict the 2503 * search for the event to the specified PMC class. 2504 */ 2505 ev = NULL; 2506 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2507 pcd = pmc_class_table[n]; 2508 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2509 strncasecmp(ctrname, pcd->pm_evc_name, 2510 pcd->pm_evc_name_size) == 0) { 2511 if ((ev = pmc_match_event_class(ctrname + 2512 pcd->pm_evc_name_size, pcd)) == NULL) { 2513 errno = EINVAL; 2514 goto out; 2515 } 2516 break; 2517 } 2518 } 2519 2520 /* 2521 * Otherwise, search for this event in all compatible PMC 2522 * classes. 2523 */ 2524 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2525 pcd = pmc_class_table[n]; 2526 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2527 ev = pmc_match_event_class(ctrname, pcd); 2528 } 2529 2530 if (ev == NULL) { 2531 errno = EINVAL; 2532 goto out; 2533 } 2534 2535 bzero(&pmc_config, sizeof(pmc_config)); 2536 pmc_config.pm_ev = ev->pm_ev_code; 2537 pmc_config.pm_class = pcd->pm_evc_class; 2538 pmc_config.pm_cpu = cpu; 2539 pmc_config.pm_mode = mode; 2540 pmc_config.pm_flags = flags; 2541 2542 if (PMC_IS_SAMPLING_MODE(mode)) 2543 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2544 2545 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2546 errno = EINVAL; 2547 goto out; 2548 } 2549 2550 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2551 goto out; 2552 2553 *pmcid = pmc_config.pm_pmcid; 2554 2555 retval = 0; 2556 2557 out: 2558 if (spec_copy) 2559 free(spec_copy); 2560 2561 return (retval); 2562} 2563 2564int 2565pmc_attach(pmc_id_t pmc, pid_t pid) 2566{ 2567 struct pmc_op_pmcattach pmc_attach_args; 2568 2569 pmc_attach_args.pm_pmc = pmc; 2570 pmc_attach_args.pm_pid = pid; 2571 2572 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2573} 2574 2575int 2576pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2577{ 2578 unsigned int i; 2579 enum pmc_class cl; 2580 2581 cl = PMC_ID_TO_CLASS(pmcid); 2582 for (i = 0; i < cpu_info.pm_nclass; i++) 2583 if (cpu_info.pm_classes[i].pm_class == cl) { 2584 *caps = cpu_info.pm_classes[i].pm_caps; 2585 return (0); 2586 } 2587 errno = EINVAL; 2588 return (-1); 2589} 2590 2591int 2592pmc_configure_logfile(int fd) 2593{ 2594 struct pmc_op_configurelog cla; 2595 2596 cla.pm_logfd = fd; 2597 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2598 return (-1); 2599 return (0); 2600} 2601 2602int 2603pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2604{ 2605 if (pmc_syscall == -1) { 2606 errno = ENXIO; 2607 return (-1); 2608 } 2609 2610 *pci = &cpu_info; 2611 return (0); 2612} 2613 2614int 2615pmc_detach(pmc_id_t pmc, pid_t pid) 2616{ 2617 struct pmc_op_pmcattach pmc_detach_args; 2618 2619 pmc_detach_args.pm_pmc = pmc; 2620 pmc_detach_args.pm_pid = pid; 2621 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2622} 2623 2624int 2625pmc_disable(int cpu, int pmc) 2626{ 2627 struct pmc_op_pmcadmin ssa; 2628 2629 ssa.pm_cpu = cpu; 2630 ssa.pm_pmc = pmc; 2631 ssa.pm_state = PMC_STATE_DISABLED; 2632 return (PMC_CALL(PMCADMIN, &ssa)); 2633} 2634 2635int 2636pmc_enable(int cpu, int pmc) 2637{ 2638 struct pmc_op_pmcadmin ssa; 2639 2640 ssa.pm_cpu = cpu; 2641 ssa.pm_pmc = pmc; 2642 ssa.pm_state = PMC_STATE_FREE; 2643 return (PMC_CALL(PMCADMIN, &ssa)); 2644} 2645 2646/* 2647 * Return a list of events known to a given PMC class. 'cl' is the 2648 * PMC class identifier, 'eventnames' is the returned list of 'const 2649 * char *' pointers pointing to the names of the events. 'nevents' is 2650 * the number of event name pointers returned. 2651 * 2652 * The space for 'eventnames' is allocated using malloc(3). The caller 2653 * is responsible for freeing this space when done. 2654 */ 2655int 2656pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2657 int *nevents) 2658{ 2659 int count; 2660 const char **names; 2661 const struct pmc_event_descr *ev; 2662 2663 switch (cl) 2664 { 2665 case PMC_CLASS_IAF: 2666 ev = iaf_event_table; 2667 count = PMC_EVENT_TABLE_SIZE(iaf); 2668 break; 2669 case PMC_CLASS_IAP: 2670 /* 2671 * Return the most appropriate set of event name 2672 * spellings for the current CPU. 2673 */ 2674 switch (cpu_info.pm_cputype) { 2675 default: 2676 case PMC_CPU_INTEL_ATOM: 2677 ev = atom_event_table; 2678 count = PMC_EVENT_TABLE_SIZE(atom); 2679 break; 2680 case PMC_CPU_INTEL_CORE: 2681 ev = core_event_table; 2682 count = PMC_EVENT_TABLE_SIZE(core); 2683 break; 2684 case PMC_CPU_INTEL_CORE2: 2685 case PMC_CPU_INTEL_CORE2EXTREME: 2686 ev = core2_event_table; 2687 count = PMC_EVENT_TABLE_SIZE(core2); 2688 break; 2689 case PMC_CPU_INTEL_COREI7: 2690 ev = corei7_event_table; 2691 count = PMC_EVENT_TABLE_SIZE(corei7); 2692 break; 2693 case PMC_CPU_INTEL_IVYBRIDGE: 2694 ev = ivybridge_event_table; 2695 count = PMC_EVENT_TABLE_SIZE(ivybridge); 2696 break; 2697 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2698 ev = ivybridge_xeon_event_table; 2699 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 2700 break; 2701 case PMC_CPU_INTEL_SANDYBRIDGE: 2702 ev = sandybridge_event_table; 2703 count = PMC_EVENT_TABLE_SIZE(sandybridge); 2704 break; 2705 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2706 ev = sandybridge_xeon_event_table; 2707 count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 2708 break; 2709 case PMC_CPU_INTEL_WESTMERE: 2710 ev = westmere_event_table; 2711 count = PMC_EVENT_TABLE_SIZE(westmere); 2712 break; 2713 } 2714 break; 2715 case PMC_CLASS_UCF: 2716 ev = ucf_event_table; 2717 count = PMC_EVENT_TABLE_SIZE(ucf); 2718 break; 2719 case PMC_CLASS_UCP: 2720 /* 2721 * Return the most appropriate set of event name 2722 * spellings for the current CPU. 2723 */ 2724 switch (cpu_info.pm_cputype) { 2725 default: 2726 case PMC_CPU_INTEL_COREI7: 2727 ev = corei7uc_event_table; 2728 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2729 break; 2730 case PMC_CPU_INTEL_SANDYBRIDGE: 2731 ev = sandybridgeuc_event_table; 2732 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); 2733 break; 2734 case PMC_CPU_INTEL_WESTMERE: 2735 ev = westmereuc_event_table; 2736 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2737 break; 2738 } 2739 break; 2740 case PMC_CLASS_TSC: 2741 ev = tsc_event_table; 2742 count = PMC_EVENT_TABLE_SIZE(tsc); 2743 break; 2744 case PMC_CLASS_K7: 2745 ev = k7_event_table; 2746 count = PMC_EVENT_TABLE_SIZE(k7); 2747 break; 2748 case PMC_CLASS_K8: 2749 ev = k8_event_table; 2750 count = PMC_EVENT_TABLE_SIZE(k8); 2751 break; 2752 case PMC_CLASS_P4: 2753 ev = p4_event_table; 2754 count = PMC_EVENT_TABLE_SIZE(p4); 2755 break; 2756 case PMC_CLASS_P5: 2757 ev = p5_event_table; 2758 count = PMC_EVENT_TABLE_SIZE(p5); 2759 break; 2760 case PMC_CLASS_P6: 2761 ev = p6_event_table; 2762 count = PMC_EVENT_TABLE_SIZE(p6); 2763 break; 2764 case PMC_CLASS_XSCALE: 2765 ev = xscale_event_table; 2766 count = PMC_EVENT_TABLE_SIZE(xscale); 2767 break; 2768 case PMC_CLASS_MIPS24K: 2769 ev = mips24k_event_table; 2770 count = PMC_EVENT_TABLE_SIZE(mips24k); 2771 break; 2772 case PMC_CLASS_OCTEON: 2773 ev = octeon_event_table; 2774 count = PMC_EVENT_TABLE_SIZE(octeon); 2775 break; 2776 case PMC_CLASS_PPC7450: 2777 ev = ppc7450_event_table; 2778 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2779 break; 2780 case PMC_CLASS_SOFT: 2781 ev = soft_event_table; 2782 count = soft_event_info.pm_nevent; 2783 break; 2784 default: 2785 errno = EINVAL; 2786 return (-1); 2787 } 2788 2789 if ((names = malloc(count * sizeof(const char *))) == NULL) 2790 return (-1); 2791 2792 *eventnames = names; 2793 *nevents = count; 2794 2795 for (;count--; ev++, names++) 2796 *names = ev->pm_ev_name; 2797 2798 return (0); 2799} 2800 2801int 2802pmc_flush_logfile(void) 2803{ 2804 return (PMC_CALL(FLUSHLOG,0)); 2805} 2806 2807int 2808pmc_close_logfile(void) 2809{ 2810 return (PMC_CALL(CLOSELOG,0)); 2811} 2812 2813int 2814pmc_get_driver_stats(struct pmc_driverstats *ds) 2815{ 2816 struct pmc_op_getdriverstats gms; 2817 2818 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2819 return (-1); 2820 2821 /* copy out fields in the current userland<->library interface */ 2822 ds->pm_intr_ignored = gms.pm_intr_ignored; 2823 ds->pm_intr_processed = gms.pm_intr_processed; 2824 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2825 ds->pm_syscalls = gms.pm_syscalls; 2826 ds->pm_syscall_errors = gms.pm_syscall_errors; 2827 ds->pm_buffer_requests = gms.pm_buffer_requests; 2828 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2829 ds->pm_log_sweeps = gms.pm_log_sweeps; 2830 return (0); 2831} 2832 2833int 2834pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2835{ 2836 struct pmc_op_getmsr gm; 2837 2838 gm.pm_pmcid = pmc; 2839 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2840 return (-1); 2841 *msr = gm.pm_msr; 2842 return (0); 2843} 2844 2845int 2846pmc_init(void) 2847{ 2848 int error, pmc_mod_id; 2849 unsigned int n; 2850 uint32_t abi_version; 2851 struct module_stat pmc_modstat; 2852 struct pmc_op_getcpuinfo op_cpu_info; 2853#if defined(__amd64__) || defined(__i386__) 2854 int cpu_has_iaf_counters; 2855 unsigned int t; 2856#endif 2857 2858 if (pmc_syscall != -1) /* already inited */ 2859 return (0); 2860 2861 /* retrieve the system call number from the KLD */ 2862 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2863 return (-1); 2864 2865 pmc_modstat.version = sizeof(struct module_stat); 2866 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2867 return (-1); 2868 2869 pmc_syscall = pmc_modstat.data.intval; 2870 2871 /* check the kernel module's ABI against our compiled-in version */ 2872 abi_version = PMC_VERSION; 2873 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2874 return (pmc_syscall = -1); 2875 2876 /* ignore patch & minor numbers for the comparision */ 2877 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2878 errno = EPROGMISMATCH; 2879 return (pmc_syscall = -1); 2880 } 2881 2882 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2883 return (pmc_syscall = -1); 2884 2885 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2886 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2887 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2888 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2889 for (n = 0; n < cpu_info.pm_nclass; n++) 2890 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 2891 2892 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 2893 sizeof(struct pmc_class_descr *)); 2894 2895 if (pmc_class_table == NULL) 2896 return (-1); 2897 2898 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 2899 pmc_class_table[n] = NULL; 2900 2901 /* 2902 * Get soft events list. 2903 */ 2904 soft_event_info.pm_class = PMC_CLASS_SOFT; 2905 if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) 2906 return (pmc_syscall = -1); 2907 2908 /* Map soft events to static list. */ 2909 for (n = 0; n < soft_event_info.pm_nevent; n++) { 2910 soft_event_table[n].pm_ev_name = 2911 soft_event_info.pm_events[n].pm_ev_name; 2912 soft_event_table[n].pm_ev_code = 2913 soft_event_info.pm_events[n].pm_ev_code; 2914 } 2915 soft_class_table_descr.pm_evc_event_table_size = \ 2916 soft_event_info.pm_nevent; 2917 soft_class_table_descr.pm_evc_event_table = \ 2918 soft_event_table; 2919 2920 /* 2921 * Fill in the class table. 2922 */ 2923 n = 0; 2924 2925 /* Fill soft events information. */ 2926 pmc_class_table[n++] = &soft_class_table_descr; 2927#if defined(__amd64__) || defined(__i386__) 2928 if (cpu_info.pm_cputype != PMC_CPU_GENERIC) 2929 pmc_class_table[n++] = &tsc_class_table_descr; 2930 2931 /* 2932 * Check if this CPU has fixed function counters. 2933 */ 2934 cpu_has_iaf_counters = 0; 2935 for (t = 0; t < cpu_info.pm_nclass; t++) 2936 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 2937 cpu_info.pm_classes[t].pm_num > 0) 2938 cpu_has_iaf_counters = 1; 2939#endif 2940 2941#define PMC_MDEP_INIT(C) do { \ 2942 pmc_mdep_event_aliases = C##_aliases; \ 2943 pmc_mdep_class_list = C##_pmc_classes; \ 2944 pmc_mdep_class_list_size = \ 2945 PMC_TABLE_SIZE(C##_pmc_classes); \ 2946 } while (0) 2947 2948#define PMC_MDEP_INIT_INTEL_V2(C) do { \ 2949 PMC_MDEP_INIT(C); \ 2950 pmc_class_table[n++] = &iaf_class_table_descr; \ 2951 if (!cpu_has_iaf_counters) \ 2952 pmc_mdep_event_aliases = \ 2953 C##_aliases_without_iaf; \ 2954 pmc_class_table[n] = &C##_class_table_descr; \ 2955 } while (0) 2956 2957 /* Configure the event name parser. */ 2958 switch (cpu_info.pm_cputype) { 2959#if defined(__i386__) 2960 case PMC_CPU_AMD_K7: 2961 PMC_MDEP_INIT(k7); 2962 pmc_class_table[n] = &k7_class_table_descr; 2963 break; 2964 case PMC_CPU_INTEL_P5: 2965 PMC_MDEP_INIT(p5); 2966 pmc_class_table[n] = &p5_class_table_descr; 2967 break; 2968 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 2969 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 2970 case PMC_CPU_INTEL_PIII: 2971 case PMC_CPU_INTEL_PM: 2972 PMC_MDEP_INIT(p6); 2973 pmc_class_table[n] = &p6_class_table_descr; 2974 break; 2975#endif 2976#if defined(__amd64__) || defined(__i386__) 2977 case PMC_CPU_AMD_K8: 2978 PMC_MDEP_INIT(k8); 2979 pmc_class_table[n] = &k8_class_table_descr; 2980 break; 2981 case PMC_CPU_INTEL_ATOM: 2982 PMC_MDEP_INIT_INTEL_V2(atom); 2983 break; 2984 case PMC_CPU_INTEL_CORE: 2985 PMC_MDEP_INIT(core); 2986 pmc_class_table[n] = &core_class_table_descr; 2987 break; 2988 case PMC_CPU_INTEL_CORE2: 2989 case PMC_CPU_INTEL_CORE2EXTREME: 2990 PMC_MDEP_INIT_INTEL_V2(core2); 2991 break; 2992 case PMC_CPU_INTEL_COREI7: 2993 pmc_class_table[n++] = &ucf_class_table_descr; 2994 pmc_class_table[n++] = &corei7uc_class_table_descr; 2995 PMC_MDEP_INIT_INTEL_V2(corei7); 2996 break; 2997 case PMC_CPU_INTEL_IVYBRIDGE: 2998 PMC_MDEP_INIT_INTEL_V2(ivybridge); 2999 break; 3000 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3001 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon); 3002 break; 3003 case PMC_CPU_INTEL_SANDYBRIDGE: 3004 pmc_class_table[n++] = &ucf_class_table_descr; 3005 pmc_class_table[n++] = &sandybridgeuc_class_table_descr; 3006 PMC_MDEP_INIT_INTEL_V2(sandybridge); 3007 break; 3008 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3009 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); 3010 break; 3011 case PMC_CPU_INTEL_WESTMERE: 3012 pmc_class_table[n++] = &ucf_class_table_descr; 3013 pmc_class_table[n++] = &westmereuc_class_table_descr; 3014 PMC_MDEP_INIT_INTEL_V2(westmere); 3015 break; 3016 case PMC_CPU_INTEL_PIV: 3017 PMC_MDEP_INIT(p4); 3018 pmc_class_table[n] = &p4_class_table_descr; 3019 break; 3020#endif 3021 case PMC_CPU_GENERIC: 3022 PMC_MDEP_INIT(generic); 3023 break; 3024#if defined(__XSCALE__) 3025 case PMC_CPU_INTEL_XSCALE: 3026 PMC_MDEP_INIT(xscale); 3027 pmc_class_table[n] = &xscale_class_table_descr; 3028 break; 3029#endif 3030#if defined(__mips__) 3031 case PMC_CPU_MIPS_24K: 3032 PMC_MDEP_INIT(mips24k); 3033 pmc_class_table[n] = &mips24k_class_table_descr; 3034 break; 3035 case PMC_CPU_MIPS_OCTEON: 3036 PMC_MDEP_INIT(octeon); 3037 pmc_class_table[n] = &octeon_class_table_descr; 3038 break; 3039#endif /* __mips__ */ 3040#if defined(__powerpc__) 3041 case PMC_CPU_PPC_7450: 3042 PMC_MDEP_INIT(ppc7450); 3043 pmc_class_table[n] = &ppc7450_class_table_descr; 3044 break; 3045#endif 3046 default: 3047 /* 3048 * Some kind of CPU this version of the library knows nothing 3049 * about. This shouldn't happen since the abi version check 3050 * should have caught this. 3051 */ 3052 errno = ENXIO; 3053 return (pmc_syscall = -1); 3054 } 3055 3056 return (0); 3057} 3058 3059const char * 3060pmc_name_of_capability(enum pmc_caps cap) 3061{ 3062 int i; 3063 3064 /* 3065 * 'cap' should have a single bit set and should be in 3066 * range. 3067 */ 3068 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 3069 cap > PMC_CAP_LAST) { 3070 errno = EINVAL; 3071 return (NULL); 3072 } 3073 3074 i = ffs(cap); 3075 return (pmc_capability_names[i - 1]); 3076} 3077 3078const char * 3079pmc_name_of_class(enum pmc_class pc) 3080{ 3081 if ((int) pc >= PMC_CLASS_FIRST && 3082 pc <= PMC_CLASS_LAST) 3083 return (pmc_class_names[pc]); 3084 3085 errno = EINVAL; 3086 return (NULL); 3087} 3088 3089const char * 3090pmc_name_of_cputype(enum pmc_cputype cp) 3091{ 3092 size_t n; 3093 3094 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 3095 if (cp == pmc_cputype_names[n].pm_cputype) 3096 return (pmc_cputype_names[n].pm_name); 3097 3098 errno = EINVAL; 3099 return (NULL); 3100} 3101 3102const char * 3103pmc_name_of_disposition(enum pmc_disp pd) 3104{ 3105 if ((int) pd >= PMC_DISP_FIRST && 3106 pd <= PMC_DISP_LAST) 3107 return (pmc_disposition_names[pd]); 3108 3109 errno = EINVAL; 3110 return (NULL); 3111} 3112 3113const char * 3114_pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 3115{ 3116 const struct pmc_event_descr *ev, *evfence; 3117 3118 ev = evfence = NULL; 3119 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 3120 ev = iaf_event_table; 3121 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 3122 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 3123 switch (cpu) { 3124 case PMC_CPU_INTEL_ATOM: 3125 ev = atom_event_table; 3126 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 3127 break; 3128 case PMC_CPU_INTEL_CORE: 3129 ev = core_event_table; 3130 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 3131 break; 3132 case PMC_CPU_INTEL_CORE2: 3133 case PMC_CPU_INTEL_CORE2EXTREME: 3134 ev = core2_event_table; 3135 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 3136 break; 3137 case PMC_CPU_INTEL_COREI7: 3138 ev = corei7_event_table; 3139 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 3140 break; 3141 case PMC_CPU_INTEL_IVYBRIDGE: 3142 ev = ivybridge_event_table; 3143 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); 3144 break; 3145 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 3146 ev = ivybridge_xeon_event_table; 3147 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon); 3148 break; 3149 case PMC_CPU_INTEL_SANDYBRIDGE: 3150 ev = sandybridge_event_table; 3151 evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); 3152 break; 3153 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 3154 ev = sandybridge_xeon_event_table; 3155 evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); 3156 break; 3157 case PMC_CPU_INTEL_WESTMERE: 3158 ev = westmere_event_table; 3159 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 3160 break; 3161 default: /* Unknown CPU type. */ 3162 break; 3163 } 3164 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 3165 ev = ucf_event_table; 3166 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 3167 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 3168 switch (cpu) { 3169 case PMC_CPU_INTEL_COREI7: 3170 ev = corei7uc_event_table; 3171 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 3172 break; 3173 case PMC_CPU_INTEL_SANDYBRIDGE: 3174 ev = sandybridgeuc_event_table; 3175 evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); 3176 break; 3177 case PMC_CPU_INTEL_WESTMERE: 3178 ev = westmereuc_event_table; 3179 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 3180 break; 3181 default: /* Unknown CPU type. */ 3182 break; 3183 } 3184 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 3185 ev = k7_event_table; 3186 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 3187 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 3188 ev = k8_event_table; 3189 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 3190 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 3191 ev = p4_event_table; 3192 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 3193 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 3194 ev = p5_event_table; 3195 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 3196 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 3197 ev = p6_event_table; 3198 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 3199 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 3200 ev = xscale_event_table; 3201 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 3202 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 3203 ev = mips24k_event_table; 3204 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); 3205 } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { 3206 ev = octeon_event_table; 3207 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); 3208 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 3209 ev = ppc7450_event_table; 3210 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); 3211 } else if (pe == PMC_EV_TSC_TSC) { 3212 ev = tsc_event_table; 3213 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 3214 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) { 3215 ev = soft_event_table; 3216 evfence = soft_event_table + soft_event_info.pm_nevent; 3217 } 3218 3219 for (; ev != evfence; ev++) 3220 if (pe == ev->pm_ev_code) 3221 return (ev->pm_ev_name); 3222 3223 return (NULL); 3224} 3225 3226const char * 3227pmc_name_of_event(enum pmc_event pe) 3228{ 3229 const char *n; 3230 3231 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3232 return (n); 3233 3234 errno = EINVAL; 3235 return (NULL); 3236} 3237 3238const char * 3239pmc_name_of_mode(enum pmc_mode pm) 3240{ 3241 if ((int) pm >= PMC_MODE_FIRST && 3242 pm <= PMC_MODE_LAST) 3243 return (pmc_mode_names[pm]); 3244 3245 errno = EINVAL; 3246 return (NULL); 3247} 3248 3249const char * 3250pmc_name_of_state(enum pmc_state ps) 3251{ 3252 if ((int) ps >= PMC_STATE_FIRST && 3253 ps <= PMC_STATE_LAST) 3254 return (pmc_state_names[ps]); 3255 3256 errno = EINVAL; 3257 return (NULL); 3258} 3259 3260int 3261pmc_ncpu(void) 3262{ 3263 if (pmc_syscall == -1) { 3264 errno = ENXIO; 3265 return (-1); 3266 } 3267 3268 return (cpu_info.pm_ncpu); 3269} 3270 3271int 3272pmc_npmc(int cpu) 3273{ 3274 if (pmc_syscall == -1) { 3275 errno = ENXIO; 3276 return (-1); 3277 } 3278 3279 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3280 errno = EINVAL; 3281 return (-1); 3282 } 3283 3284 return (cpu_info.pm_npmc); 3285} 3286 3287int 3288pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3289{ 3290 int nbytes, npmc; 3291 struct pmc_op_getpmcinfo *pmci; 3292 3293 if ((npmc = pmc_npmc(cpu)) < 0) 3294 return (-1); 3295 3296 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3297 npmc * sizeof(struct pmc_info); 3298 3299 if ((pmci = calloc(1, nbytes)) == NULL) 3300 return (-1); 3301 3302 pmci->pm_cpu = cpu; 3303 3304 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3305 free(pmci); 3306 return (-1); 3307 } 3308 3309 /* kernel<->library, library<->userland interfaces are identical */ 3310 *ppmci = (struct pmc_pmcinfo *) pmci; 3311 return (0); 3312} 3313 3314int 3315pmc_read(pmc_id_t pmc, pmc_value_t *value) 3316{ 3317 struct pmc_op_pmcrw pmc_read_op; 3318 3319 pmc_read_op.pm_pmcid = pmc; 3320 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3321 pmc_read_op.pm_value = -1; 3322 3323 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3324 return (-1); 3325 3326 *value = pmc_read_op.pm_value; 3327 return (0); 3328} 3329 3330int 3331pmc_release(pmc_id_t pmc) 3332{ 3333 struct pmc_op_simple pmc_release_args; 3334 3335 pmc_release_args.pm_pmcid = pmc; 3336 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3337} 3338 3339int 3340pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3341{ 3342 struct pmc_op_pmcrw pmc_rw_op; 3343 3344 pmc_rw_op.pm_pmcid = pmc; 3345 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3346 pmc_rw_op.pm_value = newvalue; 3347 3348 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3349 return (-1); 3350 3351 *oldvaluep = pmc_rw_op.pm_value; 3352 return (0); 3353} 3354 3355int 3356pmc_set(pmc_id_t pmc, pmc_value_t value) 3357{ 3358 struct pmc_op_pmcsetcount sc; 3359 3360 sc.pm_pmcid = pmc; 3361 sc.pm_count = value; 3362 3363 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3364 return (-1); 3365 return (0); 3366} 3367 3368int 3369pmc_start(pmc_id_t pmc) 3370{ 3371 struct pmc_op_simple pmc_start_args; 3372 3373 pmc_start_args.pm_pmcid = pmc; 3374 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3375} 3376 3377int 3378pmc_stop(pmc_id_t pmc) 3379{ 3380 struct pmc_op_simple pmc_stop_args; 3381 3382 pmc_stop_args.pm_pmcid = pmc; 3383 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3384} 3385 3386int 3387pmc_width(pmc_id_t pmcid, uint32_t *width) 3388{ 3389 unsigned int i; 3390 enum pmc_class cl; 3391 3392 cl = PMC_ID_TO_CLASS(pmcid); 3393 for (i = 0; i < cpu_info.pm_nclass; i++) 3394 if (cpu_info.pm_classes[i].pm_class == cl) { 3395 *width = cpu_info.pm_classes[i].pm_width; 3396 return (0); 3397 } 3398 errno = EINVAL; 3399 return (-1); 3400} 3401 3402int 3403pmc_write(pmc_id_t pmc, pmc_value_t value) 3404{ 3405 struct pmc_op_pmcrw pmc_write_op; 3406 3407 pmc_write_op.pm_pmcid = pmc; 3408 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3409 pmc_write_op.pm_value = value; 3410 return (PMC_CALL(PMCRW, &pmc_write_op)); 3411} 3412 3413int 3414pmc_writelog(uint32_t userdata) 3415{ 3416 struct pmc_op_writelog wl; 3417 3418 wl.pm_userdata = userdata; 3419 return (PMC_CALL(WRITELOG, &wl)); 3420} 3421