libpmc.c revision 228869
1/*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 228869 2011-12-24 19:34:52Z jhibbits $"); 29 30#include <sys/types.h> 31#include <sys/module.h> 32#include <sys/pmc.h> 33#include <sys/syscall.h> 34 35#include <ctype.h> 36#include <errno.h> 37#include <fcntl.h> 38#include <pmc.h> 39#include <stdio.h> 40#include <stdlib.h> 41#include <string.h> 42#include <strings.h> 43#include <unistd.h> 44 45#include "libpmcinternal.h" 46 47/* Function prototypes */ 48#if defined(__i386__) 49static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 50 struct pmc_op_pmcallocate *_pmc_config); 51#endif 52#if defined(__amd64__) || defined(__i386__) 53static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 54 struct pmc_op_pmcallocate *_pmc_config); 55static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 56 struct pmc_op_pmcallocate *_pmc_config); 57static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 58 struct pmc_op_pmcallocate *_pmc_config); 59static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 60 struct pmc_op_pmcallocate *_pmc_config); 61static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 62 struct pmc_op_pmcallocate *_pmc_config); 63static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 64 struct pmc_op_pmcallocate *_pmc_config); 65#endif 66#if defined(__i386__) 67static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 68 struct pmc_op_pmcallocate *_pmc_config); 69static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 70 struct pmc_op_pmcallocate *_pmc_config); 71#endif 72#if defined(__amd64__) || defined(__i386__) 73static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 74 struct pmc_op_pmcallocate *_pmc_config); 75#endif 76#if defined(__XSCALE__) 77static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, 78 struct pmc_op_pmcallocate *_pmc_config); 79#endif 80 81#if defined(__mips__) 82static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec, 83 struct pmc_op_pmcallocate *_pmc_config); 84#endif /* __mips__ */ 85 86#if defined(__powerpc__) 87static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec, 88 struct pmc_op_pmcallocate *_pmc_config); 89#endif /* __powerpc__ */ 90 91#define PMC_CALL(cmd, params) \ 92 syscall(pmc_syscall, PMC_OP_##cmd, (params)) 93 94/* 95 * Event aliases provide a way for the user to ask for generic events 96 * like "cache-misses", or "instructions-retired". These aliases are 97 * mapped to the appropriate canonical event descriptions using a 98 * lookup table. 99 */ 100struct pmc_event_alias { 101 const char *pm_alias; 102 const char *pm_spec; 103}; 104 105static const struct pmc_event_alias *pmc_mdep_event_aliases; 106 107/* 108 * The pmc_event_descr structure maps symbolic names known to the user 109 * to integer codes used by the PMC KLD. 110 */ 111struct pmc_event_descr { 112 const char *pm_ev_name; 113 enum pmc_event pm_ev_code; 114}; 115 116/* 117 * The pmc_class_descr structure maps class name prefixes for 118 * event names to event tables and other PMC class data. 119 */ 120struct pmc_class_descr { 121 const char *pm_evc_name; 122 size_t pm_evc_name_size; 123 enum pmc_class pm_evc_class; 124 const struct pmc_event_descr *pm_evc_event_table; 125 size_t pm_evc_event_table_size; 126 int (*pm_evc_allocate_pmc)(enum pmc_event _pe, 127 char *_ctrspec, struct pmc_op_pmcallocate *_pa); 128}; 129 130#define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) 131#define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) 132 133#undef __PMC_EV 134#define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, 135 136/* 137 * PMC_CLASSDEP_TABLE(NAME, CLASS) 138 * 139 * Define a table mapping event names and aliases to HWPMC event IDs. 140 */ 141#define PMC_CLASSDEP_TABLE(N, C) \ 142 static const struct pmc_event_descr N##_event_table[] = \ 143 { \ 144 __PMC_EV_##C() \ 145 } 146 147PMC_CLASSDEP_TABLE(iaf, IAF); 148PMC_CLASSDEP_TABLE(k7, K7); 149PMC_CLASSDEP_TABLE(k8, K8); 150PMC_CLASSDEP_TABLE(p4, P4); 151PMC_CLASSDEP_TABLE(p5, P5); 152PMC_CLASSDEP_TABLE(p6, P6); 153PMC_CLASSDEP_TABLE(xscale, XSCALE); 154PMC_CLASSDEP_TABLE(mips24k, MIPS24K); 155PMC_CLASSDEP_TABLE(ucf, UCF); 156PMC_CLASSDEP_TABLE(ppc7450, PPC7450); 157 158#undef __PMC_EV_ALIAS 159#define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, 160 161static const struct pmc_event_descr atom_event_table[] = 162{ 163 __PMC_EV_ALIAS_ATOM() 164}; 165 166static const struct pmc_event_descr core_event_table[] = 167{ 168 __PMC_EV_ALIAS_CORE() 169}; 170 171 172static const struct pmc_event_descr core2_event_table[] = 173{ 174 __PMC_EV_ALIAS_CORE2() 175}; 176 177static const struct pmc_event_descr corei7_event_table[] = 178{ 179 __PMC_EV_ALIAS_COREI7() 180}; 181 182static const struct pmc_event_descr westmere_event_table[] = 183{ 184 __PMC_EV_ALIAS_WESTMERE() 185}; 186 187static const struct pmc_event_descr corei7uc_event_table[] = 188{ 189 __PMC_EV_ALIAS_COREI7UC() 190}; 191 192static const struct pmc_event_descr westmereuc_event_table[] = 193{ 194 __PMC_EV_ALIAS_WESTMEREUC() 195}; 196 197/* 198 * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) 199 * 200 * Map a CPU to the PMC classes it supports. 201 */ 202#define PMC_MDEP_TABLE(N,C,...) \ 203 static const enum pmc_class N##_pmc_classes[] = { \ 204 PMC_CLASS_##C, __VA_ARGS__ \ 205 } 206 207PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 208PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC); 209PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC); 210PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 211PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); 212PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC); 213PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC); 214PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC); 215PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC); 216PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC); 217PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_XSCALE); 218PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_MIPS24K); 219PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_PPC7450); 220 221static const struct pmc_event_descr tsc_event_table[] = 222{ 223 __PMC_EV_TSC() 224}; 225 226#undef PMC_CLASS_TABLE_DESC 227#define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ 228static const struct pmc_class_descr NAME##_class_table_descr = \ 229 { \ 230 .pm_evc_name = #CLASS "-", \ 231 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ 232 .pm_evc_class = PMC_CLASS_##CLASS , \ 233 .pm_evc_event_table = EVENTS##_event_table , \ 234 .pm_evc_event_table_size = \ 235 PMC_EVENT_TABLE_SIZE(EVENTS), \ 236 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ 237 } 238 239#if defined(__i386__) || defined(__amd64__) 240PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); 241PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); 242PMC_CLASS_TABLE_DESC(core, IAP, core, iap); 243PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); 244PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); 245PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); 246PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); 247PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); 248PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); 249#endif 250#if defined(__i386__) 251PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); 252#endif 253#if defined(__i386__) || defined(__amd64__) 254PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); 255PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); 256#endif 257#if defined(__i386__) 258PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); 259PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); 260#endif 261#if defined(__i386__) || defined(__amd64__) 262PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); 263#endif 264#if defined(__XSCALE__) 265PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); 266#endif 267 268#if defined(__mips__) 269PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k); 270#endif /* __mips__ */ 271 272#if defined(__powerpc__) 273PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450); 274#endif 275 276#undef PMC_CLASS_TABLE_DESC 277 278static const struct pmc_class_descr **pmc_class_table; 279#define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass 280 281static const enum pmc_class *pmc_mdep_class_list; 282static size_t pmc_mdep_class_list_size; 283 284/* 285 * Mapping tables, mapping enumeration values to human readable 286 * strings. 287 */ 288 289static const char * pmc_capability_names[] = { 290#undef __PMC_CAP 291#define __PMC_CAP(N,V,D) #N , 292 __PMC_CAPS() 293}; 294 295static const char * pmc_class_names[] = { 296#undef __PMC_CLASS 297#define __PMC_CLASS(C) #C , 298 __PMC_CLASSES() 299}; 300 301struct pmc_cputype_map { 302 enum pmc_cputype pm_cputype; 303 const char *pm_name; 304}; 305 306static const struct pmc_cputype_map pmc_cputype_names[] = { 307#undef __PMC_CPU 308#define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , 309 __PMC_CPUS() 310}; 311 312static const char * pmc_disposition_names[] = { 313#undef __PMC_DISP 314#define __PMC_DISP(D) #D , 315 __PMC_DISPOSITIONS() 316}; 317 318static const char * pmc_mode_names[] = { 319#undef __PMC_MODE 320#define __PMC_MODE(M,N) #M , 321 __PMC_MODES() 322}; 323 324static const char * pmc_state_names[] = { 325#undef __PMC_STATE 326#define __PMC_STATE(S) #S , 327 __PMC_STATES() 328}; 329 330static int pmc_syscall = -1; /* filled in by pmc_init() */ 331 332static struct pmc_cpuinfo cpu_info; /* filled in by pmc_init() */ 333 334/* Event masks for events */ 335struct pmc_masks { 336 const char *pm_name; 337 const uint32_t pm_value; 338}; 339#define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } 340#define NULLMASK { .pm_name = NULL } 341 342#if defined(__amd64__) || defined(__i386__) 343static int 344pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask) 345{ 346 const struct pmc_masks *pm; 347 char *q, *r; 348 int c; 349 350 if (pmask == NULL) /* no mask keywords */ 351 return (-1); 352 q = strchr(p, '='); /* skip '=' */ 353 if (*++q == '\0') /* no more data */ 354 return (-1); 355 c = 0; /* count of mask keywords seen */ 356 while ((r = strsep(&q, "+")) != NULL) { 357 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); 358 pm++) 359 ; 360 if (pm->pm_name == NULL) /* not found */ 361 return (-1); 362 *evmask |= pm->pm_value; 363 c++; 364 } 365 return (c); 366} 367#endif 368 369#define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) 370#define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) 371#define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } 372 373#if defined(__i386__) 374 375/* 376 * AMD K7 (Athlon) CPUs. 377 */ 378 379static struct pmc_event_alias k7_aliases[] = { 380 EV_ALIAS("branches", "k7-retired-branches"), 381 EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), 382 EV_ALIAS("cycles", "tsc"), 383 EV_ALIAS("dc-misses", "k7-dc-misses"), 384 EV_ALIAS("ic-misses", "k7-ic-misses"), 385 EV_ALIAS("instructions", "k7-retired-instructions"), 386 EV_ALIAS("interrupts", "k7-hardware-interrupts"), 387 EV_ALIAS(NULL, NULL) 388}; 389 390#define K7_KW_COUNT "count" 391#define K7_KW_EDGE "edge" 392#define K7_KW_INV "inv" 393#define K7_KW_OS "os" 394#define K7_KW_UNITMASK "unitmask" 395#define K7_KW_USR "usr" 396 397static int 398k7_allocate_pmc(enum pmc_event pe, char *ctrspec, 399 struct pmc_op_pmcallocate *pmc_config) 400{ 401 char *e, *p, *q; 402 int c, has_unitmask; 403 uint32_t count, unitmask; 404 405 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 406 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 407 408 if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || 409 pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || 410 pe == PMC_EV_K7_DC_WRITEBACKS) { 411 has_unitmask = 1; 412 unitmask = AMD_PMC_UNITMASK_MOESI; 413 } else 414 unitmask = has_unitmask = 0; 415 416 while ((p = strsep(&ctrspec, ",")) != NULL) { 417 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { 418 q = strchr(p, '='); 419 if (*++q == '\0') /* skip '=' */ 420 return (-1); 421 422 count = strtol(q, &e, 0); 423 if (e == q || *e != '\0') 424 return (-1); 425 426 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 427 pmc_config->pm_md.pm_amd.pm_amd_config |= 428 AMD_PMC_TO_COUNTER(count); 429 430 } else if (KWMATCH(p, K7_KW_EDGE)) { 431 pmc_config->pm_caps |= PMC_CAP_EDGE; 432 } else if (KWMATCH(p, K7_KW_INV)) { 433 pmc_config->pm_caps |= PMC_CAP_INVERT; 434 } else if (KWMATCH(p, K7_KW_OS)) { 435 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 436 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { 437 if (has_unitmask == 0) 438 return (-1); 439 unitmask = 0; 440 q = strchr(p, '='); 441 if (*++q == '\0') /* skip '=' */ 442 return (-1); 443 444 while ((c = tolower(*q++)) != 0) 445 if (c == 'm') 446 unitmask |= AMD_PMC_UNITMASK_M; 447 else if (c == 'o') 448 unitmask |= AMD_PMC_UNITMASK_O; 449 else if (c == 'e') 450 unitmask |= AMD_PMC_UNITMASK_E; 451 else if (c == 's') 452 unitmask |= AMD_PMC_UNITMASK_S; 453 else if (c == 'i') 454 unitmask |= AMD_PMC_UNITMASK_I; 455 else if (c == '+') 456 continue; 457 else 458 return (-1); 459 460 if (unitmask == 0) 461 return (-1); 462 463 } else if (KWMATCH(p, K7_KW_USR)) { 464 pmc_config->pm_caps |= PMC_CAP_USER; 465 } else 466 return (-1); 467 } 468 469 if (has_unitmask) { 470 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 471 pmc_config->pm_md.pm_amd.pm_amd_config |= 472 AMD_PMC_TO_UNITMASK(unitmask); 473 } 474 475 return (0); 476 477} 478 479#endif 480 481#if defined(__amd64__) || defined(__i386__) 482 483/* 484 * Intel Core (Family 6, Model E) PMCs. 485 */ 486 487static struct pmc_event_alias core_aliases[] = { 488 EV_ALIAS("branches", "iap-br-instr-ret"), 489 EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), 490 EV_ALIAS("cycles", "tsc-tsc"), 491 EV_ALIAS("ic-misses", "iap-icache-misses"), 492 EV_ALIAS("instructions", "iap-instr-ret"), 493 EV_ALIAS("interrupts", "iap-core-hw-int-rx"), 494 EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), 495 EV_ALIAS(NULL, NULL) 496}; 497 498/* 499 * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) 500 * and Atom (Family 6, model 1CH) PMCs. 501 * 502 * We map aliases to events on the fixed-function counters if these 503 * are present. Note that not all CPUs in this family contain fixed-function 504 * counters. 505 */ 506 507static struct pmc_event_alias core2_aliases[] = { 508 EV_ALIAS("branches", "iap-br-inst-retired.any"), 509 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 510 EV_ALIAS("cycles", "tsc-tsc"), 511 EV_ALIAS("ic-misses", "iap-l1i-misses"), 512 EV_ALIAS("instructions", "iaf-instr-retired.any"), 513 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 514 EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), 515 EV_ALIAS(NULL, NULL) 516}; 517 518static struct pmc_event_alias core2_aliases_without_iaf[] = { 519 EV_ALIAS("branches", "iap-br-inst-retired.any"), 520 EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), 521 EV_ALIAS("cycles", "tsc-tsc"), 522 EV_ALIAS("ic-misses", "iap-l1i-misses"), 523 EV_ALIAS("instructions", "iap-inst-retired.any_p"), 524 EV_ALIAS("interrupts", "iap-hw-int-rcv"), 525 EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), 526 EV_ALIAS(NULL, NULL) 527}; 528 529#define atom_aliases core2_aliases 530#define atom_aliases_without_iaf core2_aliases_without_iaf 531#define corei7_aliases core2_aliases 532#define corei7_aliases_without_iaf core2_aliases_without_iaf 533#define westmere_aliases core2_aliases 534#define westmere_aliases_without_iaf core2_aliases_without_iaf 535 536#define IAF_KW_OS "os" 537#define IAF_KW_USR "usr" 538#define IAF_KW_ANYTHREAD "anythread" 539 540/* 541 * Parse an event specifier for Intel fixed function counters. 542 */ 543static int 544iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, 545 struct pmc_op_pmcallocate *pmc_config) 546{ 547 char *p; 548 549 (void) pe; 550 551 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 552 pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; 553 554 while ((p = strsep(&ctrspec, ",")) != NULL) { 555 if (KWMATCH(p, IAF_KW_OS)) 556 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 557 else if (KWMATCH(p, IAF_KW_USR)) 558 pmc_config->pm_caps |= PMC_CAP_USER; 559 else if (KWMATCH(p, IAF_KW_ANYTHREAD)) 560 pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; 561 else 562 return (-1); 563 } 564 565 return (0); 566} 567 568/* 569 * Core/Core2 support. 570 */ 571 572#define IAP_KW_AGENT "agent" 573#define IAP_KW_ANYTHREAD "anythread" 574#define IAP_KW_CACHESTATE "cachestate" 575#define IAP_KW_CMASK "cmask" 576#define IAP_KW_CORE "core" 577#define IAP_KW_EDGE "edge" 578#define IAP_KW_INV "inv" 579#define IAP_KW_OS "os" 580#define IAP_KW_PREFETCH "prefetch" 581#define IAP_KW_SNOOPRESPONSE "snoopresponse" 582#define IAP_KW_SNOOPTYPE "snooptype" 583#define IAP_KW_TRANSITION "trans" 584#define IAP_KW_USR "usr" 585#define IAP_KW_RSP "rsp" 586 587static struct pmc_masks iap_core_mask[] = { 588 PMCMASK(all, (0x3 << 14)), 589 PMCMASK(this, (0x1 << 14)), 590 NULLMASK 591}; 592 593static struct pmc_masks iap_agent_mask[] = { 594 PMCMASK(this, 0), 595 PMCMASK(any, (0x1 << 13)), 596 NULLMASK 597}; 598 599static struct pmc_masks iap_prefetch_mask[] = { 600 PMCMASK(both, (0x3 << 12)), 601 PMCMASK(only, (0x1 << 12)), 602 PMCMASK(exclude, 0), 603 NULLMASK 604}; 605 606static struct pmc_masks iap_cachestate_mask[] = { 607 PMCMASK(i, (1 << 8)), 608 PMCMASK(s, (1 << 9)), 609 PMCMASK(e, (1 << 10)), 610 PMCMASK(m, (1 << 11)), 611 NULLMASK 612}; 613 614static struct pmc_masks iap_snoopresponse_mask[] = { 615 PMCMASK(clean, (1 << 8)), 616 PMCMASK(hit, (1 << 9)), 617 PMCMASK(hitm, (1 << 11)), 618 NULLMASK 619}; 620 621static struct pmc_masks iap_snooptype_mask[] = { 622 PMCMASK(cmp2s, (1 << 8)), 623 PMCMASK(cmp2i, (1 << 9)), 624 NULLMASK 625}; 626 627static struct pmc_masks iap_transition_mask[] = { 628 PMCMASK(any, 0x00), 629 PMCMASK(frequency, 0x10), 630 NULLMASK 631}; 632 633static struct pmc_masks iap_rsp_mask[] = { 634 PMCMASK(DMND_DATA_RD, (1 << 0)), 635 PMCMASK(DMND_RFO, (1 << 1)), 636 PMCMASK(DMND_IFETCH, (1 << 2)), 637 PMCMASK(WB, (1 << 3)), 638 PMCMASK(PF_DATA_RD, (1 << 4)), 639 PMCMASK(PF_RFO, (1 << 5)), 640 PMCMASK(PF_IFETCH, (1 << 6)), 641 PMCMASK(OTHER, (1 << 7)), 642 PMCMASK(UNCORE_HIT, (1 << 8)), 643 PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), 644 PMCMASK(OTHER_CORE_HITM, (1 << 10)), 645 PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), 646 PMCMASK(REMOTE_DRAM, (1 << 13)), 647 PMCMASK(LOCAL_DRAM, (1 << 14)), 648 PMCMASK(NON_DRAM, (1 << 15)), 649 NULLMASK 650}; 651 652static int 653iap_allocate_pmc(enum pmc_event pe, char *ctrspec, 654 struct pmc_op_pmcallocate *pmc_config) 655{ 656 char *e, *p, *q; 657 uint32_t cachestate, evmask, rsp; 658 int count, n; 659 660 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 661 PMC_CAP_QUALIFIER); 662 pmc_config->pm_md.pm_iap.pm_iap_config = 0; 663 664 cachestate = evmask = rsp = 0; 665 666 /* Parse additional modifiers if present */ 667 while ((p = strsep(&ctrspec, ",")) != NULL) { 668 669 n = 0; 670 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { 671 q = strchr(p, '='); 672 if (*++q == '\0') /* skip '=' */ 673 return (-1); 674 count = strtol(q, &e, 0); 675 if (e == q || *e != '\0') 676 return (-1); 677 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 678 pmc_config->pm_md.pm_iap.pm_iap_config |= 679 IAP_CMASK(count); 680 } else if (KWMATCH(p, IAP_KW_EDGE)) { 681 pmc_config->pm_caps |= PMC_CAP_EDGE; 682 } else if (KWMATCH(p, IAP_KW_INV)) { 683 pmc_config->pm_caps |= PMC_CAP_INVERT; 684 } else if (KWMATCH(p, IAP_KW_OS)) { 685 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 686 } else if (KWMATCH(p, IAP_KW_USR)) { 687 pmc_config->pm_caps |= PMC_CAP_USER; 688 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { 689 pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; 690 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { 691 n = pmc_parse_mask(iap_core_mask, p, &evmask); 692 if (n != 1) 693 return (-1); 694 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { 695 n = pmc_parse_mask(iap_agent_mask, p, &evmask); 696 if (n != 1) 697 return (-1); 698 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { 699 n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); 700 if (n != 1) 701 return (-1); 702 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { 703 n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); 704 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && 705 KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { 706 n = pmc_parse_mask(iap_transition_mask, p, &evmask); 707 if (n != 1) 708 return (-1); 709 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || 710 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || 711 cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { 712 if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { 713 n = pmc_parse_mask(iap_snoopresponse_mask, p, 714 &evmask); 715 } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { 716 n = pmc_parse_mask(iap_snooptype_mask, p, 717 &evmask); 718 } else 719 return (-1); 720 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || 721 cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { 722 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { 723 n = pmc_parse_mask(iap_rsp_mask, p, &rsp); 724 } else 725 return (-1); 726 } else 727 return (-1); 728 729 if (n < 0) /* Parsing failed. */ 730 return (-1); 731 } 732 733 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; 734 735 /* 736 * If the event requires a 'cachestate' qualifier but was not 737 * specified by the user, use a sensible default. 738 */ 739 switch (pe) { 740 case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ 741 case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ 742 case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ 743 case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ 744 case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ 745 case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ 746 case PMC_EV_IAP_EVENT_32H: /* Core */ 747 case PMC_EV_IAP_EVENT_40H: /* Core */ 748 case PMC_EV_IAP_EVENT_41H: /* Core */ 749 case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ 750 if (cachestate == 0) 751 cachestate = (0xF << 8); 752 break; 753 case PMC_EV_IAP_EVENT_77H: /* Atom */ 754 /* IAP_EVENT_77H only accepts a cachestate qualifier on the 755 * Atom processor 756 */ 757 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) 758 cachestate = (0xF << 8); 759 break; 760 default: 761 break; 762 } 763 764 pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; 765 pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; 766 767 return (0); 768} 769 770/* 771 * Intel Uncore. 772 */ 773 774static int 775ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, 776 struct pmc_op_pmcallocate *pmc_config) 777{ 778 (void) pe; 779 (void) ctrspec; 780 781 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 782 pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; 783 784 return (0); 785} 786 787#define UCP_KW_CMASK "cmask" 788#define UCP_KW_EDGE "edge" 789#define UCP_KW_INV "inv" 790 791static int 792ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, 793 struct pmc_op_pmcallocate *pmc_config) 794{ 795 char *e, *p, *q; 796 int count, n; 797 798 (void) pe; 799 800 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | 801 PMC_CAP_QUALIFIER); 802 pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; 803 804 /* Parse additional modifiers if present */ 805 while ((p = strsep(&ctrspec, ",")) != NULL) { 806 807 n = 0; 808 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { 809 q = strchr(p, '='); 810 if (*++q == '\0') /* skip '=' */ 811 return (-1); 812 count = strtol(q, &e, 0); 813 if (e == q || *e != '\0') 814 return (-1); 815 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 816 pmc_config->pm_md.pm_ucp.pm_ucp_config |= 817 UCP_CMASK(count); 818 } else if (KWMATCH(p, UCP_KW_EDGE)) { 819 pmc_config->pm_caps |= PMC_CAP_EDGE; 820 } else if (KWMATCH(p, UCP_KW_INV)) { 821 pmc_config->pm_caps |= PMC_CAP_INVERT; 822 } else 823 return (-1); 824 825 if (n < 0) /* Parsing failed. */ 826 return (-1); 827 } 828 829 return (0); 830} 831 832/* 833 * AMD K8 PMCs. 834 * 835 * These are very similar to AMD K7 PMCs, but support more kinds of 836 * events. 837 */ 838 839static struct pmc_event_alias k8_aliases[] = { 840 EV_ALIAS("branches", "k8-fr-retired-taken-branches"), 841 EV_ALIAS("branch-mispredicts", 842 "k8-fr-retired-taken-branches-mispredicted"), 843 EV_ALIAS("cycles", "tsc"), 844 EV_ALIAS("dc-misses", "k8-dc-miss"), 845 EV_ALIAS("ic-misses", "k8-ic-miss"), 846 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), 847 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), 848 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), 849 EV_ALIAS(NULL, NULL) 850}; 851 852#define __K8MASK(N,V) PMCMASK(N,(1 << (V))) 853 854/* 855 * Parsing tables 856 */ 857 858/* fp dispatched fpu ops */ 859static const struct pmc_masks k8_mask_fdfo[] = { 860 __K8MASK(add-pipe-excluding-junk-ops, 0), 861 __K8MASK(multiply-pipe-excluding-junk-ops, 1), 862 __K8MASK(store-pipe-excluding-junk-ops, 2), 863 __K8MASK(add-pipe-junk-ops, 3), 864 __K8MASK(multiply-pipe-junk-ops, 4), 865 __K8MASK(store-pipe-junk-ops, 5), 866 NULLMASK 867}; 868 869/* ls segment register loads */ 870static const struct pmc_masks k8_mask_lsrl[] = { 871 __K8MASK(es, 0), 872 __K8MASK(cs, 1), 873 __K8MASK(ss, 2), 874 __K8MASK(ds, 3), 875 __K8MASK(fs, 4), 876 __K8MASK(gs, 5), 877 __K8MASK(hs, 6), 878 NULLMASK 879}; 880 881/* ls locked operation */ 882static const struct pmc_masks k8_mask_llo[] = { 883 __K8MASK(locked-instructions, 0), 884 __K8MASK(cycles-in-request, 1), 885 __K8MASK(cycles-to-complete, 2), 886 NULLMASK 887}; 888 889/* dc refill from {l2,system} and dc copyback */ 890static const struct pmc_masks k8_mask_dc[] = { 891 __K8MASK(invalid, 0), 892 __K8MASK(shared, 1), 893 __K8MASK(exclusive, 2), 894 __K8MASK(owner, 3), 895 __K8MASK(modified, 4), 896 NULLMASK 897}; 898 899/* dc one bit ecc error */ 900static const struct pmc_masks k8_mask_dobee[] = { 901 __K8MASK(scrubber, 0), 902 __K8MASK(piggyback, 1), 903 NULLMASK 904}; 905 906/* dc dispatched prefetch instructions */ 907static const struct pmc_masks k8_mask_ddpi[] = { 908 __K8MASK(load, 0), 909 __K8MASK(store, 1), 910 __K8MASK(nta, 2), 911 NULLMASK 912}; 913 914/* dc dcache accesses by locks */ 915static const struct pmc_masks k8_mask_dabl[] = { 916 __K8MASK(accesses, 0), 917 __K8MASK(misses, 1), 918 NULLMASK 919}; 920 921/* bu internal l2 request */ 922static const struct pmc_masks k8_mask_bilr[] = { 923 __K8MASK(ic-fill, 0), 924 __K8MASK(dc-fill, 1), 925 __K8MASK(tlb-reload, 2), 926 __K8MASK(tag-snoop, 3), 927 __K8MASK(cancelled, 4), 928 NULLMASK 929}; 930 931/* bu fill request l2 miss */ 932static const struct pmc_masks k8_mask_bfrlm[] = { 933 __K8MASK(ic-fill, 0), 934 __K8MASK(dc-fill, 1), 935 __K8MASK(tlb-reload, 2), 936 NULLMASK 937}; 938 939/* bu fill into l2 */ 940static const struct pmc_masks k8_mask_bfil[] = { 941 __K8MASK(dirty-l2-victim, 0), 942 __K8MASK(victim-from-l2, 1), 943 NULLMASK 944}; 945 946/* fr retired fpu instructions */ 947static const struct pmc_masks k8_mask_frfi[] = { 948 __K8MASK(x87, 0), 949 __K8MASK(mmx-3dnow, 1), 950 __K8MASK(packed-sse-sse2, 2), 951 __K8MASK(scalar-sse-sse2, 3), 952 NULLMASK 953}; 954 955/* fr retired fastpath double op instructions */ 956static const struct pmc_masks k8_mask_frfdoi[] = { 957 __K8MASK(low-op-pos-0, 0), 958 __K8MASK(low-op-pos-1, 1), 959 __K8MASK(low-op-pos-2, 2), 960 NULLMASK 961}; 962 963/* fr fpu exceptions */ 964static const struct pmc_masks k8_mask_ffe[] = { 965 __K8MASK(x87-reclass-microfaults, 0), 966 __K8MASK(sse-retype-microfaults, 1), 967 __K8MASK(sse-reclass-microfaults, 2), 968 __K8MASK(sse-and-x87-microtraps, 3), 969 NULLMASK 970}; 971 972/* nb memory controller page access event */ 973static const struct pmc_masks k8_mask_nmcpae[] = { 974 __K8MASK(page-hit, 0), 975 __K8MASK(page-miss, 1), 976 __K8MASK(page-conflict, 2), 977 NULLMASK 978}; 979 980/* nb memory controller turnaround */ 981static const struct pmc_masks k8_mask_nmct[] = { 982 __K8MASK(dimm-turnaround, 0), 983 __K8MASK(read-to-write-turnaround, 1), 984 __K8MASK(write-to-read-turnaround, 2), 985 NULLMASK 986}; 987 988/* nb memory controller bypass saturation */ 989static const struct pmc_masks k8_mask_nmcbs[] = { 990 __K8MASK(memory-controller-hi-pri-bypass, 0), 991 __K8MASK(memory-controller-lo-pri-bypass, 1), 992 __K8MASK(dram-controller-interface-bypass, 2), 993 __K8MASK(dram-controller-queue-bypass, 3), 994 NULLMASK 995}; 996 997/* nb sized commands */ 998static const struct pmc_masks k8_mask_nsc[] = { 999 __K8MASK(nonpostwrszbyte, 0), 1000 __K8MASK(nonpostwrszdword, 1), 1001 __K8MASK(postwrszbyte, 2), 1002 __K8MASK(postwrszdword, 3), 1003 __K8MASK(rdszbyte, 4), 1004 __K8MASK(rdszdword, 5), 1005 __K8MASK(rdmodwr, 6), 1006 NULLMASK 1007}; 1008 1009/* nb probe result */ 1010static const struct pmc_masks k8_mask_npr[] = { 1011 __K8MASK(probe-miss, 0), 1012 __K8MASK(probe-hit, 1), 1013 __K8MASK(probe-hit-dirty-no-memory-cancel, 2), 1014 __K8MASK(probe-hit-dirty-with-memory-cancel, 3), 1015 NULLMASK 1016}; 1017 1018/* nb hypertransport bus bandwidth */ 1019static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ 1020 __K8MASK(command, 0), 1021 __K8MASK(data, 1), 1022 __K8MASK(buffer-release, 2), 1023 __K8MASK(nop, 3), 1024 NULLMASK 1025}; 1026 1027#undef __K8MASK 1028 1029#define K8_KW_COUNT "count" 1030#define K8_KW_EDGE "edge" 1031#define K8_KW_INV "inv" 1032#define K8_KW_MASK "mask" 1033#define K8_KW_OS "os" 1034#define K8_KW_USR "usr" 1035 1036static int 1037k8_allocate_pmc(enum pmc_event pe, char *ctrspec, 1038 struct pmc_op_pmcallocate *pmc_config) 1039{ 1040 char *e, *p, *q; 1041 int n; 1042 uint32_t count, evmask; 1043 const struct pmc_masks *pm, *pmask; 1044 1045 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1046 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 1047 1048 pmask = NULL; 1049 evmask = 0; 1050 1051#define __K8SETMASK(M) pmask = k8_mask_##M 1052 1053 /* setup parsing tables */ 1054 switch (pe) { 1055 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1056 __K8SETMASK(fdfo); 1057 break; 1058 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: 1059 __K8SETMASK(lsrl); 1060 break; 1061 case PMC_EV_K8_LS_LOCKED_OPERATION: 1062 __K8SETMASK(llo); 1063 break; 1064 case PMC_EV_K8_DC_REFILL_FROM_L2: 1065 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: 1066 case PMC_EV_K8_DC_COPYBACK: 1067 __K8SETMASK(dc); 1068 break; 1069 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: 1070 __K8SETMASK(dobee); 1071 break; 1072 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: 1073 __K8SETMASK(ddpi); 1074 break; 1075 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1076 __K8SETMASK(dabl); 1077 break; 1078 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: 1079 __K8SETMASK(bilr); 1080 break; 1081 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: 1082 __K8SETMASK(bfrlm); 1083 break; 1084 case PMC_EV_K8_BU_FILL_INTO_L2: 1085 __K8SETMASK(bfil); 1086 break; 1087 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1088 __K8SETMASK(frfi); 1089 break; 1090 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1091 __K8SETMASK(frfdoi); 1092 break; 1093 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1094 __K8SETMASK(ffe); 1095 break; 1096 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: 1097 __K8SETMASK(nmcpae); 1098 break; 1099 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: 1100 __K8SETMASK(nmct); 1101 break; 1102 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: 1103 __K8SETMASK(nmcbs); 1104 break; 1105 case PMC_EV_K8_NB_SIZED_COMMANDS: 1106 __K8SETMASK(nsc); 1107 break; 1108 case PMC_EV_K8_NB_PROBE_RESULT: 1109 __K8SETMASK(npr); 1110 break; 1111 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: 1112 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: 1113 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: 1114 __K8SETMASK(nhbb); 1115 break; 1116 1117 default: 1118 break; /* no options defined */ 1119 } 1120 1121 while ((p = strsep(&ctrspec, ",")) != NULL) { 1122 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { 1123 q = strchr(p, '='); 1124 if (*++q == '\0') /* skip '=' */ 1125 return (-1); 1126 1127 count = strtol(q, &e, 0); 1128 if (e == q || *e != '\0') 1129 return (-1); 1130 1131 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1132 pmc_config->pm_md.pm_amd.pm_amd_config |= 1133 AMD_PMC_TO_COUNTER(count); 1134 1135 } else if (KWMATCH(p, K8_KW_EDGE)) { 1136 pmc_config->pm_caps |= PMC_CAP_EDGE; 1137 } else if (KWMATCH(p, K8_KW_INV)) { 1138 pmc_config->pm_caps |= PMC_CAP_INVERT; 1139 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { 1140 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1141 return (-1); 1142 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1143 } else if (KWMATCH(p, K8_KW_OS)) { 1144 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1145 } else if (KWMATCH(p, K8_KW_USR)) { 1146 pmc_config->pm_caps |= PMC_CAP_USER; 1147 } else 1148 return (-1); 1149 } 1150 1151 /* other post processing */ 1152 switch (pe) { 1153 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: 1154 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: 1155 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: 1156 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: 1157 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: 1158 case PMC_EV_K8_FR_FPU_EXCEPTIONS: 1159 /* XXX only available in rev B and later */ 1160 break; 1161 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: 1162 /* XXX only available in rev C and later */ 1163 break; 1164 case PMC_EV_K8_LS_LOCKED_OPERATION: 1165 /* XXX CPU Rev A,B evmask is to be zero */ 1166 if (evmask & (evmask - 1)) /* > 1 bit set */ 1167 return (-1); 1168 if (evmask == 0) { 1169 evmask = 0x01; /* Rev C and later: #instrs */ 1170 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1171 } 1172 break; 1173 default: 1174 if (evmask == 0 && pmask != NULL) { 1175 for (pm = pmask; pm->pm_name; pm++) 1176 evmask |= pm->pm_value; 1177 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1178 } 1179 } 1180 1181 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 1182 pmc_config->pm_md.pm_amd.pm_amd_config = 1183 AMD_PMC_TO_UNITMASK(evmask); 1184 1185 return (0); 1186} 1187 1188#endif 1189 1190#if defined(__amd64__) || defined(__i386__) 1191 1192/* 1193 * Intel P4 PMCs 1194 */ 1195 1196static struct pmc_event_alias p4_aliases[] = { 1197 EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), 1198 EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), 1199 EV_ALIAS("cycles", "tsc"), 1200 EV_ALIAS("instructions", 1201 "p4-instr-retired,mask=nbogusntag+nbogustag"), 1202 EV_ALIAS("unhalted-cycles", "p4-global-power-events"), 1203 EV_ALIAS(NULL, NULL) 1204}; 1205 1206#define P4_KW_ACTIVE "active" 1207#define P4_KW_ACTIVE_ANY "any" 1208#define P4_KW_ACTIVE_BOTH "both" 1209#define P4_KW_ACTIVE_NONE "none" 1210#define P4_KW_ACTIVE_SINGLE "single" 1211#define P4_KW_BUSREQTYPE "busreqtype" 1212#define P4_KW_CASCADE "cascade" 1213#define P4_KW_EDGE "edge" 1214#define P4_KW_INV "complement" 1215#define P4_KW_OS "os" 1216#define P4_KW_MASK "mask" 1217#define P4_KW_PRECISE "precise" 1218#define P4_KW_TAG "tag" 1219#define P4_KW_THRESHOLD "threshold" 1220#define P4_KW_USR "usr" 1221 1222#define __P4MASK(N,V) PMCMASK(N, (1 << (V))) 1223 1224static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ 1225 __P4MASK(dd, 0), 1226 __P4MASK(db, 1), 1227 __P4MASK(di, 2), 1228 __P4MASK(bd, 3), 1229 __P4MASK(bb, 4), 1230 __P4MASK(bi, 5), 1231 __P4MASK(id, 6), 1232 __P4MASK(ib, 7), 1233 NULLMASK 1234}; 1235 1236static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ 1237 __P4MASK(tcmiss, 0), 1238 NULLMASK, 1239}; 1240 1241static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ 1242 __P4MASK(hit, 0), 1243 __P4MASK(miss, 1), 1244 __P4MASK(hit-uc, 2), 1245 NULLMASK 1246}; 1247 1248static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ 1249 __P4MASK(st-rb-full, 2), 1250 __P4MASK(64k-conf, 3), 1251 NULLMASK 1252}; 1253 1254static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ 1255 __P4MASK(lsc, 0), 1256 __P4MASK(ssc, 1), 1257 NULLMASK 1258}; 1259 1260static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ 1261 __P4MASK(split-ld, 1), 1262 NULLMASK 1263}; 1264 1265static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ 1266 __P4MASK(split-st, 1), 1267 NULLMASK 1268}; 1269 1270static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ 1271 __P4MASK(no-sta, 1), 1272 __P4MASK(no-std, 3), 1273 __P4MASK(partial-data, 4), 1274 __P4MASK(unalgn-addr, 5), 1275 NULLMASK 1276}; 1277 1278static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ 1279 __P4MASK(dtmiss, 0), 1280 __P4MASK(itmiss, 1), 1281 NULLMASK 1282}; 1283 1284static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ 1285 __P4MASK(rd-2ndl-hits, 0), 1286 __P4MASK(rd-2ndl-hite, 1), 1287 __P4MASK(rd-2ndl-hitm, 2), 1288 __P4MASK(rd-3rdl-hits, 3), 1289 __P4MASK(rd-3rdl-hite, 4), 1290 __P4MASK(rd-3rdl-hitm, 5), 1291 __P4MASK(rd-2ndl-miss, 8), 1292 __P4MASK(rd-3rdl-miss, 9), 1293 __P4MASK(wr-2ndl-miss, 10), 1294 NULLMASK 1295}; 1296 1297static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ 1298 __P4MASK(all-read, 5), 1299 __P4MASK(all-write, 6), 1300 __P4MASK(mem-uc, 7), 1301 __P4MASK(mem-wc, 8), 1302 __P4MASK(mem-wt, 9), 1303 __P4MASK(mem-wp, 10), 1304 __P4MASK(mem-wb, 11), 1305 __P4MASK(own, 13), 1306 __P4MASK(other, 14), 1307 __P4MASK(prefetch, 15), 1308 NULLMASK 1309}; 1310 1311static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ 1312 __P4MASK(all-read, 5), 1313 __P4MASK(all-write, 6), 1314 __P4MASK(mem-uc, 7), 1315 __P4MASK(mem-wc, 8), 1316 __P4MASK(mem-wt, 9), 1317 __P4MASK(mem-wp, 10), 1318 __P4MASK(mem-wb, 11), 1319 __P4MASK(own, 13), 1320 __P4MASK(other, 14), 1321 __P4MASK(prefetch, 15), 1322 NULLMASK 1323}; 1324 1325static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ 1326 __P4MASK(drdy-drv, 0), 1327 __P4MASK(drdy-own, 1), 1328 __P4MASK(drdy-other, 2), 1329 __P4MASK(dbsy-drv, 3), 1330 __P4MASK(dbsy-own, 4), 1331 __P4MASK(dbsy-other, 5), 1332 NULLMASK 1333}; 1334 1335static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ 1336 __P4MASK(req-type0, 0), 1337 __P4MASK(req-type1, 1), 1338 __P4MASK(req-len0, 2), 1339 __P4MASK(req-len1, 3), 1340 __P4MASK(req-io-type, 5), 1341 __P4MASK(req-lock-type, 6), 1342 __P4MASK(req-cache-type, 7), 1343 __P4MASK(req-split-type, 8), 1344 __P4MASK(req-dem-type, 9), 1345 __P4MASK(req-ord-type, 10), 1346 __P4MASK(mem-type0, 11), 1347 __P4MASK(mem-type1, 12), 1348 __P4MASK(mem-type2, 13), 1349 NULLMASK 1350}; 1351 1352static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ 1353 __P4MASK(all, 15), 1354 NULLMASK 1355}; 1356 1357static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ 1358 __P4MASK(all, 15), 1359 NULLMASK 1360}; 1361 1362static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ 1363 __P4MASK(all, 15), 1364 NULLMASK 1365}; 1366 1367static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ 1368 __P4MASK(all, 15), 1369 NULLMASK 1370}; 1371 1372static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ 1373 __P4MASK(all, 15), 1374 NULLMASK 1375}; 1376 1377static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ 1378 __P4MASK(all, 15), 1379 NULLMASK 1380}; 1381 1382static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ 1383 __P4MASK(all, 15), 1384 NULLMASK 1385}; 1386 1387static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ 1388 __P4MASK(all, 15), 1389 NULLMASK 1390}; 1391 1392static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ 1393 __P4MASK(allp0, 3), 1394 __P4MASK(allp2, 4), 1395 NULLMASK 1396}; 1397 1398static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ 1399 __P4MASK(running, 0), 1400 NULLMASK 1401}; 1402 1403static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ 1404 __P4MASK(cisc, 0), 1405 NULLMASK 1406}; 1407 1408static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ 1409 __P4MASK(from-tc-build, 0), 1410 __P4MASK(from-tc-deliver, 1), 1411 __P4MASK(from-rom, 2), 1412 NULLMASK 1413}; 1414 1415static const struct pmc_masks p4_mask_rmbt[] = { 1416 /* retired mispred branch type */ 1417 __P4MASK(conditional, 1), 1418 __P4MASK(call, 2), 1419 __P4MASK(return, 3), 1420 __P4MASK(indirect, 4), 1421 NULLMASK 1422}; 1423 1424static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ 1425 __P4MASK(conditional, 1), 1426 __P4MASK(call, 2), 1427 __P4MASK(retired, 3), 1428 __P4MASK(indirect, 4), 1429 NULLMASK 1430}; 1431 1432static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ 1433 __P4MASK(sbfull, 5), 1434 NULLMASK 1435}; 1436 1437static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ 1438 __P4MASK(wcb-evicts, 0), 1439 __P4MASK(wcb-full-evict, 1), 1440 NULLMASK 1441}; 1442 1443static const struct pmc_masks p4_mask_fee[] = { /* front end event */ 1444 __P4MASK(nbogus, 0), 1445 __P4MASK(bogus, 1), 1446 NULLMASK 1447}; 1448 1449static const struct pmc_masks p4_mask_ee[] = { /* execution event */ 1450 __P4MASK(nbogus0, 0), 1451 __P4MASK(nbogus1, 1), 1452 __P4MASK(nbogus2, 2), 1453 __P4MASK(nbogus3, 3), 1454 __P4MASK(bogus0, 4), 1455 __P4MASK(bogus1, 5), 1456 __P4MASK(bogus2, 6), 1457 __P4MASK(bogus3, 7), 1458 NULLMASK 1459}; 1460 1461static const struct pmc_masks p4_mask_re[] = { /* replay event */ 1462 __P4MASK(nbogus, 0), 1463 __P4MASK(bogus, 1), 1464 NULLMASK 1465}; 1466 1467static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ 1468 __P4MASK(nbogusntag, 0), 1469 __P4MASK(nbogustag, 1), 1470 __P4MASK(bogusntag, 2), 1471 __P4MASK(bogustag, 3), 1472 NULLMASK 1473}; 1474 1475static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ 1476 __P4MASK(nbogus, 0), 1477 __P4MASK(bogus, 1), 1478 NULLMASK 1479}; 1480 1481static const struct pmc_masks p4_mask_ut[] = { /* uop type */ 1482 __P4MASK(tagloads, 1), 1483 __P4MASK(tagstores, 2), 1484 NULLMASK 1485}; 1486 1487static const struct pmc_masks p4_mask_br[] = { /* branch retired */ 1488 __P4MASK(mmnp, 0), 1489 __P4MASK(mmnm, 1), 1490 __P4MASK(mmtp, 2), 1491 __P4MASK(mmtm, 3), 1492 NULLMASK 1493}; 1494 1495static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ 1496 __P4MASK(nbogus, 0), 1497 NULLMASK 1498}; 1499 1500static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ 1501 __P4MASK(fpsu, 0), 1502 __P4MASK(fpso, 1), 1503 __P4MASK(poao, 2), 1504 __P4MASK(poau, 3), 1505 __P4MASK(prea, 4), 1506 NULLMASK 1507}; 1508 1509static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ 1510 __P4MASK(clear, 0), 1511 __P4MASK(moclear, 2), 1512 __P4MASK(smclear, 3), 1513 NULLMASK 1514}; 1515 1516/* P4 event parser */ 1517static int 1518p4_allocate_pmc(enum pmc_event pe, char *ctrspec, 1519 struct pmc_op_pmcallocate *pmc_config) 1520{ 1521 1522 char *e, *p, *q; 1523 int count, has_tag, has_busreqtype, n; 1524 uint32_t evmask, cccractivemask; 1525 const struct pmc_masks *pm, *pmask; 1526 1527 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1528 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = 1529 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; 1530 1531 pmask = NULL; 1532 evmask = 0; 1533 cccractivemask = 0x3; 1534 has_tag = has_busreqtype = 0; 1535 1536#define __P4SETMASK(M) do { \ 1537 pmask = p4_mask_##M; \ 1538} while (0) 1539 1540 switch (pe) { 1541 case PMC_EV_P4_TC_DELIVER_MODE: 1542 __P4SETMASK(tcdm); 1543 break; 1544 case PMC_EV_P4_BPU_FETCH_REQUEST: 1545 __P4SETMASK(bfr); 1546 break; 1547 case PMC_EV_P4_ITLB_REFERENCE: 1548 __P4SETMASK(ir); 1549 break; 1550 case PMC_EV_P4_MEMORY_CANCEL: 1551 __P4SETMASK(memcan); 1552 break; 1553 case PMC_EV_P4_MEMORY_COMPLETE: 1554 __P4SETMASK(memcomp); 1555 break; 1556 case PMC_EV_P4_LOAD_PORT_REPLAY: 1557 __P4SETMASK(lpr); 1558 break; 1559 case PMC_EV_P4_STORE_PORT_REPLAY: 1560 __P4SETMASK(spr); 1561 break; 1562 case PMC_EV_P4_MOB_LOAD_REPLAY: 1563 __P4SETMASK(mlr); 1564 break; 1565 case PMC_EV_P4_PAGE_WALK_TYPE: 1566 __P4SETMASK(pwt); 1567 break; 1568 case PMC_EV_P4_BSQ_CACHE_REFERENCE: 1569 __P4SETMASK(bcr); 1570 break; 1571 case PMC_EV_P4_IOQ_ALLOCATION: 1572 __P4SETMASK(ia); 1573 has_busreqtype = 1; 1574 break; 1575 case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: 1576 __P4SETMASK(iae); 1577 has_busreqtype = 1; 1578 break; 1579 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1580 __P4SETMASK(fda); 1581 break; 1582 case PMC_EV_P4_BSQ_ALLOCATION: 1583 __P4SETMASK(ba); 1584 break; 1585 case PMC_EV_P4_SSE_INPUT_ASSIST: 1586 __P4SETMASK(sia); 1587 break; 1588 case PMC_EV_P4_PACKED_SP_UOP: 1589 __P4SETMASK(psu); 1590 break; 1591 case PMC_EV_P4_PACKED_DP_UOP: 1592 __P4SETMASK(pdu); 1593 break; 1594 case PMC_EV_P4_SCALAR_SP_UOP: 1595 __P4SETMASK(ssu); 1596 break; 1597 case PMC_EV_P4_SCALAR_DP_UOP: 1598 __P4SETMASK(sdu); 1599 break; 1600 case PMC_EV_P4_64BIT_MMX_UOP: 1601 __P4SETMASK(64bmu); 1602 break; 1603 case PMC_EV_P4_128BIT_MMX_UOP: 1604 __P4SETMASK(128bmu); 1605 break; 1606 case PMC_EV_P4_X87_FP_UOP: 1607 __P4SETMASK(xfu); 1608 break; 1609 case PMC_EV_P4_X87_SIMD_MOVES_UOP: 1610 __P4SETMASK(xsmu); 1611 break; 1612 case PMC_EV_P4_GLOBAL_POWER_EVENTS: 1613 __P4SETMASK(gpe); 1614 break; 1615 case PMC_EV_P4_TC_MS_XFER: 1616 __P4SETMASK(tmx); 1617 break; 1618 case PMC_EV_P4_UOP_QUEUE_WRITES: 1619 __P4SETMASK(uqw); 1620 break; 1621 case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: 1622 __P4SETMASK(rmbt); 1623 break; 1624 case PMC_EV_P4_RETIRED_BRANCH_TYPE: 1625 __P4SETMASK(rbt); 1626 break; 1627 case PMC_EV_P4_RESOURCE_STALL: 1628 __P4SETMASK(rs); 1629 break; 1630 case PMC_EV_P4_WC_BUFFER: 1631 __P4SETMASK(wb); 1632 break; 1633 case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: 1634 case PMC_EV_P4_B2B_CYCLES: 1635 case PMC_EV_P4_BNR: 1636 case PMC_EV_P4_SNOOP: 1637 case PMC_EV_P4_RESPONSE: 1638 break; 1639 case PMC_EV_P4_FRONT_END_EVENT: 1640 __P4SETMASK(fee); 1641 break; 1642 case PMC_EV_P4_EXECUTION_EVENT: 1643 __P4SETMASK(ee); 1644 break; 1645 case PMC_EV_P4_REPLAY_EVENT: 1646 __P4SETMASK(re); 1647 break; 1648 case PMC_EV_P4_INSTR_RETIRED: 1649 __P4SETMASK(insret); 1650 break; 1651 case PMC_EV_P4_UOPS_RETIRED: 1652 __P4SETMASK(ur); 1653 break; 1654 case PMC_EV_P4_UOP_TYPE: 1655 __P4SETMASK(ut); 1656 break; 1657 case PMC_EV_P4_BRANCH_RETIRED: 1658 __P4SETMASK(br); 1659 break; 1660 case PMC_EV_P4_MISPRED_BRANCH_RETIRED: 1661 __P4SETMASK(mbr); 1662 break; 1663 case PMC_EV_P4_X87_ASSIST: 1664 __P4SETMASK(xa); 1665 break; 1666 case PMC_EV_P4_MACHINE_CLEAR: 1667 __P4SETMASK(machclr); 1668 break; 1669 default: 1670 return (-1); 1671 } 1672 1673 /* process additional flags */ 1674 while ((p = strsep(&ctrspec, ",")) != NULL) { 1675 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { 1676 q = strchr(p, '='); 1677 if (*++q == '\0') /* skip '=' */ 1678 return (-1); 1679 1680 if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) 1681 cccractivemask = 0x0; 1682 else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) 1683 cccractivemask = 0x1; 1684 else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) 1685 cccractivemask = 0x2; 1686 else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) 1687 cccractivemask = 0x3; 1688 else 1689 return (-1); 1690 1691 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { 1692 if (has_busreqtype == 0) 1693 return (-1); 1694 1695 q = strchr(p, '='); 1696 if (*++q == '\0') /* skip '=' */ 1697 return (-1); 1698 1699 count = strtol(q, &e, 0); 1700 if (e == q || *e != '\0') 1701 return (-1); 1702 evmask = (evmask & ~0x1F) | (count & 0x1F); 1703 } else if (KWMATCH(p, P4_KW_CASCADE)) 1704 pmc_config->pm_caps |= PMC_CAP_CASCADE; 1705 else if (KWMATCH(p, P4_KW_EDGE)) 1706 pmc_config->pm_caps |= PMC_CAP_EDGE; 1707 else if (KWMATCH(p, P4_KW_INV)) 1708 pmc_config->pm_caps |= PMC_CAP_INVERT; 1709 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { 1710 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 1711 return (-1); 1712 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1713 } else if (KWMATCH(p, P4_KW_OS)) 1714 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 1715 else if (KWMATCH(p, P4_KW_PRECISE)) 1716 pmc_config->pm_caps |= PMC_CAP_PRECISE; 1717 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { 1718 if (has_tag == 0) 1719 return (-1); 1720 1721 q = strchr(p, '='); 1722 if (*++q == '\0') /* skip '=' */ 1723 return (-1); 1724 1725 count = strtol(q, &e, 0); 1726 if (e == q || *e != '\0') 1727 return (-1); 1728 1729 pmc_config->pm_caps |= PMC_CAP_TAGGING; 1730 pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= 1731 P4_ESCR_TO_TAG_VALUE(count); 1732 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { 1733 q = strchr(p, '='); 1734 if (*++q == '\0') /* skip '=' */ 1735 return (-1); 1736 1737 count = strtol(q, &e, 0); 1738 if (e == q || *e != '\0') 1739 return (-1); 1740 1741 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 1742 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= 1743 ~P4_CCCR_THRESHOLD_MASK; 1744 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1745 P4_CCCR_TO_THRESHOLD(count); 1746 } else if (KWMATCH(p, P4_KW_USR)) 1747 pmc_config->pm_caps |= PMC_CAP_USER; 1748 else 1749 return (-1); 1750 } 1751 1752 /* other post processing */ 1753 if (pe == PMC_EV_P4_IOQ_ALLOCATION || 1754 pe == PMC_EV_P4_FSB_DATA_ACTIVITY || 1755 pe == PMC_EV_P4_BSQ_ALLOCATION) 1756 pmc_config->pm_caps |= PMC_CAP_EDGE; 1757 1758 /* fill in thread activity mask */ 1759 pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= 1760 P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); 1761 1762 if (evmask) 1763 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1764 1765 switch (pe) { 1766 case PMC_EV_P4_FSB_DATA_ACTIVITY: 1767 if ((evmask & 0x06) == 0x06 || 1768 (evmask & 0x18) == 0x18) 1769 return (-1); /* can't have own+other bits together */ 1770 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ 1771 evmask = 0x1D; 1772 break; 1773 case PMC_EV_P4_MACHINE_CLEAR: 1774 /* only one bit is allowed to be set */ 1775 if ((evmask & (evmask - 1)) != 0) 1776 return (-1); 1777 if (evmask == 0) { 1778 evmask = 0x1; /* 'CLEAR' */ 1779 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1780 } 1781 break; 1782 default: 1783 if (evmask == 0 && pmask) { 1784 for (pm = pmask; pm->pm_name; pm++) 1785 evmask |= pm->pm_value; 1786 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 1787 } 1788 } 1789 1790 pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 1791 P4_ESCR_TO_EVENT_MASK(evmask); 1792 1793 return (0); 1794} 1795 1796#endif 1797 1798#if defined(__i386__) 1799 1800/* 1801 * Pentium style PMCs 1802 */ 1803 1804static struct pmc_event_alias p5_aliases[] = { 1805 EV_ALIAS("branches", "p5-taken-branches"), 1806 EV_ALIAS("cycles", "tsc"), 1807 EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), 1808 EV_ALIAS("ic-misses", "p5-code-cache-miss"), 1809 EV_ALIAS("instructions", "p5-instructions-executed"), 1810 EV_ALIAS("interrupts", "p5-hardware-interrupts"), 1811 EV_ALIAS("unhalted-cycles", 1812 "p5-number-of-cycles-not-in-halt-state"), 1813 EV_ALIAS(NULL, NULL) 1814}; 1815 1816static int 1817p5_allocate_pmc(enum pmc_event pe, char *ctrspec, 1818 struct pmc_op_pmcallocate *pmc_config) 1819{ 1820 return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ 1821} 1822 1823/* 1824 * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, 1825 * and Pentium M CPUs. 1826 */ 1827 1828static struct pmc_event_alias p6_aliases[] = { 1829 EV_ALIAS("branches", "p6-br-inst-retired"), 1830 EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), 1831 EV_ALIAS("cycles", "tsc"), 1832 EV_ALIAS("dc-misses", "p6-dcu-lines-in"), 1833 EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), 1834 EV_ALIAS("instructions", "p6-inst-retired"), 1835 EV_ALIAS("interrupts", "p6-hw-int-rx"), 1836 EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), 1837 EV_ALIAS(NULL, NULL) 1838}; 1839 1840#define P6_KW_CMASK "cmask" 1841#define P6_KW_EDGE "edge" 1842#define P6_KW_INV "inv" 1843#define P6_KW_OS "os" 1844#define P6_KW_UMASK "umask" 1845#define P6_KW_USR "usr" 1846 1847static struct pmc_masks p6_mask_mesi[] = { 1848 PMCMASK(m, 0x01), 1849 PMCMASK(e, 0x02), 1850 PMCMASK(s, 0x04), 1851 PMCMASK(i, 0x08), 1852 NULLMASK 1853}; 1854 1855static struct pmc_masks p6_mask_mesihw[] = { 1856 PMCMASK(m, 0x01), 1857 PMCMASK(e, 0x02), 1858 PMCMASK(s, 0x04), 1859 PMCMASK(i, 0x08), 1860 PMCMASK(nonhw, 0x00), 1861 PMCMASK(hw, 0x10), 1862 PMCMASK(both, 0x30), 1863 NULLMASK 1864}; 1865 1866static struct pmc_masks p6_mask_hw[] = { 1867 PMCMASK(nonhw, 0x00), 1868 PMCMASK(hw, 0x10), 1869 PMCMASK(both, 0x30), 1870 NULLMASK 1871}; 1872 1873static struct pmc_masks p6_mask_any[] = { 1874 PMCMASK(self, 0x00), 1875 PMCMASK(any, 0x20), 1876 NULLMASK 1877}; 1878 1879static struct pmc_masks p6_mask_ekp[] = { 1880 PMCMASK(nta, 0x00), 1881 PMCMASK(t1, 0x01), 1882 PMCMASK(t2, 0x02), 1883 PMCMASK(wos, 0x03), 1884 NULLMASK 1885}; 1886 1887static struct pmc_masks p6_mask_pps[] = { 1888 PMCMASK(packed-and-scalar, 0x00), 1889 PMCMASK(scalar, 0x01), 1890 NULLMASK 1891}; 1892 1893static struct pmc_masks p6_mask_mite[] = { 1894 PMCMASK(packed-multiply, 0x01), 1895 PMCMASK(packed-shift, 0x02), 1896 PMCMASK(pack, 0x04), 1897 PMCMASK(unpack, 0x08), 1898 PMCMASK(packed-logical, 0x10), 1899 PMCMASK(packed-arithmetic, 0x20), 1900 NULLMASK 1901}; 1902 1903static struct pmc_masks p6_mask_fmt[] = { 1904 PMCMASK(mmxtofp, 0x00), 1905 PMCMASK(fptommx, 0x01), 1906 NULLMASK 1907}; 1908 1909static struct pmc_masks p6_mask_sr[] = { 1910 PMCMASK(es, 0x01), 1911 PMCMASK(ds, 0x02), 1912 PMCMASK(fs, 0x04), 1913 PMCMASK(gs, 0x08), 1914 NULLMASK 1915}; 1916 1917static struct pmc_masks p6_mask_eet[] = { 1918 PMCMASK(all, 0x00), 1919 PMCMASK(freq, 0x02), 1920 NULLMASK 1921}; 1922 1923static struct pmc_masks p6_mask_efur[] = { 1924 PMCMASK(all, 0x00), 1925 PMCMASK(loadop, 0x01), 1926 PMCMASK(stdsta, 0x02), 1927 NULLMASK 1928}; 1929 1930static struct pmc_masks p6_mask_essir[] = { 1931 PMCMASK(sse-packed-single, 0x00), 1932 PMCMASK(sse-packed-single-scalar-single, 0x01), 1933 PMCMASK(sse2-packed-double, 0x02), 1934 PMCMASK(sse2-scalar-double, 0x03), 1935 NULLMASK 1936}; 1937 1938static struct pmc_masks p6_mask_esscir[] = { 1939 PMCMASK(sse-packed-single, 0x00), 1940 PMCMASK(sse-scalar-single, 0x01), 1941 PMCMASK(sse2-packed-double, 0x02), 1942 PMCMASK(sse2-scalar-double, 0x03), 1943 NULLMASK 1944}; 1945 1946/* P6 event parser */ 1947static int 1948p6_allocate_pmc(enum pmc_event pe, char *ctrspec, 1949 struct pmc_op_pmcallocate *pmc_config) 1950{ 1951 char *e, *p, *q; 1952 uint32_t evmask; 1953 int count, n; 1954 const struct pmc_masks *pm, *pmask; 1955 1956 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 1957 pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; 1958 1959 evmask = 0; 1960 1961#define P6MASKSET(M) pmask = p6_mask_ ## M 1962 1963 switch(pe) { 1964 case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; 1965 case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; 1966 case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; 1967 case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; 1968 case PMC_EV_P6_BUS_DRDY_CLOCKS: 1969 case PMC_EV_P6_BUS_LOCK_CLOCKS: 1970 case PMC_EV_P6_BUS_TRAN_BRD: 1971 case PMC_EV_P6_BUS_TRAN_RFO: 1972 case PMC_EV_P6_BUS_TRANS_WB: 1973 case PMC_EV_P6_BUS_TRAN_IFETCH: 1974 case PMC_EV_P6_BUS_TRAN_INVAL: 1975 case PMC_EV_P6_BUS_TRAN_PWR: 1976 case PMC_EV_P6_BUS_TRANS_P: 1977 case PMC_EV_P6_BUS_TRANS_IO: 1978 case PMC_EV_P6_BUS_TRAN_DEF: 1979 case PMC_EV_P6_BUS_TRAN_BURST: 1980 case PMC_EV_P6_BUS_TRAN_ANY: 1981 case PMC_EV_P6_BUS_TRAN_MEM: 1982 P6MASKSET(any); break; 1983 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 1984 case PMC_EV_P6_EMON_KNI_PREF_MISS: 1985 P6MASKSET(ekp); break; 1986 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 1987 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 1988 P6MASKSET(pps); break; 1989 case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: 1990 P6MASKSET(mite); break; 1991 case PMC_EV_P6_FP_MMX_TRANS: 1992 P6MASKSET(fmt); break; 1993 case PMC_EV_P6_SEG_RENAME_STALLS: 1994 case PMC_EV_P6_SEG_REG_RENAMES: 1995 P6MASKSET(sr); break; 1996 case PMC_EV_P6_EMON_EST_TRANS: 1997 P6MASKSET(eet); break; 1998 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 1999 P6MASKSET(efur); break; 2000 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2001 P6MASKSET(essir); break; 2002 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2003 P6MASKSET(esscir); break; 2004 default: 2005 pmask = NULL; 2006 break; 2007 } 2008 2009 /* Pentium M PMCs have a few events with different semantics */ 2010 if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { 2011 if (pe == PMC_EV_P6_L2_LD || 2012 pe == PMC_EV_P6_L2_LINES_IN || 2013 pe == PMC_EV_P6_L2_LINES_OUT) 2014 P6MASKSET(mesihw); 2015 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) 2016 P6MASKSET(hw); 2017 } 2018 2019 /* Parse additional modifiers if present */ 2020 while ((p = strsep(&ctrspec, ",")) != NULL) { 2021 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { 2022 q = strchr(p, '='); 2023 if (*++q == '\0') /* skip '=' */ 2024 return (-1); 2025 count = strtol(q, &e, 0); 2026 if (e == q || *e != '\0') 2027 return (-1); 2028 pmc_config->pm_caps |= PMC_CAP_THRESHOLD; 2029 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2030 P6_EVSEL_TO_CMASK(count); 2031 } else if (KWMATCH(p, P6_KW_EDGE)) { 2032 pmc_config->pm_caps |= PMC_CAP_EDGE; 2033 } else if (KWMATCH(p, P6_KW_INV)) { 2034 pmc_config->pm_caps |= PMC_CAP_INVERT; 2035 } else if (KWMATCH(p, P6_KW_OS)) { 2036 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2037 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { 2038 evmask = 0; 2039 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) 2040 return (-1); 2041 if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || 2042 pe == PMC_EV_P6_BUS_LOCK_CLOCKS || 2043 pe == PMC_EV_P6_BUS_TRAN_BRD || 2044 pe == PMC_EV_P6_BUS_TRAN_RFO || 2045 pe == PMC_EV_P6_BUS_TRAN_IFETCH || 2046 pe == PMC_EV_P6_BUS_TRAN_INVAL || 2047 pe == PMC_EV_P6_BUS_TRAN_PWR || 2048 pe == PMC_EV_P6_BUS_TRAN_DEF || 2049 pe == PMC_EV_P6_BUS_TRAN_BURST || 2050 pe == PMC_EV_P6_BUS_TRAN_ANY || 2051 pe == PMC_EV_P6_BUS_TRAN_MEM || 2052 pe == PMC_EV_P6_BUS_TRANS_IO || 2053 pe == PMC_EV_P6_BUS_TRANS_P || 2054 pe == PMC_EV_P6_BUS_TRANS_WB || 2055 pe == PMC_EV_P6_EMON_EST_TRANS || 2056 pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || 2057 pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || 2058 pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || 2059 pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || 2060 pe == PMC_EV_P6_EMON_KNI_PREF_MISS || 2061 pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || 2062 pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || 2063 pe == PMC_EV_P6_FP_MMX_TRANS) 2064 && (n > 1)) /* Only one mask keyword is allowed. */ 2065 return (-1); 2066 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2067 } else if (KWMATCH(p, P6_KW_USR)) { 2068 pmc_config->pm_caps |= PMC_CAP_USER; 2069 } else 2070 return (-1); 2071 } 2072 2073 /* post processing */ 2074 switch (pe) { 2075 2076 /* 2077 * The following events default to an evmask of 0 2078 */ 2079 2080 /* default => 'self' */ 2081 case PMC_EV_P6_BUS_DRDY_CLOCKS: 2082 case PMC_EV_P6_BUS_LOCK_CLOCKS: 2083 case PMC_EV_P6_BUS_TRAN_BRD: 2084 case PMC_EV_P6_BUS_TRAN_RFO: 2085 case PMC_EV_P6_BUS_TRANS_WB: 2086 case PMC_EV_P6_BUS_TRAN_IFETCH: 2087 case PMC_EV_P6_BUS_TRAN_INVAL: 2088 case PMC_EV_P6_BUS_TRAN_PWR: 2089 case PMC_EV_P6_BUS_TRANS_P: 2090 case PMC_EV_P6_BUS_TRANS_IO: 2091 case PMC_EV_P6_BUS_TRAN_DEF: 2092 case PMC_EV_P6_BUS_TRAN_BURST: 2093 case PMC_EV_P6_BUS_TRAN_ANY: 2094 case PMC_EV_P6_BUS_TRAN_MEM: 2095 2096 /* default => 'nta' */ 2097 case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: 2098 case PMC_EV_P6_EMON_KNI_PREF_MISS: 2099 2100 /* default => 'packed and scalar' */ 2101 case PMC_EV_P6_EMON_KNI_INST_RETIRED: 2102 case PMC_EV_P6_EMON_KNI_COMP_INST_RET: 2103 2104 /* default => 'mmx to fp transitions' */ 2105 case PMC_EV_P6_FP_MMX_TRANS: 2106 2107 /* default => 'SSE Packed Single' */ 2108 case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: 2109 case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: 2110 2111 /* default => 'all fused micro-ops' */ 2112 case PMC_EV_P6_EMON_FUSED_UOPS_RET: 2113 2114 /* default => 'all transitions' */ 2115 case PMC_EV_P6_EMON_EST_TRANS: 2116 break; 2117 2118 case PMC_EV_P6_MMX_UOPS_EXEC: 2119 evmask = 0x0F; /* only value allowed */ 2120 break; 2121 2122 default: 2123 /* 2124 * For all other events, set the default event mask 2125 * to a logical OR of all the allowed event mask bits. 2126 */ 2127 if (evmask == 0 && pmask) { 2128 for (pm = pmask; pm->pm_name; pm++) 2129 evmask |= pm->pm_value; 2130 pmc_config->pm_caps |= PMC_CAP_QUALIFIER; 2131 } 2132 2133 break; 2134 } 2135 2136 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) 2137 pmc_config->pm_md.pm_ppro.pm_ppro_config |= 2138 P6_EVSEL_TO_UMASK(evmask); 2139 2140 return (0); 2141} 2142 2143#endif 2144 2145#if defined(__i386__) || defined(__amd64__) 2146static int 2147tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, 2148 struct pmc_op_pmcallocate *pmc_config) 2149{ 2150 if (pe != PMC_EV_TSC_TSC) 2151 return (-1); 2152 2153 /* TSC events must be unqualified. */ 2154 if (ctrspec && *ctrspec != '\0') 2155 return (-1); 2156 2157 pmc_config->pm_md.pm_amd.pm_amd_config = 0; 2158 pmc_config->pm_caps |= PMC_CAP_READ; 2159 2160 return (0); 2161} 2162#endif 2163 2164#if defined(__XSCALE__) 2165 2166static struct pmc_event_alias xscale_aliases[] = { 2167 EV_ALIAS("branches", "BRANCH_RETIRED"), 2168 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2169 EV_ALIAS("dc-misses", "DC_MISS"), 2170 EV_ALIAS("ic-misses", "IC_MISS"), 2171 EV_ALIAS("instructions", "INSTR_RETIRED"), 2172 EV_ALIAS(NULL, NULL) 2173}; 2174static int 2175xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2176 struct pmc_op_pmcallocate *pmc_config __unused) 2177{ 2178 switch (pe) { 2179 default: 2180 break; 2181 } 2182 2183 return (0); 2184} 2185#endif 2186 2187#if defined(__mips__) 2188 2189static struct pmc_event_alias mips24k_aliases[] = { 2190 EV_ALIAS("instructions", "INSTR_EXECUTED"), 2191 EV_ALIAS("branches", "BRANCH_COMPLETED"), 2192 EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), 2193 EV_ALIAS(NULL, NULL) 2194}; 2195 2196#define MIPS24K_KW_OS "os" 2197#define MIPS24K_KW_USR "usr" 2198#define MIPS24K_KW_ANYTHREAD "anythread" 2199 2200static int 2201mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2202 struct pmc_op_pmcallocate *pmc_config __unused) 2203{ 2204 char *p; 2205 2206 (void) pe; 2207 2208 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2209 2210 while ((p = strsep(&ctrspec, ",")) != NULL) { 2211 if (KWMATCH(p, MIPS24K_KW_OS)) 2212 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2213 else if (KWMATCH(p, MIPS24K_KW_USR)) 2214 pmc_config->pm_caps |= PMC_CAP_USER; 2215 else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD)) 2216 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2217 else 2218 return (-1); 2219 } 2220 2221 return (0); 2222} 2223#endif /* __mips__ */ 2224 2225#if defined(__powerpc__) 2226 2227static struct pmc_event_alias ppc7450_aliases[] = { 2228 EV_ALIAS("instructions", "INSTR_COMPLETED"), 2229 EV_ALIAS("branches", "BRANCHES_COMPLETED"), 2230 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), 2231 EV_ALIAS(NULL, NULL) 2232}; 2233 2234#define PPC7450_KW_OS "os" 2235#define PPC7450_KW_USR "usr" 2236#define PPC7450_KW_ANYTHREAD "anythread" 2237 2238static int 2239ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, 2240 struct pmc_op_pmcallocate *pmc_config __unused) 2241{ 2242 char *p; 2243 2244 (void) pe; 2245 2246 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); 2247 2248 while ((p = strsep(&ctrspec, ",")) != NULL) { 2249 if (KWMATCH(p, PPC7450_KW_OS)) 2250 pmc_config->pm_caps |= PMC_CAP_SYSTEM; 2251 else if (KWMATCH(p, PPC7450_KW_USR)) 2252 pmc_config->pm_caps |= PMC_CAP_USER; 2253 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD)) 2254 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); 2255 else 2256 return (-1); 2257 } 2258 2259 return (0); 2260} 2261#endif /* __powerpc__ */ 2262 2263 2264/* 2265 * Match an event name `name' with its canonical form. 2266 * 2267 * Matches are case insensitive and spaces, periods, underscores and 2268 * hyphen characters are considered to match each other. 2269 * 2270 * Returns 1 for a match, 0 otherwise. 2271 */ 2272 2273static int 2274pmc_match_event_name(const char *name, const char *canonicalname) 2275{ 2276 int cc, nc; 2277 const unsigned char *c, *n; 2278 2279 c = (const unsigned char *) canonicalname; 2280 n = (const unsigned char *) name; 2281 2282 for (; (nc = *n) && (cc = *c); n++, c++) { 2283 2284 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && 2285 (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) 2286 continue; 2287 2288 if (toupper(nc) == toupper(cc)) 2289 continue; 2290 2291 2292 return (0); 2293 } 2294 2295 if (*n == '\0' && *c == '\0') 2296 return (1); 2297 2298 return (0); 2299} 2300 2301/* 2302 * Match an event name against all the event named supported by a 2303 * PMC class. 2304 * 2305 * Returns an event descriptor pointer on match or NULL otherwise. 2306 */ 2307static const struct pmc_event_descr * 2308pmc_match_event_class(const char *name, 2309 const struct pmc_class_descr *pcd) 2310{ 2311 size_t n; 2312 const struct pmc_event_descr *ev; 2313 2314 ev = pcd->pm_evc_event_table; 2315 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) 2316 if (pmc_match_event_name(name, ev->pm_ev_name)) 2317 return (ev); 2318 2319 return (NULL); 2320} 2321 2322static int 2323pmc_mdep_is_compatible_class(enum pmc_class pc) 2324{ 2325 size_t n; 2326 2327 for (n = 0; n < pmc_mdep_class_list_size; n++) 2328 if (pmc_mdep_class_list[n] == pc) 2329 return (1); 2330 return (0); 2331} 2332 2333/* 2334 * API entry points 2335 */ 2336 2337int 2338pmc_allocate(const char *ctrspec, enum pmc_mode mode, 2339 uint32_t flags, int cpu, pmc_id_t *pmcid) 2340{ 2341 size_t n; 2342 int retval; 2343 char *r, *spec_copy; 2344 const char *ctrname; 2345 const struct pmc_event_descr *ev; 2346 const struct pmc_event_alias *alias; 2347 struct pmc_op_pmcallocate pmc_config; 2348 const struct pmc_class_descr *pcd; 2349 2350 spec_copy = NULL; 2351 retval = -1; 2352 2353 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && 2354 mode != PMC_MODE_SC && mode != PMC_MODE_TC) { 2355 errno = EINVAL; 2356 goto out; 2357 } 2358 2359 /* replace an event alias with the canonical event specifier */ 2360 if (pmc_mdep_event_aliases) 2361 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) 2362 if (!strcasecmp(ctrspec, alias->pm_alias)) { 2363 spec_copy = strdup(alias->pm_spec); 2364 break; 2365 } 2366 2367 if (spec_copy == NULL) 2368 spec_copy = strdup(ctrspec); 2369 2370 r = spec_copy; 2371 ctrname = strsep(&r, ","); 2372 2373 /* 2374 * If a explicit class prefix was given by the user, restrict the 2375 * search for the event to the specified PMC class. 2376 */ 2377 ev = NULL; 2378 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { 2379 pcd = pmc_class_table[n]; 2380 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && 2381 strncasecmp(ctrname, pcd->pm_evc_name, 2382 pcd->pm_evc_name_size) == 0) { 2383 if ((ev = pmc_match_event_class(ctrname + 2384 pcd->pm_evc_name_size, pcd)) == NULL) { 2385 errno = EINVAL; 2386 goto out; 2387 } 2388 break; 2389 } 2390 } 2391 2392 /* 2393 * Otherwise, search for this event in all compatible PMC 2394 * classes. 2395 */ 2396 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { 2397 pcd = pmc_class_table[n]; 2398 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) 2399 ev = pmc_match_event_class(ctrname, pcd); 2400 } 2401 2402 if (ev == NULL) { 2403 errno = EINVAL; 2404 goto out; 2405 } 2406 2407 bzero(&pmc_config, sizeof(pmc_config)); 2408 pmc_config.pm_ev = ev->pm_ev_code; 2409 pmc_config.pm_class = pcd->pm_evc_class; 2410 pmc_config.pm_cpu = cpu; 2411 pmc_config.pm_mode = mode; 2412 pmc_config.pm_flags = flags; 2413 2414 if (PMC_IS_SAMPLING_MODE(mode)) 2415 pmc_config.pm_caps |= PMC_CAP_INTERRUPT; 2416 2417 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { 2418 errno = EINVAL; 2419 goto out; 2420 } 2421 2422 if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) 2423 goto out; 2424 2425 *pmcid = pmc_config.pm_pmcid; 2426 2427 retval = 0; 2428 2429 out: 2430 if (spec_copy) 2431 free(spec_copy); 2432 2433 return (retval); 2434} 2435 2436int 2437pmc_attach(pmc_id_t pmc, pid_t pid) 2438{ 2439 struct pmc_op_pmcattach pmc_attach_args; 2440 2441 pmc_attach_args.pm_pmc = pmc; 2442 pmc_attach_args.pm_pid = pid; 2443 2444 return (PMC_CALL(PMCATTACH, &pmc_attach_args)); 2445} 2446 2447int 2448pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) 2449{ 2450 unsigned int i; 2451 enum pmc_class cl; 2452 2453 cl = PMC_ID_TO_CLASS(pmcid); 2454 for (i = 0; i < cpu_info.pm_nclass; i++) 2455 if (cpu_info.pm_classes[i].pm_class == cl) { 2456 *caps = cpu_info.pm_classes[i].pm_caps; 2457 return (0); 2458 } 2459 errno = EINVAL; 2460 return (-1); 2461} 2462 2463int 2464pmc_configure_logfile(int fd) 2465{ 2466 struct pmc_op_configurelog cla; 2467 2468 cla.pm_logfd = fd; 2469 if (PMC_CALL(CONFIGURELOG, &cla) < 0) 2470 return (-1); 2471 return (0); 2472} 2473 2474int 2475pmc_cpuinfo(const struct pmc_cpuinfo **pci) 2476{ 2477 if (pmc_syscall == -1) { 2478 errno = ENXIO; 2479 return (-1); 2480 } 2481 2482 *pci = &cpu_info; 2483 return (0); 2484} 2485 2486int 2487pmc_detach(pmc_id_t pmc, pid_t pid) 2488{ 2489 struct pmc_op_pmcattach pmc_detach_args; 2490 2491 pmc_detach_args.pm_pmc = pmc; 2492 pmc_detach_args.pm_pid = pid; 2493 return (PMC_CALL(PMCDETACH, &pmc_detach_args)); 2494} 2495 2496int 2497pmc_disable(int cpu, int pmc) 2498{ 2499 struct pmc_op_pmcadmin ssa; 2500 2501 ssa.pm_cpu = cpu; 2502 ssa.pm_pmc = pmc; 2503 ssa.pm_state = PMC_STATE_DISABLED; 2504 return (PMC_CALL(PMCADMIN, &ssa)); 2505} 2506 2507int 2508pmc_enable(int cpu, int pmc) 2509{ 2510 struct pmc_op_pmcadmin ssa; 2511 2512 ssa.pm_cpu = cpu; 2513 ssa.pm_pmc = pmc; 2514 ssa.pm_state = PMC_STATE_FREE; 2515 return (PMC_CALL(PMCADMIN, &ssa)); 2516} 2517 2518/* 2519 * Return a list of events known to a given PMC class. 'cl' is the 2520 * PMC class identifier, 'eventnames' is the returned list of 'const 2521 * char *' pointers pointing to the names of the events. 'nevents' is 2522 * the number of event name pointers returned. 2523 * 2524 * The space for 'eventnames' is allocated using malloc(3). The caller 2525 * is responsible for freeing this space when done. 2526 */ 2527int 2528pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, 2529 int *nevents) 2530{ 2531 int count; 2532 const char **names; 2533 const struct pmc_event_descr *ev; 2534 2535 switch (cl) 2536 { 2537 case PMC_CLASS_IAF: 2538 ev = iaf_event_table; 2539 count = PMC_EVENT_TABLE_SIZE(iaf); 2540 break; 2541 case PMC_CLASS_IAP: 2542 /* 2543 * Return the most appropriate set of event name 2544 * spellings for the current CPU. 2545 */ 2546 switch (cpu_info.pm_cputype) { 2547 default: 2548 case PMC_CPU_INTEL_ATOM: 2549 ev = atom_event_table; 2550 count = PMC_EVENT_TABLE_SIZE(atom); 2551 break; 2552 case PMC_CPU_INTEL_CORE: 2553 ev = core_event_table; 2554 count = PMC_EVENT_TABLE_SIZE(core); 2555 break; 2556 case PMC_CPU_INTEL_CORE2: 2557 case PMC_CPU_INTEL_CORE2EXTREME: 2558 ev = core2_event_table; 2559 count = PMC_EVENT_TABLE_SIZE(core2); 2560 break; 2561 case PMC_CPU_INTEL_COREI7: 2562 ev = corei7_event_table; 2563 count = PMC_EVENT_TABLE_SIZE(corei7); 2564 break; 2565 case PMC_CPU_INTEL_WESTMERE: 2566 ev = westmere_event_table; 2567 count = PMC_EVENT_TABLE_SIZE(westmere); 2568 break; 2569 } 2570 break; 2571 case PMC_CLASS_UCF: 2572 ev = ucf_event_table; 2573 count = PMC_EVENT_TABLE_SIZE(ucf); 2574 break; 2575 case PMC_CLASS_UCP: 2576 /* 2577 * Return the most appropriate set of event name 2578 * spellings for the current CPU. 2579 */ 2580 switch (cpu_info.pm_cputype) { 2581 default: 2582 case PMC_CPU_INTEL_COREI7: 2583 ev = corei7uc_event_table; 2584 count = PMC_EVENT_TABLE_SIZE(corei7uc); 2585 break; 2586 case PMC_CPU_INTEL_WESTMERE: 2587 ev = westmereuc_event_table; 2588 count = PMC_EVENT_TABLE_SIZE(westmereuc); 2589 break; 2590 } 2591 break; 2592 case PMC_CLASS_TSC: 2593 ev = tsc_event_table; 2594 count = PMC_EVENT_TABLE_SIZE(tsc); 2595 break; 2596 case PMC_CLASS_K7: 2597 ev = k7_event_table; 2598 count = PMC_EVENT_TABLE_SIZE(k7); 2599 break; 2600 case PMC_CLASS_K8: 2601 ev = k8_event_table; 2602 count = PMC_EVENT_TABLE_SIZE(k8); 2603 break; 2604 case PMC_CLASS_P4: 2605 ev = p4_event_table; 2606 count = PMC_EVENT_TABLE_SIZE(p4); 2607 break; 2608 case PMC_CLASS_P5: 2609 ev = p5_event_table; 2610 count = PMC_EVENT_TABLE_SIZE(p5); 2611 break; 2612 case PMC_CLASS_P6: 2613 ev = p6_event_table; 2614 count = PMC_EVENT_TABLE_SIZE(p6); 2615 break; 2616 case PMC_CLASS_XSCALE: 2617 ev = xscale_event_table; 2618 count = PMC_EVENT_TABLE_SIZE(xscale); 2619 break; 2620 case PMC_CLASS_MIPS24K: 2621 ev = mips24k_event_table; 2622 count = PMC_EVENT_TABLE_SIZE(mips24k); 2623 break; 2624 case PMC_CLASS_PPC7450: 2625 ev = ppc7450_event_table; 2626 count = PMC_EVENT_TABLE_SIZE(ppc7450); 2627 break; 2628 default: 2629 errno = EINVAL; 2630 return (-1); 2631 } 2632 2633 if ((names = malloc(count * sizeof(const char *))) == NULL) 2634 return (-1); 2635 2636 *eventnames = names; 2637 *nevents = count; 2638 2639 for (;count--; ev++, names++) 2640 *names = ev->pm_ev_name; 2641 return (0); 2642} 2643 2644int 2645pmc_flush_logfile(void) 2646{ 2647 return (PMC_CALL(FLUSHLOG,0)); 2648} 2649 2650int 2651pmc_close_logfile(void) 2652{ 2653 return (PMC_CALL(CLOSELOG,0)); 2654} 2655 2656int 2657pmc_get_driver_stats(struct pmc_driverstats *ds) 2658{ 2659 struct pmc_op_getdriverstats gms; 2660 2661 if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) 2662 return (-1); 2663 2664 /* copy out fields in the current userland<->library interface */ 2665 ds->pm_intr_ignored = gms.pm_intr_ignored; 2666 ds->pm_intr_processed = gms.pm_intr_processed; 2667 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; 2668 ds->pm_syscalls = gms.pm_syscalls; 2669 ds->pm_syscall_errors = gms.pm_syscall_errors; 2670 ds->pm_buffer_requests = gms.pm_buffer_requests; 2671 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; 2672 ds->pm_log_sweeps = gms.pm_log_sweeps; 2673 return (0); 2674} 2675 2676int 2677pmc_get_msr(pmc_id_t pmc, uint32_t *msr) 2678{ 2679 struct pmc_op_getmsr gm; 2680 2681 gm.pm_pmcid = pmc; 2682 if (PMC_CALL(PMCGETMSR, &gm) < 0) 2683 return (-1); 2684 *msr = gm.pm_msr; 2685 return (0); 2686} 2687 2688int 2689pmc_init(void) 2690{ 2691 int error, pmc_mod_id; 2692 unsigned int n; 2693 uint32_t abi_version; 2694 struct module_stat pmc_modstat; 2695 struct pmc_op_getcpuinfo op_cpu_info; 2696#if defined(__amd64__) || defined(__i386__) 2697 int cpu_has_iaf_counters; 2698 unsigned int t; 2699#endif 2700 2701 if (pmc_syscall != -1) /* already inited */ 2702 return (0); 2703 2704 /* retrieve the system call number from the KLD */ 2705 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) 2706 return (-1); 2707 2708 pmc_modstat.version = sizeof(struct module_stat); 2709 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) 2710 return (-1); 2711 2712 pmc_syscall = pmc_modstat.data.intval; 2713 2714 /* check the kernel module's ABI against our compiled-in version */ 2715 abi_version = PMC_VERSION; 2716 if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) 2717 return (pmc_syscall = -1); 2718 2719 /* ignore patch & minor numbers for the comparision */ 2720 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { 2721 errno = EPROGMISMATCH; 2722 return (pmc_syscall = -1); 2723 } 2724 2725 if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) 2726 return (pmc_syscall = -1); 2727 2728 cpu_info.pm_cputype = op_cpu_info.pm_cputype; 2729 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; 2730 cpu_info.pm_npmc = op_cpu_info.pm_npmc; 2731 cpu_info.pm_nclass = op_cpu_info.pm_nclass; 2732 for (n = 0; n < cpu_info.pm_nclass; n++) 2733 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; 2734 2735 pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * 2736 sizeof(struct pmc_class_descr *)); 2737 2738 if (pmc_class_table == NULL) 2739 return (-1); 2740 2741 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) 2742 pmc_class_table[n] = NULL; 2743 2744 /* 2745 * Fill in the class table. 2746 */ 2747 n = 0; 2748#if defined(__amd64__) || defined(__i386__) 2749 pmc_class_table[n++] = &tsc_class_table_descr; 2750 2751 /* 2752 * Check if this CPU has fixed function counters. 2753 */ 2754 cpu_has_iaf_counters = 0; 2755 for (t = 0; t < cpu_info.pm_nclass; t++) 2756 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && 2757 cpu_info.pm_classes[t].pm_num > 0) 2758 cpu_has_iaf_counters = 1; 2759#endif 2760 2761#define PMC_MDEP_INIT(C) do { \ 2762 pmc_mdep_event_aliases = C##_aliases; \ 2763 pmc_mdep_class_list = C##_pmc_classes; \ 2764 pmc_mdep_class_list_size = \ 2765 PMC_TABLE_SIZE(C##_pmc_classes); \ 2766 } while (0) 2767 2768#define PMC_MDEP_INIT_INTEL_V2(C) do { \ 2769 PMC_MDEP_INIT(C); \ 2770 pmc_class_table[n++] = &iaf_class_table_descr; \ 2771 if (!cpu_has_iaf_counters) \ 2772 pmc_mdep_event_aliases = \ 2773 C##_aliases_without_iaf; \ 2774 pmc_class_table[n] = &C##_class_table_descr; \ 2775 } while (0) 2776 2777 /* Configure the event name parser. */ 2778 switch (cpu_info.pm_cputype) { 2779#if defined(__i386__) 2780 case PMC_CPU_AMD_K7: 2781 PMC_MDEP_INIT(k7); 2782 pmc_class_table[n] = &k7_class_table_descr; 2783 break; 2784 case PMC_CPU_INTEL_P5: 2785 PMC_MDEP_INIT(p5); 2786 pmc_class_table[n] = &p5_class_table_descr; 2787 break; 2788 case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ 2789 case PMC_CPU_INTEL_PII: /* similar PMCs. */ 2790 case PMC_CPU_INTEL_PIII: 2791 case PMC_CPU_INTEL_PM: 2792 PMC_MDEP_INIT(p6); 2793 pmc_class_table[n] = &p6_class_table_descr; 2794 break; 2795#endif 2796#if defined(__amd64__) || defined(__i386__) 2797 case PMC_CPU_AMD_K8: 2798 PMC_MDEP_INIT(k8); 2799 pmc_class_table[n] = &k8_class_table_descr; 2800 break; 2801 case PMC_CPU_INTEL_ATOM: 2802 PMC_MDEP_INIT_INTEL_V2(atom); 2803 break; 2804 case PMC_CPU_INTEL_CORE: 2805 PMC_MDEP_INIT(core); 2806 pmc_class_table[n] = &core_class_table_descr; 2807 break; 2808 case PMC_CPU_INTEL_CORE2: 2809 case PMC_CPU_INTEL_CORE2EXTREME: 2810 PMC_MDEP_INIT_INTEL_V2(core2); 2811 break; 2812 case PMC_CPU_INTEL_COREI7: 2813 pmc_class_table[n++] = &ucf_class_table_descr; 2814 pmc_class_table[n++] = &corei7uc_class_table_descr; 2815 PMC_MDEP_INIT_INTEL_V2(corei7); 2816 break; 2817 case PMC_CPU_INTEL_WESTMERE: 2818 pmc_class_table[n++] = &ucf_class_table_descr; 2819 pmc_class_table[n++] = &westmereuc_class_table_descr; 2820 PMC_MDEP_INIT_INTEL_V2(westmere); 2821 break; 2822 case PMC_CPU_INTEL_PIV: 2823 PMC_MDEP_INIT(p4); 2824 pmc_class_table[n] = &p4_class_table_descr; 2825 break; 2826#endif 2827#if defined(__XSCALE__) 2828 case PMC_CPU_INTEL_XSCALE: 2829 PMC_MDEP_INIT(xscale); 2830 pmc_class_table[n] = &xscale_class_table_descr; 2831 break; 2832#endif 2833#if defined(__mips__) 2834 case PMC_CPU_MIPS_24K: 2835 PMC_MDEP_INIT(mips24k); 2836 pmc_class_table[n] = &mips24k_class_table_descr; 2837 break; 2838#endif /* __mips__ */ 2839#if defined(__powerpc__) 2840 case PMC_CPU_PPC_7450: 2841 PMC_MDEP_INIT(ppc7450); 2842 pmc_class_table[n] = &ppc7450_class_table_descr; 2843 break; 2844#endif 2845 default: 2846 /* 2847 * Some kind of CPU this version of the library knows nothing 2848 * about. This shouldn't happen since the abi version check 2849 * should have caught this. 2850 */ 2851 errno = ENXIO; 2852 return (pmc_syscall = -1); 2853 } 2854 2855 return (0); 2856} 2857 2858const char * 2859pmc_name_of_capability(enum pmc_caps cap) 2860{ 2861 int i; 2862 2863 /* 2864 * 'cap' should have a single bit set and should be in 2865 * range. 2866 */ 2867 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || 2868 cap > PMC_CAP_LAST) { 2869 errno = EINVAL; 2870 return (NULL); 2871 } 2872 2873 i = ffs(cap); 2874 return (pmc_capability_names[i - 1]); 2875} 2876 2877const char * 2878pmc_name_of_class(enum pmc_class pc) 2879{ 2880 if ((int) pc >= PMC_CLASS_FIRST && 2881 pc <= PMC_CLASS_LAST) 2882 return (pmc_class_names[pc]); 2883 2884 errno = EINVAL; 2885 return (NULL); 2886} 2887 2888const char * 2889pmc_name_of_cputype(enum pmc_cputype cp) 2890{ 2891 size_t n; 2892 2893 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) 2894 if (cp == pmc_cputype_names[n].pm_cputype) 2895 return (pmc_cputype_names[n].pm_name); 2896 2897 errno = EINVAL; 2898 return (NULL); 2899} 2900 2901const char * 2902pmc_name_of_disposition(enum pmc_disp pd) 2903{ 2904 if ((int) pd >= PMC_DISP_FIRST && 2905 pd <= PMC_DISP_LAST) 2906 return (pmc_disposition_names[pd]); 2907 2908 errno = EINVAL; 2909 return (NULL); 2910} 2911 2912const char * 2913_pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) 2914{ 2915 const struct pmc_event_descr *ev, *evfence; 2916 2917 ev = evfence = NULL; 2918 if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { 2919 ev = iaf_event_table; 2920 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); 2921 } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { 2922 switch (cpu) { 2923 case PMC_CPU_INTEL_ATOM: 2924 ev = atom_event_table; 2925 evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); 2926 break; 2927 case PMC_CPU_INTEL_CORE: 2928 ev = core_event_table; 2929 evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); 2930 break; 2931 case PMC_CPU_INTEL_CORE2: 2932 case PMC_CPU_INTEL_CORE2EXTREME: 2933 ev = core2_event_table; 2934 evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); 2935 break; 2936 case PMC_CPU_INTEL_COREI7: 2937 ev = corei7_event_table; 2938 evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); 2939 break; 2940 case PMC_CPU_INTEL_WESTMERE: 2941 ev = westmere_event_table; 2942 evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); 2943 break; 2944 default: /* Unknown CPU type. */ 2945 break; 2946 } 2947 } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { 2948 ev = ucf_event_table; 2949 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); 2950 } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { 2951 switch (cpu) { 2952 case PMC_CPU_INTEL_COREI7: 2953 ev = corei7uc_event_table; 2954 evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); 2955 break; 2956 case PMC_CPU_INTEL_WESTMERE: 2957 ev = westmereuc_event_table; 2958 evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); 2959 break; 2960 default: /* Unknown CPU type. */ 2961 break; 2962 } 2963 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { 2964 ev = k7_event_table; 2965 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); 2966 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { 2967 ev = k8_event_table; 2968 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); 2969 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { 2970 ev = p4_event_table; 2971 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); 2972 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { 2973 ev = p5_event_table; 2974 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); 2975 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { 2976 ev = p6_event_table; 2977 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); 2978 } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { 2979 ev = xscale_event_table; 2980 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); 2981 } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { 2982 ev = mips24k_event_table; 2983 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k 2984); 2985 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { 2986 ev = ppc7450_event_table; 2987 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450 2988); 2989 } else if (pe == PMC_EV_TSC_TSC) { 2990 ev = tsc_event_table; 2991 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); 2992 } 2993 2994 for (; ev != evfence; ev++) 2995 if (pe == ev->pm_ev_code) 2996 return (ev->pm_ev_name); 2997 2998 return (NULL); 2999} 3000 3001const char * 3002pmc_name_of_event(enum pmc_event pe) 3003{ 3004 const char *n; 3005 3006 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) 3007 return (n); 3008 3009 errno = EINVAL; 3010 return (NULL); 3011} 3012 3013const char * 3014pmc_name_of_mode(enum pmc_mode pm) 3015{ 3016 if ((int) pm >= PMC_MODE_FIRST && 3017 pm <= PMC_MODE_LAST) 3018 return (pmc_mode_names[pm]); 3019 3020 errno = EINVAL; 3021 return (NULL); 3022} 3023 3024const char * 3025pmc_name_of_state(enum pmc_state ps) 3026{ 3027 if ((int) ps >= PMC_STATE_FIRST && 3028 ps <= PMC_STATE_LAST) 3029 return (pmc_state_names[ps]); 3030 3031 errno = EINVAL; 3032 return (NULL); 3033} 3034 3035int 3036pmc_ncpu(void) 3037{ 3038 if (pmc_syscall == -1) { 3039 errno = ENXIO; 3040 return (-1); 3041 } 3042 3043 return (cpu_info.pm_ncpu); 3044} 3045 3046int 3047pmc_npmc(int cpu) 3048{ 3049 if (pmc_syscall == -1) { 3050 errno = ENXIO; 3051 return (-1); 3052 } 3053 3054 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { 3055 errno = EINVAL; 3056 return (-1); 3057 } 3058 3059 return (cpu_info.pm_npmc); 3060} 3061 3062int 3063pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) 3064{ 3065 int nbytes, npmc; 3066 struct pmc_op_getpmcinfo *pmci; 3067 3068 if ((npmc = pmc_npmc(cpu)) < 0) 3069 return (-1); 3070 3071 nbytes = sizeof(struct pmc_op_getpmcinfo) + 3072 npmc * sizeof(struct pmc_info); 3073 3074 if ((pmci = calloc(1, nbytes)) == NULL) 3075 return (-1); 3076 3077 pmci->pm_cpu = cpu; 3078 3079 if (PMC_CALL(GETPMCINFO, pmci) < 0) { 3080 free(pmci); 3081 return (-1); 3082 } 3083 3084 /* kernel<->library, library<->userland interfaces are identical */ 3085 *ppmci = (struct pmc_pmcinfo *) pmci; 3086 return (0); 3087} 3088 3089int 3090pmc_read(pmc_id_t pmc, pmc_value_t *value) 3091{ 3092 struct pmc_op_pmcrw pmc_read_op; 3093 3094 pmc_read_op.pm_pmcid = pmc; 3095 pmc_read_op.pm_flags = PMC_F_OLDVALUE; 3096 pmc_read_op.pm_value = -1; 3097 3098 if (PMC_CALL(PMCRW, &pmc_read_op) < 0) 3099 return (-1); 3100 3101 *value = pmc_read_op.pm_value; 3102 return (0); 3103} 3104 3105int 3106pmc_release(pmc_id_t pmc) 3107{ 3108 struct pmc_op_simple pmc_release_args; 3109 3110 pmc_release_args.pm_pmcid = pmc; 3111 return (PMC_CALL(PMCRELEASE, &pmc_release_args)); 3112} 3113 3114int 3115pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) 3116{ 3117 struct pmc_op_pmcrw pmc_rw_op; 3118 3119 pmc_rw_op.pm_pmcid = pmc; 3120 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; 3121 pmc_rw_op.pm_value = newvalue; 3122 3123 if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) 3124 return (-1); 3125 3126 *oldvaluep = pmc_rw_op.pm_value; 3127 return (0); 3128} 3129 3130int 3131pmc_set(pmc_id_t pmc, pmc_value_t value) 3132{ 3133 struct pmc_op_pmcsetcount sc; 3134 3135 sc.pm_pmcid = pmc; 3136 sc.pm_count = value; 3137 3138 if (PMC_CALL(PMCSETCOUNT, &sc) < 0) 3139 return (-1); 3140 return (0); 3141} 3142 3143int 3144pmc_start(pmc_id_t pmc) 3145{ 3146 struct pmc_op_simple pmc_start_args; 3147 3148 pmc_start_args.pm_pmcid = pmc; 3149 return (PMC_CALL(PMCSTART, &pmc_start_args)); 3150} 3151 3152int 3153pmc_stop(pmc_id_t pmc) 3154{ 3155 struct pmc_op_simple pmc_stop_args; 3156 3157 pmc_stop_args.pm_pmcid = pmc; 3158 return (PMC_CALL(PMCSTOP, &pmc_stop_args)); 3159} 3160 3161int 3162pmc_width(pmc_id_t pmcid, uint32_t *width) 3163{ 3164 unsigned int i; 3165 enum pmc_class cl; 3166 3167 cl = PMC_ID_TO_CLASS(pmcid); 3168 for (i = 0; i < cpu_info.pm_nclass; i++) 3169 if (cpu_info.pm_classes[i].pm_class == cl) { 3170 *width = cpu_info.pm_classes[i].pm_width; 3171 return (0); 3172 } 3173 errno = EINVAL; 3174 return (-1); 3175} 3176 3177int 3178pmc_write(pmc_id_t pmc, pmc_value_t value) 3179{ 3180 struct pmc_op_pmcrw pmc_write_op; 3181 3182 pmc_write_op.pm_pmcid = pmc; 3183 pmc_write_op.pm_flags = PMC_F_NEWVALUE; 3184 pmc_write_op.pm_value = value; 3185 return (PMC_CALL(PMCRW, &pmc_write_op)); 3186} 3187 3188int 3189pmc_writelog(uint32_t userdata) 3190{ 3191 struct pmc_op_writelog wl; 3192 3193 wl.pm_userdata = userdata; 3194 return (PMC_CALL(WRITELOG, &wl)); 3195} 3196