fpu_mul.c revision 92986
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_mul.c 8.1 (Berkeley) 6/11/93 43 * $NetBSD: fpu_mul.c,v 1.2 1994/11/20 20:52:44 deraadt Exp $ 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: head/lib/libc/sparc64/fpu/fpu_mul.c 92986 2002-03-22 21:53:29Z obrien $"); 48 49/* 50 * Perform an FPU multiply (return x * y). 51 */ 52 53#include <sys/types.h> 54 55#include <machine/frame.h> 56#include <machine/fp.h> 57 58#include "fpu_arith.h" 59#include "fpu_emu.h" 60#include "fpu_extern.h" 61 62/* 63 * The multiplication algorithm for normal numbers is as follows: 64 * 65 * The fraction of the product is built in the usual stepwise fashion. 66 * Each step consists of shifting the accumulator right one bit 67 * (maintaining any guard bits) and, if the next bit in y is set, 68 * adding the multiplicand (x) to the accumulator. Then, in any case, 69 * we advance one bit leftward in y. Algorithmically: 70 * 71 * A = 0; 72 * for (bit = 0; bit < FP_NMANT; bit++) { 73 * sticky |= A & 1, A >>= 1; 74 * if (Y & (1 << bit)) 75 * A += X; 76 * } 77 * 78 * (X and Y here represent the mantissas of x and y respectively.) 79 * The resultant accumulator (A) is the product's mantissa. It may 80 * be as large as 11.11111... in binary and hence may need to be 81 * shifted right, but at most one bit. 82 * 83 * Since we do not have efficient multiword arithmetic, we code the 84 * accumulator as four separate words, just like any other mantissa. 85 * We use local `register' variables in the hope that this is faster 86 * than memory. We keep x->fp_mant in locals for the same reason. 87 * 88 * In the algorithm above, the bits in y are inspected one at a time. 89 * We will pick them up 32 at a time and then deal with those 32, one 90 * at a time. Note, however, that we know several things about y: 91 * 92 * - the guard and round bits at the bottom are sure to be zero; 93 * 94 * - often many low bits are zero (y is often from a single or double 95 * precision source); 96 * 97 * - bit FP_NMANT-1 is set, and FP_1*2 fits in a word. 98 * 99 * We can also test for 32-zero-bits swiftly. In this case, the center 100 * part of the loop---setting sticky, shifting A, and not adding---will 101 * run 32 times without adding X to A. We can do a 32-bit shift faster 102 * by simply moving words. Since zeros are common, we optimize this case. 103 * Furthermore, since A is initially zero, we can omit the shift as well 104 * until we reach a nonzero word. 105 */ 106struct fpn * 107__fpu_mul(fe) 108 struct fpemu *fe; 109{ 110 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 111 u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m; 112 int sticky; 113 FPU_DECL_CARRY 114 115 /* 116 * Put the `heavier' operand on the right (see fpu_emu.h). 117 * Then we will have one of the following cases, taken in the 118 * following order: 119 * 120 * - y = NaN. Implied: if only one is a signalling NaN, y is. 121 * The result is y. 122 * - y = Inf. Implied: x != NaN (is 0, number, or Inf: the NaN 123 * case was taken care of earlier). 124 * If x = 0, the result is NaN. Otherwise the result 125 * is y, with its sign reversed if x is negative. 126 * - x = 0. Implied: y is 0 or number. 127 * The result is 0 (with XORed sign as usual). 128 * - other. Implied: both x and y are numbers. 129 * The result is x * y (XOR sign, multiply bits, add exponents). 130 */ 131 ORDER(x, y); 132 if (ISNAN(y)) { 133 y->fp_sign ^= x->fp_sign; 134 return (y); 135 } 136 if (ISINF(y)) { 137 if (ISZERO(x)) 138 return (__fpu_newnan(fe)); 139 y->fp_sign ^= x->fp_sign; 140 return (y); 141 } 142 if (ISZERO(x)) { 143 x->fp_sign ^= y->fp_sign; 144 return (x); 145 } 146 147 /* 148 * Setup. In the code below, the mask `m' will hold the current 149 * mantissa byte from y. The variable `bit' denotes the bit 150 * within m. We also define some macros to deal with everything. 151 */ 152 x3 = x->fp_mant[3]; 153 x2 = x->fp_mant[2]; 154 x1 = x->fp_mant[1]; 155 x0 = x->fp_mant[0]; 156 sticky = a3 = a2 = a1 = a0 = 0; 157 158#define ADD /* A += X */ \ 159 FPU_ADDS(a3, a3, x3); \ 160 FPU_ADDCS(a2, a2, x2); \ 161 FPU_ADDCS(a1, a1, x1); \ 162 FPU_ADDC(a0, a0, x0) 163 164#define SHR1 /* A >>= 1, with sticky */ \ 165 sticky |= a3 & 1, a3 = (a3 >> 1) | (a2 << 31), \ 166 a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 167 168#define SHR32 /* A >>= 32, with sticky */ \ 169 sticky |= a3, a3 = a2, a2 = a1, a1 = a0, a0 = 0 170 171#define STEP /* each 1-bit step of the multiplication */ \ 172 SHR1; if (bit & m) { ADD; }; bit <<= 1 173 174 /* 175 * We are ready to begin. The multiply loop runs once for each 176 * of the four 32-bit words. Some words, however, are special. 177 * As noted above, the low order bits of Y are often zero. Even 178 * if not, the first loop can certainly skip the guard bits. 179 * The last word of y has its highest 1-bit in position FP_NMANT-1, 180 * so we stop the loop when we move past that bit. 181 */ 182 if ((m = y->fp_mant[3]) == 0) { 183 /* SHR32; */ /* unneeded since A==0 */ 184 } else { 185 bit = 1 << FP_NG; 186 do { 187 STEP; 188 } while (bit != 0); 189 } 190 if ((m = y->fp_mant[2]) == 0) { 191 SHR32; 192 } else { 193 bit = 1; 194 do { 195 STEP; 196 } while (bit != 0); 197 } 198 if ((m = y->fp_mant[1]) == 0) { 199 SHR32; 200 } else { 201 bit = 1; 202 do { 203 STEP; 204 } while (bit != 0); 205 } 206 m = y->fp_mant[0]; /* definitely != 0 */ 207 bit = 1; 208 do { 209 STEP; 210 } while (bit <= m); 211 212 /* 213 * Done with mantissa calculation. Get exponent and handle 214 * 11.111...1 case, then put result in place. We reuse x since 215 * it already has the right class (FP_NUM). 216 */ 217 m = x->fp_exp + y->fp_exp; 218 if (a0 >= FP_2) { 219 SHR1; 220 m++; 221 } 222 x->fp_sign ^= y->fp_sign; 223 x->fp_exp = m; 224 x->fp_sticky = sticky; 225 x->fp_mant[3] = a3; 226 x->fp_mant[2] = a2; 227 x->fp_mant[1] = a1; 228 x->fp_mant[0] = a0; 229 return (x); 230} 231