fpu_implode.c revision 92889
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 43 * from: NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp 44 * 45 * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_implode.c 92889 2002-03-21 18:49:23Z obrien $ 46 */ 47 48/* 49 * FPU subroutines: `implode' internal format numbers into the machine's 50 * `packed binary' format. 51 */ 52 53#include <sys/param.h> 54 55#include <machine/frame.h> 56#include <machine/fp.h> 57#include <machine/fsr.h> 58#include <machine/ieee.h> 59#include <machine/instr.h> 60 61#include "fpu_arith.h" 62#include "fpu_emu.h" 63#include "fpu_extern.h" 64 65static int round __P((struct fpemu *, struct fpn *)); 66static int toinf __P((struct fpemu *, int)); 67 68/* 69 * Round a number (algorithm from Motorola MC68882 manual, modified for 70 * our internal format). Set inexact exception if rounding is required. 71 * Return true iff we rounded up. 72 * 73 * After rounding, we discard the guard and round bits by shifting right 74 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 75 * This saves effort later. 76 * 77 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 78 * responsibility to fix this if necessary. 79 */ 80static int 81round(struct fpemu *fe, struct fpn *fp) 82{ 83 u_int m0, m1, m2, m3; 84 int gr, s; 85 86 m0 = fp->fp_mant[0]; 87 m1 = fp->fp_mant[1]; 88 m2 = fp->fp_mant[2]; 89 m3 = fp->fp_mant[3]; 90 gr = m3 & 3; 91 s = fp->fp_sticky; 92 93 /* mant >>= FP_NG */ 94 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 95 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 96 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 97 m0 >>= FP_NG; 98 99 if ((gr | s) == 0) /* result is exact: no rounding needed */ 100 goto rounddown; 101 102 fe->fe_cx |= FSR_NX; /* inexact */ 103 104 /* Go to rounddown to round down; break to round up. */ 105 switch (FSR_GET_RD(fe->fe_fsr)) { 106 case FSR_RD_N: 107 default: 108 /* 109 * Round only if guard is set (gr & 2). If guard is set, 110 * but round & sticky both clear, then we want to round 111 * but have a tie, so round to even, i.e., add 1 iff odd. 112 */ 113 if ((gr & 2) == 0) 114 goto rounddown; 115 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 116 break; 117 goto rounddown; 118 119 case FSR_RD_Z: 120 /* Round towards zero, i.e., down. */ 121 goto rounddown; 122 123 case FSR_RD_NINF: 124 /* Round towards -Inf: up if negative, down if positive. */ 125 if (fp->fp_sign) 126 break; 127 goto rounddown; 128 129 case FSR_RD_PINF: 130 /* Round towards +Inf: up if positive, down otherwise. */ 131 if (!fp->fp_sign) 132 break; 133 goto rounddown; 134 } 135 136 /* Bump low bit of mantissa, with carry. */ 137 FPU_ADDS(m3, m3, 1); 138 FPU_ADDCS(m2, m2, 0); 139 FPU_ADDCS(m1, m1, 0); 140 FPU_ADDC(m0, m0, 0); 141 fp->fp_mant[0] = m0; 142 fp->fp_mant[1] = m1; 143 fp->fp_mant[2] = m2; 144 fp->fp_mant[3] = m3; 145 return (1); 146 147rounddown: 148 fp->fp_mant[0] = m0; 149 fp->fp_mant[1] = m1; 150 fp->fp_mant[2] = m2; 151 fp->fp_mant[3] = m3; 152 return (0); 153} 154 155/* 156 * For overflow: return true if overflow is to go to +/-Inf, according 157 * to the sign of the overflowing result. If false, overflow is to go 158 * to the largest magnitude value instead. 159 */ 160static int 161toinf(struct fpemu *fe, int sign) 162{ 163 int inf; 164 165 /* look at rounding direction */ 166 switch (FSR_GET_RD(fe->fe_fsr)) { 167 default: 168 case FSR_RD_N: /* the nearest value is always Inf */ 169 inf = 1; 170 break; 171 172 case FSR_RD_Z: /* toward 0 => never towards Inf */ 173 inf = 0; 174 break; 175 176 case FSR_RD_PINF: /* toward +Inf iff positive */ 177 inf = sign == 0; 178 break; 179 180 case FSR_RD_NINF: /* toward -Inf iff negative */ 181 inf = sign; 182 break; 183 } 184 return (inf); 185} 186 187/* 188 * fpn -> int (int value returned as return value). 189 * 190 * N.B.: this conversion always rounds towards zero (this is a peculiarity 191 * of the SPARC instruction set). 192 */ 193u_int 194__fpu_ftoi(fe, fp) 195 struct fpemu *fe; 196 struct fpn *fp; 197{ 198 u_int i; 199 int sign, exp; 200 201 sign = fp->fp_sign; 202 switch (fp->fp_class) { 203 204 case FPC_ZERO: 205 return (0); 206 207 case FPC_NUM: 208 /* 209 * If exp >= 2^32, overflow. Otherwise shift value right 210 * into last mantissa word (this will not exceed 0xffffffff), 211 * shifting any guard and round bits out into the sticky 212 * bit. Then ``round'' towards zero, i.e., just set an 213 * inexact exception if sticky is set (see round()). 214 * If the result is > 0x80000000, or is positive and equals 215 * 0x80000000, overflow; otherwise the last fraction word 216 * is the result. 217 */ 218 if ((exp = fp->fp_exp) >= 32) 219 break; 220 /* NB: the following includes exp < 0 cases */ 221 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 222 fe->fe_cx |= FSR_NX; 223 i = fp->fp_mant[3]; 224 if (i >= ((u_int)0x80000000 + sign)) 225 break; 226 return (sign ? -i : i); 227 228 default: /* Inf, qNaN, sNaN */ 229 break; 230 } 231 /* overflow: replace any inexact exception with invalid */ 232 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 233 return (0x7fffffff + sign); 234} 235 236/* 237 * fpn -> extended int (high bits of int value returned as return value). 238 * 239 * N.B.: this conversion always rounds towards zero (this is a peculiarity 240 * of the SPARC instruction set). 241 */ 242u_int 243__fpu_ftox(fe, fp, res) 244 struct fpemu *fe; 245 struct fpn *fp; 246 u_int *res; 247{ 248 u_int64_t i; 249 int sign, exp; 250 251 sign = fp->fp_sign; 252 switch (fp->fp_class) { 253 254 case FPC_ZERO: 255 res[1] = 0; 256 return (0); 257 258 case FPC_NUM: 259 /* 260 * If exp >= 2^64, overflow. Otherwise shift value right 261 * into last mantissa word (this will not exceed 0xffffffffffffffff), 262 * shifting any guard and round bits out into the sticky 263 * bit. Then ``round'' towards zero, i.e., just set an 264 * inexact exception if sticky is set (see round()). 265 * If the result is > 0x8000000000000000, or is positive and equals 266 * 0x8000000000000000, overflow; otherwise the last fraction word 267 * is the result. 268 */ 269 if ((exp = fp->fp_exp) >= 64) 270 break; 271 /* NB: the following includes exp < 0 cases */ 272 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 273 fe->fe_cx |= FSR_NX; 274 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 275 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 276 break; 277 if (sign) 278 i = -1; 279 res[1] = (int)i; 280 return (i >> 32); 281 282 default: /* Inf, qNaN, sNaN */ 283 break; 284 } 285 /* overflow: replace any inexact exception with invalid */ 286 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 287 return (0x7fffffffffffffffLL + sign); 288} 289 290/* 291 * fpn -> single (32 bit single returned as return value). 292 * We assume <= 29 bits in a single-precision fraction (1.f part). 293 */ 294u_int 295__fpu_ftos(fe, fp) 296 struct fpemu *fe; 297 struct fpn *fp; 298{ 299 u_int sign = fp->fp_sign << 31; 300 int exp; 301 302#define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 303#define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 304 305 /* Take care of non-numbers first. */ 306 if (ISNAN(fp)) { 307 /* 308 * Preserve upper bits of NaN, per SPARC V8 appendix N. 309 * Note that fp->fp_mant[0] has the quiet bit set, 310 * even if it is classified as a signalling NaN. 311 */ 312 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 313 exp = SNG_EXP_INFNAN; 314 goto done; 315 } 316 if (ISINF(fp)) 317 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 318 if (ISZERO(fp)) 319 return (sign); 320 321 /* 322 * Normals (including subnormals). Drop all the fraction bits 323 * (including the explicit ``implied'' 1 bit) down into the 324 * single-precision range. If the number is subnormal, move 325 * the ``implied'' 1 into the explicit range as well, and shift 326 * right to introduce leading zeroes. Rounding then acts 327 * differently for normals and subnormals: the largest subnormal 328 * may round to the smallest normal (1.0 x 2^minexp), or may 329 * remain subnormal. In the latter case, signal an underflow 330 * if the result was inexact or if underflow traps are enabled. 331 * 332 * Rounding a normal, on the other hand, always produces another 333 * normal (although either way the result might be too big for 334 * single precision, and cause an overflow). If rounding a 335 * normal produces 2.0 in the fraction, we need not adjust that 336 * fraction at all, since both 1.0 and 2.0 are zero under the 337 * fraction mask. 338 * 339 * Note that the guard and round bits vanish from the number after 340 * rounding. 341 */ 342 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 343 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 344 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 345 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 346 return (sign | SNG_EXP(1) | 0); 347 if ((fe->fe_cx & FSR_NX) || 348 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 349 fe->fe_cx |= FSR_UF; 350 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 351 } 352 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 353 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 354#ifdef DIAGNOSTIC 355 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 356 __fpu_panic("fpu_ftos"); 357#endif 358 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 359 exp++; 360 if (exp >= SNG_EXP_INFNAN) { 361 /* overflow to inf or to max single */ 362 fe->fe_cx |= FSR_OF | FSR_NX; 363 if (toinf(fe, sign)) 364 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 365 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 366 } 367done: 368 /* phew, made it */ 369 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 370} 371 372/* 373 * fpn -> double (32 bit high-order result returned; 32-bit low order result 374 * left in res[1]). Assumes <= 61 bits in double precision fraction. 375 * 376 * This code mimics fpu_ftos; see it for comments. 377 */ 378u_int 379__fpu_ftod(fe, fp, res) 380 struct fpemu *fe; 381 struct fpn *fp; 382 u_int *res; 383{ 384 u_int sign = fp->fp_sign << 31; 385 int exp; 386 387#define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 388#define DBL_MASK (DBL_EXP(1) - 1) 389 390 if (ISNAN(fp)) { 391 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 392 exp = DBL_EXP_INFNAN; 393 goto done; 394 } 395 if (ISINF(fp)) { 396 sign |= DBL_EXP(DBL_EXP_INFNAN); 397 goto zero; 398 } 399 if (ISZERO(fp)) { 400zero: res[1] = 0; 401 return (sign); 402 } 403 404 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 405 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 406 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 407 res[1] = 0; 408 return (sign | DBL_EXP(1) | 0); 409 } 410 if ((fe->fe_cx & FSR_NX) || 411 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 412 fe->fe_cx |= FSR_UF; 413 exp = 0; 414 goto done; 415 } 416 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 417 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 418 exp++; 419 if (exp >= DBL_EXP_INFNAN) { 420 fe->fe_cx |= FSR_OF | FSR_NX; 421 if (toinf(fe, sign)) { 422 res[1] = 0; 423 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 424 } 425 res[1] = ~0; 426 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 427 } 428done: 429 res[1] = fp->fp_mant[3]; 430 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 431} 432 433/* 434 * fpn -> extended (32 bit high-order result returned; low-order fraction 435 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 436 * our internal format *is* extended precision, plus 2 bits for guard/round, 437 * so we can avoid a small bit of work. 438 */ 439u_int 440__fpu_ftoq(fe, fp, res) 441 struct fpemu *fe; 442 struct fpn *fp; 443 u_int *res; 444{ 445 u_int sign = fp->fp_sign << 31; 446 int exp; 447 448#define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 449#define EXT_MASK (EXT_EXP(1) - 1) 450 451 if (ISNAN(fp)) { 452 (void) __fpu_shr(fp, 2); /* since we are not rounding */ 453 exp = EXT_EXP_INFNAN; 454 goto done; 455 } 456 if (ISINF(fp)) { 457 sign |= EXT_EXP(EXT_EXP_INFNAN); 458 goto zero; 459 } 460 if (ISZERO(fp)) { 461zero: res[1] = res[2] = res[3] = 0; 462 return (sign); 463 } 464 465 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 466 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 467 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 468 res[1] = res[2] = res[3] = 0; 469 return (sign | EXT_EXP(1) | 0); 470 } 471 if ((fe->fe_cx & FSR_NX) || 472 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 473 fe->fe_cx |= FSR_UF; 474 exp = 0; 475 goto done; 476 } 477 /* Since internal == extended, no need to shift here. */ 478 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 479 exp++; 480 if (exp >= EXT_EXP_INFNAN) { 481 fe->fe_cx |= FSR_OF | FSR_NX; 482 if (toinf(fe, sign)) { 483 res[1] = res[2] = res[3] = 0; 484 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 485 } 486 res[1] = res[2] = res[3] = ~0; 487 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 488 } 489done: 490 res[1] = fp->fp_mant[1]; 491 res[2] = fp->fp_mant[2]; 492 res[3] = fp->fp_mant[3]; 493 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 494} 495 496/* 497 * Implode an fpn, writing the result into the given space. 498 */ 499void 500__fpu_implode(fe, fp, type, space) 501 struct fpemu *fe; 502 struct fpn *fp; 503 int type; 504 u_int *space; 505{ 506 507 switch (type) { 508 509 case FTYPE_LNG: 510 space[0] = __fpu_ftox(fe, fp, space); 511 break; 512 513 case FTYPE_INT: 514 space[0] = __fpu_ftoi(fe, fp); 515 break; 516 517 case FTYPE_SNG: 518 space[0] = __fpu_ftos(fe, fp); 519 break; 520 521 case FTYPE_DBL: 522 space[0] = __fpu_ftod(fe, fp, space); 523 break; 524 525 case FTYPE_EXT: 526 /* funky rounding precision options ?? */ 527 space[0] = __fpu_ftoq(fe, fp, space); 528 break; 529 530 default: 531 __fpu_panic("fpu_implode"); 532 } 533 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n", 534 space[0], space[1], space[2], space[3])); 535} 536