OPENSSL_ia32cap.pod revision 306195 
1=pod
2
3=head1 NAME
4
5OPENSSL_ia32cap, OPENSSL_ia32cap_loc - the IA-32 processor capabilities vector
6
7=head1 SYNOPSIS
8
9 unsigned long *OPENSSL_ia32cap_loc(void);
10 #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
11
12=head1 DESCRIPTION
13
14Value returned by OPENSSL_ia32cap_loc() is address of a variable
15containing IA-32 processor capabilities bit vector as it appears in
16EDX:ECX register pair after executing CPUID instruction with EAX=1
17input value (see Intel Application Note #241618). Naturally it's
18meaningful on x86 and x86_64 platforms only. The variable is normally
19set up automatically upon toolkit initialization, but can be
20manipulated afterwards to modify crypto library behaviour. For the
21moment of this writing following bits are significant:
22
23=over
24
25=item bit #4 denoting presence of Time-Stamp Counter.
26
27=item bit #19 denoting availability of CLFLUSH instruction;
28
29=item bit #20, reserved by Intel, is used to choose among RC4 code paths;
30
31=item bit #23 denoting MMX support;
32
33=item bit #24, FXSR bit, denoting availability of XMM registers;
34
35=item bit #25 denoting SSE support;
36
37=item bit #26 denoting SSE2 support;
38
39=item bit #28 denoting Hyperthreading, which is used to distinguish
40cores with shared cache;
41
42=item bit #30, reserved by Intel, denotes specifically Intel CPUs;
43
44=item bit #33 denoting availability of PCLMULQDQ instruction;
45
46=item bit #41 denoting SSSE3, Supplemental SSE3, support;
47
48=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
49
50=item bit #57 denoting AES-NI instruction set extension;
51
52=item bit #59, OSXSAVE bit, denoting availability of YMM registers;
53
54=item bit #60 denoting AVX extension;
55
56=item bit #62 denoting availability of RDRAND instruction;
57
58=back
59
60For example, clearing bit #26 at run-time disables high-performance
61SSE2 code present in the crypto library, while clearing bit #24
62disables SSE2 code operating on 128-bit XMM register bank. You might
63have to do the latter if target OpenSSL application is executed on SSE2
64capable CPU, but under control of OS that does not enable XMM
65registers. Even though you can manipulate the value programmatically,
66you most likely will find it more appropriate to set up an environment
67variable with the same name prior starting target application, e.g. on
68Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or
69better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same
70effect without modifying the application source code. Alternatively you
71can reconfigure the toolkit with no-sse2 option and recompile.
72
73Less intuitive is clearing bit #28. The truth is that it's not copied
74from CPUID output verbatim, but is adjusted to reflect whether or not
75the data cache is actually shared between logical cores. This in turn
76affects the decision on whether or not expensive countermeasures
77against cache-timing attacks are applied, most notably in AES assembler
78module.
79
80The vector is further extended with EBX value returned by CPUID with
81EAX=7 and ECX=0 as input. Following bits are significant:
82
83=over
84
85=item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
86
87=item bit #64+5 denoting availability of AVX2 instructions;
88
89=item bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL
90and RORX;
91
92=item bit #64+18 denoting availability of RDSEED instruction;
93
94=item bit #64+19 denoting availability of ADCX and ADOX instructions;
95
96=back
97