t4fw_ri_api.h revision 331769
1/* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31#ifndef _T4FW_RI_API_H_ 32#define _T4FW_RI_API_H_ 33 34#include "t4fw_api.h" 35 36enum fw_ri_wr_opcode { 37 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 38 FW_RI_READ_REQ = 0x1, 39 FW_RI_READ_RESP = 0x2, 40 FW_RI_SEND = 0x3, 41 FW_RI_SEND_WITH_INV = 0x4, 42 FW_RI_SEND_WITH_SE = 0x5, 43 FW_RI_SEND_WITH_SE_INV = 0x6, 44 FW_RI_TERMINATE = 0x7, 45 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 46 FW_RI_BIND_MW = 0x9, 47 FW_RI_FAST_REGISTER = 0xa, 48 FW_RI_LOCAL_INV = 0xb, 49 FW_RI_QP_MODIFY = 0xc, 50 FW_RI_BYPASS = 0xd, 51 FW_RI_RECEIVE = 0xe, 52 53 FW_RI_SGE_EC_CR_RETURN = 0xf 54}; 55 56enum fw_ri_wr_flags { 57 FW_RI_COMPLETION_FLAG = 0x01, 58 FW_RI_NOTIFICATION_FLAG = 0x02, 59 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 60 FW_RI_READ_FENCE_FLAG = 0x08, 61 FW_RI_LOCAL_FENCE_FLAG = 0x10, 62 FW_RI_RDMA_READ_INVALIDATE = 0x20 63}; 64 65enum fw_ri_mpa_attrs { 66 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 67 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 68 FW_RI_MPA_CRC_ENABLE = 0x04, 69 FW_RI_MPA_IETF_ENABLE = 0x08 70}; 71 72enum fw_ri_qp_caps { 73 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 74 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 75 FW_RI_QP_BIND_ENABLE = 0x04, 76 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 77 FW_RI_QP_STAG0_ENABLE = 0x10 78}; 79 80enum fw_ri_addr_type { 81 FW_RI_ZERO_BASED_TO = 0x00, 82 FW_RI_VA_BASED_TO = 0x01 83}; 84 85enum fw_ri_mem_perms { 86 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 87 FW_RI_MEM_ACCESS_REM_READ = 0x02, 88 FW_RI_MEM_ACCESS_REM = 0x03, 89 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 90 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 91 FW_RI_MEM_ACCESS_LOCAL = 0x0C 92}; 93 94enum fw_ri_stag_type { 95 FW_RI_STAG_NSMR = 0x00, 96 FW_RI_STAG_SMR = 0x01, 97 FW_RI_STAG_MW = 0x02, 98 FW_RI_STAG_MW_RELAXED = 0x03 99}; 100 101enum fw_ri_data_op { 102 FW_RI_DATA_IMMD = 0x81, 103 FW_RI_DATA_DSGL = 0x82, 104 FW_RI_DATA_ISGL = 0x83 105}; 106 107enum fw_ri_sgl_depth { 108 FW_RI_SGL_DEPTH_MAX_SQ = 16, 109 FW_RI_SGL_DEPTH_MAX_RQ = 4 110}; 111 112struct fw_ri_dsge_pair { 113 __be32 len[2]; 114 __be64 addr[2]; 115}; 116 117struct fw_ri_dsgl { 118 __u8 op; 119 __u8 r1; 120 __be16 nsge; 121 __be32 len0; 122 __be64 addr0; 123#ifndef C99_NOT_SUPPORTED 124 struct fw_ri_dsge_pair sge[0]; 125#endif 126}; 127 128struct fw_ri_sge { 129 __be32 stag; 130 __be32 len; 131 __be64 to; 132}; 133 134struct fw_ri_isgl { 135 __u8 op; 136 __u8 r1; 137 __be16 nsge; 138 __be32 r2; 139#ifndef C99_NOT_SUPPORTED 140 struct fw_ri_sge sge[0]; 141#endif 142}; 143 144struct fw_ri_immd { 145 __u8 op; 146 __u8 r1; 147 __be16 r2; 148 __be32 immdlen; 149#ifndef C99_NOT_SUPPORTED 150 __u8 data[0]; 151#endif 152}; 153 154struct fw_ri_tpte { 155 __be32 valid_to_pdid; 156 __be32 locread_to_qpid; 157 __be32 nosnoop_pbladdr; 158 __be32 len_lo; 159 __be32 va_hi; 160 __be32 va_lo_fbo; 161 __be32 dca_mwbcnt_pstag; 162 __be32 len_hi; 163}; 164 165#define FW_RI_TPTE_VALID_S 31 166#define FW_RI_TPTE_VALID_M 0x1 167#define FW_RI_TPTE_VALID_V(x) ((x) << FW_RI_TPTE_VALID_S) 168#define FW_RI_TPTE_VALID_G(x) \ 169 (((x) >> FW_RI_TPTE_VALID_S) & FW_RI_TPTE_VALID_M) 170#define FW_RI_TPTE_VALID_F FW_RI_TPTE_VALID_V(1U) 171 172#define FW_RI_TPTE_STAGKEY_S 23 173#define FW_RI_TPTE_STAGKEY_M 0xff 174#define FW_RI_TPTE_STAGKEY_V(x) ((x) << FW_RI_TPTE_STAGKEY_S) 175#define FW_RI_TPTE_STAGKEY_G(x) \ 176 (((x) >> FW_RI_TPTE_STAGKEY_S) & FW_RI_TPTE_STAGKEY_M) 177 178#define FW_RI_TPTE_STAGSTATE_S 22 179#define FW_RI_TPTE_STAGSTATE_M 0x1 180#define FW_RI_TPTE_STAGSTATE_V(x) ((x) << FW_RI_TPTE_STAGSTATE_S) 181#define FW_RI_TPTE_STAGSTATE_G(x) \ 182 (((x) >> FW_RI_TPTE_STAGSTATE_S) & FW_RI_TPTE_STAGSTATE_M) 183#define FW_RI_TPTE_STAGSTATE_F FW_RI_TPTE_STAGSTATE_V(1U) 184 185#define FW_RI_TPTE_STAGTYPE_S 20 186#define FW_RI_TPTE_STAGTYPE_M 0x3 187#define FW_RI_TPTE_STAGTYPE_V(x) ((x) << FW_RI_TPTE_STAGTYPE_S) 188#define FW_RI_TPTE_STAGTYPE_G(x) \ 189 (((x) >> FW_RI_TPTE_STAGTYPE_S) & FW_RI_TPTE_STAGTYPE_M) 190 191#define FW_RI_TPTE_PDID_S 0 192#define FW_RI_TPTE_PDID_M 0xfffff 193#define FW_RI_TPTE_PDID_V(x) ((x) << FW_RI_TPTE_PDID_S) 194#define FW_RI_TPTE_PDID_G(x) \ 195 (((x) >> FW_RI_TPTE_PDID_S) & FW_RI_TPTE_PDID_M) 196 197#define FW_RI_TPTE_PERM_S 28 198#define FW_RI_TPTE_PERM_M 0xf 199#define FW_RI_TPTE_PERM_V(x) ((x) << FW_RI_TPTE_PERM_S) 200#define FW_RI_TPTE_PERM_G(x) \ 201 (((x) >> FW_RI_TPTE_PERM_S) & FW_RI_TPTE_PERM_M) 202 203#define FW_RI_TPTE_REMINVDIS_S 27 204#define FW_RI_TPTE_REMINVDIS_M 0x1 205#define FW_RI_TPTE_REMINVDIS_V(x) ((x) << FW_RI_TPTE_REMINVDIS_S) 206#define FW_RI_TPTE_REMINVDIS_G(x) \ 207 (((x) >> FW_RI_TPTE_REMINVDIS_S) & FW_RI_TPTE_REMINVDIS_M) 208#define FW_RI_TPTE_REMINVDIS_F FW_RI_TPTE_REMINVDIS_V(1U) 209 210#define FW_RI_TPTE_ADDRTYPE_S 26 211#define FW_RI_TPTE_ADDRTYPE_M 1 212#define FW_RI_TPTE_ADDRTYPE_V(x) ((x) << FW_RI_TPTE_ADDRTYPE_S) 213#define FW_RI_TPTE_ADDRTYPE_G(x) \ 214 (((x) >> FW_RI_TPTE_ADDRTYPE_S) & FW_RI_TPTE_ADDRTYPE_M) 215#define FW_RI_TPTE_ADDRTYPE_F FW_RI_TPTE_ADDRTYPE_V(1U) 216 217#define FW_RI_TPTE_MWBINDEN_S 25 218#define FW_RI_TPTE_MWBINDEN_M 0x1 219#define FW_RI_TPTE_MWBINDEN_V(x) ((x) << FW_RI_TPTE_MWBINDEN_S) 220#define FW_RI_TPTE_MWBINDEN_G(x) \ 221 (((x) >> FW_RI_TPTE_MWBINDEN_S) & FW_RI_TPTE_MWBINDEN_M) 222#define FW_RI_TPTE_MWBINDEN_F FW_RI_TPTE_MWBINDEN_V(1U) 223 224#define FW_RI_TPTE_PS_S 20 225#define FW_RI_TPTE_PS_M 0x1f 226#define FW_RI_TPTE_PS_V(x) ((x) << FW_RI_TPTE_PS_S) 227#define FW_RI_TPTE_PS_G(x) \ 228 (((x) >> FW_RI_TPTE_PS_S) & FW_RI_TPTE_PS_M) 229 230#define FW_RI_TPTE_QPID_S 0 231#define FW_RI_TPTE_QPID_M 0xfffff 232#define FW_RI_TPTE_QPID_V(x) ((x) << FW_RI_TPTE_QPID_S) 233#define FW_RI_TPTE_QPID_G(x) \ 234 (((x) >> FW_RI_TPTE_QPID_S) & FW_RI_TPTE_QPID_M) 235 236#define FW_RI_TPTE_NOSNOOP_S 30 237#define FW_RI_TPTE_NOSNOOP_M 0x1 238#define FW_RI_TPTE_NOSNOOP_V(x) ((x) << FW_RI_TPTE_NOSNOOP_S) 239#define FW_RI_TPTE_NOSNOOP_G(x) \ 240 (((x) >> FW_RI_TPTE_NOSNOOP_S) & FW_RI_TPTE_NOSNOOP_M) 241#define FW_RI_TPTE_NOSNOOP_F FW_RI_TPTE_NOSNOOP_V(1U) 242 243#define FW_RI_TPTE_PBLADDR_S 0 244#define FW_RI_TPTE_PBLADDR_M 0x1fffffff 245#define FW_RI_TPTE_PBLADDR_V(x) ((x) << FW_RI_TPTE_PBLADDR_S) 246#define FW_RI_TPTE_PBLADDR_G(x) \ 247 (((x) >> FW_RI_TPTE_PBLADDR_S) & FW_RI_TPTE_PBLADDR_M) 248 249#define FW_RI_TPTE_DCA_S 24 250#define FW_RI_TPTE_DCA_M 0x1f 251#define FW_RI_TPTE_DCA_V(x) ((x) << FW_RI_TPTE_DCA_S) 252#define FW_RI_TPTE_DCA_G(x) \ 253 (((x) >> FW_RI_TPTE_DCA_S) & FW_RI_TPTE_DCA_M) 254 255#define FW_RI_TPTE_MWBCNT_PSTAG_S 0 256#define FW_RI_TPTE_MWBCNT_PSTAG_M 0xffffff 257#define FW_RI_TPTE_MWBCNT_PSTAT_V(x) \ 258 ((x) << FW_RI_TPTE_MWBCNT_PSTAG_S) 259#define FW_RI_TPTE_MWBCNT_PSTAG_G(x) \ 260 (((x) >> FW_RI_TPTE_MWBCNT_PSTAG_S) & FW_RI_TPTE_MWBCNT_PSTAG_M) 261 262enum fw_ri_res_type { 263 FW_RI_RES_TYPE_SQ, 264 FW_RI_RES_TYPE_RQ, 265 FW_RI_RES_TYPE_CQ, 266}; 267 268enum fw_ri_res_op { 269 FW_RI_RES_OP_WRITE, 270 FW_RI_RES_OP_RESET, 271}; 272 273struct fw_ri_res { 274 union fw_ri_restype { 275 struct fw_ri_res_sqrq { 276 __u8 restype; 277 __u8 op; 278 __be16 r3; 279 __be32 eqid; 280 __be32 r4[2]; 281 __be32 fetchszm_to_iqid; 282 __be32 dcaen_to_eqsize; 283 __be64 eqaddr; 284 } sqrq; 285 struct fw_ri_res_cq { 286 __u8 restype; 287 __u8 op; 288 __be16 r3; 289 __be32 iqid; 290 __be32 r4[2]; 291 __be32 iqandst_to_iqandstindex; 292 __be16 iqdroprss_to_iqesize; 293 __be16 iqsize; 294 __be64 iqaddr; 295 __be32 iqns_iqro; 296 __be32 r6_lo; 297 __be64 r7; 298 } cq; 299 } u; 300}; 301 302struct fw_ri_res_wr { 303 __be32 op_nres; 304 __be32 len16_pkd; 305 __u64 cookie; 306#ifndef C99_NOT_SUPPORTED 307 struct fw_ri_res res[0]; 308#endif 309}; 310 311#define FW_RI_RES_WR_NRES_S 0 312#define FW_RI_RES_WR_NRES_M 0xff 313#define FW_RI_RES_WR_NRES_V(x) ((x) << FW_RI_RES_WR_NRES_S) 314#define FW_RI_RES_WR_NRES_G(x) \ 315 (((x) >> FW_RI_RES_WR_NRES_S) & FW_RI_RES_WR_NRES_M) 316 317#define FW_RI_RES_WR_FETCHSZM_S 26 318#define FW_RI_RES_WR_FETCHSZM_M 0x1 319#define FW_RI_RES_WR_FETCHSZM_V(x) ((x) << FW_RI_RES_WR_FETCHSZM_S) 320#define FW_RI_RES_WR_FETCHSZM_G(x) \ 321 (((x) >> FW_RI_RES_WR_FETCHSZM_S) & FW_RI_RES_WR_FETCHSZM_M) 322#define FW_RI_RES_WR_FETCHSZM_F FW_RI_RES_WR_FETCHSZM_V(1U) 323 324#define FW_RI_RES_WR_STATUSPGNS_S 25 325#define FW_RI_RES_WR_STATUSPGNS_M 0x1 326#define FW_RI_RES_WR_STATUSPGNS_V(x) ((x) << FW_RI_RES_WR_STATUSPGNS_S) 327#define FW_RI_RES_WR_STATUSPGNS_G(x) \ 328 (((x) >> FW_RI_RES_WR_STATUSPGNS_S) & FW_RI_RES_WR_STATUSPGNS_M) 329#define FW_RI_RES_WR_STATUSPGNS_F FW_RI_RES_WR_STATUSPGNS_V(1U) 330 331#define FW_RI_RES_WR_STATUSPGRO_S 24 332#define FW_RI_RES_WR_STATUSPGRO_M 0x1 333#define FW_RI_RES_WR_STATUSPGRO_V(x) ((x) << FW_RI_RES_WR_STATUSPGRO_S) 334#define FW_RI_RES_WR_STATUSPGRO_G(x) \ 335 (((x) >> FW_RI_RES_WR_STATUSPGRO_S) & FW_RI_RES_WR_STATUSPGRO_M) 336#define FW_RI_RES_WR_STATUSPGRO_F FW_RI_RES_WR_STATUSPGRO_V(1U) 337 338#define FW_RI_RES_WR_FETCHNS_S 23 339#define FW_RI_RES_WR_FETCHNS_M 0x1 340#define FW_RI_RES_WR_FETCHNS_V(x) ((x) << FW_RI_RES_WR_FETCHNS_S) 341#define FW_RI_RES_WR_FETCHNS_G(x) \ 342 (((x) >> FW_RI_RES_WR_FETCHNS_S) & FW_RI_RES_WR_FETCHNS_M) 343#define FW_RI_RES_WR_FETCHNS_F FW_RI_RES_WR_FETCHNS_V(1U) 344 345#define FW_RI_RES_WR_FETCHRO_S 22 346#define FW_RI_RES_WR_FETCHRO_M 0x1 347#define FW_RI_RES_WR_FETCHRO_V(x) ((x) << FW_RI_RES_WR_FETCHRO_S) 348#define FW_RI_RES_WR_FETCHRO_G(x) \ 349 (((x) >> FW_RI_RES_WR_FETCHRO_S) & FW_RI_RES_WR_FETCHRO_M) 350#define FW_RI_RES_WR_FETCHRO_F FW_RI_RES_WR_FETCHRO_V(1U) 351 352#define FW_RI_RES_WR_HOSTFCMODE_S 20 353#define FW_RI_RES_WR_HOSTFCMODE_M 0x3 354#define FW_RI_RES_WR_HOSTFCMODE_V(x) ((x) << FW_RI_RES_WR_HOSTFCMODE_S) 355#define FW_RI_RES_WR_HOSTFCMODE_G(x) \ 356 (((x) >> FW_RI_RES_WR_HOSTFCMODE_S) & FW_RI_RES_WR_HOSTFCMODE_M) 357 358#define FW_RI_RES_WR_CPRIO_S 19 359#define FW_RI_RES_WR_CPRIO_M 0x1 360#define FW_RI_RES_WR_CPRIO_V(x) ((x) << FW_RI_RES_WR_CPRIO_S) 361#define FW_RI_RES_WR_CPRIO_G(x) \ 362 (((x) >> FW_RI_RES_WR_CPRIO_S) & FW_RI_RES_WR_CPRIO_M) 363#define FW_RI_RES_WR_CPRIO_F FW_RI_RES_WR_CPRIO_V(1U) 364 365#define FW_RI_RES_WR_ONCHIP_S 18 366#define FW_RI_RES_WR_ONCHIP_M 0x1 367#define FW_RI_RES_WR_ONCHIP_V(x) ((x) << FW_RI_RES_WR_ONCHIP_S) 368#define FW_RI_RES_WR_ONCHIP_G(x) \ 369 (((x) >> FW_RI_RES_WR_ONCHIP_S) & FW_RI_RES_WR_ONCHIP_M) 370#define FW_RI_RES_WR_ONCHIP_F FW_RI_RES_WR_ONCHIP_V(1U) 371 372#define FW_RI_RES_WR_PCIECHN_S 16 373#define FW_RI_RES_WR_PCIECHN_M 0x3 374#define FW_RI_RES_WR_PCIECHN_V(x) ((x) << FW_RI_RES_WR_PCIECHN_S) 375#define FW_RI_RES_WR_PCIECHN_G(x) \ 376 (((x) >> FW_RI_RES_WR_PCIECHN_S) & FW_RI_RES_WR_PCIECHN_M) 377 378#define FW_RI_RES_WR_IQID_S 0 379#define FW_RI_RES_WR_IQID_M 0xffff 380#define FW_RI_RES_WR_IQID_V(x) ((x) << FW_RI_RES_WR_IQID_S) 381#define FW_RI_RES_WR_IQID_G(x) \ 382 (((x) >> FW_RI_RES_WR_IQID_S) & FW_RI_RES_WR_IQID_M) 383 384#define FW_RI_RES_WR_DCAEN_S 31 385#define FW_RI_RES_WR_DCAEN_M 0x1 386#define FW_RI_RES_WR_DCAEN_V(x) ((x) << FW_RI_RES_WR_DCAEN_S) 387#define FW_RI_RES_WR_DCAEN_G(x) \ 388 (((x) >> FW_RI_RES_WR_DCAEN_S) & FW_RI_RES_WR_DCAEN_M) 389#define FW_RI_RES_WR_DCAEN_F FW_RI_RES_WR_DCAEN_V(1U) 390 391#define FW_RI_RES_WR_DCACPU_S 26 392#define FW_RI_RES_WR_DCACPU_M 0x1f 393#define FW_RI_RES_WR_DCACPU_V(x) ((x) << FW_RI_RES_WR_DCACPU_S) 394#define FW_RI_RES_WR_DCACPU_G(x) \ 395 (((x) >> FW_RI_RES_WR_DCACPU_S) & FW_RI_RES_WR_DCACPU_M) 396 397#define FW_RI_RES_WR_FBMIN_S 23 398#define FW_RI_RES_WR_FBMIN_M 0x7 399#define FW_RI_RES_WR_FBMIN_V(x) ((x) << FW_RI_RES_WR_FBMIN_S) 400#define FW_RI_RES_WR_FBMIN_G(x) \ 401 (((x) >> FW_RI_RES_WR_FBMIN_S) & FW_RI_RES_WR_FBMIN_M) 402 403#define FW_RI_RES_WR_FBMAX_S 20 404#define FW_RI_RES_WR_FBMAX_M 0x7 405#define FW_RI_RES_WR_FBMAX_V(x) ((x) << FW_RI_RES_WR_FBMAX_S) 406#define FW_RI_RES_WR_FBMAX_G(x) \ 407 (((x) >> FW_RI_RES_WR_FBMAX_S) & FW_RI_RES_WR_FBMAX_M) 408 409#define FW_RI_RES_WR_CIDXFTHRESHO_S 19 410#define FW_RI_RES_WR_CIDXFTHRESHO_M 0x1 411#define FW_RI_RES_WR_CIDXFTHRESHO_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESHO_S) 412#define FW_RI_RES_WR_CIDXFTHRESHO_G(x) \ 413 (((x) >> FW_RI_RES_WR_CIDXFTHRESHO_S) & FW_RI_RES_WR_CIDXFTHRESHO_M) 414#define FW_RI_RES_WR_CIDXFTHRESHO_F FW_RI_RES_WR_CIDXFTHRESHO_V(1U) 415 416#define FW_RI_RES_WR_CIDXFTHRESH_S 16 417#define FW_RI_RES_WR_CIDXFTHRESH_M 0x7 418#define FW_RI_RES_WR_CIDXFTHRESH_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESH_S) 419#define FW_RI_RES_WR_CIDXFTHRESH_G(x) \ 420 (((x) >> FW_RI_RES_WR_CIDXFTHRESH_S) & FW_RI_RES_WR_CIDXFTHRESH_M) 421 422#define FW_RI_RES_WR_EQSIZE_S 0 423#define FW_RI_RES_WR_EQSIZE_M 0xffff 424#define FW_RI_RES_WR_EQSIZE_V(x) ((x) << FW_RI_RES_WR_EQSIZE_S) 425#define FW_RI_RES_WR_EQSIZE_G(x) \ 426 (((x) >> FW_RI_RES_WR_EQSIZE_S) & FW_RI_RES_WR_EQSIZE_M) 427 428#define FW_RI_RES_WR_IQANDST_S 15 429#define FW_RI_RES_WR_IQANDST_M 0x1 430#define FW_RI_RES_WR_IQANDST_V(x) ((x) << FW_RI_RES_WR_IQANDST_S) 431#define FW_RI_RES_WR_IQANDST_G(x) \ 432 (((x) >> FW_RI_RES_WR_IQANDST_S) & FW_RI_RES_WR_IQANDST_M) 433#define FW_RI_RES_WR_IQANDST_F FW_RI_RES_WR_IQANDST_V(1U) 434 435#define FW_RI_RES_WR_IQANUS_S 14 436#define FW_RI_RES_WR_IQANUS_M 0x1 437#define FW_RI_RES_WR_IQANUS_V(x) ((x) << FW_RI_RES_WR_IQANUS_S) 438#define FW_RI_RES_WR_IQANUS_G(x) \ 439 (((x) >> FW_RI_RES_WR_IQANUS_S) & FW_RI_RES_WR_IQANUS_M) 440#define FW_RI_RES_WR_IQANUS_F FW_RI_RES_WR_IQANUS_V(1U) 441 442#define FW_RI_RES_WR_IQANUD_S 12 443#define FW_RI_RES_WR_IQANUD_M 0x3 444#define FW_RI_RES_WR_IQANUD_V(x) ((x) << FW_RI_RES_WR_IQANUD_S) 445#define FW_RI_RES_WR_IQANUD_G(x) \ 446 (((x) >> FW_RI_RES_WR_IQANUD_S) & FW_RI_RES_WR_IQANUD_M) 447 448#define FW_RI_RES_WR_IQANDSTINDEX_S 0 449#define FW_RI_RES_WR_IQANDSTINDEX_M 0xfff 450#define FW_RI_RES_WR_IQANDSTINDEX_V(x) ((x) << FW_RI_RES_WR_IQANDSTINDEX_S) 451#define FW_RI_RES_WR_IQANDSTINDEX_G(x) \ 452 (((x) >> FW_RI_RES_WR_IQANDSTINDEX_S) & FW_RI_RES_WR_IQANDSTINDEX_M) 453 454#define FW_RI_RES_WR_IQDROPRSS_S 15 455#define FW_RI_RES_WR_IQDROPRSS_M 0x1 456#define FW_RI_RES_WR_IQDROPRSS_V(x) ((x) << FW_RI_RES_WR_IQDROPRSS_S) 457#define FW_RI_RES_WR_IQDROPRSS_G(x) \ 458 (((x) >> FW_RI_RES_WR_IQDROPRSS_S) & FW_RI_RES_WR_IQDROPRSS_M) 459#define FW_RI_RES_WR_IQDROPRSS_F FW_RI_RES_WR_IQDROPRSS_V(1U) 460 461#define FW_RI_RES_WR_IQGTSMODE_S 14 462#define FW_RI_RES_WR_IQGTSMODE_M 0x1 463#define FW_RI_RES_WR_IQGTSMODE_V(x) ((x) << FW_RI_RES_WR_IQGTSMODE_S) 464#define FW_RI_RES_WR_IQGTSMODE_G(x) \ 465 (((x) >> FW_RI_RES_WR_IQGTSMODE_S) & FW_RI_RES_WR_IQGTSMODE_M) 466#define FW_RI_RES_WR_IQGTSMODE_F FW_RI_RES_WR_IQGTSMODE_V(1U) 467 468#define FW_RI_RES_WR_IQPCIECH_S 12 469#define FW_RI_RES_WR_IQPCIECH_M 0x3 470#define FW_RI_RES_WR_IQPCIECH_V(x) ((x) << FW_RI_RES_WR_IQPCIECH_S) 471#define FW_RI_RES_WR_IQPCIECH_G(x) \ 472 (((x) >> FW_RI_RES_WR_IQPCIECH_S) & FW_RI_RES_WR_IQPCIECH_M) 473 474#define FW_RI_RES_WR_IQDCAEN_S 11 475#define FW_RI_RES_WR_IQDCAEN_M 0x1 476#define FW_RI_RES_WR_IQDCAEN_V(x) ((x) << FW_RI_RES_WR_IQDCAEN_S) 477#define FW_RI_RES_WR_IQDCAEN_G(x) \ 478 (((x) >> FW_RI_RES_WR_IQDCAEN_S) & FW_RI_RES_WR_IQDCAEN_M) 479#define FW_RI_RES_WR_IQDCAEN_F FW_RI_RES_WR_IQDCAEN_V(1U) 480 481#define FW_RI_RES_WR_IQDCACPU_S 6 482#define FW_RI_RES_WR_IQDCACPU_M 0x1f 483#define FW_RI_RES_WR_IQDCACPU_V(x) ((x) << FW_RI_RES_WR_IQDCACPU_S) 484#define FW_RI_RES_WR_IQDCACPU_G(x) \ 485 (((x) >> FW_RI_RES_WR_IQDCACPU_S) & FW_RI_RES_WR_IQDCACPU_M) 486 487#define FW_RI_RES_WR_IQINTCNTTHRESH_S 4 488#define FW_RI_RES_WR_IQINTCNTTHRESH_M 0x3 489#define FW_RI_RES_WR_IQINTCNTTHRESH_V(x) \ 490 ((x) << FW_RI_RES_WR_IQINTCNTTHRESH_S) 491#define FW_RI_RES_WR_IQINTCNTTHRESH_G(x) \ 492 (((x) >> FW_RI_RES_WR_IQINTCNTTHRESH_S) & FW_RI_RES_WR_IQINTCNTTHRESH_M) 493 494#define FW_RI_RES_WR_IQO_S 3 495#define FW_RI_RES_WR_IQO_M 0x1 496#define FW_RI_RES_WR_IQO_V(x) ((x) << FW_RI_RES_WR_IQO_S) 497#define FW_RI_RES_WR_IQO_G(x) \ 498 (((x) >> FW_RI_RES_WR_IQO_S) & FW_RI_RES_WR_IQO_M) 499#define FW_RI_RES_WR_IQO_F FW_RI_RES_WR_IQO_V(1U) 500 501#define FW_RI_RES_WR_IQCPRIO_S 2 502#define FW_RI_RES_WR_IQCPRIO_M 0x1 503#define FW_RI_RES_WR_IQCPRIO_V(x) ((x) << FW_RI_RES_WR_IQCPRIO_S) 504#define FW_RI_RES_WR_IQCPRIO_G(x) \ 505 (((x) >> FW_RI_RES_WR_IQCPRIO_S) & FW_RI_RES_WR_IQCPRIO_M) 506#define FW_RI_RES_WR_IQCPRIO_F FW_RI_RES_WR_IQCPRIO_V(1U) 507 508#define FW_RI_RES_WR_IQESIZE_S 0 509#define FW_RI_RES_WR_IQESIZE_M 0x3 510#define FW_RI_RES_WR_IQESIZE_V(x) ((x) << FW_RI_RES_WR_IQESIZE_S) 511#define FW_RI_RES_WR_IQESIZE_G(x) \ 512 (((x) >> FW_RI_RES_WR_IQESIZE_S) & FW_RI_RES_WR_IQESIZE_M) 513 514#define FW_RI_RES_WR_IQNS_S 31 515#define FW_RI_RES_WR_IQNS_M 0x1 516#define FW_RI_RES_WR_IQNS_V(x) ((x) << FW_RI_RES_WR_IQNS_S) 517#define FW_RI_RES_WR_IQNS_G(x) \ 518 (((x) >> FW_RI_RES_WR_IQNS_S) & FW_RI_RES_WR_IQNS_M) 519#define FW_RI_RES_WR_IQNS_F FW_RI_RES_WR_IQNS_V(1U) 520 521#define FW_RI_RES_WR_IQRO_S 30 522#define FW_RI_RES_WR_IQRO_M 0x1 523#define FW_RI_RES_WR_IQRO_V(x) ((x) << FW_RI_RES_WR_IQRO_S) 524#define FW_RI_RES_WR_IQRO_G(x) \ 525 (((x) >> FW_RI_RES_WR_IQRO_S) & FW_RI_RES_WR_IQRO_M) 526#define FW_RI_RES_WR_IQRO_F FW_RI_RES_WR_IQRO_V(1U) 527 528struct fw_ri_rdma_write_wr { 529 __u8 opcode; 530 __u8 flags; 531 __u16 wrid; 532 __u8 r1[3]; 533 __u8 len16; 534 __be64 r2; 535 __be32 plen; 536 __be32 stag_sink; 537 __be64 to_sink; 538#ifndef C99_NOT_SUPPORTED 539 union { 540 struct fw_ri_immd immd_src[0]; 541 struct fw_ri_isgl isgl_src[0]; 542 } u; 543#endif 544}; 545 546struct fw_ri_send_wr { 547 __u8 opcode; 548 __u8 flags; 549 __u16 wrid; 550 __u8 r1[3]; 551 __u8 len16; 552 __be32 sendop_pkd; 553 __be32 stag_inv; 554 __be32 plen; 555 __be32 r3; 556 __be64 r4; 557#ifndef C99_NOT_SUPPORTED 558 union { 559 struct fw_ri_immd immd_src[0]; 560 struct fw_ri_isgl isgl_src[0]; 561 } u; 562#endif 563}; 564 565#define FW_RI_SEND_WR_SENDOP_S 0 566#define FW_RI_SEND_WR_SENDOP_M 0xf 567#define FW_RI_SEND_WR_SENDOP_V(x) ((x) << FW_RI_SEND_WR_SENDOP_S) 568#define FW_RI_SEND_WR_SENDOP_G(x) \ 569 (((x) >> FW_RI_SEND_WR_SENDOP_S) & FW_RI_SEND_WR_SENDOP_M) 570 571struct fw_ri_rdma_read_wr { 572 __u8 opcode; 573 __u8 flags; 574 __u16 wrid; 575 __u8 r1[3]; 576 __u8 len16; 577 __be64 r2; 578 __be32 stag_sink; 579 __be32 to_sink_hi; 580 __be32 to_sink_lo; 581 __be32 plen; 582 __be32 stag_src; 583 __be32 to_src_hi; 584 __be32 to_src_lo; 585 __be32 r5; 586}; 587 588struct fw_ri_recv_wr { 589 __u8 opcode; 590 __u8 r1; 591 __u16 wrid; 592 __u8 r2[3]; 593 __u8 len16; 594 struct fw_ri_isgl isgl; 595}; 596 597struct fw_ri_bind_mw_wr { 598 __u8 opcode; 599 __u8 flags; 600 __u16 wrid; 601 __u8 r1[3]; 602 __u8 len16; 603 __u8 qpbinde_to_dcacpu; 604 __u8 pgsz_shift; 605 __u8 addr_type; 606 __u8 mem_perms; 607 __be32 stag_mr; 608 __be32 stag_mw; 609 __be32 r3; 610 __be64 len_mw; 611 __be64 va_fbo; 612 __be64 r4; 613}; 614 615#define FW_RI_BIND_MW_WR_QPBINDE_S 6 616#define FW_RI_BIND_MW_WR_QPBINDE_M 0x1 617#define FW_RI_BIND_MW_WR_QPBINDE_V(x) ((x) << FW_RI_BIND_MW_WR_QPBINDE_S) 618#define FW_RI_BIND_MW_WR_QPBINDE_G(x) \ 619 (((x) >> FW_RI_BIND_MW_WR_QPBINDE_S) & FW_RI_BIND_MW_WR_QPBINDE_M) 620#define FW_RI_BIND_MW_WR_QPBINDE_F FW_RI_BIND_MW_WR_QPBINDE_V(1U) 621 622#define FW_RI_BIND_MW_WR_NS_S 5 623#define FW_RI_BIND_MW_WR_NS_M 0x1 624#define FW_RI_BIND_MW_WR_NS_V(x) ((x) << FW_RI_BIND_MW_WR_NS_S) 625#define FW_RI_BIND_MW_WR_NS_G(x) \ 626 (((x) >> FW_RI_BIND_MW_WR_NS_S) & FW_RI_BIND_MW_WR_NS_M) 627#define FW_RI_BIND_MW_WR_NS_F FW_RI_BIND_MW_WR_NS_V(1U) 628 629#define FW_RI_BIND_MW_WR_DCACPU_S 0 630#define FW_RI_BIND_MW_WR_DCACPU_M 0x1f 631#define FW_RI_BIND_MW_WR_DCACPU_V(x) ((x) << FW_RI_BIND_MW_WR_DCACPU_S) 632#define FW_RI_BIND_MW_WR_DCACPU_G(x) \ 633 (((x) >> FW_RI_BIND_MW_WR_DCACPU_S) & FW_RI_BIND_MW_WR_DCACPU_M) 634 635struct fw_ri_fr_nsmr_wr { 636 __u8 opcode; 637 __u8 flags; 638 __u16 wrid; 639 __u8 r1[3]; 640 __u8 len16; 641 __u8 qpbinde_to_dcacpu; 642 __u8 pgsz_shift; 643 __u8 addr_type; 644 __u8 mem_perms; 645 __be32 stag; 646 __be32 len_hi; 647 __be32 len_lo; 648 __be32 va_hi; 649 __be32 va_lo_fbo; 650}; 651 652#define FW_RI_FR_NSMR_WR_QPBINDE_S 6 653#define FW_RI_FR_NSMR_WR_QPBINDE_M 0x1 654#define FW_RI_FR_NSMR_WR_QPBINDE_V(x) ((x) << FW_RI_FR_NSMR_WR_QPBINDE_S) 655#define FW_RI_FR_NSMR_WR_QPBINDE_G(x) \ 656 (((x) >> FW_RI_FR_NSMR_WR_QPBINDE_S) & FW_RI_FR_NSMR_WR_QPBINDE_M) 657#define FW_RI_FR_NSMR_WR_QPBINDE_F FW_RI_FR_NSMR_WR_QPBINDE_V(1U) 658 659#define FW_RI_FR_NSMR_WR_NS_S 5 660#define FW_RI_FR_NSMR_WR_NS_M 0x1 661#define FW_RI_FR_NSMR_WR_NS_V(x) ((x) << FW_RI_FR_NSMR_WR_NS_S) 662#define FW_RI_FR_NSMR_WR_NS_G(x) \ 663 (((x) >> FW_RI_FR_NSMR_WR_NS_S) & FW_RI_FR_NSMR_WR_NS_M) 664#define FW_RI_FR_NSMR_WR_NS_F FW_RI_FR_NSMR_WR_NS_V(1U) 665 666#define FW_RI_FR_NSMR_WR_DCACPU_S 0 667#define FW_RI_FR_NSMR_WR_DCACPU_M 0x1f 668#define FW_RI_FR_NSMR_WR_DCACPU_V(x) ((x) << FW_RI_FR_NSMR_WR_DCACPU_S) 669#define FW_RI_FR_NSMR_WR_DCACPU_G(x) \ 670 (((x) >> FW_RI_FR_NSMR_WR_DCACPU_S) & FW_RI_FR_NSMR_WR_DCACPU_M) 671 672struct fw_ri_inv_lstag_wr { 673 __u8 opcode; 674 __u8 flags; 675 __u16 wrid; 676 __u8 r1[3]; 677 __u8 len16; 678 __be32 r2; 679 __be32 stag_inv; 680}; 681 682enum fw_ri_type { 683 FW_RI_TYPE_INIT, 684 FW_RI_TYPE_FINI, 685 FW_RI_TYPE_TERMINATE 686}; 687 688enum fw_ri_init_p2ptype { 689 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 690 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 691 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 692 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 693 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 694 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 695 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 696}; 697 698struct fw_ri_wr { 699 __be32 op_compl; 700 __be32 flowid_len16; 701 __u64 cookie; 702 union fw_ri { 703 struct fw_ri_init { 704 __u8 type; 705 __u8 mpareqbit_p2ptype; 706 __u8 r4[2]; 707 __u8 mpa_attrs; 708 __u8 qp_caps; 709 __be16 nrqe; 710 __be32 pdid; 711 __be32 qpid; 712 __be32 sq_eqid; 713 __be32 rq_eqid; 714 __be32 scqid; 715 __be32 rcqid; 716 __be32 ord_max; 717 __be32 ird_max; 718 __be32 iss; 719 __be32 irs; 720 __be32 hwrqsize; 721 __be32 hwrqaddr; 722 __be64 r5; 723 union fw_ri_init_p2p { 724 struct fw_ri_rdma_write_wr write; 725 struct fw_ri_rdma_read_wr read; 726 struct fw_ri_send_wr send; 727 } u; 728 } init; 729 struct fw_ri_fini { 730 __u8 type; 731 __u8 r3[7]; 732 __be64 r4; 733 } fini; 734 struct fw_ri_terminate { 735 __u8 type; 736 __u8 r3[3]; 737 __be32 immdlen; 738 __u8 termmsg[40]; 739 } terminate; 740 } u; 741}; 742 743#define FW_RI_WR_MPAREQBIT_S 7 744#define FW_RI_WR_MPAREQBIT_M 0x1 745#define FW_RI_WR_MPAREQBIT_V(x) ((x) << FW_RI_WR_MPAREQBIT_S) 746#define FW_RI_WR_MPAREQBIT_G(x) \ 747 (((x) >> FW_RI_WR_MPAREQBIT_S) & FW_RI_WR_MPAREQBIT_M) 748#define FW_RI_WR_MPAREQBIT_F FW_RI_WR_MPAREQBIT_V(1U) 749 750#define FW_RI_WR_P2PTYPE_S 0 751#define FW_RI_WR_P2PTYPE_M 0xf 752#define FW_RI_WR_P2PTYPE_V(x) ((x) << FW_RI_WR_P2PTYPE_S) 753#define FW_RI_WR_P2PTYPE_G(x) \ 754 (((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M) 755 756#endif /* _T4FW_RI_API_H_ */ 757