1321936Shselasky/* 2321936Shselasky * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3321936Shselasky * 4321936Shselasky * This software is available to you under a choice of one of two 5321936Shselasky * licenses. You may choose to be licensed under the terms of the GNU 6321936Shselasky * General Public License (GPL) Version 2, available from the file 7321936Shselasky * COPYING in the main directory of this source tree, or the 8321936Shselasky * OpenIB.org BSD license below: 9321936Shselasky * 10321936Shselasky * Redistribution and use in source and binary forms, with or 11321936Shselasky * without modification, are permitted provided that the following 12321936Shselasky * conditions are met: 13321936Shselasky * 14321936Shselasky * - Redistributions of source code must retain the above 15321936Shselasky * copyright notice, this list of conditions and the following 16321936Shselasky * disclaimer. 17321936Shselasky * - Redistributions in binary form must reproduce the above 18321936Shselasky * copyright notice, this list of conditions and the following 19321936Shselasky * disclaimer in the documentation and/or other materials 20321936Shselasky * provided with the distribution. 21321936Shselasky * 22321936Shselasky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23321936Shselasky * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24321936Shselasky * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25321936Shselasky * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26321936Shselasky * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27321936Shselasky * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28321936Shselasky * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29321936Shselasky * SOFTWARE. 30321936Shselasky */ 31321936Shselasky#ifndef _T4FW_RI_API_H_ 32321936Shselasky#define _T4FW_RI_API_H_ 33321936Shselasky 34321936Shselasky#include "t4fw_api.h" 35321936Shselasky 36321936Shselaskyenum fw_ri_wr_opcode { 37321936Shselasky FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 38321936Shselasky FW_RI_READ_REQ = 0x1, 39321936Shselasky FW_RI_READ_RESP = 0x2, 40321936Shselasky FW_RI_SEND = 0x3, 41321936Shselasky FW_RI_SEND_WITH_INV = 0x4, 42321936Shselasky FW_RI_SEND_WITH_SE = 0x5, 43321936Shselasky FW_RI_SEND_WITH_SE_INV = 0x6, 44321936Shselasky FW_RI_TERMINATE = 0x7, 45321936Shselasky FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 46321936Shselasky FW_RI_BIND_MW = 0x9, 47321936Shselasky FW_RI_FAST_REGISTER = 0xa, 48321936Shselasky FW_RI_LOCAL_INV = 0xb, 49321936Shselasky FW_RI_QP_MODIFY = 0xc, 50321936Shselasky FW_RI_BYPASS = 0xd, 51321936Shselasky FW_RI_RECEIVE = 0xe, 52321936Shselasky 53321936Shselasky FW_RI_SGE_EC_CR_RETURN = 0xf 54321936Shselasky}; 55321936Shselasky 56321936Shselaskyenum fw_ri_wr_flags { 57321936Shselasky FW_RI_COMPLETION_FLAG = 0x01, 58321936Shselasky FW_RI_NOTIFICATION_FLAG = 0x02, 59321936Shselasky FW_RI_SOLICITED_EVENT_FLAG = 0x04, 60321936Shselasky FW_RI_READ_FENCE_FLAG = 0x08, 61321936Shselasky FW_RI_LOCAL_FENCE_FLAG = 0x10, 62321936Shselasky FW_RI_RDMA_READ_INVALIDATE = 0x20 63321936Shselasky}; 64321936Shselasky 65321936Shselaskyenum fw_ri_mpa_attrs { 66321936Shselasky FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 67321936Shselasky FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 68321936Shselasky FW_RI_MPA_CRC_ENABLE = 0x04, 69321936Shselasky FW_RI_MPA_IETF_ENABLE = 0x08 70321936Shselasky}; 71321936Shselasky 72321936Shselaskyenum fw_ri_qp_caps { 73321936Shselasky FW_RI_QP_RDMA_READ_ENABLE = 0x01, 74321936Shselasky FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 75321936Shselasky FW_RI_QP_BIND_ENABLE = 0x04, 76321936Shselasky FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 77321936Shselasky FW_RI_QP_STAG0_ENABLE = 0x10 78321936Shselasky}; 79321936Shselasky 80321936Shselaskyenum fw_ri_addr_type { 81321936Shselasky FW_RI_ZERO_BASED_TO = 0x00, 82321936Shselasky FW_RI_VA_BASED_TO = 0x01 83321936Shselasky}; 84321936Shselasky 85321936Shselaskyenum fw_ri_mem_perms { 86321936Shselasky FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 87321936Shselasky FW_RI_MEM_ACCESS_REM_READ = 0x02, 88321936Shselasky FW_RI_MEM_ACCESS_REM = 0x03, 89321936Shselasky FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 90321936Shselasky FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 91321936Shselasky FW_RI_MEM_ACCESS_LOCAL = 0x0C 92321936Shselasky}; 93321936Shselasky 94321936Shselaskyenum fw_ri_stag_type { 95321936Shselasky FW_RI_STAG_NSMR = 0x00, 96321936Shselasky FW_RI_STAG_SMR = 0x01, 97321936Shselasky FW_RI_STAG_MW = 0x02, 98321936Shselasky FW_RI_STAG_MW_RELAXED = 0x03 99321936Shselasky}; 100321936Shselasky 101321936Shselaskyenum fw_ri_data_op { 102321936Shselasky FW_RI_DATA_IMMD = 0x81, 103321936Shselasky FW_RI_DATA_DSGL = 0x82, 104321936Shselasky FW_RI_DATA_ISGL = 0x83 105321936Shselasky}; 106321936Shselasky 107321936Shselaskyenum fw_ri_sgl_depth { 108321936Shselasky FW_RI_SGL_DEPTH_MAX_SQ = 16, 109321936Shselasky FW_RI_SGL_DEPTH_MAX_RQ = 4 110321936Shselasky}; 111321936Shselasky 112321936Shselaskystruct fw_ri_dsge_pair { 113321936Shselasky __be32 len[2]; 114321936Shselasky __be64 addr[2]; 115321936Shselasky}; 116321936Shselasky 117321936Shselaskystruct fw_ri_dsgl { 118321936Shselasky __u8 op; 119321936Shselasky __u8 r1; 120321936Shselasky __be16 nsge; 121321936Shselasky __be32 len0; 122321936Shselasky __be64 addr0; 123321936Shselasky#ifndef C99_NOT_SUPPORTED 124321936Shselasky struct fw_ri_dsge_pair sge[0]; 125321936Shselasky#endif 126321936Shselasky}; 127321936Shselasky 128321936Shselaskystruct fw_ri_sge { 129321936Shselasky __be32 stag; 130321936Shselasky __be32 len; 131321936Shselasky __be64 to; 132321936Shselasky}; 133321936Shselasky 134321936Shselaskystruct fw_ri_isgl { 135321936Shselasky __u8 op; 136321936Shselasky __u8 r1; 137321936Shselasky __be16 nsge; 138321936Shselasky __be32 r2; 139321936Shselasky#ifndef C99_NOT_SUPPORTED 140321936Shselasky struct fw_ri_sge sge[0]; 141321936Shselasky#endif 142321936Shselasky}; 143321936Shselasky 144321936Shselaskystruct fw_ri_immd { 145321936Shselasky __u8 op; 146321936Shselasky __u8 r1; 147321936Shselasky __be16 r2; 148321936Shselasky __be32 immdlen; 149321936Shselasky#ifndef C99_NOT_SUPPORTED 150321936Shselasky __u8 data[0]; 151321936Shselasky#endif 152321936Shselasky}; 153321936Shselasky 154321936Shselaskystruct fw_ri_tpte { 155321936Shselasky __be32 valid_to_pdid; 156321936Shselasky __be32 locread_to_qpid; 157321936Shselasky __be32 nosnoop_pbladdr; 158321936Shselasky __be32 len_lo; 159321936Shselasky __be32 va_hi; 160321936Shselasky __be32 va_lo_fbo; 161321936Shselasky __be32 dca_mwbcnt_pstag; 162321936Shselasky __be32 len_hi; 163321936Shselasky}; 164321936Shselasky 165321936Shselasky#define FW_RI_TPTE_VALID_S 31 166321936Shselasky#define FW_RI_TPTE_VALID_M 0x1 167321936Shselasky#define FW_RI_TPTE_VALID_V(x) ((x) << FW_RI_TPTE_VALID_S) 168321936Shselasky#define FW_RI_TPTE_VALID_G(x) \ 169321936Shselasky (((x) >> FW_RI_TPTE_VALID_S) & FW_RI_TPTE_VALID_M) 170321936Shselasky#define FW_RI_TPTE_VALID_F FW_RI_TPTE_VALID_V(1U) 171321936Shselasky 172321936Shselasky#define FW_RI_TPTE_STAGKEY_S 23 173321936Shselasky#define FW_RI_TPTE_STAGKEY_M 0xff 174321936Shselasky#define FW_RI_TPTE_STAGKEY_V(x) ((x) << FW_RI_TPTE_STAGKEY_S) 175321936Shselasky#define FW_RI_TPTE_STAGKEY_G(x) \ 176321936Shselasky (((x) >> FW_RI_TPTE_STAGKEY_S) & FW_RI_TPTE_STAGKEY_M) 177321936Shselasky 178321936Shselasky#define FW_RI_TPTE_STAGSTATE_S 22 179321936Shselasky#define FW_RI_TPTE_STAGSTATE_M 0x1 180321936Shselasky#define FW_RI_TPTE_STAGSTATE_V(x) ((x) << FW_RI_TPTE_STAGSTATE_S) 181321936Shselasky#define FW_RI_TPTE_STAGSTATE_G(x) \ 182321936Shselasky (((x) >> FW_RI_TPTE_STAGSTATE_S) & FW_RI_TPTE_STAGSTATE_M) 183321936Shselasky#define FW_RI_TPTE_STAGSTATE_F FW_RI_TPTE_STAGSTATE_V(1U) 184321936Shselasky 185321936Shselasky#define FW_RI_TPTE_STAGTYPE_S 20 186321936Shselasky#define FW_RI_TPTE_STAGTYPE_M 0x3 187321936Shselasky#define FW_RI_TPTE_STAGTYPE_V(x) ((x) << FW_RI_TPTE_STAGTYPE_S) 188321936Shselasky#define FW_RI_TPTE_STAGTYPE_G(x) \ 189321936Shselasky (((x) >> FW_RI_TPTE_STAGTYPE_S) & FW_RI_TPTE_STAGTYPE_M) 190321936Shselasky 191321936Shselasky#define FW_RI_TPTE_PDID_S 0 192321936Shselasky#define FW_RI_TPTE_PDID_M 0xfffff 193321936Shselasky#define FW_RI_TPTE_PDID_V(x) ((x) << FW_RI_TPTE_PDID_S) 194321936Shselasky#define FW_RI_TPTE_PDID_G(x) \ 195321936Shselasky (((x) >> FW_RI_TPTE_PDID_S) & FW_RI_TPTE_PDID_M) 196321936Shselasky 197321936Shselasky#define FW_RI_TPTE_PERM_S 28 198321936Shselasky#define FW_RI_TPTE_PERM_M 0xf 199321936Shselasky#define FW_RI_TPTE_PERM_V(x) ((x) << FW_RI_TPTE_PERM_S) 200321936Shselasky#define FW_RI_TPTE_PERM_G(x) \ 201321936Shselasky (((x) >> FW_RI_TPTE_PERM_S) & FW_RI_TPTE_PERM_M) 202321936Shselasky 203321936Shselasky#define FW_RI_TPTE_REMINVDIS_S 27 204321936Shselasky#define FW_RI_TPTE_REMINVDIS_M 0x1 205321936Shselasky#define FW_RI_TPTE_REMINVDIS_V(x) ((x) << FW_RI_TPTE_REMINVDIS_S) 206321936Shselasky#define FW_RI_TPTE_REMINVDIS_G(x) \ 207321936Shselasky (((x) >> FW_RI_TPTE_REMINVDIS_S) & FW_RI_TPTE_REMINVDIS_M) 208321936Shselasky#define FW_RI_TPTE_REMINVDIS_F FW_RI_TPTE_REMINVDIS_V(1U) 209321936Shselasky 210321936Shselasky#define FW_RI_TPTE_ADDRTYPE_S 26 211321936Shselasky#define FW_RI_TPTE_ADDRTYPE_M 1 212321936Shselasky#define FW_RI_TPTE_ADDRTYPE_V(x) ((x) << FW_RI_TPTE_ADDRTYPE_S) 213321936Shselasky#define FW_RI_TPTE_ADDRTYPE_G(x) \ 214321936Shselasky (((x) >> FW_RI_TPTE_ADDRTYPE_S) & FW_RI_TPTE_ADDRTYPE_M) 215321936Shselasky#define FW_RI_TPTE_ADDRTYPE_F FW_RI_TPTE_ADDRTYPE_V(1U) 216321936Shselasky 217321936Shselasky#define FW_RI_TPTE_MWBINDEN_S 25 218321936Shselasky#define FW_RI_TPTE_MWBINDEN_M 0x1 219321936Shselasky#define FW_RI_TPTE_MWBINDEN_V(x) ((x) << FW_RI_TPTE_MWBINDEN_S) 220321936Shselasky#define FW_RI_TPTE_MWBINDEN_G(x) \ 221321936Shselasky (((x) >> FW_RI_TPTE_MWBINDEN_S) & FW_RI_TPTE_MWBINDEN_M) 222321936Shselasky#define FW_RI_TPTE_MWBINDEN_F FW_RI_TPTE_MWBINDEN_V(1U) 223321936Shselasky 224321936Shselasky#define FW_RI_TPTE_PS_S 20 225321936Shselasky#define FW_RI_TPTE_PS_M 0x1f 226321936Shselasky#define FW_RI_TPTE_PS_V(x) ((x) << FW_RI_TPTE_PS_S) 227321936Shselasky#define FW_RI_TPTE_PS_G(x) \ 228321936Shselasky (((x) >> FW_RI_TPTE_PS_S) & FW_RI_TPTE_PS_M) 229321936Shselasky 230321936Shselasky#define FW_RI_TPTE_QPID_S 0 231321936Shselasky#define FW_RI_TPTE_QPID_M 0xfffff 232321936Shselasky#define FW_RI_TPTE_QPID_V(x) ((x) << FW_RI_TPTE_QPID_S) 233321936Shselasky#define FW_RI_TPTE_QPID_G(x) \ 234321936Shselasky (((x) >> FW_RI_TPTE_QPID_S) & FW_RI_TPTE_QPID_M) 235321936Shselasky 236321936Shselasky#define FW_RI_TPTE_NOSNOOP_S 30 237321936Shselasky#define FW_RI_TPTE_NOSNOOP_M 0x1 238321936Shselasky#define FW_RI_TPTE_NOSNOOP_V(x) ((x) << FW_RI_TPTE_NOSNOOP_S) 239321936Shselasky#define FW_RI_TPTE_NOSNOOP_G(x) \ 240321936Shselasky (((x) >> FW_RI_TPTE_NOSNOOP_S) & FW_RI_TPTE_NOSNOOP_M) 241321936Shselasky#define FW_RI_TPTE_NOSNOOP_F FW_RI_TPTE_NOSNOOP_V(1U) 242321936Shselasky 243321936Shselasky#define FW_RI_TPTE_PBLADDR_S 0 244321936Shselasky#define FW_RI_TPTE_PBLADDR_M 0x1fffffff 245321936Shselasky#define FW_RI_TPTE_PBLADDR_V(x) ((x) << FW_RI_TPTE_PBLADDR_S) 246321936Shselasky#define FW_RI_TPTE_PBLADDR_G(x) \ 247321936Shselasky (((x) >> FW_RI_TPTE_PBLADDR_S) & FW_RI_TPTE_PBLADDR_M) 248321936Shselasky 249321936Shselasky#define FW_RI_TPTE_DCA_S 24 250321936Shselasky#define FW_RI_TPTE_DCA_M 0x1f 251321936Shselasky#define FW_RI_TPTE_DCA_V(x) ((x) << FW_RI_TPTE_DCA_S) 252321936Shselasky#define FW_RI_TPTE_DCA_G(x) \ 253321936Shselasky (((x) >> FW_RI_TPTE_DCA_S) & FW_RI_TPTE_DCA_M) 254321936Shselasky 255321936Shselasky#define FW_RI_TPTE_MWBCNT_PSTAG_S 0 256321936Shselasky#define FW_RI_TPTE_MWBCNT_PSTAG_M 0xffffff 257321936Shselasky#define FW_RI_TPTE_MWBCNT_PSTAT_V(x) \ 258321936Shselasky ((x) << FW_RI_TPTE_MWBCNT_PSTAG_S) 259321936Shselasky#define FW_RI_TPTE_MWBCNT_PSTAG_G(x) \ 260321936Shselasky (((x) >> FW_RI_TPTE_MWBCNT_PSTAG_S) & FW_RI_TPTE_MWBCNT_PSTAG_M) 261321936Shselasky 262321936Shselaskyenum fw_ri_res_type { 263321936Shselasky FW_RI_RES_TYPE_SQ, 264321936Shselasky FW_RI_RES_TYPE_RQ, 265321936Shselasky FW_RI_RES_TYPE_CQ, 266321936Shselasky}; 267321936Shselasky 268321936Shselaskyenum fw_ri_res_op { 269321936Shselasky FW_RI_RES_OP_WRITE, 270321936Shselasky FW_RI_RES_OP_RESET, 271321936Shselasky}; 272321936Shselasky 273321936Shselaskystruct fw_ri_res { 274321936Shselasky union fw_ri_restype { 275321936Shselasky struct fw_ri_res_sqrq { 276321936Shselasky __u8 restype; 277321936Shselasky __u8 op; 278321936Shselasky __be16 r3; 279321936Shselasky __be32 eqid; 280321936Shselasky __be32 r4[2]; 281321936Shselasky __be32 fetchszm_to_iqid; 282321936Shselasky __be32 dcaen_to_eqsize; 283321936Shselasky __be64 eqaddr; 284321936Shselasky } sqrq; 285321936Shselasky struct fw_ri_res_cq { 286321936Shselasky __u8 restype; 287321936Shselasky __u8 op; 288321936Shselasky __be16 r3; 289321936Shselasky __be32 iqid; 290321936Shselasky __be32 r4[2]; 291321936Shselasky __be32 iqandst_to_iqandstindex; 292321936Shselasky __be16 iqdroprss_to_iqesize; 293321936Shselasky __be16 iqsize; 294321936Shselasky __be64 iqaddr; 295321936Shselasky __be32 iqns_iqro; 296321936Shselasky __be32 r6_lo; 297321936Shselasky __be64 r7; 298321936Shselasky } cq; 299321936Shselasky } u; 300321936Shselasky}; 301321936Shselasky 302321936Shselaskystruct fw_ri_res_wr { 303321936Shselasky __be32 op_nres; 304321936Shselasky __be32 len16_pkd; 305321936Shselasky __u64 cookie; 306321936Shselasky#ifndef C99_NOT_SUPPORTED 307321936Shselasky struct fw_ri_res res[0]; 308321936Shselasky#endif 309321936Shselasky}; 310321936Shselasky 311321936Shselasky#define FW_RI_RES_WR_NRES_S 0 312321936Shselasky#define FW_RI_RES_WR_NRES_M 0xff 313321936Shselasky#define FW_RI_RES_WR_NRES_V(x) ((x) << FW_RI_RES_WR_NRES_S) 314321936Shselasky#define FW_RI_RES_WR_NRES_G(x) \ 315321936Shselasky (((x) >> FW_RI_RES_WR_NRES_S) & FW_RI_RES_WR_NRES_M) 316321936Shselasky 317321936Shselasky#define FW_RI_RES_WR_FETCHSZM_S 26 318321936Shselasky#define FW_RI_RES_WR_FETCHSZM_M 0x1 319321936Shselasky#define FW_RI_RES_WR_FETCHSZM_V(x) ((x) << FW_RI_RES_WR_FETCHSZM_S) 320321936Shselasky#define FW_RI_RES_WR_FETCHSZM_G(x) \ 321321936Shselasky (((x) >> FW_RI_RES_WR_FETCHSZM_S) & FW_RI_RES_WR_FETCHSZM_M) 322321936Shselasky#define FW_RI_RES_WR_FETCHSZM_F FW_RI_RES_WR_FETCHSZM_V(1U) 323321936Shselasky 324321936Shselasky#define FW_RI_RES_WR_STATUSPGNS_S 25 325321936Shselasky#define FW_RI_RES_WR_STATUSPGNS_M 0x1 326321936Shselasky#define FW_RI_RES_WR_STATUSPGNS_V(x) ((x) << FW_RI_RES_WR_STATUSPGNS_S) 327321936Shselasky#define FW_RI_RES_WR_STATUSPGNS_G(x) \ 328321936Shselasky (((x) >> FW_RI_RES_WR_STATUSPGNS_S) & FW_RI_RES_WR_STATUSPGNS_M) 329321936Shselasky#define FW_RI_RES_WR_STATUSPGNS_F FW_RI_RES_WR_STATUSPGNS_V(1U) 330321936Shselasky 331321936Shselasky#define FW_RI_RES_WR_STATUSPGRO_S 24 332321936Shselasky#define FW_RI_RES_WR_STATUSPGRO_M 0x1 333321936Shselasky#define FW_RI_RES_WR_STATUSPGRO_V(x) ((x) << FW_RI_RES_WR_STATUSPGRO_S) 334321936Shselasky#define FW_RI_RES_WR_STATUSPGRO_G(x) \ 335321936Shselasky (((x) >> FW_RI_RES_WR_STATUSPGRO_S) & FW_RI_RES_WR_STATUSPGRO_M) 336321936Shselasky#define FW_RI_RES_WR_STATUSPGRO_F FW_RI_RES_WR_STATUSPGRO_V(1U) 337321936Shselasky 338321936Shselasky#define FW_RI_RES_WR_FETCHNS_S 23 339321936Shselasky#define FW_RI_RES_WR_FETCHNS_M 0x1 340321936Shselasky#define FW_RI_RES_WR_FETCHNS_V(x) ((x) << FW_RI_RES_WR_FETCHNS_S) 341321936Shselasky#define FW_RI_RES_WR_FETCHNS_G(x) \ 342321936Shselasky (((x) >> FW_RI_RES_WR_FETCHNS_S) & FW_RI_RES_WR_FETCHNS_M) 343321936Shselasky#define FW_RI_RES_WR_FETCHNS_F FW_RI_RES_WR_FETCHNS_V(1U) 344321936Shselasky 345321936Shselasky#define FW_RI_RES_WR_FETCHRO_S 22 346321936Shselasky#define FW_RI_RES_WR_FETCHRO_M 0x1 347321936Shselasky#define FW_RI_RES_WR_FETCHRO_V(x) ((x) << FW_RI_RES_WR_FETCHRO_S) 348321936Shselasky#define FW_RI_RES_WR_FETCHRO_G(x) \ 349321936Shselasky (((x) >> FW_RI_RES_WR_FETCHRO_S) & FW_RI_RES_WR_FETCHRO_M) 350321936Shselasky#define FW_RI_RES_WR_FETCHRO_F FW_RI_RES_WR_FETCHRO_V(1U) 351321936Shselasky 352321936Shselasky#define FW_RI_RES_WR_HOSTFCMODE_S 20 353321936Shselasky#define FW_RI_RES_WR_HOSTFCMODE_M 0x3 354321936Shselasky#define FW_RI_RES_WR_HOSTFCMODE_V(x) ((x) << FW_RI_RES_WR_HOSTFCMODE_S) 355321936Shselasky#define FW_RI_RES_WR_HOSTFCMODE_G(x) \ 356321936Shselasky (((x) >> FW_RI_RES_WR_HOSTFCMODE_S) & FW_RI_RES_WR_HOSTFCMODE_M) 357321936Shselasky 358321936Shselasky#define FW_RI_RES_WR_CPRIO_S 19 359321936Shselasky#define FW_RI_RES_WR_CPRIO_M 0x1 360321936Shselasky#define FW_RI_RES_WR_CPRIO_V(x) ((x) << FW_RI_RES_WR_CPRIO_S) 361321936Shselasky#define FW_RI_RES_WR_CPRIO_G(x) \ 362321936Shselasky (((x) >> FW_RI_RES_WR_CPRIO_S) & FW_RI_RES_WR_CPRIO_M) 363321936Shselasky#define FW_RI_RES_WR_CPRIO_F FW_RI_RES_WR_CPRIO_V(1U) 364321936Shselasky 365321936Shselasky#define FW_RI_RES_WR_ONCHIP_S 18 366321936Shselasky#define FW_RI_RES_WR_ONCHIP_M 0x1 367321936Shselasky#define FW_RI_RES_WR_ONCHIP_V(x) ((x) << FW_RI_RES_WR_ONCHIP_S) 368321936Shselasky#define FW_RI_RES_WR_ONCHIP_G(x) \ 369321936Shselasky (((x) >> FW_RI_RES_WR_ONCHIP_S) & FW_RI_RES_WR_ONCHIP_M) 370321936Shselasky#define FW_RI_RES_WR_ONCHIP_F FW_RI_RES_WR_ONCHIP_V(1U) 371321936Shselasky 372321936Shselasky#define FW_RI_RES_WR_PCIECHN_S 16 373321936Shselasky#define FW_RI_RES_WR_PCIECHN_M 0x3 374321936Shselasky#define FW_RI_RES_WR_PCIECHN_V(x) ((x) << FW_RI_RES_WR_PCIECHN_S) 375321936Shselasky#define FW_RI_RES_WR_PCIECHN_G(x) \ 376321936Shselasky (((x) >> FW_RI_RES_WR_PCIECHN_S) & FW_RI_RES_WR_PCIECHN_M) 377321936Shselasky 378321936Shselasky#define FW_RI_RES_WR_IQID_S 0 379321936Shselasky#define FW_RI_RES_WR_IQID_M 0xffff 380321936Shselasky#define FW_RI_RES_WR_IQID_V(x) ((x) << FW_RI_RES_WR_IQID_S) 381321936Shselasky#define FW_RI_RES_WR_IQID_G(x) \ 382321936Shselasky (((x) >> FW_RI_RES_WR_IQID_S) & FW_RI_RES_WR_IQID_M) 383321936Shselasky 384321936Shselasky#define FW_RI_RES_WR_DCAEN_S 31 385321936Shselasky#define FW_RI_RES_WR_DCAEN_M 0x1 386321936Shselasky#define FW_RI_RES_WR_DCAEN_V(x) ((x) << FW_RI_RES_WR_DCAEN_S) 387321936Shselasky#define FW_RI_RES_WR_DCAEN_G(x) \ 388321936Shselasky (((x) >> FW_RI_RES_WR_DCAEN_S) & FW_RI_RES_WR_DCAEN_M) 389321936Shselasky#define FW_RI_RES_WR_DCAEN_F FW_RI_RES_WR_DCAEN_V(1U) 390321936Shselasky 391321936Shselasky#define FW_RI_RES_WR_DCACPU_S 26 392321936Shselasky#define FW_RI_RES_WR_DCACPU_M 0x1f 393321936Shselasky#define FW_RI_RES_WR_DCACPU_V(x) ((x) << FW_RI_RES_WR_DCACPU_S) 394321936Shselasky#define FW_RI_RES_WR_DCACPU_G(x) \ 395321936Shselasky (((x) >> FW_RI_RES_WR_DCACPU_S) & FW_RI_RES_WR_DCACPU_M) 396321936Shselasky 397321936Shselasky#define FW_RI_RES_WR_FBMIN_S 23 398321936Shselasky#define FW_RI_RES_WR_FBMIN_M 0x7 399321936Shselasky#define FW_RI_RES_WR_FBMIN_V(x) ((x) << FW_RI_RES_WR_FBMIN_S) 400321936Shselasky#define FW_RI_RES_WR_FBMIN_G(x) \ 401321936Shselasky (((x) >> FW_RI_RES_WR_FBMIN_S) & FW_RI_RES_WR_FBMIN_M) 402321936Shselasky 403321936Shselasky#define FW_RI_RES_WR_FBMAX_S 20 404321936Shselasky#define FW_RI_RES_WR_FBMAX_M 0x7 405321936Shselasky#define FW_RI_RES_WR_FBMAX_V(x) ((x) << FW_RI_RES_WR_FBMAX_S) 406321936Shselasky#define FW_RI_RES_WR_FBMAX_G(x) \ 407321936Shselasky (((x) >> FW_RI_RES_WR_FBMAX_S) & FW_RI_RES_WR_FBMAX_M) 408321936Shselasky 409321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESHO_S 19 410321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESHO_M 0x1 411321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESHO_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESHO_S) 412321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESHO_G(x) \ 413321936Shselasky (((x) >> FW_RI_RES_WR_CIDXFTHRESHO_S) & FW_RI_RES_WR_CIDXFTHRESHO_M) 414321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESHO_F FW_RI_RES_WR_CIDXFTHRESHO_V(1U) 415321936Shselasky 416321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESH_S 16 417321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESH_M 0x7 418321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESH_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESH_S) 419321936Shselasky#define FW_RI_RES_WR_CIDXFTHRESH_G(x) \ 420321936Shselasky (((x) >> FW_RI_RES_WR_CIDXFTHRESH_S) & FW_RI_RES_WR_CIDXFTHRESH_M) 421321936Shselasky 422321936Shselasky#define FW_RI_RES_WR_EQSIZE_S 0 423321936Shselasky#define FW_RI_RES_WR_EQSIZE_M 0xffff 424321936Shselasky#define FW_RI_RES_WR_EQSIZE_V(x) ((x) << FW_RI_RES_WR_EQSIZE_S) 425321936Shselasky#define FW_RI_RES_WR_EQSIZE_G(x) \ 426321936Shselasky (((x) >> FW_RI_RES_WR_EQSIZE_S) & FW_RI_RES_WR_EQSIZE_M) 427321936Shselasky 428321936Shselasky#define FW_RI_RES_WR_IQANDST_S 15 429321936Shselasky#define FW_RI_RES_WR_IQANDST_M 0x1 430321936Shselasky#define FW_RI_RES_WR_IQANDST_V(x) ((x) << FW_RI_RES_WR_IQANDST_S) 431321936Shselasky#define FW_RI_RES_WR_IQANDST_G(x) \ 432321936Shselasky (((x) >> FW_RI_RES_WR_IQANDST_S) & FW_RI_RES_WR_IQANDST_M) 433321936Shselasky#define FW_RI_RES_WR_IQANDST_F FW_RI_RES_WR_IQANDST_V(1U) 434321936Shselasky 435321936Shselasky#define FW_RI_RES_WR_IQANUS_S 14 436321936Shselasky#define FW_RI_RES_WR_IQANUS_M 0x1 437321936Shselasky#define FW_RI_RES_WR_IQANUS_V(x) ((x) << FW_RI_RES_WR_IQANUS_S) 438321936Shselasky#define FW_RI_RES_WR_IQANUS_G(x) \ 439321936Shselasky (((x) >> FW_RI_RES_WR_IQANUS_S) & FW_RI_RES_WR_IQANUS_M) 440321936Shselasky#define FW_RI_RES_WR_IQANUS_F FW_RI_RES_WR_IQANUS_V(1U) 441321936Shselasky 442321936Shselasky#define FW_RI_RES_WR_IQANUD_S 12 443321936Shselasky#define FW_RI_RES_WR_IQANUD_M 0x3 444321936Shselasky#define FW_RI_RES_WR_IQANUD_V(x) ((x) << FW_RI_RES_WR_IQANUD_S) 445321936Shselasky#define FW_RI_RES_WR_IQANUD_G(x) \ 446321936Shselasky (((x) >> FW_RI_RES_WR_IQANUD_S) & FW_RI_RES_WR_IQANUD_M) 447321936Shselasky 448321936Shselasky#define FW_RI_RES_WR_IQANDSTINDEX_S 0 449321936Shselasky#define FW_RI_RES_WR_IQANDSTINDEX_M 0xfff 450321936Shselasky#define FW_RI_RES_WR_IQANDSTINDEX_V(x) ((x) << FW_RI_RES_WR_IQANDSTINDEX_S) 451321936Shselasky#define FW_RI_RES_WR_IQANDSTINDEX_G(x) \ 452321936Shselasky (((x) >> FW_RI_RES_WR_IQANDSTINDEX_S) & FW_RI_RES_WR_IQANDSTINDEX_M) 453321936Shselasky 454321936Shselasky#define FW_RI_RES_WR_IQDROPRSS_S 15 455321936Shselasky#define FW_RI_RES_WR_IQDROPRSS_M 0x1 456321936Shselasky#define FW_RI_RES_WR_IQDROPRSS_V(x) ((x) << FW_RI_RES_WR_IQDROPRSS_S) 457321936Shselasky#define FW_RI_RES_WR_IQDROPRSS_G(x) \ 458321936Shselasky (((x) >> FW_RI_RES_WR_IQDROPRSS_S) & FW_RI_RES_WR_IQDROPRSS_M) 459321936Shselasky#define FW_RI_RES_WR_IQDROPRSS_F FW_RI_RES_WR_IQDROPRSS_V(1U) 460321936Shselasky 461321936Shselasky#define FW_RI_RES_WR_IQGTSMODE_S 14 462321936Shselasky#define FW_RI_RES_WR_IQGTSMODE_M 0x1 463321936Shselasky#define FW_RI_RES_WR_IQGTSMODE_V(x) ((x) << FW_RI_RES_WR_IQGTSMODE_S) 464321936Shselasky#define FW_RI_RES_WR_IQGTSMODE_G(x) \ 465321936Shselasky (((x) >> FW_RI_RES_WR_IQGTSMODE_S) & FW_RI_RES_WR_IQGTSMODE_M) 466321936Shselasky#define FW_RI_RES_WR_IQGTSMODE_F FW_RI_RES_WR_IQGTSMODE_V(1U) 467321936Shselasky 468321936Shselasky#define FW_RI_RES_WR_IQPCIECH_S 12 469321936Shselasky#define FW_RI_RES_WR_IQPCIECH_M 0x3 470321936Shselasky#define FW_RI_RES_WR_IQPCIECH_V(x) ((x) << FW_RI_RES_WR_IQPCIECH_S) 471321936Shselasky#define FW_RI_RES_WR_IQPCIECH_G(x) \ 472321936Shselasky (((x) >> FW_RI_RES_WR_IQPCIECH_S) & FW_RI_RES_WR_IQPCIECH_M) 473321936Shselasky 474321936Shselasky#define FW_RI_RES_WR_IQDCAEN_S 11 475321936Shselasky#define FW_RI_RES_WR_IQDCAEN_M 0x1 476321936Shselasky#define FW_RI_RES_WR_IQDCAEN_V(x) ((x) << FW_RI_RES_WR_IQDCAEN_S) 477321936Shselasky#define FW_RI_RES_WR_IQDCAEN_G(x) \ 478321936Shselasky (((x) >> FW_RI_RES_WR_IQDCAEN_S) & FW_RI_RES_WR_IQDCAEN_M) 479321936Shselasky#define FW_RI_RES_WR_IQDCAEN_F FW_RI_RES_WR_IQDCAEN_V(1U) 480321936Shselasky 481321936Shselasky#define FW_RI_RES_WR_IQDCACPU_S 6 482321936Shselasky#define FW_RI_RES_WR_IQDCACPU_M 0x1f 483321936Shselasky#define FW_RI_RES_WR_IQDCACPU_V(x) ((x) << FW_RI_RES_WR_IQDCACPU_S) 484321936Shselasky#define FW_RI_RES_WR_IQDCACPU_G(x) \ 485321936Shselasky (((x) >> FW_RI_RES_WR_IQDCACPU_S) & FW_RI_RES_WR_IQDCACPU_M) 486321936Shselasky 487321936Shselasky#define FW_RI_RES_WR_IQINTCNTTHRESH_S 4 488321936Shselasky#define FW_RI_RES_WR_IQINTCNTTHRESH_M 0x3 489321936Shselasky#define FW_RI_RES_WR_IQINTCNTTHRESH_V(x) \ 490321936Shselasky ((x) << FW_RI_RES_WR_IQINTCNTTHRESH_S) 491321936Shselasky#define FW_RI_RES_WR_IQINTCNTTHRESH_G(x) \ 492321936Shselasky (((x) >> FW_RI_RES_WR_IQINTCNTTHRESH_S) & FW_RI_RES_WR_IQINTCNTTHRESH_M) 493321936Shselasky 494321936Shselasky#define FW_RI_RES_WR_IQO_S 3 495321936Shselasky#define FW_RI_RES_WR_IQO_M 0x1 496321936Shselasky#define FW_RI_RES_WR_IQO_V(x) ((x) << FW_RI_RES_WR_IQO_S) 497321936Shselasky#define FW_RI_RES_WR_IQO_G(x) \ 498321936Shselasky (((x) >> FW_RI_RES_WR_IQO_S) & FW_RI_RES_WR_IQO_M) 499321936Shselasky#define FW_RI_RES_WR_IQO_F FW_RI_RES_WR_IQO_V(1U) 500321936Shselasky 501321936Shselasky#define FW_RI_RES_WR_IQCPRIO_S 2 502321936Shselasky#define FW_RI_RES_WR_IQCPRIO_M 0x1 503321936Shselasky#define FW_RI_RES_WR_IQCPRIO_V(x) ((x) << FW_RI_RES_WR_IQCPRIO_S) 504321936Shselasky#define FW_RI_RES_WR_IQCPRIO_G(x) \ 505321936Shselasky (((x) >> FW_RI_RES_WR_IQCPRIO_S) & FW_RI_RES_WR_IQCPRIO_M) 506321936Shselasky#define FW_RI_RES_WR_IQCPRIO_F FW_RI_RES_WR_IQCPRIO_V(1U) 507321936Shselasky 508321936Shselasky#define FW_RI_RES_WR_IQESIZE_S 0 509321936Shselasky#define FW_RI_RES_WR_IQESIZE_M 0x3 510321936Shselasky#define FW_RI_RES_WR_IQESIZE_V(x) ((x) << FW_RI_RES_WR_IQESIZE_S) 511321936Shselasky#define FW_RI_RES_WR_IQESIZE_G(x) \ 512321936Shselasky (((x) >> FW_RI_RES_WR_IQESIZE_S) & FW_RI_RES_WR_IQESIZE_M) 513321936Shselasky 514321936Shselasky#define FW_RI_RES_WR_IQNS_S 31 515321936Shselasky#define FW_RI_RES_WR_IQNS_M 0x1 516321936Shselasky#define FW_RI_RES_WR_IQNS_V(x) ((x) << FW_RI_RES_WR_IQNS_S) 517321936Shselasky#define FW_RI_RES_WR_IQNS_G(x) \ 518321936Shselasky (((x) >> FW_RI_RES_WR_IQNS_S) & FW_RI_RES_WR_IQNS_M) 519321936Shselasky#define FW_RI_RES_WR_IQNS_F FW_RI_RES_WR_IQNS_V(1U) 520321936Shselasky 521321936Shselasky#define FW_RI_RES_WR_IQRO_S 30 522321936Shselasky#define FW_RI_RES_WR_IQRO_M 0x1 523321936Shselasky#define FW_RI_RES_WR_IQRO_V(x) ((x) << FW_RI_RES_WR_IQRO_S) 524321936Shselasky#define FW_RI_RES_WR_IQRO_G(x) \ 525321936Shselasky (((x) >> FW_RI_RES_WR_IQRO_S) & FW_RI_RES_WR_IQRO_M) 526321936Shselasky#define FW_RI_RES_WR_IQRO_F FW_RI_RES_WR_IQRO_V(1U) 527321936Shselasky 528321936Shselaskystruct fw_ri_rdma_write_wr { 529321936Shselasky __u8 opcode; 530321936Shselasky __u8 flags; 531321936Shselasky __u16 wrid; 532321936Shselasky __u8 r1[3]; 533321936Shselasky __u8 len16; 534321936Shselasky __be64 r2; 535321936Shselasky __be32 plen; 536321936Shselasky __be32 stag_sink; 537321936Shselasky __be64 to_sink; 538321936Shselasky#ifndef C99_NOT_SUPPORTED 539321936Shselasky union { 540321936Shselasky struct fw_ri_immd immd_src[0]; 541321936Shselasky struct fw_ri_isgl isgl_src[0]; 542321936Shselasky } u; 543321936Shselasky#endif 544321936Shselasky}; 545321936Shselasky 546321936Shselaskystruct fw_ri_send_wr { 547321936Shselasky __u8 opcode; 548321936Shselasky __u8 flags; 549321936Shselasky __u16 wrid; 550321936Shselasky __u8 r1[3]; 551321936Shselasky __u8 len16; 552321936Shselasky __be32 sendop_pkd; 553321936Shselasky __be32 stag_inv; 554321936Shselasky __be32 plen; 555321936Shselasky __be32 r3; 556321936Shselasky __be64 r4; 557321936Shselasky#ifndef C99_NOT_SUPPORTED 558321936Shselasky union { 559321936Shselasky struct fw_ri_immd immd_src[0]; 560321936Shselasky struct fw_ri_isgl isgl_src[0]; 561321936Shselasky } u; 562321936Shselasky#endif 563321936Shselasky}; 564321936Shselasky 565321936Shselasky#define FW_RI_SEND_WR_SENDOP_S 0 566321936Shselasky#define FW_RI_SEND_WR_SENDOP_M 0xf 567321936Shselasky#define FW_RI_SEND_WR_SENDOP_V(x) ((x) << FW_RI_SEND_WR_SENDOP_S) 568321936Shselasky#define FW_RI_SEND_WR_SENDOP_G(x) \ 569321936Shselasky (((x) >> FW_RI_SEND_WR_SENDOP_S) & FW_RI_SEND_WR_SENDOP_M) 570321936Shselasky 571321936Shselaskystruct fw_ri_rdma_read_wr { 572321936Shselasky __u8 opcode; 573321936Shselasky __u8 flags; 574321936Shselasky __u16 wrid; 575321936Shselasky __u8 r1[3]; 576321936Shselasky __u8 len16; 577321936Shselasky __be64 r2; 578321936Shselasky __be32 stag_sink; 579321936Shselasky __be32 to_sink_hi; 580321936Shselasky __be32 to_sink_lo; 581321936Shselasky __be32 plen; 582321936Shselasky __be32 stag_src; 583321936Shselasky __be32 to_src_hi; 584321936Shselasky __be32 to_src_lo; 585321936Shselasky __be32 r5; 586321936Shselasky}; 587321936Shselasky 588321936Shselaskystruct fw_ri_recv_wr { 589321936Shselasky __u8 opcode; 590321936Shselasky __u8 r1; 591321936Shselasky __u16 wrid; 592321936Shselasky __u8 r2[3]; 593321936Shselasky __u8 len16; 594321936Shselasky struct fw_ri_isgl isgl; 595321936Shselasky}; 596321936Shselasky 597321936Shselaskystruct fw_ri_bind_mw_wr { 598321936Shselasky __u8 opcode; 599321936Shselasky __u8 flags; 600321936Shselasky __u16 wrid; 601321936Shselasky __u8 r1[3]; 602321936Shselasky __u8 len16; 603321936Shselasky __u8 qpbinde_to_dcacpu; 604321936Shselasky __u8 pgsz_shift; 605321936Shselasky __u8 addr_type; 606321936Shselasky __u8 mem_perms; 607321936Shselasky __be32 stag_mr; 608321936Shselasky __be32 stag_mw; 609321936Shselasky __be32 r3; 610321936Shselasky __be64 len_mw; 611321936Shselasky __be64 va_fbo; 612321936Shselasky __be64 r4; 613321936Shselasky}; 614321936Shselasky 615321936Shselasky#define FW_RI_BIND_MW_WR_QPBINDE_S 6 616321936Shselasky#define FW_RI_BIND_MW_WR_QPBINDE_M 0x1 617321936Shselasky#define FW_RI_BIND_MW_WR_QPBINDE_V(x) ((x) << FW_RI_BIND_MW_WR_QPBINDE_S) 618321936Shselasky#define FW_RI_BIND_MW_WR_QPBINDE_G(x) \ 619321936Shselasky (((x) >> FW_RI_BIND_MW_WR_QPBINDE_S) & FW_RI_BIND_MW_WR_QPBINDE_M) 620321936Shselasky#define FW_RI_BIND_MW_WR_QPBINDE_F FW_RI_BIND_MW_WR_QPBINDE_V(1U) 621321936Shselasky 622321936Shselasky#define FW_RI_BIND_MW_WR_NS_S 5 623321936Shselasky#define FW_RI_BIND_MW_WR_NS_M 0x1 624321936Shselasky#define FW_RI_BIND_MW_WR_NS_V(x) ((x) << FW_RI_BIND_MW_WR_NS_S) 625321936Shselasky#define FW_RI_BIND_MW_WR_NS_G(x) \ 626321936Shselasky (((x) >> FW_RI_BIND_MW_WR_NS_S) & FW_RI_BIND_MW_WR_NS_M) 627321936Shselasky#define FW_RI_BIND_MW_WR_NS_F FW_RI_BIND_MW_WR_NS_V(1U) 628321936Shselasky 629321936Shselasky#define FW_RI_BIND_MW_WR_DCACPU_S 0 630321936Shselasky#define FW_RI_BIND_MW_WR_DCACPU_M 0x1f 631321936Shselasky#define FW_RI_BIND_MW_WR_DCACPU_V(x) ((x) << FW_RI_BIND_MW_WR_DCACPU_S) 632321936Shselasky#define FW_RI_BIND_MW_WR_DCACPU_G(x) \ 633321936Shselasky (((x) >> FW_RI_BIND_MW_WR_DCACPU_S) & FW_RI_BIND_MW_WR_DCACPU_M) 634321936Shselasky 635321936Shselaskystruct fw_ri_fr_nsmr_wr { 636321936Shselasky __u8 opcode; 637321936Shselasky __u8 flags; 638321936Shselasky __u16 wrid; 639321936Shselasky __u8 r1[3]; 640321936Shselasky __u8 len16; 641321936Shselasky __u8 qpbinde_to_dcacpu; 642321936Shselasky __u8 pgsz_shift; 643321936Shselasky __u8 addr_type; 644321936Shselasky __u8 mem_perms; 645321936Shselasky __be32 stag; 646321936Shselasky __be32 len_hi; 647321936Shselasky __be32 len_lo; 648321936Shselasky __be32 va_hi; 649321936Shselasky __be32 va_lo_fbo; 650321936Shselasky}; 651321936Shselasky 652321936Shselasky#define FW_RI_FR_NSMR_WR_QPBINDE_S 6 653321936Shselasky#define FW_RI_FR_NSMR_WR_QPBINDE_M 0x1 654321936Shselasky#define FW_RI_FR_NSMR_WR_QPBINDE_V(x) ((x) << FW_RI_FR_NSMR_WR_QPBINDE_S) 655321936Shselasky#define FW_RI_FR_NSMR_WR_QPBINDE_G(x) \ 656321936Shselasky (((x) >> FW_RI_FR_NSMR_WR_QPBINDE_S) & FW_RI_FR_NSMR_WR_QPBINDE_M) 657321936Shselasky#define FW_RI_FR_NSMR_WR_QPBINDE_F FW_RI_FR_NSMR_WR_QPBINDE_V(1U) 658321936Shselasky 659321936Shselasky#define FW_RI_FR_NSMR_WR_NS_S 5 660321936Shselasky#define FW_RI_FR_NSMR_WR_NS_M 0x1 661321936Shselasky#define FW_RI_FR_NSMR_WR_NS_V(x) ((x) << FW_RI_FR_NSMR_WR_NS_S) 662321936Shselasky#define FW_RI_FR_NSMR_WR_NS_G(x) \ 663321936Shselasky (((x) >> FW_RI_FR_NSMR_WR_NS_S) & FW_RI_FR_NSMR_WR_NS_M) 664321936Shselasky#define FW_RI_FR_NSMR_WR_NS_F FW_RI_FR_NSMR_WR_NS_V(1U) 665321936Shselasky 666321936Shselasky#define FW_RI_FR_NSMR_WR_DCACPU_S 0 667321936Shselasky#define FW_RI_FR_NSMR_WR_DCACPU_M 0x1f 668321936Shselasky#define FW_RI_FR_NSMR_WR_DCACPU_V(x) ((x) << FW_RI_FR_NSMR_WR_DCACPU_S) 669321936Shselasky#define FW_RI_FR_NSMR_WR_DCACPU_G(x) \ 670321936Shselasky (((x) >> FW_RI_FR_NSMR_WR_DCACPU_S) & FW_RI_FR_NSMR_WR_DCACPU_M) 671321936Shselasky 672321936Shselaskystruct fw_ri_inv_lstag_wr { 673321936Shselasky __u8 opcode; 674321936Shselasky __u8 flags; 675321936Shselasky __u16 wrid; 676321936Shselasky __u8 r1[3]; 677321936Shselasky __u8 len16; 678321936Shselasky __be32 r2; 679321936Shselasky __be32 stag_inv; 680321936Shselasky}; 681321936Shselasky 682321936Shselaskyenum fw_ri_type { 683321936Shselasky FW_RI_TYPE_INIT, 684321936Shselasky FW_RI_TYPE_FINI, 685321936Shselasky FW_RI_TYPE_TERMINATE 686321936Shselasky}; 687321936Shselasky 688321936Shselaskyenum fw_ri_init_p2ptype { 689321936Shselasky FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 690321936Shselasky FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 691321936Shselasky FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 692321936Shselasky FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 693321936Shselasky FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 694321936Shselasky FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 695321936Shselasky FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 696321936Shselasky}; 697321936Shselasky 698321936Shselaskystruct fw_ri_wr { 699321936Shselasky __be32 op_compl; 700321936Shselasky __be32 flowid_len16; 701321936Shselasky __u64 cookie; 702321936Shselasky union fw_ri { 703321936Shselasky struct fw_ri_init { 704321936Shselasky __u8 type; 705321936Shselasky __u8 mpareqbit_p2ptype; 706321936Shselasky __u8 r4[2]; 707321936Shselasky __u8 mpa_attrs; 708321936Shselasky __u8 qp_caps; 709321936Shselasky __be16 nrqe; 710321936Shselasky __be32 pdid; 711321936Shselasky __be32 qpid; 712321936Shselasky __be32 sq_eqid; 713321936Shselasky __be32 rq_eqid; 714321936Shselasky __be32 scqid; 715321936Shselasky __be32 rcqid; 716321936Shselasky __be32 ord_max; 717321936Shselasky __be32 ird_max; 718321936Shselasky __be32 iss; 719321936Shselasky __be32 irs; 720321936Shselasky __be32 hwrqsize; 721321936Shselasky __be32 hwrqaddr; 722321936Shselasky __be64 r5; 723321936Shselasky union fw_ri_init_p2p { 724321936Shselasky struct fw_ri_rdma_write_wr write; 725321936Shselasky struct fw_ri_rdma_read_wr read; 726321936Shselasky struct fw_ri_send_wr send; 727321936Shselasky } u; 728321936Shselasky } init; 729321936Shselasky struct fw_ri_fini { 730321936Shselasky __u8 type; 731321936Shselasky __u8 r3[7]; 732321936Shselasky __be64 r4; 733321936Shselasky } fini; 734321936Shselasky struct fw_ri_terminate { 735321936Shselasky __u8 type; 736321936Shselasky __u8 r3[3]; 737321936Shselasky __be32 immdlen; 738321936Shselasky __u8 termmsg[40]; 739321936Shselasky } terminate; 740321936Shselasky } u; 741321936Shselasky}; 742321936Shselasky 743321936Shselasky#define FW_RI_WR_MPAREQBIT_S 7 744321936Shselasky#define FW_RI_WR_MPAREQBIT_M 0x1 745321936Shselasky#define FW_RI_WR_MPAREQBIT_V(x) ((x) << FW_RI_WR_MPAREQBIT_S) 746321936Shselasky#define FW_RI_WR_MPAREQBIT_G(x) \ 747321936Shselasky (((x) >> FW_RI_WR_MPAREQBIT_S) & FW_RI_WR_MPAREQBIT_M) 748321936Shselasky#define FW_RI_WR_MPAREQBIT_F FW_RI_WR_MPAREQBIT_V(1U) 749321936Shselasky 750321936Shselasky#define FW_RI_WR_P2PTYPE_S 0 751321936Shselasky#define FW_RI_WR_P2PTYPE_M 0xf 752321936Shselasky#define FW_RI_WR_P2PTYPE_V(x) ((x) << FW_RI_WR_P2PTYPE_S) 753321936Shselasky#define FW_RI_WR_P2PTYPE_G(x) \ 754321936Shselasky (((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M) 755321936Shselasky 756321936Shselasky#endif /* _T4FW_RI_API_H_ */ 757