1321936Shselasky/* 2321936Shselasky * This file is part of the Chelsio T4 Ethernet driver for Linux. 3321936Shselasky * 4321936Shselasky * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5321936Shselasky * 6321936Shselasky * This software is available to you under a choice of one of two 7321936Shselasky * licenses. You may choose to be licensed under the terms of the GNU 8321936Shselasky * General Public License (GPL) Version 2, available from the file 9321936Shselasky * COPYING in the main directory of this source tree, or the 10321936Shselasky * OpenIB.org BSD license below: 11321936Shselasky * 12321936Shselasky * Redistribution and use in source and binary forms, with or 13321936Shselasky * without modification, are permitted provided that the following 14321936Shselasky * conditions are met: 15321936Shselasky * 16321936Shselasky * - Redistributions of source code must retain the above 17321936Shselasky * copyright notice, this list of conditions and the following 18321936Shselasky * disclaimer. 19321936Shselasky * 20321936Shselasky * - Redistributions in binary form must reproduce the above 21321936Shselasky * copyright notice, this list of conditions and the following 22321936Shselasky * disclaimer in the documentation and/or other materials 23321936Shselasky * provided with the distribution. 24321936Shselasky * 25321936Shselasky * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26321936Shselasky * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27321936Shselasky * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28321936Shselasky * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29321936Shselasky * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30321936Shselasky * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31321936Shselasky * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32321936Shselasky * SOFTWARE. 33321936Shselasky */ 34321936Shselasky 35321936Shselasky#ifndef __T4_REGS_H 36321936Shselasky#define __T4_REGS_H 37321936Shselasky 38321936Shselasky#define MYPF_BASE 0x1b000 39321936Shselasky#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40321936Shselasky 41321936Shselasky#define PF0_BASE 0x1e000 42321936Shselasky#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43321936Shselasky 44321936Shselasky#define PF_STRIDE 0x400 45321936Shselasky#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46321936Shselasky#define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47321936Shselasky 48321936Shselasky#define MYPORT_BASE 0x1c000 49321936Shselasky#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50321936Shselasky 51321936Shselasky#define PORT0_BASE 0x20000 52321936Shselasky#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53321936Shselasky 54321936Shselasky#define PORT_STRIDE 0x2000 55321936Shselasky#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56321936Shselasky#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57321936Shselasky 58321936Shselasky#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59321936Shselasky#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60321936Shselasky 61321936Shselasky#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62321936Shselasky#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63321936Shselasky#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64321936Shselasky#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65321936Shselasky 66321936Shselasky#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 67321936Shselasky 68321936Shselasky#define SGE_PF_KDOORBELL_A 0x0 69321936Shselasky 70321936Shselasky#define QID_S 15 71321936Shselasky#define QID_V(x) ((x) << QID_S) 72321936Shselasky 73321936Shselasky#define DBPRIO_S 14 74321936Shselasky#define DBPRIO_V(x) ((x) << DBPRIO_S) 75321936Shselasky#define DBPRIO_F DBPRIO_V(1U) 76321936Shselasky 77321936Shselasky#define PIDX_S 0 78321936Shselasky#define PIDX_V(x) ((x) << PIDX_S) 79321936Shselasky 80321936Shselasky#define SGE_VF_KDOORBELL_A 0x0 81321936Shselasky 82321936Shselasky#define DBTYPE_S 13 83321936Shselasky#define DBTYPE_V(x) ((x) << DBTYPE_S) 84321936Shselasky#define DBTYPE_F DBTYPE_V(1U) 85321936Shselasky 86321936Shselasky#define PIDX_T5_S 0 87321936Shselasky#define PIDX_T5_M 0x1fffU 88321936Shselasky#define PIDX_T5_V(x) ((x) << PIDX_T5_S) 89321936Shselasky#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M) 90321936Shselasky 91321936Shselasky#define SGE_PF_GTS_A 0x4 92321936Shselasky 93321936Shselasky#define INGRESSQID_S 16 94321936Shselasky#define INGRESSQID_V(x) ((x) << INGRESSQID_S) 95321936Shselasky 96321936Shselasky#define TIMERREG_S 13 97321936Shselasky#define TIMERREG_V(x) ((x) << TIMERREG_S) 98321936Shselasky 99321936Shselasky#define SEINTARM_S 12 100321936Shselasky#define SEINTARM_V(x) ((x) << SEINTARM_S) 101321936Shselasky 102321936Shselasky#define CIDXINC_S 0 103321936Shselasky#define CIDXINC_M 0xfffU 104321936Shselasky#define CIDXINC_V(x) ((x) << CIDXINC_S) 105321936Shselasky 106321936Shselasky#define SGE_CONTROL_A 0x1008 107321936Shselasky#define SGE_CONTROL2_A 0x1124 108321936Shselasky 109321936Shselasky#define RXPKTCPLMODE_S 18 110321936Shselasky#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S) 111321936Shselasky#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U) 112321936Shselasky 113321936Shselasky#define EGRSTATUSPAGESIZE_S 17 114321936Shselasky#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S) 115321936Shselasky#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U) 116321936Shselasky 117321936Shselasky#define PKTSHIFT_S 10 118321936Shselasky#define PKTSHIFT_M 0x7U 119321936Shselasky#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S) 120321936Shselasky#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M) 121321936Shselasky 122321936Shselasky#define INGPCIEBOUNDARY_S 7 123321936Shselasky#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S) 124321936Shselasky 125321936Shselasky#define INGPADBOUNDARY_S 4 126321936Shselasky#define INGPADBOUNDARY_M 0x7U 127321936Shselasky#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S) 128321936Shselasky#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M) 129321936Shselasky 130321936Shselasky#define EGRPCIEBOUNDARY_S 1 131321936Shselasky#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S) 132321936Shselasky 133321936Shselasky#define INGPACKBOUNDARY_S 16 134321936Shselasky#define INGPACKBOUNDARY_M 0x7U 135321936Shselasky#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S) 136321936Shselasky#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \ 137321936Shselasky & INGPACKBOUNDARY_M) 138321936Shselasky 139321936Shselasky#define VFIFO_ENABLE_S 10 140321936Shselasky#define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S) 141321936Shselasky#define VFIFO_ENABLE_F VFIFO_ENABLE_V(1U) 142321936Shselasky 143321936Shselasky#define SGE_DBVFIFO_BADDR_A 0x1138 144321936Shselasky 145321936Shselasky#define DBVFIFO_SIZE_S 6 146321936Shselasky#define DBVFIFO_SIZE_M 0xfffU 147321936Shselasky#define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M) 148321936Shselasky 149321936Shselasky#define T6_DBVFIFO_SIZE_S 0 150321936Shselasky#define T6_DBVFIFO_SIZE_M 0x1fffU 151321936Shselasky#define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M) 152321936Shselasky 153321936Shselasky#define GLOBALENABLE_S 0 154321936Shselasky#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S) 155321936Shselasky#define GLOBALENABLE_F GLOBALENABLE_V(1U) 156321936Shselasky 157321936Shselasky#define SGE_HOST_PAGE_SIZE_A 0x100c 158321936Shselasky 159321936Shselasky#define HOSTPAGESIZEPF7_S 28 160321936Shselasky#define HOSTPAGESIZEPF7_M 0xfU 161321936Shselasky#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S) 162321936Shselasky#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M) 163321936Shselasky 164321936Shselasky#define HOSTPAGESIZEPF6_S 24 165321936Shselasky#define HOSTPAGESIZEPF6_M 0xfU 166321936Shselasky#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S) 167321936Shselasky#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M) 168321936Shselasky 169321936Shselasky#define HOSTPAGESIZEPF5_S 20 170321936Shselasky#define HOSTPAGESIZEPF5_M 0xfU 171321936Shselasky#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S) 172321936Shselasky#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M) 173321936Shselasky 174321936Shselasky#define HOSTPAGESIZEPF4_S 16 175321936Shselasky#define HOSTPAGESIZEPF4_M 0xfU 176321936Shselasky#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S) 177321936Shselasky#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M) 178321936Shselasky 179321936Shselasky#define HOSTPAGESIZEPF3_S 12 180321936Shselasky#define HOSTPAGESIZEPF3_M 0xfU 181321936Shselasky#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S) 182321936Shselasky#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M) 183321936Shselasky 184321936Shselasky#define HOSTPAGESIZEPF2_S 8 185321936Shselasky#define HOSTPAGESIZEPF2_M 0xfU 186321936Shselasky#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S) 187321936Shselasky#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M) 188321936Shselasky 189321936Shselasky#define HOSTPAGESIZEPF1_S 4 190321936Shselasky#define HOSTPAGESIZEPF1_M 0xfU 191321936Shselasky#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S) 192321936Shselasky#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M) 193321936Shselasky 194321936Shselasky#define HOSTPAGESIZEPF0_S 0 195321936Shselasky#define HOSTPAGESIZEPF0_M 0xfU 196321936Shselasky#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S) 197321936Shselasky#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M) 198321936Shselasky 199321936Shselasky#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010 200321936Shselasky#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014 201321936Shselasky 202321936Shselasky#define QUEUESPERPAGEPF1_S 4 203321936Shselasky 204321936Shselasky#define QUEUESPERPAGEPF0_S 0 205321936Shselasky#define QUEUESPERPAGEPF0_M 0xfU 206321936Shselasky#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S) 207321936Shselasky#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M) 208321936Shselasky 209321936Shselasky#define SGE_INT_CAUSE1_A 0x1024 210321936Shselasky#define SGE_INT_CAUSE2_A 0x1030 211321936Shselasky#define SGE_INT_CAUSE3_A 0x103c 212321936Shselasky 213321936Shselasky#define ERR_FLM_DBP_S 31 214321936Shselasky#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S) 215321936Shselasky#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U) 216321936Shselasky 217321936Shselasky#define ERR_FLM_IDMA1_S 30 218321936Shselasky#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S) 219321936Shselasky#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U) 220321936Shselasky 221321936Shselasky#define ERR_FLM_IDMA0_S 29 222321936Shselasky#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S) 223321936Shselasky#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U) 224321936Shselasky 225321936Shselasky#define ERR_FLM_HINT_S 28 226321936Shselasky#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S) 227321936Shselasky#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U) 228321936Shselasky 229321936Shselasky#define ERR_PCIE_ERROR3_S 27 230321936Shselasky#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S) 231321936Shselasky#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U) 232321936Shselasky 233321936Shselasky#define ERR_PCIE_ERROR2_S 26 234321936Shselasky#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S) 235321936Shselasky#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U) 236321936Shselasky 237321936Shselasky#define ERR_PCIE_ERROR1_S 25 238321936Shselasky#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S) 239321936Shselasky#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U) 240321936Shselasky 241321936Shselasky#define ERR_PCIE_ERROR0_S 24 242321936Shselasky#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S) 243321936Shselasky#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U) 244321936Shselasky 245321936Shselasky#define ERR_CPL_EXCEED_IQE_SIZE_S 22 246321936Shselasky#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S) 247321936Shselasky#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U) 248321936Shselasky 249321936Shselasky#define ERR_INVALID_CIDX_INC_S 21 250321936Shselasky#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S) 251321936Shselasky#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U) 252321936Shselasky 253321936Shselasky#define ERR_CPL_OPCODE_0_S 19 254321936Shselasky#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S) 255321936Shselasky#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U) 256321936Shselasky 257321936Shselasky#define ERR_DROPPED_DB_S 18 258321936Shselasky#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S) 259321936Shselasky#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U) 260321936Shselasky 261321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID1_S 17 262321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S) 263321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U) 264321936Shselasky 265321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID0_S 16 266321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S) 267321936Shselasky#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U) 268321936Shselasky 269321936Shselasky#define ERR_BAD_DB_PIDX3_S 15 270321936Shselasky#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S) 271321936Shselasky#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U) 272321936Shselasky 273321936Shselasky#define ERR_BAD_DB_PIDX2_S 14 274321936Shselasky#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S) 275321936Shselasky#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U) 276321936Shselasky 277321936Shselasky#define ERR_BAD_DB_PIDX1_S 13 278321936Shselasky#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S) 279321936Shselasky#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U) 280321936Shselasky 281321936Shselasky#define ERR_BAD_DB_PIDX0_S 12 282321936Shselasky#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S) 283321936Shselasky#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U) 284321936Shselasky 285321936Shselasky#define ERR_ING_CTXT_PRIO_S 10 286321936Shselasky#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S) 287321936Shselasky#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U) 288321936Shselasky 289321936Shselasky#define ERR_EGR_CTXT_PRIO_S 9 290321936Shselasky#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S) 291321936Shselasky#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U) 292321936Shselasky 293321936Shselasky#define DBFIFO_HP_INT_S 8 294321936Shselasky#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S) 295321936Shselasky#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U) 296321936Shselasky 297321936Shselasky#define DBFIFO_LP_INT_S 7 298321936Shselasky#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S) 299321936Shselasky#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U) 300321936Shselasky 301321936Shselasky#define INGRESS_SIZE_ERR_S 5 302321936Shselasky#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S) 303321936Shselasky#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U) 304321936Shselasky 305321936Shselasky#define EGRESS_SIZE_ERR_S 4 306321936Shselasky#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S) 307321936Shselasky#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U) 308321936Shselasky 309321936Shselasky#define SGE_INT_ENABLE3_A 0x1040 310321936Shselasky#define SGE_FL_BUFFER_SIZE0_A 0x1044 311321936Shselasky#define SGE_FL_BUFFER_SIZE1_A 0x1048 312321936Shselasky#define SGE_FL_BUFFER_SIZE2_A 0x104c 313321936Shselasky#define SGE_FL_BUFFER_SIZE3_A 0x1050 314321936Shselasky#define SGE_FL_BUFFER_SIZE4_A 0x1054 315321936Shselasky#define SGE_FL_BUFFER_SIZE5_A 0x1058 316321936Shselasky#define SGE_FL_BUFFER_SIZE6_A 0x105c 317321936Shselasky#define SGE_FL_BUFFER_SIZE7_A 0x1060 318321936Shselasky#define SGE_FL_BUFFER_SIZE8_A 0x1064 319321936Shselasky 320321936Shselasky#define SGE_IMSG_CTXT_BADDR_A 0x1088 321321936Shselasky#define SGE_FLM_CACHE_BADDR_A 0x108c 322321936Shselasky#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0 323321936Shselasky 324321936Shselasky#define THRESHOLD_0_S 24 325321936Shselasky#define THRESHOLD_0_M 0x3fU 326321936Shselasky#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S) 327321936Shselasky#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M) 328321936Shselasky 329321936Shselasky#define THRESHOLD_1_S 16 330321936Shselasky#define THRESHOLD_1_M 0x3fU 331321936Shselasky#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S) 332321936Shselasky#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M) 333321936Shselasky 334321936Shselasky#define THRESHOLD_2_S 8 335321936Shselasky#define THRESHOLD_2_M 0x3fU 336321936Shselasky#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S) 337321936Shselasky#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M) 338321936Shselasky 339321936Shselasky#define THRESHOLD_3_S 0 340321936Shselasky#define THRESHOLD_3_M 0x3fU 341321936Shselasky#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S) 342321936Shselasky#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M) 343321936Shselasky 344321936Shselasky#define SGE_CONM_CTRL_A 0x1094 345321936Shselasky 346321936Shselasky#define EGRTHRESHOLD_S 8 347321936Shselasky#define EGRTHRESHOLD_M 0x3fU 348321936Shselasky#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S) 349321936Shselasky#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M) 350321936Shselasky 351321936Shselasky#define EGRTHRESHOLDPACKING_S 14 352321936Shselasky#define EGRTHRESHOLDPACKING_M 0x3fU 353321936Shselasky#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S) 354321936Shselasky#define EGRTHRESHOLDPACKING_G(x) \ 355321936Shselasky (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M) 356321936Shselasky 357321936Shselasky#define T6_EGRTHRESHOLDPACKING_S 16 358321936Shselasky#define T6_EGRTHRESHOLDPACKING_M 0xffU 359321936Shselasky#define T6_EGRTHRESHOLDPACKING_G(x) \ 360321936Shselasky (((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M) 361321936Shselasky 362321936Shselasky#define SGE_TIMESTAMP_LO_A 0x1098 363321936Shselasky#define SGE_TIMESTAMP_HI_A 0x109c 364321936Shselasky 365321936Shselasky#define TSOP_S 28 366321936Shselasky#define TSOP_M 0x3U 367321936Shselasky#define TSOP_V(x) ((x) << TSOP_S) 368321936Shselasky#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M) 369321936Shselasky 370321936Shselasky#define TSVAL_S 0 371321936Shselasky#define TSVAL_M 0xfffffffU 372321936Shselasky#define TSVAL_V(x) ((x) << TSVAL_S) 373321936Shselasky#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M) 374321936Shselasky 375321936Shselasky#define SGE_DBFIFO_STATUS_A 0x10a4 376321936Shselasky#define SGE_DBVFIFO_SIZE_A 0x113c 377321936Shselasky 378321936Shselasky#define HP_INT_THRESH_S 28 379321936Shselasky#define HP_INT_THRESH_M 0xfU 380321936Shselasky#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) 381321936Shselasky 382321936Shselasky#define LP_INT_THRESH_S 12 383321936Shselasky#define LP_INT_THRESH_M 0xfU 384321936Shselasky#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) 385321936Shselasky 386321936Shselasky#define SGE_DOORBELL_CONTROL_A 0x10a8 387321936Shselasky 388321936Shselasky#define NOCOALESCE_S 26 389321936Shselasky#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S) 390321936Shselasky#define NOCOALESCE_F NOCOALESCE_V(1U) 391321936Shselasky 392321936Shselasky#define ENABLE_DROP_S 13 393321936Shselasky#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) 394321936Shselasky#define ENABLE_DROP_F ENABLE_DROP_V(1U) 395321936Shselasky 396321936Shselasky#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8 397321936Shselasky 398321936Shselasky#define TIMERVALUE0_S 16 399321936Shselasky#define TIMERVALUE0_M 0xffffU 400321936Shselasky#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S) 401321936Shselasky#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M) 402321936Shselasky 403321936Shselasky#define TIMERVALUE1_S 0 404321936Shselasky#define TIMERVALUE1_M 0xffffU 405321936Shselasky#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S) 406321936Shselasky#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M) 407321936Shselasky 408321936Shselasky#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc 409321936Shselasky 410321936Shselasky#define TIMERVALUE2_S 16 411321936Shselasky#define TIMERVALUE2_M 0xffffU 412321936Shselasky#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S) 413321936Shselasky#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M) 414321936Shselasky 415321936Shselasky#define TIMERVALUE3_S 0 416321936Shselasky#define TIMERVALUE3_M 0xffffU 417321936Shselasky#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S) 418321936Shselasky#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M) 419321936Shselasky 420321936Shselasky#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0 421321936Shselasky 422321936Shselasky#define TIMERVALUE4_S 16 423321936Shselasky#define TIMERVALUE4_M 0xffffU 424321936Shselasky#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S) 425321936Shselasky#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M) 426321936Shselasky 427321936Shselasky#define TIMERVALUE5_S 0 428321936Shselasky#define TIMERVALUE5_M 0xffffU 429321936Shselasky#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S) 430321936Shselasky#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M) 431321936Shselasky 432321936Shselasky#define SGE_DEBUG_INDEX_A 0x10cc 433321936Shselasky#define SGE_DEBUG_DATA_HIGH_A 0x10d0 434321936Shselasky#define SGE_DEBUG_DATA_LOW_A 0x10d4 435321936Shselasky 436321936Shselasky#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8 437321936Shselasky#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc 438321936Shselasky#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8 439321936Shselasky 440321936Shselasky#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4 441321936Shselasky#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8 442321936Shselasky 443321936Shselasky#define SGE_ERROR_STATS_A 0x1100 444321936Shselasky 445321936Shselasky#define UNCAPTURED_ERROR_S 18 446321936Shselasky#define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S) 447321936Shselasky#define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U) 448321936Shselasky 449321936Shselasky#define ERROR_QID_VALID_S 17 450321936Shselasky#define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S) 451321936Shselasky#define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U) 452321936Shselasky 453321936Shselasky#define ERROR_QID_S 0 454321936Shselasky#define ERROR_QID_M 0x1ffffU 455321936Shselasky#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M) 456321936Shselasky 457321936Shselasky#define HP_INT_THRESH_S 28 458321936Shselasky#define HP_INT_THRESH_M 0xfU 459321936Shselasky#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S) 460321936Shselasky 461321936Shselasky#define HP_COUNT_S 16 462321936Shselasky#define HP_COUNT_M 0x7ffU 463321936Shselasky#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M) 464321936Shselasky 465321936Shselasky#define LP_INT_THRESH_S 12 466321936Shselasky#define LP_INT_THRESH_M 0xfU 467321936Shselasky#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S) 468321936Shselasky 469321936Shselasky#define LP_COUNT_S 0 470321936Shselasky#define LP_COUNT_M 0x7ffU 471321936Shselasky#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M) 472321936Shselasky 473321936Shselasky#define LP_INT_THRESH_T5_S 18 474321936Shselasky#define LP_INT_THRESH_T5_M 0xfffU 475321936Shselasky#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S) 476321936Shselasky 477321936Shselasky#define LP_COUNT_T5_S 0 478321936Shselasky#define LP_COUNT_T5_M 0x3ffffU 479321936Shselasky#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M) 480321936Shselasky 481321936Shselasky#define SGE_DOORBELL_CONTROL_A 0x10a8 482321936Shselasky 483321936Shselasky#define SGE_STAT_TOTAL_A 0x10e4 484321936Shselasky#define SGE_STAT_MATCH_A 0x10e8 485321936Shselasky#define SGE_STAT_CFG_A 0x10ec 486321936Shselasky 487321936Shselasky#define STATMODE_S 2 488321936Shselasky#define STATMODE_V(x) ((x) << STATMODE_S) 489321936Shselasky 490321936Shselasky#define STATSOURCE_T5_S 9 491321936Shselasky#define STATSOURCE_T5_M 0xfU 492321936Shselasky#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S) 493321936Shselasky#define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M) 494321936Shselasky 495321936Shselasky#define T6_STATMODE_S 0 496321936Shselasky#define T6_STATMODE_V(x) ((x) << T6_STATMODE_S) 497321936Shselasky 498321936Shselasky#define SGE_DBFIFO_STATUS2_A 0x1118 499321936Shselasky 500321936Shselasky#define HP_INT_THRESH_T5_S 10 501321936Shselasky#define HP_INT_THRESH_T5_M 0xfU 502321936Shselasky#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S) 503321936Shselasky 504321936Shselasky#define HP_COUNT_T5_S 0 505321936Shselasky#define HP_COUNT_T5_M 0x3ffU 506321936Shselasky#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M) 507321936Shselasky 508321936Shselasky#define ENABLE_DROP_S 13 509321936Shselasky#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S) 510321936Shselasky#define ENABLE_DROP_F ENABLE_DROP_V(1U) 511321936Shselasky 512321936Shselasky#define DROPPED_DB_S 0 513321936Shselasky#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S) 514321936Shselasky#define DROPPED_DB_F DROPPED_DB_V(1U) 515321936Shselasky 516321936Shselasky#define SGE_CTXT_CMD_A 0x11fc 517321936Shselasky#define SGE_DBQ_CTXT_BADDR_A 0x1084 518321936Shselasky 519321936Shselasky/* registers for module PCIE */ 520321936Shselasky#define PCIE_PF_CFG_A 0x40 521321936Shselasky 522321936Shselasky#define AIVEC_S 4 523321936Shselasky#define AIVEC_M 0x3ffU 524321936Shselasky#define AIVEC_V(x) ((x) << AIVEC_S) 525321936Shselasky 526321936Shselasky#define PCIE_PF_CLI_A 0x44 527321936Shselasky#define PCIE_INT_CAUSE_A 0x3004 528321936Shselasky 529321936Shselasky#define UNXSPLCPLERR_S 29 530321936Shselasky#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S) 531321936Shselasky#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U) 532321936Shselasky 533321936Shselasky#define PCIEPINT_S 28 534321936Shselasky#define PCIEPINT_V(x) ((x) << PCIEPINT_S) 535321936Shselasky#define PCIEPINT_F PCIEPINT_V(1U) 536321936Shselasky 537321936Shselasky#define PCIESINT_S 27 538321936Shselasky#define PCIESINT_V(x) ((x) << PCIESINT_S) 539321936Shselasky#define PCIESINT_F PCIESINT_V(1U) 540321936Shselasky 541321936Shselasky#define RPLPERR_S 26 542321936Shselasky#define RPLPERR_V(x) ((x) << RPLPERR_S) 543321936Shselasky#define RPLPERR_F RPLPERR_V(1U) 544321936Shselasky 545321936Shselasky#define RXWRPERR_S 25 546321936Shselasky#define RXWRPERR_V(x) ((x) << RXWRPERR_S) 547321936Shselasky#define RXWRPERR_F RXWRPERR_V(1U) 548321936Shselasky 549321936Shselasky#define RXCPLPERR_S 24 550321936Shselasky#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S) 551321936Shselasky#define RXCPLPERR_F RXCPLPERR_V(1U) 552321936Shselasky 553321936Shselasky#define PIOTAGPERR_S 23 554321936Shselasky#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S) 555321936Shselasky#define PIOTAGPERR_F PIOTAGPERR_V(1U) 556321936Shselasky 557321936Shselasky#define MATAGPERR_S 22 558321936Shselasky#define MATAGPERR_V(x) ((x) << MATAGPERR_S) 559321936Shselasky#define MATAGPERR_F MATAGPERR_V(1U) 560321936Shselasky 561321936Shselasky#define INTXCLRPERR_S 21 562321936Shselasky#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S) 563321936Shselasky#define INTXCLRPERR_F INTXCLRPERR_V(1U) 564321936Shselasky 565321936Shselasky#define FIDPERR_S 20 566321936Shselasky#define FIDPERR_V(x) ((x) << FIDPERR_S) 567321936Shselasky#define FIDPERR_F FIDPERR_V(1U) 568321936Shselasky 569321936Shselasky#define CFGSNPPERR_S 19 570321936Shselasky#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S) 571321936Shselasky#define CFGSNPPERR_F CFGSNPPERR_V(1U) 572321936Shselasky 573321936Shselasky#define HRSPPERR_S 18 574321936Shselasky#define HRSPPERR_V(x) ((x) << HRSPPERR_S) 575321936Shselasky#define HRSPPERR_F HRSPPERR_V(1U) 576321936Shselasky 577321936Shselasky#define HREQPERR_S 17 578321936Shselasky#define HREQPERR_V(x) ((x) << HREQPERR_S) 579321936Shselasky#define HREQPERR_F HREQPERR_V(1U) 580321936Shselasky 581321936Shselasky#define HCNTPERR_S 16 582321936Shselasky#define HCNTPERR_V(x) ((x) << HCNTPERR_S) 583321936Shselasky#define HCNTPERR_F HCNTPERR_V(1U) 584321936Shselasky 585321936Shselasky#define DRSPPERR_S 15 586321936Shselasky#define DRSPPERR_V(x) ((x) << DRSPPERR_S) 587321936Shselasky#define DRSPPERR_F DRSPPERR_V(1U) 588321936Shselasky 589321936Shselasky#define DREQPERR_S 14 590321936Shselasky#define DREQPERR_V(x) ((x) << DREQPERR_S) 591321936Shselasky#define DREQPERR_F DREQPERR_V(1U) 592321936Shselasky 593321936Shselasky#define DCNTPERR_S 13 594321936Shselasky#define DCNTPERR_V(x) ((x) << DCNTPERR_S) 595321936Shselasky#define DCNTPERR_F DCNTPERR_V(1U) 596321936Shselasky 597321936Shselasky#define CRSPPERR_S 12 598321936Shselasky#define CRSPPERR_V(x) ((x) << CRSPPERR_S) 599321936Shselasky#define CRSPPERR_F CRSPPERR_V(1U) 600321936Shselasky 601321936Shselasky#define CREQPERR_S 11 602321936Shselasky#define CREQPERR_V(x) ((x) << CREQPERR_S) 603321936Shselasky#define CREQPERR_F CREQPERR_V(1U) 604321936Shselasky 605321936Shselasky#define CCNTPERR_S 10 606321936Shselasky#define CCNTPERR_V(x) ((x) << CCNTPERR_S) 607321936Shselasky#define CCNTPERR_F CCNTPERR_V(1U) 608321936Shselasky 609321936Shselasky#define TARTAGPERR_S 9 610321936Shselasky#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S) 611321936Shselasky#define TARTAGPERR_F TARTAGPERR_V(1U) 612321936Shselasky 613321936Shselasky#define PIOREQPERR_S 8 614321936Shselasky#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S) 615321936Shselasky#define PIOREQPERR_F PIOREQPERR_V(1U) 616321936Shselasky 617321936Shselasky#define PIOCPLPERR_S 7 618321936Shselasky#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S) 619321936Shselasky#define PIOCPLPERR_F PIOCPLPERR_V(1U) 620321936Shselasky 621321936Shselasky#define MSIXDIPERR_S 6 622321936Shselasky#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S) 623321936Shselasky#define MSIXDIPERR_F MSIXDIPERR_V(1U) 624321936Shselasky 625321936Shselasky#define MSIXDATAPERR_S 5 626321936Shselasky#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S) 627321936Shselasky#define MSIXDATAPERR_F MSIXDATAPERR_V(1U) 628321936Shselasky 629321936Shselasky#define MSIXADDRHPERR_S 4 630321936Shselasky#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S) 631321936Shselasky#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U) 632321936Shselasky 633321936Shselasky#define MSIXADDRLPERR_S 3 634321936Shselasky#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S) 635321936Shselasky#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U) 636321936Shselasky 637321936Shselasky#define MSIDATAPERR_S 2 638321936Shselasky#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S) 639321936Shselasky#define MSIDATAPERR_F MSIDATAPERR_V(1U) 640321936Shselasky 641321936Shselasky#define MSIADDRHPERR_S 1 642321936Shselasky#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S) 643321936Shselasky#define MSIADDRHPERR_F MSIADDRHPERR_V(1U) 644321936Shselasky 645321936Shselasky#define MSIADDRLPERR_S 0 646321936Shselasky#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S) 647321936Shselasky#define MSIADDRLPERR_F MSIADDRLPERR_V(1U) 648321936Shselasky 649321936Shselasky#define READRSPERR_S 29 650321936Shselasky#define READRSPERR_V(x) ((x) << READRSPERR_S) 651321936Shselasky#define READRSPERR_F READRSPERR_V(1U) 652321936Shselasky 653321936Shselasky#define TRGT1GRPPERR_S 28 654321936Shselasky#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S) 655321936Shselasky#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U) 656321936Shselasky 657321936Shselasky#define IPSOTPERR_S 27 658321936Shselasky#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S) 659321936Shselasky#define IPSOTPERR_F IPSOTPERR_V(1U) 660321936Shselasky 661321936Shselasky#define IPRETRYPERR_S 26 662321936Shselasky#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S) 663321936Shselasky#define IPRETRYPERR_F IPRETRYPERR_V(1U) 664321936Shselasky 665321936Shselasky#define IPRXDATAGRPPERR_S 25 666321936Shselasky#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S) 667321936Shselasky#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U) 668321936Shselasky 669321936Shselasky#define IPRXHDRGRPPERR_S 24 670321936Shselasky#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S) 671321936Shselasky#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U) 672321936Shselasky 673321936Shselasky#define MAGRPPERR_S 22 674321936Shselasky#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S) 675321936Shselasky#define MAGRPPERR_F MAGRPPERR_V(1U) 676321936Shselasky 677321936Shselasky#define VFIDPERR_S 21 678321936Shselasky#define VFIDPERR_V(x) ((x) << VFIDPERR_S) 679321936Shselasky#define VFIDPERR_F VFIDPERR_V(1U) 680321936Shselasky 681321936Shselasky#define HREQWRPERR_S 16 682321936Shselasky#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S) 683321936Shselasky#define HREQWRPERR_F HREQWRPERR_V(1U) 684321936Shselasky 685321936Shselasky#define DREQWRPERR_S 13 686321936Shselasky#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S) 687321936Shselasky#define DREQWRPERR_F DREQWRPERR_V(1U) 688321936Shselasky 689321936Shselasky#define CREQRDPERR_S 11 690321936Shselasky#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S) 691321936Shselasky#define CREQRDPERR_F CREQRDPERR_V(1U) 692321936Shselasky 693321936Shselasky#define MSTTAGQPERR_S 10 694321936Shselasky#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S) 695321936Shselasky#define MSTTAGQPERR_F MSTTAGQPERR_V(1U) 696321936Shselasky 697321936Shselasky#define PIOREQGRPPERR_S 8 698321936Shselasky#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S) 699321936Shselasky#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U) 700321936Shselasky 701321936Shselasky#define PIOCPLGRPPERR_S 7 702321936Shselasky#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S) 703321936Shselasky#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U) 704321936Shselasky 705321936Shselasky#define MSIXSTIPERR_S 2 706321936Shselasky#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S) 707321936Shselasky#define MSIXSTIPERR_F MSIXSTIPERR_V(1U) 708321936Shselasky 709321936Shselasky#define MSTTIMEOUTPERR_S 1 710321936Shselasky#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S) 711321936Shselasky#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U) 712321936Shselasky 713321936Shselasky#define MSTGRPPERR_S 0 714321936Shselasky#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S) 715321936Shselasky#define MSTGRPPERR_F MSTGRPPERR_V(1U) 716321936Shselasky 717321936Shselasky#define PCIE_NONFAT_ERR_A 0x3010 718321936Shselasky#define PCIE_CFG_SPACE_REQ_A 0x3060 719321936Shselasky#define PCIE_CFG_SPACE_DATA_A 0x3064 720321936Shselasky#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068 721321936Shselasky 722321936Shselasky#define PCIEOFST_S 10 723321936Shselasky#define PCIEOFST_M 0x3fffffU 724321936Shselasky#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M) 725321936Shselasky 726321936Shselasky#define BIR_S 8 727321936Shselasky#define BIR_M 0x3U 728321936Shselasky#define BIR_V(x) ((x) << BIR_S) 729321936Shselasky#define BIR_G(x) (((x) >> BIR_S) & BIR_M) 730321936Shselasky 731321936Shselasky#define WINDOW_S 0 732321936Shselasky#define WINDOW_M 0xffU 733321936Shselasky#define WINDOW_V(x) ((x) << WINDOW_S) 734321936Shselasky#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M) 735321936Shselasky 736321936Shselasky#define PCIE_MEM_ACCESS_OFFSET_A 0x306c 737321936Shselasky 738321936Shselasky#define ENABLE_S 30 739321936Shselasky#define ENABLE_V(x) ((x) << ENABLE_S) 740321936Shselasky#define ENABLE_F ENABLE_V(1U) 741321936Shselasky 742321936Shselasky#define LOCALCFG_S 28 743321936Shselasky#define LOCALCFG_V(x) ((x) << LOCALCFG_S) 744321936Shselasky#define LOCALCFG_F LOCALCFG_V(1U) 745321936Shselasky 746321936Shselasky#define FUNCTION_S 12 747321936Shselasky#define FUNCTION_V(x) ((x) << FUNCTION_S) 748321936Shselasky 749321936Shselasky#define REGISTER_S 0 750321936Shselasky#define REGISTER_V(x) ((x) << REGISTER_S) 751321936Shselasky 752321936Shselasky#define T6_ENABLE_S 31 753321936Shselasky#define T6_ENABLE_V(x) ((x) << T6_ENABLE_S) 754321936Shselasky#define T6_ENABLE_F T6_ENABLE_V(1U) 755321936Shselasky 756321936Shselasky#define PFNUM_S 0 757321936Shselasky#define PFNUM_V(x) ((x) << PFNUM_S) 758321936Shselasky 759321936Shselasky#define PCIE_FW_A 0x30b8 760321936Shselasky#define PCIE_FW_PF_A 0x30bc 761321936Shselasky 762321936Shselasky#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908 763321936Shselasky 764321936Shselasky#define RNPP_S 31 765321936Shselasky#define RNPP_V(x) ((x) << RNPP_S) 766321936Shselasky#define RNPP_F RNPP_V(1U) 767321936Shselasky 768321936Shselasky#define RPCP_S 29 769321936Shselasky#define RPCP_V(x) ((x) << RPCP_S) 770321936Shselasky#define RPCP_F RPCP_V(1U) 771321936Shselasky 772321936Shselasky#define RCIP_S 27 773321936Shselasky#define RCIP_V(x) ((x) << RCIP_S) 774321936Shselasky#define RCIP_F RCIP_V(1U) 775321936Shselasky 776321936Shselasky#define RCCP_S 26 777321936Shselasky#define RCCP_V(x) ((x) << RCCP_S) 778321936Shselasky#define RCCP_F RCCP_V(1U) 779321936Shselasky 780321936Shselasky#define RFTP_S 23 781321936Shselasky#define RFTP_V(x) ((x) << RFTP_S) 782321936Shselasky#define RFTP_F RFTP_V(1U) 783321936Shselasky 784321936Shselasky#define PTRP_S 20 785321936Shselasky#define PTRP_V(x) ((x) << PTRP_S) 786321936Shselasky#define PTRP_F PTRP_V(1U) 787321936Shselasky 788321936Shselasky#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4 789321936Shselasky 790321936Shselasky#define TPCP_S 30 791321936Shselasky#define TPCP_V(x) ((x) << TPCP_S) 792321936Shselasky#define TPCP_F TPCP_V(1U) 793321936Shselasky 794321936Shselasky#define TNPP_S 29 795321936Shselasky#define TNPP_V(x) ((x) << TNPP_S) 796321936Shselasky#define TNPP_F TNPP_V(1U) 797321936Shselasky 798321936Shselasky#define TFTP_S 28 799321936Shselasky#define TFTP_V(x) ((x) << TFTP_S) 800321936Shselasky#define TFTP_F TFTP_V(1U) 801321936Shselasky 802321936Shselasky#define TCAP_S 27 803321936Shselasky#define TCAP_V(x) ((x) << TCAP_S) 804321936Shselasky#define TCAP_F TCAP_V(1U) 805321936Shselasky 806321936Shselasky#define TCIP_S 26 807321936Shselasky#define TCIP_V(x) ((x) << TCIP_S) 808321936Shselasky#define TCIP_F TCIP_V(1U) 809321936Shselasky 810321936Shselasky#define RCAP_S 25 811321936Shselasky#define RCAP_V(x) ((x) << RCAP_S) 812321936Shselasky#define RCAP_F RCAP_V(1U) 813321936Shselasky 814321936Shselasky#define PLUP_S 23 815321936Shselasky#define PLUP_V(x) ((x) << PLUP_S) 816321936Shselasky#define PLUP_F PLUP_V(1U) 817321936Shselasky 818321936Shselasky#define PLDN_S 22 819321936Shselasky#define PLDN_V(x) ((x) << PLDN_S) 820321936Shselasky#define PLDN_F PLDN_V(1U) 821321936Shselasky 822321936Shselasky#define OTDD_S 21 823321936Shselasky#define OTDD_V(x) ((x) << OTDD_S) 824321936Shselasky#define OTDD_F OTDD_V(1U) 825321936Shselasky 826321936Shselasky#define GTRP_S 20 827321936Shselasky#define GTRP_V(x) ((x) << GTRP_S) 828321936Shselasky#define GTRP_F GTRP_V(1U) 829321936Shselasky 830321936Shselasky#define RDPE_S 18 831321936Shselasky#define RDPE_V(x) ((x) << RDPE_S) 832321936Shselasky#define RDPE_F RDPE_V(1U) 833321936Shselasky 834321936Shselasky#define TDCE_S 17 835321936Shselasky#define TDCE_V(x) ((x) << TDCE_S) 836321936Shselasky#define TDCE_F TDCE_V(1U) 837321936Shselasky 838321936Shselasky#define TDUE_S 16 839321936Shselasky#define TDUE_V(x) ((x) << TDUE_S) 840321936Shselasky#define TDUE_F TDUE_V(1U) 841321936Shselasky 842321936Shselasky/* registers for module MC */ 843321936Shselasky#define MC_INT_CAUSE_A 0x7518 844321936Shselasky#define MC_P_INT_CAUSE_A 0x41318 845321936Shselasky 846321936Shselasky#define ECC_UE_INT_CAUSE_S 2 847321936Shselasky#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S) 848321936Shselasky#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U) 849321936Shselasky 850321936Shselasky#define ECC_CE_INT_CAUSE_S 1 851321936Shselasky#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S) 852321936Shselasky#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U) 853321936Shselasky 854321936Shselasky#define PERR_INT_CAUSE_S 0 855321936Shselasky#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S) 856321936Shselasky#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U) 857321936Shselasky 858321936Shselasky#define MC_ECC_STATUS_A 0x751c 859321936Shselasky#define MC_P_ECC_STATUS_A 0x4131c 860321936Shselasky 861321936Shselasky#define ECC_CECNT_S 16 862321936Shselasky#define ECC_CECNT_M 0xffffU 863321936Shselasky#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S) 864321936Shselasky#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M) 865321936Shselasky 866321936Shselasky#define ECC_UECNT_S 0 867321936Shselasky#define ECC_UECNT_M 0xffffU 868321936Shselasky#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S) 869321936Shselasky#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M) 870321936Shselasky 871321936Shselasky#define MC_BIST_CMD_A 0x7600 872321936Shselasky 873321936Shselasky#define START_BIST_S 31 874321936Shselasky#define START_BIST_V(x) ((x) << START_BIST_S) 875321936Shselasky#define START_BIST_F START_BIST_V(1U) 876321936Shselasky 877321936Shselasky#define BIST_CMD_GAP_S 8 878321936Shselasky#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S) 879321936Shselasky 880321936Shselasky#define BIST_OPCODE_S 0 881321936Shselasky#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S) 882321936Shselasky 883321936Shselasky#define MC_BIST_CMD_ADDR_A 0x7604 884321936Shselasky#define MC_BIST_CMD_LEN_A 0x7608 885321936Shselasky#define MC_BIST_DATA_PATTERN_A 0x760c 886321936Shselasky 887321936Shselasky#define MC_BIST_STATUS_RDATA_A 0x7688 888321936Shselasky 889321936Shselasky/* registers for module MA */ 890321936Shselasky#define MA_EDRAM0_BAR_A 0x77c0 891321936Shselasky 892321936Shselasky#define EDRAM0_BASE_S 16 893321936Shselasky#define EDRAM0_BASE_M 0xfffU 894321936Shselasky#define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M) 895321936Shselasky 896321936Shselasky#define EDRAM0_SIZE_S 0 897321936Shselasky#define EDRAM0_SIZE_M 0xfffU 898321936Shselasky#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S) 899321936Shselasky#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M) 900321936Shselasky 901321936Shselasky#define MA_EDRAM1_BAR_A 0x77c4 902321936Shselasky 903321936Shselasky#define EDRAM1_BASE_S 16 904321936Shselasky#define EDRAM1_BASE_M 0xfffU 905321936Shselasky#define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M) 906321936Shselasky 907321936Shselasky#define EDRAM1_SIZE_S 0 908321936Shselasky#define EDRAM1_SIZE_M 0xfffU 909321936Shselasky#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S) 910321936Shselasky#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M) 911321936Shselasky 912321936Shselasky#define MA_EXT_MEMORY_BAR_A 0x77c8 913321936Shselasky 914321936Shselasky#define EXT_MEM_BASE_S 16 915321936Shselasky#define EXT_MEM_BASE_M 0xfffU 916321936Shselasky#define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S) 917321936Shselasky#define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M) 918321936Shselasky 919321936Shselasky#define EXT_MEM_SIZE_S 0 920321936Shselasky#define EXT_MEM_SIZE_M 0xfffU 921321936Shselasky#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S) 922321936Shselasky#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M) 923321936Shselasky 924321936Shselasky#define MA_EXT_MEMORY1_BAR_A 0x7808 925321936Shselasky 926321936Shselasky#define EXT_MEM1_BASE_S 16 927321936Shselasky#define EXT_MEM1_BASE_M 0xfffU 928321936Shselasky#define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M) 929321936Shselasky 930321936Shselasky#define EXT_MEM1_SIZE_S 0 931321936Shselasky#define EXT_MEM1_SIZE_M 0xfffU 932321936Shselasky#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S) 933321936Shselasky#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M) 934321936Shselasky 935321936Shselasky#define MA_EXT_MEMORY0_BAR_A 0x77c8 936321936Shselasky 937321936Shselasky#define EXT_MEM0_BASE_S 16 938321936Shselasky#define EXT_MEM0_BASE_M 0xfffU 939321936Shselasky#define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M) 940321936Shselasky 941321936Shselasky#define EXT_MEM0_SIZE_S 0 942321936Shselasky#define EXT_MEM0_SIZE_M 0xfffU 943321936Shselasky#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S) 944321936Shselasky#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M) 945321936Shselasky 946321936Shselasky#define MA_TARGET_MEM_ENABLE_A 0x77d8 947321936Shselasky 948321936Shselasky#define EXT_MEM_ENABLE_S 2 949321936Shselasky#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S) 950321936Shselasky#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U) 951321936Shselasky 952321936Shselasky#define EDRAM1_ENABLE_S 1 953321936Shselasky#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S) 954321936Shselasky#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U) 955321936Shselasky 956321936Shselasky#define EDRAM0_ENABLE_S 0 957321936Shselasky#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S) 958321936Shselasky#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U) 959321936Shselasky 960321936Shselasky#define EXT_MEM1_ENABLE_S 4 961321936Shselasky#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S) 962321936Shselasky#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U) 963321936Shselasky 964321936Shselasky#define EXT_MEM0_ENABLE_S 2 965321936Shselasky#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S) 966321936Shselasky#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U) 967321936Shselasky 968321936Shselasky#define MA_INT_CAUSE_A 0x77e0 969321936Shselasky 970321936Shselasky#define MEM_PERR_INT_CAUSE_S 1 971321936Shselasky#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S) 972321936Shselasky#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U) 973321936Shselasky 974321936Shselasky#define MEM_WRAP_INT_CAUSE_S 0 975321936Shselasky#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S) 976321936Shselasky#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U) 977321936Shselasky 978321936Shselasky#define MA_INT_WRAP_STATUS_A 0x77e4 979321936Shselasky 980321936Shselasky#define MEM_WRAP_ADDRESS_S 4 981321936Shselasky#define MEM_WRAP_ADDRESS_M 0xfffffffU 982321936Shselasky#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M) 983321936Shselasky 984321936Shselasky#define MEM_WRAP_CLIENT_NUM_S 0 985321936Shselasky#define MEM_WRAP_CLIENT_NUM_M 0xfU 986321936Shselasky#define MEM_WRAP_CLIENT_NUM_G(x) \ 987321936Shselasky (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M) 988321936Shselasky 989321936Shselasky#define MA_PARITY_ERROR_STATUS_A 0x77f4 990321936Shselasky#define MA_PARITY_ERROR_STATUS1_A 0x77f4 991321936Shselasky#define MA_PARITY_ERROR_STATUS2_A 0x7804 992321936Shselasky 993321936Shselasky/* registers for module EDC_0 */ 994321936Shselasky#define EDC_0_BASE_ADDR 0x7900 995321936Shselasky 996321936Shselasky#define EDC_BIST_CMD_A 0x7904 997321936Shselasky#define EDC_BIST_CMD_ADDR_A 0x7908 998321936Shselasky#define EDC_BIST_CMD_LEN_A 0x790c 999321936Shselasky#define EDC_BIST_DATA_PATTERN_A 0x7910 1000321936Shselasky#define EDC_BIST_STATUS_RDATA_A 0x7928 1001321936Shselasky#define EDC_INT_CAUSE_A 0x7978 1002321936Shselasky 1003321936Shselasky#define ECC_UE_PAR_S 5 1004321936Shselasky#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S) 1005321936Shselasky#define ECC_UE_PAR_F ECC_UE_PAR_V(1U) 1006321936Shselasky 1007321936Shselasky#define ECC_CE_PAR_S 4 1008321936Shselasky#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S) 1009321936Shselasky#define ECC_CE_PAR_F ECC_CE_PAR_V(1U) 1010321936Shselasky 1011321936Shselasky#define PERR_PAR_CAUSE_S 3 1012321936Shselasky#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S) 1013321936Shselasky#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U) 1014321936Shselasky 1015321936Shselasky#define EDC_ECC_STATUS_A 0x797c 1016321936Shselasky 1017321936Shselasky/* registers for module EDC_1 */ 1018321936Shselasky#define EDC_1_BASE_ADDR 0x7980 1019321936Shselasky 1020321936Shselasky/* registers for module CIM */ 1021321936Shselasky#define CIM_BOOT_CFG_A 0x7b00 1022321936Shselasky#define CIM_SDRAM_BASE_ADDR_A 0x7b14 1023321936Shselasky#define CIM_SDRAM_ADDR_SIZE_A 0x7b18 1024321936Shselasky#define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c 1025321936Shselasky#define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20 1026321936Shselasky#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290 1027321936Shselasky 1028321936Shselasky#define BOOTADDR_M 0xffffff00U 1029321936Shselasky 1030321936Shselasky#define UPCRST_S 0 1031321936Shselasky#define UPCRST_V(x) ((x) << UPCRST_S) 1032321936Shselasky#define UPCRST_F UPCRST_V(1U) 1033321936Shselasky 1034321936Shselasky#define CIM_PF_MAILBOX_DATA_A 0x240 1035321936Shselasky#define CIM_PF_MAILBOX_CTRL_A 0x280 1036321936Shselasky 1037321936Shselasky#define MBMSGVALID_S 3 1038321936Shselasky#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S) 1039321936Shselasky#define MBMSGVALID_F MBMSGVALID_V(1U) 1040321936Shselasky 1041321936Shselasky#define MBINTREQ_S 2 1042321936Shselasky#define MBINTREQ_V(x) ((x) << MBINTREQ_S) 1043321936Shselasky#define MBINTREQ_F MBINTREQ_V(1U) 1044321936Shselasky 1045321936Shselasky#define MBOWNER_S 0 1046321936Shselasky#define MBOWNER_M 0x3U 1047321936Shselasky#define MBOWNER_V(x) ((x) << MBOWNER_S) 1048321936Shselasky#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M) 1049321936Shselasky 1050321936Shselasky#define CIM_PF_HOST_INT_ENABLE_A 0x288 1051321936Shselasky 1052321936Shselasky#define MBMSGRDYINTEN_S 19 1053321936Shselasky#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S) 1054321936Shselasky#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U) 1055321936Shselasky 1056321936Shselasky#define CIM_PF_HOST_INT_CAUSE_A 0x28c 1057321936Shselasky 1058321936Shselasky#define MBMSGRDYINT_S 19 1059321936Shselasky#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S) 1060321936Shselasky#define MBMSGRDYINT_F MBMSGRDYINT_V(1U) 1061321936Shselasky 1062321936Shselasky#define CIM_HOST_INT_CAUSE_A 0x7b2c 1063321936Shselasky 1064321936Shselasky#define TIEQOUTPARERRINT_S 20 1065321936Shselasky#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S) 1066321936Shselasky#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U) 1067321936Shselasky 1068321936Shselasky#define TIEQINPARERRINT_S 19 1069321936Shselasky#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S) 1070321936Shselasky#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U) 1071321936Shselasky 1072321936Shselasky#define PREFDROPINT_S 1 1073321936Shselasky#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S) 1074321936Shselasky#define PREFDROPINT_F PREFDROPINT_V(1U) 1075321936Shselasky 1076321936Shselasky#define UPACCNONZERO_S 0 1077321936Shselasky#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S) 1078321936Shselasky#define UPACCNONZERO_F UPACCNONZERO_V(1U) 1079321936Shselasky 1080321936Shselasky#define MBHOSTPARERR_S 18 1081321936Shselasky#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S) 1082321936Shselasky#define MBHOSTPARERR_F MBHOSTPARERR_V(1U) 1083321936Shselasky 1084321936Shselasky#define MBUPPARERR_S 17 1085321936Shselasky#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S) 1086321936Shselasky#define MBUPPARERR_F MBUPPARERR_V(1U) 1087321936Shselasky 1088321936Shselasky#define IBQTP0PARERR_S 16 1089321936Shselasky#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S) 1090321936Shselasky#define IBQTP0PARERR_F IBQTP0PARERR_V(1U) 1091321936Shselasky 1092321936Shselasky#define IBQTP1PARERR_S 15 1093321936Shselasky#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S) 1094321936Shselasky#define IBQTP1PARERR_F IBQTP1PARERR_V(1U) 1095321936Shselasky 1096321936Shselasky#define IBQULPPARERR_S 14 1097321936Shselasky#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S) 1098321936Shselasky#define IBQULPPARERR_F IBQULPPARERR_V(1U) 1099321936Shselasky 1100321936Shselasky#define IBQSGELOPARERR_S 13 1101321936Shselasky#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S) 1102321936Shselasky#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U) 1103321936Shselasky 1104321936Shselasky#define IBQSGEHIPARERR_S 12 1105321936Shselasky#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S) 1106321936Shselasky#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U) 1107321936Shselasky 1108321936Shselasky#define IBQNCSIPARERR_S 11 1109321936Shselasky#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S) 1110321936Shselasky#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U) 1111321936Shselasky 1112321936Shselasky#define OBQULP0PARERR_S 10 1113321936Shselasky#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S) 1114321936Shselasky#define OBQULP0PARERR_F OBQULP0PARERR_V(1U) 1115321936Shselasky 1116321936Shselasky#define OBQULP1PARERR_S 9 1117321936Shselasky#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S) 1118321936Shselasky#define OBQULP1PARERR_F OBQULP1PARERR_V(1U) 1119321936Shselasky 1120321936Shselasky#define OBQULP2PARERR_S 8 1121321936Shselasky#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S) 1122321936Shselasky#define OBQULP2PARERR_F OBQULP2PARERR_V(1U) 1123321936Shselasky 1124321936Shselasky#define OBQULP3PARERR_S 7 1125321936Shselasky#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S) 1126321936Shselasky#define OBQULP3PARERR_F OBQULP3PARERR_V(1U) 1127321936Shselasky 1128321936Shselasky#define OBQSGEPARERR_S 6 1129321936Shselasky#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S) 1130321936Shselasky#define OBQSGEPARERR_F OBQSGEPARERR_V(1U) 1131321936Shselasky 1132321936Shselasky#define OBQNCSIPARERR_S 5 1133321936Shselasky#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S) 1134321936Shselasky#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U) 1135321936Shselasky 1136321936Shselasky#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34 1137321936Shselasky 1138321936Shselasky#define EEPROMWRINT_S 30 1139321936Shselasky#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S) 1140321936Shselasky#define EEPROMWRINT_F EEPROMWRINT_V(1U) 1141321936Shselasky 1142321936Shselasky#define TIMEOUTMAINT_S 29 1143321936Shselasky#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S) 1144321936Shselasky#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U) 1145321936Shselasky 1146321936Shselasky#define TIMEOUTINT_S 28 1147321936Shselasky#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S) 1148321936Shselasky#define TIMEOUTINT_F TIMEOUTINT_V(1U) 1149321936Shselasky 1150321936Shselasky#define RSPOVRLOOKUPINT_S 27 1151321936Shselasky#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S) 1152321936Shselasky#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U) 1153321936Shselasky 1154321936Shselasky#define REQOVRLOOKUPINT_S 26 1155321936Shselasky#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S) 1156321936Shselasky#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U) 1157321936Shselasky 1158321936Shselasky#define BLKWRPLINT_S 25 1159321936Shselasky#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S) 1160321936Shselasky#define BLKWRPLINT_F BLKWRPLINT_V(1U) 1161321936Shselasky 1162321936Shselasky#define BLKRDPLINT_S 24 1163321936Shselasky#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S) 1164321936Shselasky#define BLKRDPLINT_F BLKRDPLINT_V(1U) 1165321936Shselasky 1166321936Shselasky#define SGLWRPLINT_S 23 1167321936Shselasky#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S) 1168321936Shselasky#define SGLWRPLINT_F SGLWRPLINT_V(1U) 1169321936Shselasky 1170321936Shselasky#define SGLRDPLINT_S 22 1171321936Shselasky#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S) 1172321936Shselasky#define SGLRDPLINT_F SGLRDPLINT_V(1U) 1173321936Shselasky 1174321936Shselasky#define BLKWRCTLINT_S 21 1175321936Shselasky#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S) 1176321936Shselasky#define BLKWRCTLINT_F BLKWRCTLINT_V(1U) 1177321936Shselasky 1178321936Shselasky#define BLKRDCTLINT_S 20 1179321936Shselasky#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S) 1180321936Shselasky#define BLKRDCTLINT_F BLKRDCTLINT_V(1U) 1181321936Shselasky 1182321936Shselasky#define SGLWRCTLINT_S 19 1183321936Shselasky#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S) 1184321936Shselasky#define SGLWRCTLINT_F SGLWRCTLINT_V(1U) 1185321936Shselasky 1186321936Shselasky#define SGLRDCTLINT_S 18 1187321936Shselasky#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S) 1188321936Shselasky#define SGLRDCTLINT_F SGLRDCTLINT_V(1U) 1189321936Shselasky 1190321936Shselasky#define BLKWREEPROMINT_S 17 1191321936Shselasky#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S) 1192321936Shselasky#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U) 1193321936Shselasky 1194321936Shselasky#define BLKRDEEPROMINT_S 16 1195321936Shselasky#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S) 1196321936Shselasky#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U) 1197321936Shselasky 1198321936Shselasky#define SGLWREEPROMINT_S 15 1199321936Shselasky#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S) 1200321936Shselasky#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U) 1201321936Shselasky 1202321936Shselasky#define SGLRDEEPROMINT_S 14 1203321936Shselasky#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S) 1204321936Shselasky#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U) 1205321936Shselasky 1206321936Shselasky#define BLKWRFLASHINT_S 13 1207321936Shselasky#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S) 1208321936Shselasky#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U) 1209321936Shselasky 1210321936Shselasky#define BLKRDFLASHINT_S 12 1211321936Shselasky#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S) 1212321936Shselasky#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U) 1213321936Shselasky 1214321936Shselasky#define SGLWRFLASHINT_S 11 1215321936Shselasky#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S) 1216321936Shselasky#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U) 1217321936Shselasky 1218321936Shselasky#define SGLRDFLASHINT_S 10 1219321936Shselasky#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S) 1220321936Shselasky#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U) 1221321936Shselasky 1222321936Shselasky#define BLKWRBOOTINT_S 9 1223321936Shselasky#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S) 1224321936Shselasky#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U) 1225321936Shselasky 1226321936Shselasky#define BLKRDBOOTINT_S 8 1227321936Shselasky#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S) 1228321936Shselasky#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U) 1229321936Shselasky 1230321936Shselasky#define SGLWRBOOTINT_S 7 1231321936Shselasky#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S) 1232321936Shselasky#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U) 1233321936Shselasky 1234321936Shselasky#define SGLRDBOOTINT_S 6 1235321936Shselasky#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S) 1236321936Shselasky#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U) 1237321936Shselasky 1238321936Shselasky#define ILLWRBEINT_S 5 1239321936Shselasky#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S) 1240321936Shselasky#define ILLWRBEINT_F ILLWRBEINT_V(1U) 1241321936Shselasky 1242321936Shselasky#define ILLRDBEINT_S 4 1243321936Shselasky#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S) 1244321936Shselasky#define ILLRDBEINT_F ILLRDBEINT_V(1U) 1245321936Shselasky 1246321936Shselasky#define ILLRDINT_S 3 1247321936Shselasky#define ILLRDINT_V(x) ((x) << ILLRDINT_S) 1248321936Shselasky#define ILLRDINT_F ILLRDINT_V(1U) 1249321936Shselasky 1250321936Shselasky#define ILLWRINT_S 2 1251321936Shselasky#define ILLWRINT_V(x) ((x) << ILLWRINT_S) 1252321936Shselasky#define ILLWRINT_F ILLWRINT_V(1U) 1253321936Shselasky 1254321936Shselasky#define ILLTRANSINT_S 1 1255321936Shselasky#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S) 1256321936Shselasky#define ILLTRANSINT_F ILLTRANSINT_V(1U) 1257321936Shselasky 1258321936Shselasky#define RSVDSPACEINT_S 0 1259321936Shselasky#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) 1260321936Shselasky#define RSVDSPACEINT_F RSVDSPACEINT_V(1U) 1261321936Shselasky 1262321936Shselasky/* registers for module TP */ 1263321936Shselasky#define DBGLAWHLF_S 23 1264321936Shselasky#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S) 1265321936Shselasky#define DBGLAWHLF_F DBGLAWHLF_V(1U) 1266321936Shselasky 1267321936Shselasky#define DBGLAWPTR_S 16 1268321936Shselasky#define DBGLAWPTR_M 0x7fU 1269321936Shselasky#define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M) 1270321936Shselasky 1271321936Shselasky#define DBGLAENABLE_S 12 1272321936Shselasky#define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S) 1273321936Shselasky#define DBGLAENABLE_F DBGLAENABLE_V(1U) 1274321936Shselasky 1275321936Shselasky#define DBGLARPTR_S 0 1276321936Shselasky#define DBGLARPTR_M 0x7fU 1277321936Shselasky#define DBGLARPTR_V(x) ((x) << DBGLARPTR_S) 1278321936Shselasky 1279321936Shselasky#define TP_DBG_LA_DATAL_A 0x7ed8 1280321936Shselasky#define TP_DBG_LA_CONFIG_A 0x7ed4 1281321936Shselasky#define TP_OUT_CONFIG_A 0x7d04 1282321936Shselasky#define TP_GLOBAL_CONFIG_A 0x7d08 1283321936Shselasky 1284321936Shselasky#define TP_CMM_TCB_BASE_A 0x7d10 1285321936Shselasky#define TP_CMM_MM_BASE_A 0x7d14 1286321936Shselasky#define TP_CMM_TIMER_BASE_A 0x7d18 1287321936Shselasky#define TP_PMM_TX_BASE_A 0x7d20 1288321936Shselasky#define TP_PMM_RX_BASE_A 0x7d28 1289321936Shselasky#define TP_PMM_RX_PAGE_SIZE_A 0x7d2c 1290321936Shselasky#define TP_PMM_RX_MAX_PAGE_A 0x7d30 1291321936Shselasky#define TP_PMM_TX_PAGE_SIZE_A 0x7d34 1292321936Shselasky#define TP_PMM_TX_MAX_PAGE_A 0x7d38 1293321936Shselasky#define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c 1294321936Shselasky 1295321936Shselasky#define PMRXNUMCHN_S 31 1296321936Shselasky#define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S) 1297321936Shselasky#define PMRXNUMCHN_F PMRXNUMCHN_V(1U) 1298321936Shselasky 1299321936Shselasky#define PMTXNUMCHN_S 30 1300321936Shselasky#define PMTXNUMCHN_M 0x3U 1301321936Shselasky#define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M) 1302321936Shselasky 1303321936Shselasky#define PMTXMAXPAGE_S 0 1304321936Shselasky#define PMTXMAXPAGE_M 0x1fffffU 1305321936Shselasky#define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M) 1306321936Shselasky 1307321936Shselasky#define PMRXMAXPAGE_S 0 1308321936Shselasky#define PMRXMAXPAGE_M 0x1fffffU 1309321936Shselasky#define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M) 1310321936Shselasky 1311321936Shselasky#define DBGLAMODE_S 14 1312321936Shselasky#define DBGLAMODE_M 0x3U 1313321936Shselasky#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M) 1314321936Shselasky 1315321936Shselasky#define FIVETUPLELOOKUP_S 17 1316321936Shselasky#define FIVETUPLELOOKUP_M 0x3U 1317321936Shselasky#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S) 1318321936Shselasky#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M) 1319321936Shselasky 1320321936Shselasky#define TP_PARA_REG2_A 0x7d68 1321321936Shselasky 1322321936Shselasky#define MAXRXDATA_S 16 1323321936Shselasky#define MAXRXDATA_M 0xffffU 1324321936Shselasky#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M) 1325321936Shselasky 1326321936Shselasky#define TP_TIMER_RESOLUTION_A 0x7d90 1327321936Shselasky 1328321936Shselasky#define TIMERRESOLUTION_S 16 1329321936Shselasky#define TIMERRESOLUTION_M 0xffU 1330321936Shselasky#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M) 1331321936Shselasky 1332321936Shselasky#define TIMESTAMPRESOLUTION_S 8 1333321936Shselasky#define TIMESTAMPRESOLUTION_M 0xffU 1334321936Shselasky#define TIMESTAMPRESOLUTION_G(x) \ 1335321936Shselasky (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M) 1336321936Shselasky 1337321936Shselasky#define DELAYEDACKRESOLUTION_S 0 1338321936Shselasky#define DELAYEDACKRESOLUTION_M 0xffU 1339321936Shselasky#define DELAYEDACKRESOLUTION_G(x) \ 1340321936Shselasky (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M) 1341321936Shselasky 1342321936Shselasky#define TP_SHIFT_CNT_A 0x7dc0 1343321936Shselasky#define TP_RXT_MIN_A 0x7d98 1344321936Shselasky#define TP_RXT_MAX_A 0x7d9c 1345321936Shselasky#define TP_PERS_MIN_A 0x7da0 1346321936Shselasky#define TP_PERS_MAX_A 0x7da4 1347321936Shselasky#define TP_KEEP_IDLE_A 0x7da8 1348321936Shselasky#define TP_KEEP_INTVL_A 0x7dac 1349321936Shselasky#define TP_INIT_SRTT_A 0x7db0 1350321936Shselasky#define TP_DACK_TIMER_A 0x7db4 1351321936Shselasky#define TP_FINWAIT2_TIMER_A 0x7db8 1352321936Shselasky 1353321936Shselasky#define INITSRTT_S 0 1354321936Shselasky#define INITSRTT_M 0xffffU 1355321936Shselasky#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M) 1356321936Shselasky 1357321936Shselasky#define PERSMAX_S 0 1358321936Shselasky#define PERSMAX_M 0x3fffffffU 1359321936Shselasky#define PERSMAX_V(x) ((x) << PERSMAX_S) 1360321936Shselasky#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M) 1361321936Shselasky 1362321936Shselasky#define SYNSHIFTMAX_S 24 1363321936Shselasky#define SYNSHIFTMAX_M 0xffU 1364321936Shselasky#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S) 1365321936Shselasky#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M) 1366321936Shselasky 1367321936Shselasky#define RXTSHIFTMAXR1_S 20 1368321936Shselasky#define RXTSHIFTMAXR1_M 0xfU 1369321936Shselasky#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S) 1370321936Shselasky#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M) 1371321936Shselasky 1372321936Shselasky#define RXTSHIFTMAXR2_S 16 1373321936Shselasky#define RXTSHIFTMAXR2_M 0xfU 1374321936Shselasky#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S) 1375321936Shselasky#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M) 1376321936Shselasky 1377321936Shselasky#define PERSHIFTBACKOFFMAX_S 12 1378321936Shselasky#define PERSHIFTBACKOFFMAX_M 0xfU 1379321936Shselasky#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S) 1380321936Shselasky#define PERSHIFTBACKOFFMAX_G(x) \ 1381321936Shselasky (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M) 1382321936Shselasky 1383321936Shselasky#define PERSHIFTMAX_S 8 1384321936Shselasky#define PERSHIFTMAX_M 0xfU 1385321936Shselasky#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S) 1386321936Shselasky#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M) 1387321936Shselasky 1388321936Shselasky#define KEEPALIVEMAXR1_S 4 1389321936Shselasky#define KEEPALIVEMAXR1_M 0xfU 1390321936Shselasky#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S) 1391321936Shselasky#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M) 1392321936Shselasky 1393321936Shselasky#define KEEPALIVEMAXR2_S 0 1394321936Shselasky#define KEEPALIVEMAXR2_M 0xfU 1395321936Shselasky#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S) 1396321936Shselasky#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M) 1397321936Shselasky 1398321936Shselasky#define ROWINDEX_S 16 1399321936Shselasky#define ROWINDEX_V(x) ((x) << ROWINDEX_S) 1400321936Shselasky 1401321936Shselasky#define TP_CCTRL_TABLE_A 0x7ddc 1402321936Shselasky#define TP_MTU_TABLE_A 0x7de4 1403321936Shselasky 1404321936Shselasky#define MTUINDEX_S 24 1405321936Shselasky#define MTUINDEX_V(x) ((x) << MTUINDEX_S) 1406321936Shselasky 1407321936Shselasky#define MTUWIDTH_S 16 1408321936Shselasky#define MTUWIDTH_M 0xfU 1409321936Shselasky#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S) 1410321936Shselasky#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M) 1411321936Shselasky 1412321936Shselasky#define MTUVALUE_S 0 1413321936Shselasky#define MTUVALUE_M 0x3fffU 1414321936Shselasky#define MTUVALUE_V(x) ((x) << MTUVALUE_S) 1415321936Shselasky#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M) 1416321936Shselasky 1417321936Shselasky#define TP_RSS_LKP_TABLE_A 0x7dec 1418321936Shselasky#define TP_CMM_MM_RX_FLST_BASE_A 0x7e60 1419321936Shselasky#define TP_CMM_MM_TX_FLST_BASE_A 0x7e64 1420321936Shselasky#define TP_CMM_MM_PS_FLST_BASE_A 0x7e68 1421321936Shselasky 1422321936Shselasky#define LKPTBLROWVLD_S 31 1423321936Shselasky#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S) 1424321936Shselasky#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U) 1425321936Shselasky 1426321936Shselasky#define LKPTBLQUEUE1_S 10 1427321936Shselasky#define LKPTBLQUEUE1_M 0x3ffU 1428321936Shselasky#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M) 1429321936Shselasky 1430321936Shselasky#define LKPTBLQUEUE0_S 0 1431321936Shselasky#define LKPTBLQUEUE0_M 0x3ffU 1432321936Shselasky#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M) 1433321936Shselasky 1434321936Shselasky#define TP_PIO_ADDR_A 0x7e40 1435321936Shselasky#define TP_PIO_DATA_A 0x7e44 1436321936Shselasky#define TP_MIB_INDEX_A 0x7e50 1437321936Shselasky#define TP_MIB_DATA_A 0x7e54 1438321936Shselasky#define TP_INT_CAUSE_A 0x7e74 1439321936Shselasky 1440321936Shselasky#define FLMTXFLSTEMPTY_S 30 1441321936Shselasky#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S) 1442321936Shselasky#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U) 1443321936Shselasky 1444321936Shselasky#define TP_TX_ORATE_A 0x7ebc 1445321936Shselasky 1446321936Shselasky#define OFDRATE3_S 24 1447321936Shselasky#define OFDRATE3_M 0xffU 1448321936Shselasky#define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M) 1449321936Shselasky 1450321936Shselasky#define OFDRATE2_S 16 1451321936Shselasky#define OFDRATE2_M 0xffU 1452321936Shselasky#define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M) 1453321936Shselasky 1454321936Shselasky#define OFDRATE1_S 8 1455321936Shselasky#define OFDRATE1_M 0xffU 1456321936Shselasky#define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M) 1457321936Shselasky 1458321936Shselasky#define OFDRATE0_S 0 1459321936Shselasky#define OFDRATE0_M 0xffU 1460321936Shselasky#define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M) 1461321936Shselasky 1462321936Shselasky#define TP_TX_TRATE_A 0x7ed0 1463321936Shselasky 1464321936Shselasky#define TNLRATE3_S 24 1465321936Shselasky#define TNLRATE3_M 0xffU 1466321936Shselasky#define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M) 1467321936Shselasky 1468321936Shselasky#define TNLRATE2_S 16 1469321936Shselasky#define TNLRATE2_M 0xffU 1470321936Shselasky#define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M) 1471321936Shselasky 1472321936Shselasky#define TNLRATE1_S 8 1473321936Shselasky#define TNLRATE1_M 0xffU 1474321936Shselasky#define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M) 1475321936Shselasky 1476321936Shselasky#define TNLRATE0_S 0 1477321936Shselasky#define TNLRATE0_M 0xffU 1478321936Shselasky#define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M) 1479321936Shselasky 1480321936Shselasky#define TP_VLAN_PRI_MAP_A 0x140 1481321936Shselasky 1482321936Shselasky#define FRAGMENTATION_S 9 1483321936Shselasky#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S) 1484321936Shselasky#define FRAGMENTATION_F FRAGMENTATION_V(1U) 1485321936Shselasky 1486321936Shselasky#define MPSHITTYPE_S 8 1487321936Shselasky#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S) 1488321936Shselasky#define MPSHITTYPE_F MPSHITTYPE_V(1U) 1489321936Shselasky 1490321936Shselasky#define MACMATCH_S 7 1491321936Shselasky#define MACMATCH_V(x) ((x) << MACMATCH_S) 1492321936Shselasky#define MACMATCH_F MACMATCH_V(1U) 1493321936Shselasky 1494321936Shselasky#define ETHERTYPE_S 6 1495321936Shselasky#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S) 1496321936Shselasky#define ETHERTYPE_F ETHERTYPE_V(1U) 1497321936Shselasky 1498321936Shselasky#define PROTOCOL_S 5 1499321936Shselasky#define PROTOCOL_V(x) ((x) << PROTOCOL_S) 1500321936Shselasky#define PROTOCOL_F PROTOCOL_V(1U) 1501321936Shselasky 1502321936Shselasky#define TOS_S 4 1503321936Shselasky#define TOS_V(x) ((x) << TOS_S) 1504321936Shselasky#define TOS_F TOS_V(1U) 1505321936Shselasky 1506321936Shselasky#define VLAN_S 3 1507321936Shselasky#define VLAN_V(x) ((x) << VLAN_S) 1508321936Shselasky#define VLAN_F VLAN_V(1U) 1509321936Shselasky 1510321936Shselasky#define VNIC_ID_S 2 1511321936Shselasky#define VNIC_ID_V(x) ((x) << VNIC_ID_S) 1512321936Shselasky#define VNIC_ID_F VNIC_ID_V(1U) 1513321936Shselasky 1514321936Shselasky#define PORT_S 1 1515321936Shselasky#define PORT_V(x) ((x) << PORT_S) 1516321936Shselasky#define PORT_F PORT_V(1U) 1517321936Shselasky 1518321936Shselasky#define FCOE_S 0 1519321936Shselasky#define FCOE_V(x) ((x) << FCOE_S) 1520321936Shselasky#define FCOE_F FCOE_V(1U) 1521321936Shselasky 1522321936Shselasky#define FILTERMODE_S 15 1523321936Shselasky#define FILTERMODE_V(x) ((x) << FILTERMODE_S) 1524321936Shselasky#define FILTERMODE_F FILTERMODE_V(1U) 1525321936Shselasky 1526321936Shselasky#define FCOEMASK_S 14 1527321936Shselasky#define FCOEMASK_V(x) ((x) << FCOEMASK_S) 1528321936Shselasky#define FCOEMASK_F FCOEMASK_V(1U) 1529321936Shselasky 1530321936Shselasky#define TP_INGRESS_CONFIG_A 0x141 1531321936Shselasky 1532321936Shselasky#define VNIC_S 11 1533321936Shselasky#define VNIC_V(x) ((x) << VNIC_S) 1534321936Shselasky#define VNIC_F VNIC_V(1U) 1535321936Shselasky 1536321936Shselasky#define CSUM_HAS_PSEUDO_HDR_S 10 1537321936Shselasky#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S) 1538321936Shselasky#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U) 1539321936Shselasky 1540321936Shselasky#define TP_MIB_MAC_IN_ERR_0_A 0x0 1541321936Shselasky#define TP_MIB_HDR_IN_ERR_0_A 0x4 1542321936Shselasky#define TP_MIB_TCP_IN_ERR_0_A 0x8 1543321936Shselasky#define TP_MIB_TCP_OUT_RST_A 0xc 1544321936Shselasky#define TP_MIB_TCP_IN_SEG_HI_A 0x10 1545321936Shselasky#define TP_MIB_TCP_IN_SEG_LO_A 0x11 1546321936Shselasky#define TP_MIB_TCP_OUT_SEG_HI_A 0x12 1547321936Shselasky#define TP_MIB_TCP_OUT_SEG_LO_A 0x13 1548321936Shselasky#define TP_MIB_TCP_RXT_SEG_HI_A 0x14 1549321936Shselasky#define TP_MIB_TCP_RXT_SEG_LO_A 0x15 1550321936Shselasky#define TP_MIB_TNL_CNG_DROP_0_A 0x18 1551321936Shselasky#define TP_MIB_OFD_CHN_DROP_0_A 0x1c 1552321936Shselasky#define TP_MIB_TCP_V6IN_ERR_0_A 0x28 1553321936Shselasky#define TP_MIB_TCP_V6OUT_RST_A 0x2c 1554321936Shselasky#define TP_MIB_OFD_ARP_DROP_A 0x36 1555321936Shselasky#define TP_MIB_CPL_IN_REQ_0_A 0x38 1556321936Shselasky#define TP_MIB_CPL_OUT_RSP_0_A 0x3c 1557321936Shselasky#define TP_MIB_TNL_DROP_0_A 0x44 1558321936Shselasky#define TP_MIB_FCOE_DDP_0_A 0x48 1559321936Shselasky#define TP_MIB_FCOE_DROP_0_A 0x4c 1560321936Shselasky#define TP_MIB_FCOE_BYTE_0_HI_A 0x50 1561321936Shselasky#define TP_MIB_OFD_VLN_DROP_0_A 0x58 1562321936Shselasky#define TP_MIB_USM_PKTS_A 0x5c 1563321936Shselasky#define TP_MIB_RQE_DFR_PKT_A 0x64 1564321936Shselasky 1565321936Shselasky#define ULP_TX_INT_CAUSE_A 0x8dcc 1566321936Shselasky#define ULP_TX_TPT_LLIMIT_A 0x8dd4 1567321936Shselasky#define ULP_TX_TPT_ULIMIT_A 0x8dd8 1568321936Shselasky#define ULP_TX_PBL_LLIMIT_A 0x8ddc 1569321936Shselasky#define ULP_TX_PBL_ULIMIT_A 0x8de0 1570321936Shselasky#define ULP_TX_ERR_TABLE_BASE_A 0x8e04 1571321936Shselasky 1572321936Shselasky#define PBL_BOUND_ERR_CH3_S 31 1573321936Shselasky#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S) 1574321936Shselasky#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U) 1575321936Shselasky 1576321936Shselasky#define PBL_BOUND_ERR_CH2_S 30 1577321936Shselasky#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S) 1578321936Shselasky#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U) 1579321936Shselasky 1580321936Shselasky#define PBL_BOUND_ERR_CH1_S 29 1581321936Shselasky#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S) 1582321936Shselasky#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U) 1583321936Shselasky 1584321936Shselasky#define PBL_BOUND_ERR_CH0_S 28 1585321936Shselasky#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S) 1586321936Shselasky#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U) 1587321936Shselasky 1588321936Shselasky#define PM_RX_INT_CAUSE_A 0x8fdc 1589321936Shselasky#define PM_RX_STAT_CONFIG_A 0x8fc8 1590321936Shselasky#define PM_RX_STAT_COUNT_A 0x8fcc 1591321936Shselasky#define PM_RX_STAT_LSB_A 0x8fd0 1592321936Shselasky#define PM_RX_DBG_CTRL_A 0x8fd0 1593321936Shselasky#define PM_RX_DBG_DATA_A 0x8fd4 1594321936Shselasky#define PM_RX_DBG_STAT_MSB_A 0x10013 1595321936Shselasky 1596321936Shselasky#define PMRX_FRAMING_ERROR_F 0x003ffff0U 1597321936Shselasky 1598321936Shselasky#define ZERO_E_CMD_ERROR_S 22 1599321936Shselasky#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S) 1600321936Shselasky#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U) 1601321936Shselasky 1602321936Shselasky#define OCSPI_PAR_ERROR_S 3 1603321936Shselasky#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S) 1604321936Shselasky#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U) 1605321936Shselasky 1606321936Shselasky#define DB_OPTIONS_PAR_ERROR_S 2 1607321936Shselasky#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S) 1608321936Shselasky#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U) 1609321936Shselasky 1610321936Shselasky#define IESPI_PAR_ERROR_S 1 1611321936Shselasky#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S) 1612321936Shselasky#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U) 1613321936Shselasky 1614321936Shselasky#define PMRX_E_PCMD_PAR_ERROR_S 0 1615321936Shselasky#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S) 1616321936Shselasky#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U) 1617321936Shselasky 1618321936Shselasky#define PM_TX_INT_CAUSE_A 0x8ffc 1619321936Shselasky#define PM_TX_STAT_CONFIG_A 0x8fe8 1620321936Shselasky#define PM_TX_STAT_COUNT_A 0x8fec 1621321936Shselasky#define PM_TX_STAT_LSB_A 0x8ff0 1622321936Shselasky#define PM_TX_DBG_CTRL_A 0x8ff0 1623321936Shselasky#define PM_TX_DBG_DATA_A 0x8ff4 1624321936Shselasky#define PM_TX_DBG_STAT_MSB_A 0x1001a 1625321936Shselasky 1626321936Shselasky#define PCMD_LEN_OVFL0_S 31 1627321936Shselasky#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S) 1628321936Shselasky#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U) 1629321936Shselasky 1630321936Shselasky#define PCMD_LEN_OVFL1_S 30 1631321936Shselasky#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S) 1632321936Shselasky#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U) 1633321936Shselasky 1634321936Shselasky#define PCMD_LEN_OVFL2_S 29 1635321936Shselasky#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S) 1636321936Shselasky#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U) 1637321936Shselasky 1638321936Shselasky#define ZERO_C_CMD_ERROR_S 28 1639321936Shselasky#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S) 1640321936Shselasky#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U) 1641321936Shselasky 1642321936Shselasky#define PMTX_FRAMING_ERROR_F 0x0ffffff0U 1643321936Shselasky 1644321936Shselasky#define OESPI_PAR_ERROR_S 3 1645321936Shselasky#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S) 1646321936Shselasky#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U) 1647321936Shselasky 1648321936Shselasky#define ICSPI_PAR_ERROR_S 1 1649321936Shselasky#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S) 1650321936Shselasky#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U) 1651321936Shselasky 1652321936Shselasky#define PMTX_C_PCMD_PAR_ERROR_S 0 1653321936Shselasky#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S) 1654321936Shselasky#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U) 1655321936Shselasky 1656321936Shselasky#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 1657321936Shselasky#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 1658321936Shselasky#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 1659321936Shselasky#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 1660321936Shselasky#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 1661321936Shselasky#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 1662321936Shselasky#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 1663321936Shselasky#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 1664321936Shselasky#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 1665321936Shselasky#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 1666321936Shselasky#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 1667321936Shselasky#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 1668321936Shselasky#define MPS_PORT_STAT_TX_PORT_64B_L 0x430 1669321936Shselasky#define MPS_PORT_STAT_TX_PORT_64B_H 0x434 1670321936Shselasky#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 1671321936Shselasky#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 1672321936Shselasky#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 1673321936Shselasky#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 1674321936Shselasky#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 1675321936Shselasky#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 1676321936Shselasky#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 1677321936Shselasky#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 1678321936Shselasky#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 1679321936Shselasky#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 1680321936Shselasky#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 1681321936Shselasky#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 1682321936Shselasky#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 1683321936Shselasky#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 1684321936Shselasky#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 1685321936Shselasky#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 1686321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 1687321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 1688321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 1689321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 1690321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 1691321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 1692321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 1693321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 1694321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 1695321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 1696321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 1697321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 1698321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 1699321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 1700321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 1701321936Shselasky#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 1702321936Shselasky#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 1703321936Shselasky#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 1704321936Shselasky#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 1705321936Shselasky#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 1706321936Shselasky#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 1707321936Shselasky#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 1708321936Shselasky#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 1709321936Shselasky#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 1710321936Shselasky#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 1711321936Shselasky#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 1712321936Shselasky#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 1713321936Shselasky#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 1714321936Shselasky#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 1715321936Shselasky#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 1716321936Shselasky#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 1717321936Shselasky#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 1718321936Shselasky#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 1719321936Shselasky#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 1720321936Shselasky#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 1721321936Shselasky#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 1722321936Shselasky#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 1723321936Shselasky#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 1724321936Shselasky#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 1725321936Shselasky#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 1726321936Shselasky#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 1727321936Shselasky#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 1728321936Shselasky#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 1729321936Shselasky#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 1730321936Shselasky#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 1731321936Shselasky#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 1732321936Shselasky#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 1733321936Shselasky#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 1734321936Shselasky#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 1735321936Shselasky#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 1736321936Shselasky#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 1737321936Shselasky#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 1738321936Shselasky#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 1739321936Shselasky#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 1740321936Shselasky#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 1741321936Shselasky#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 1742321936Shselasky#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 1743321936Shselasky#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 1744321936Shselasky#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 1745321936Shselasky#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 1746321936Shselasky#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 1747321936Shselasky#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 1748321936Shselasky#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 1749321936Shselasky#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 1750321936Shselasky#define MPS_PORT_STAT_RX_PORT_64B_L 0x590 1751321936Shselasky#define MPS_PORT_STAT_RX_PORT_64B_H 0x594 1752321936Shselasky#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 1753321936Shselasky#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 1754321936Shselasky#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 1755321936Shselasky#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 1756321936Shselasky#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 1757321936Shselasky#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 1758321936Shselasky#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 1759321936Shselasky#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 1760321936Shselasky#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 1761321936Shselasky#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 1762321936Shselasky#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 1763321936Shselasky#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 1764321936Shselasky#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 1765321936Shselasky#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 1766321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 1767321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 1768321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 1769321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 1770321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 1771321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 1772321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 1773321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 1774321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 1775321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 1776321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 1777321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 1778321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 1779321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 1780321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 1781321936Shselasky#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 1782321936Shselasky#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 1783321936Shselasky#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 1784321936Shselasky#define MAC_PORT_MAGIC_MACID_LO 0x824 1785321936Shselasky#define MAC_PORT_MAGIC_MACID_HI 0x828 1786321936Shselasky 1787321936Shselasky#define MAC_PORT_EPIO_DATA0_A 0x8c0 1788321936Shselasky#define MAC_PORT_EPIO_DATA1_A 0x8c4 1789321936Shselasky#define MAC_PORT_EPIO_DATA2_A 0x8c8 1790321936Shselasky#define MAC_PORT_EPIO_DATA3_A 0x8cc 1791321936Shselasky#define MAC_PORT_EPIO_OP_A 0x8d0 1792321936Shselasky 1793321936Shselasky#define MAC_PORT_CFG2_A 0x818 1794321936Shselasky 1795321936Shselasky#define MPS_CMN_CTL_A 0x9000 1796321936Shselasky 1797321936Shselasky#define NUMPORTS_S 0 1798321936Shselasky#define NUMPORTS_M 0x3U 1799321936Shselasky#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M) 1800321936Shselasky 1801321936Shselasky#define MPS_INT_CAUSE_A 0x9008 1802321936Shselasky#define MPS_TX_INT_CAUSE_A 0x9408 1803321936Shselasky 1804321936Shselasky#define FRMERR_S 15 1805321936Shselasky#define FRMERR_V(x) ((x) << FRMERR_S) 1806321936Shselasky#define FRMERR_F FRMERR_V(1U) 1807321936Shselasky 1808321936Shselasky#define SECNTERR_S 14 1809321936Shselasky#define SECNTERR_V(x) ((x) << SECNTERR_S) 1810321936Shselasky#define SECNTERR_F SECNTERR_V(1U) 1811321936Shselasky 1812321936Shselasky#define BUBBLE_S 13 1813321936Shselasky#define BUBBLE_V(x) ((x) << BUBBLE_S) 1814321936Shselasky#define BUBBLE_F BUBBLE_V(1U) 1815321936Shselasky 1816321936Shselasky#define TXDESCFIFO_S 9 1817321936Shselasky#define TXDESCFIFO_M 0xfU 1818321936Shselasky#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S) 1819321936Shselasky 1820321936Shselasky#define TXDATAFIFO_S 5 1821321936Shselasky#define TXDATAFIFO_M 0xfU 1822321936Shselasky#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S) 1823321936Shselasky 1824321936Shselasky#define NCSIFIFO_S 4 1825321936Shselasky#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S) 1826321936Shselasky#define NCSIFIFO_F NCSIFIFO_V(1U) 1827321936Shselasky 1828321936Shselasky#define TPFIFO_S 0 1829321936Shselasky#define TPFIFO_M 0xfU 1830321936Shselasky#define TPFIFO_V(x) ((x) << TPFIFO_S) 1831321936Shselasky 1832321936Shselasky#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614 1833321936Shselasky#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620 1834321936Shselasky#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c 1835321936Shselasky 1836321936Shselasky#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 1837321936Shselasky#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 1838321936Shselasky#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 1839321936Shselasky#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 1840321936Shselasky#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 1841321936Shselasky#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 1842321936Shselasky#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 1843321936Shselasky#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 1844321936Shselasky#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 1845321936Shselasky#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 1846321936Shselasky#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 1847321936Shselasky#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 1848321936Shselasky#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 1849321936Shselasky#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 1850321936Shselasky#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 1851321936Shselasky#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 1852321936Shselasky#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 1853321936Shselasky#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 1854321936Shselasky#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 1855321936Shselasky#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 1856321936Shselasky#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 1857321936Shselasky#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 1858321936Shselasky#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 1859321936Shselasky#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 1860321936Shselasky#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 1861321936Shselasky#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 1862321936Shselasky#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 1863321936Shselasky#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 1864321936Shselasky#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 1865321936Shselasky#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 1866321936Shselasky#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 1867321936Shselasky#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 1868321936Shselasky 1869321936Shselasky#define MPS_TRC_CFG_A 0x9800 1870321936Shselasky 1871321936Shselasky#define TRCFIFOEMPTY_S 4 1872321936Shselasky#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S) 1873321936Shselasky#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U) 1874321936Shselasky 1875321936Shselasky#define TRCIGNOREDROPINPUT_S 3 1876321936Shselasky#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S) 1877321936Shselasky#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U) 1878321936Shselasky 1879321936Shselasky#define TRCKEEPDUPLICATES_S 2 1880321936Shselasky#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S) 1881321936Shselasky#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U) 1882321936Shselasky 1883321936Shselasky#define TRCEN_S 1 1884321936Shselasky#define TRCEN_V(x) ((x) << TRCEN_S) 1885321936Shselasky#define TRCEN_F TRCEN_V(1U) 1886321936Shselasky 1887321936Shselasky#define TRCMULTIFILTER_S 0 1888321936Shselasky#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S) 1889321936Shselasky#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U) 1890321936Shselasky 1891321936Shselasky#define MPS_TRC_RSS_CONTROL_A 0x9808 1892321936Shselasky#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4 1893321936Shselasky#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc 1894321936Shselasky#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004 1895321936Shselasky#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c 1896321936Shselasky 1897321936Shselasky#define RSSCONTROL_S 16 1898321936Shselasky#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S) 1899321936Shselasky 1900321936Shselasky#define QUEUENUMBER_S 0 1901321936Shselasky#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S) 1902321936Shselasky 1903321936Shselasky#define TFINVERTMATCH_S 24 1904321936Shselasky#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S) 1905321936Shselasky#define TFINVERTMATCH_F TFINVERTMATCH_V(1U) 1906321936Shselasky 1907321936Shselasky#define TFEN_S 22 1908321936Shselasky#define TFEN_V(x) ((x) << TFEN_S) 1909321936Shselasky#define TFEN_F TFEN_V(1U) 1910321936Shselasky 1911321936Shselasky#define TFPORT_S 18 1912321936Shselasky#define TFPORT_M 0xfU 1913321936Shselasky#define TFPORT_V(x) ((x) << TFPORT_S) 1914321936Shselasky#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M) 1915321936Shselasky 1916321936Shselasky#define TFLENGTH_S 8 1917321936Shselasky#define TFLENGTH_M 0x1fU 1918321936Shselasky#define TFLENGTH_V(x) ((x) << TFLENGTH_S) 1919321936Shselasky#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M) 1920321936Shselasky 1921321936Shselasky#define TFOFFSET_S 0 1922321936Shselasky#define TFOFFSET_M 0x1fU 1923321936Shselasky#define TFOFFSET_V(x) ((x) << TFOFFSET_S) 1924321936Shselasky#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M) 1925321936Shselasky 1926321936Shselasky#define T5_TFINVERTMATCH_S 25 1927321936Shselasky#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S) 1928321936Shselasky#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U) 1929321936Shselasky 1930321936Shselasky#define T5_TFEN_S 23 1931321936Shselasky#define T5_TFEN_V(x) ((x) << T5_TFEN_S) 1932321936Shselasky#define T5_TFEN_F T5_TFEN_V(1U) 1933321936Shselasky 1934321936Shselasky#define T5_TFPORT_S 18 1935321936Shselasky#define T5_TFPORT_M 0x1fU 1936321936Shselasky#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S) 1937321936Shselasky#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M) 1938321936Shselasky 1939321936Shselasky#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810 1940321936Shselasky#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820 1941321936Shselasky 1942321936Shselasky#define TFMINPKTSIZE_S 16 1943321936Shselasky#define TFMINPKTSIZE_M 0x1ffU 1944321936Shselasky#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S) 1945321936Shselasky#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M) 1946321936Shselasky 1947321936Shselasky#define TFCAPTUREMAX_S 0 1948321936Shselasky#define TFCAPTUREMAX_M 0x3fffU 1949321936Shselasky#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S) 1950321936Shselasky#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M) 1951321936Shselasky 1952321936Shselasky#define MPS_TRC_FILTER0_MATCH_A 0x9c00 1953321936Shselasky#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80 1954321936Shselasky#define MPS_TRC_FILTER1_MATCH_A 0x9d00 1955321936Shselasky 1956321936Shselasky#define TP_RSS_CONFIG_A 0x7df0 1957321936Shselasky 1958321936Shselasky#define TNL4TUPENIPV6_S 31 1959321936Shselasky#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S) 1960321936Shselasky#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U) 1961321936Shselasky 1962321936Shselasky#define TNL2TUPENIPV6_S 30 1963321936Shselasky#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S) 1964321936Shselasky#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U) 1965321936Shselasky 1966321936Shselasky#define TNL4TUPENIPV4_S 29 1967321936Shselasky#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S) 1968321936Shselasky#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U) 1969321936Shselasky 1970321936Shselasky#define TNL2TUPENIPV4_S 28 1971321936Shselasky#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S) 1972321936Shselasky#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U) 1973321936Shselasky 1974321936Shselasky#define TNLTCPSEL_S 27 1975321936Shselasky#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S) 1976321936Shselasky#define TNLTCPSEL_F TNLTCPSEL_V(1U) 1977321936Shselasky 1978321936Shselasky#define TNLIP6SEL_S 26 1979321936Shselasky#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S) 1980321936Shselasky#define TNLIP6SEL_F TNLIP6SEL_V(1U) 1981321936Shselasky 1982321936Shselasky#define TNLVRTSEL_S 25 1983321936Shselasky#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S) 1984321936Shselasky#define TNLVRTSEL_F TNLVRTSEL_V(1U) 1985321936Shselasky 1986321936Shselasky#define TNLMAPEN_S 24 1987321936Shselasky#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S) 1988321936Shselasky#define TNLMAPEN_F TNLMAPEN_V(1U) 1989321936Shselasky 1990321936Shselasky#define OFDHASHSAVE_S 19 1991321936Shselasky#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S) 1992321936Shselasky#define OFDHASHSAVE_F OFDHASHSAVE_V(1U) 1993321936Shselasky 1994321936Shselasky#define OFDVRTSEL_S 18 1995321936Shselasky#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S) 1996321936Shselasky#define OFDVRTSEL_F OFDVRTSEL_V(1U) 1997321936Shselasky 1998321936Shselasky#define OFDMAPEN_S 17 1999321936Shselasky#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S) 2000321936Shselasky#define OFDMAPEN_F OFDMAPEN_V(1U) 2001321936Shselasky 2002321936Shselasky#define OFDLKPEN_S 16 2003321936Shselasky#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S) 2004321936Shselasky#define OFDLKPEN_F OFDLKPEN_V(1U) 2005321936Shselasky 2006321936Shselasky#define SYN4TUPENIPV6_S 15 2007321936Shselasky#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S) 2008321936Shselasky#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U) 2009321936Shselasky 2010321936Shselasky#define SYN2TUPENIPV6_S 14 2011321936Shselasky#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S) 2012321936Shselasky#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U) 2013321936Shselasky 2014321936Shselasky#define SYN4TUPENIPV4_S 13 2015321936Shselasky#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S) 2016321936Shselasky#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U) 2017321936Shselasky 2018321936Shselasky#define SYN2TUPENIPV4_S 12 2019321936Shselasky#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S) 2020321936Shselasky#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U) 2021321936Shselasky 2022321936Shselasky#define SYNIP6SEL_S 11 2023321936Shselasky#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S) 2024321936Shselasky#define SYNIP6SEL_F SYNIP6SEL_V(1U) 2025321936Shselasky 2026321936Shselasky#define SYNVRTSEL_S 10 2027321936Shselasky#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S) 2028321936Shselasky#define SYNVRTSEL_F SYNVRTSEL_V(1U) 2029321936Shselasky 2030321936Shselasky#define SYNMAPEN_S 9 2031321936Shselasky#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S) 2032321936Shselasky#define SYNMAPEN_F SYNMAPEN_V(1U) 2033321936Shselasky 2034321936Shselasky#define SYNLKPEN_S 8 2035321936Shselasky#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S) 2036321936Shselasky#define SYNLKPEN_F SYNLKPEN_V(1U) 2037321936Shselasky 2038321936Shselasky#define CHANNELENABLE_S 7 2039321936Shselasky#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S) 2040321936Shselasky#define CHANNELENABLE_F CHANNELENABLE_V(1U) 2041321936Shselasky 2042321936Shselasky#define PORTENABLE_S 6 2043321936Shselasky#define PORTENABLE_V(x) ((x) << PORTENABLE_S) 2044321936Shselasky#define PORTENABLE_F PORTENABLE_V(1U) 2045321936Shselasky 2046321936Shselasky#define TNLALLLOOKUP_S 5 2047321936Shselasky#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S) 2048321936Shselasky#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U) 2049321936Shselasky 2050321936Shselasky#define VIRTENABLE_S 4 2051321936Shselasky#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S) 2052321936Shselasky#define VIRTENABLE_F VIRTENABLE_V(1U) 2053321936Shselasky 2054321936Shselasky#define CONGESTIONENABLE_S 3 2055321936Shselasky#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S) 2056321936Shselasky#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U) 2057321936Shselasky 2058321936Shselasky#define HASHTOEPLITZ_S 2 2059321936Shselasky#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S) 2060321936Shselasky#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U) 2061321936Shselasky 2062321936Shselasky#define UDPENABLE_S 1 2063321936Shselasky#define UDPENABLE_V(x) ((x) << UDPENABLE_S) 2064321936Shselasky#define UDPENABLE_F UDPENABLE_V(1U) 2065321936Shselasky 2066321936Shselasky#define DISABLE_S 0 2067321936Shselasky#define DISABLE_V(x) ((x) << DISABLE_S) 2068321936Shselasky#define DISABLE_F DISABLE_V(1U) 2069321936Shselasky 2070321936Shselasky#define TP_RSS_CONFIG_TNL_A 0x7df4 2071321936Shselasky 2072321936Shselasky#define MASKSIZE_S 28 2073321936Shselasky#define MASKSIZE_M 0xfU 2074321936Shselasky#define MASKSIZE_V(x) ((x) << MASKSIZE_S) 2075321936Shselasky#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M) 2076321936Shselasky 2077321936Shselasky#define MASKFILTER_S 16 2078321936Shselasky#define MASKFILTER_M 0x7ffU 2079321936Shselasky#define MASKFILTER_V(x) ((x) << MASKFILTER_S) 2080321936Shselasky#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M) 2081321936Shselasky 2082321936Shselasky#define USEWIRECH_S 0 2083321936Shselasky#define USEWIRECH_V(x) ((x) << USEWIRECH_S) 2084321936Shselasky#define USEWIRECH_F USEWIRECH_V(1U) 2085321936Shselasky 2086321936Shselasky#define HASHALL_S 2 2087321936Shselasky#define HASHALL_V(x) ((x) << HASHALL_S) 2088321936Shselasky#define HASHALL_F HASHALL_V(1U) 2089321936Shselasky 2090321936Shselasky#define HASHETH_S 1 2091321936Shselasky#define HASHETH_V(x) ((x) << HASHETH_S) 2092321936Shselasky#define HASHETH_F HASHETH_V(1U) 2093321936Shselasky 2094321936Shselasky#define TP_RSS_CONFIG_OFD_A 0x7df8 2095321936Shselasky 2096321936Shselasky#define RRCPLMAPEN_S 20 2097321936Shselasky#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S) 2098321936Shselasky#define RRCPLMAPEN_F RRCPLMAPEN_V(1U) 2099321936Shselasky 2100321936Shselasky#define RRCPLQUEWIDTH_S 16 2101321936Shselasky#define RRCPLQUEWIDTH_M 0xfU 2102321936Shselasky#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S) 2103321936Shselasky#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M) 2104321936Shselasky 2105321936Shselasky#define TP_RSS_CONFIG_SYN_A 0x7dfc 2106321936Shselasky#define TP_RSS_CONFIG_VRT_A 0x7e00 2107321936Shselasky 2108321936Shselasky#define VFRDRG_S 25 2109321936Shselasky#define VFRDRG_V(x) ((x) << VFRDRG_S) 2110321936Shselasky#define VFRDRG_F VFRDRG_V(1U) 2111321936Shselasky 2112321936Shselasky#define VFRDEN_S 24 2113321936Shselasky#define VFRDEN_V(x) ((x) << VFRDEN_S) 2114321936Shselasky#define VFRDEN_F VFRDEN_V(1U) 2115321936Shselasky 2116321936Shselasky#define VFPERREN_S 23 2117321936Shselasky#define VFPERREN_V(x) ((x) << VFPERREN_S) 2118321936Shselasky#define VFPERREN_F VFPERREN_V(1U) 2119321936Shselasky 2120321936Shselasky#define KEYPERREN_S 22 2121321936Shselasky#define KEYPERREN_V(x) ((x) << KEYPERREN_S) 2122321936Shselasky#define KEYPERREN_F KEYPERREN_V(1U) 2123321936Shselasky 2124321936Shselasky#define DISABLEVLAN_S 21 2125321936Shselasky#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S) 2126321936Shselasky#define DISABLEVLAN_F DISABLEVLAN_V(1U) 2127321936Shselasky 2128321936Shselasky#define ENABLEUP0_S 20 2129321936Shselasky#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S) 2130321936Shselasky#define ENABLEUP0_F ENABLEUP0_V(1U) 2131321936Shselasky 2132321936Shselasky#define HASHDELAY_S 16 2133321936Shselasky#define HASHDELAY_M 0xfU 2134321936Shselasky#define HASHDELAY_V(x) ((x) << HASHDELAY_S) 2135321936Shselasky#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M) 2136321936Shselasky 2137321936Shselasky#define VFWRADDR_S 8 2138321936Shselasky#define VFWRADDR_M 0x7fU 2139321936Shselasky#define VFWRADDR_V(x) ((x) << VFWRADDR_S) 2140321936Shselasky#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M) 2141321936Shselasky 2142321936Shselasky#define KEYMODE_S 6 2143321936Shselasky#define KEYMODE_M 0x3U 2144321936Shselasky#define KEYMODE_V(x) ((x) << KEYMODE_S) 2145321936Shselasky#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M) 2146321936Shselasky 2147321936Shselasky#define VFWREN_S 5 2148321936Shselasky#define VFWREN_V(x) ((x) << VFWREN_S) 2149321936Shselasky#define VFWREN_F VFWREN_V(1U) 2150321936Shselasky 2151321936Shselasky#define KEYWREN_S 4 2152321936Shselasky#define KEYWREN_V(x) ((x) << KEYWREN_S) 2153321936Shselasky#define KEYWREN_F KEYWREN_V(1U) 2154321936Shselasky 2155321936Shselasky#define KEYWRADDR_S 0 2156321936Shselasky#define KEYWRADDR_M 0xfU 2157321936Shselasky#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S) 2158321936Shselasky#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M) 2159321936Shselasky 2160321936Shselasky#define KEYWRADDRX_S 30 2161321936Shselasky#define KEYWRADDRX_M 0x3U 2162321936Shselasky#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S) 2163321936Shselasky#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M) 2164321936Shselasky 2165321936Shselasky#define KEYEXTEND_S 26 2166321936Shselasky#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S) 2167321936Shselasky#define KEYEXTEND_F KEYEXTEND_V(1U) 2168321936Shselasky 2169321936Shselasky#define LKPIDXSIZE_S 24 2170321936Shselasky#define LKPIDXSIZE_M 0x3U 2171321936Shselasky#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S) 2172321936Shselasky#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M) 2173321936Shselasky 2174321936Shselasky#define TP_RSS_VFL_CONFIG_A 0x3a 2175321936Shselasky#define TP_RSS_VFH_CONFIG_A 0x3b 2176321936Shselasky 2177321936Shselasky#define ENABLEUDPHASH_S 31 2178321936Shselasky#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S) 2179321936Shselasky#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U) 2180321936Shselasky 2181321936Shselasky#define VFUPEN_S 30 2182321936Shselasky#define VFUPEN_V(x) ((x) << VFUPEN_S) 2183321936Shselasky#define VFUPEN_F VFUPEN_V(1U) 2184321936Shselasky 2185321936Shselasky#define VFVLNEX_S 28 2186321936Shselasky#define VFVLNEX_V(x) ((x) << VFVLNEX_S) 2187321936Shselasky#define VFVLNEX_F VFVLNEX_V(1U) 2188321936Shselasky 2189321936Shselasky#define VFPRTEN_S 27 2190321936Shselasky#define VFPRTEN_V(x) ((x) << VFPRTEN_S) 2191321936Shselasky#define VFPRTEN_F VFPRTEN_V(1U) 2192321936Shselasky 2193321936Shselasky#define VFCHNEN_S 26 2194321936Shselasky#define VFCHNEN_V(x) ((x) << VFCHNEN_S) 2195321936Shselasky#define VFCHNEN_F VFCHNEN_V(1U) 2196321936Shselasky 2197321936Shselasky#define DEFAULTQUEUE_S 16 2198321936Shselasky#define DEFAULTQUEUE_M 0x3ffU 2199321936Shselasky#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M) 2200321936Shselasky 2201321936Shselasky#define VFIP6TWOTUPEN_S 6 2202321936Shselasky#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S) 2203321936Shselasky#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U) 2204321936Shselasky 2205321936Shselasky#define VFIP4FOURTUPEN_S 5 2206321936Shselasky#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S) 2207321936Shselasky#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U) 2208321936Shselasky 2209321936Shselasky#define VFIP4TWOTUPEN_S 4 2210321936Shselasky#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S) 2211321936Shselasky#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U) 2212321936Shselasky 2213321936Shselasky#define KEYINDEX_S 0 2214321936Shselasky#define KEYINDEX_M 0xfU 2215321936Shselasky#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M) 2216321936Shselasky 2217321936Shselasky#define MAPENABLE_S 31 2218321936Shselasky#define MAPENABLE_V(x) ((x) << MAPENABLE_S) 2219321936Shselasky#define MAPENABLE_F MAPENABLE_V(1U) 2220321936Shselasky 2221321936Shselasky#define CHNENABLE_S 30 2222321936Shselasky#define CHNENABLE_V(x) ((x) << CHNENABLE_S) 2223321936Shselasky#define CHNENABLE_F CHNENABLE_V(1U) 2224321936Shselasky 2225321936Shselasky#define PRTENABLE_S 29 2226321936Shselasky#define PRTENABLE_V(x) ((x) << PRTENABLE_S) 2227321936Shselasky#define PRTENABLE_F PRTENABLE_V(1U) 2228321936Shselasky 2229321936Shselasky#define UDPFOURTUPEN_S 28 2230321936Shselasky#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S) 2231321936Shselasky#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U) 2232321936Shselasky 2233321936Shselasky#define IP6FOURTUPEN_S 27 2234321936Shselasky#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S) 2235321936Shselasky#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U) 2236321936Shselasky 2237321936Shselasky#define IP6TWOTUPEN_S 26 2238321936Shselasky#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S) 2239321936Shselasky#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U) 2240321936Shselasky 2241321936Shselasky#define IP4FOURTUPEN_S 25 2242321936Shselasky#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S) 2243321936Shselasky#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U) 2244321936Shselasky 2245321936Shselasky#define IP4TWOTUPEN_S 24 2246321936Shselasky#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S) 2247321936Shselasky#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U) 2248321936Shselasky 2249321936Shselasky#define IVFWIDTH_S 20 2250321936Shselasky#define IVFWIDTH_M 0xfU 2251321936Shselasky#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S) 2252321936Shselasky#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M) 2253321936Shselasky 2254321936Shselasky#define CH1DEFAULTQUEUE_S 10 2255321936Shselasky#define CH1DEFAULTQUEUE_M 0x3ffU 2256321936Shselasky#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S) 2257321936Shselasky#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M) 2258321936Shselasky 2259321936Shselasky#define CH0DEFAULTQUEUE_S 0 2260321936Shselasky#define CH0DEFAULTQUEUE_M 0x3ffU 2261321936Shselasky#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S) 2262321936Shselasky#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M) 2263321936Shselasky 2264321936Shselasky#define VFLKPIDX_S 8 2265321936Shselasky#define VFLKPIDX_M 0xffU 2266321936Shselasky#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M) 2267321936Shselasky 2268321936Shselasky#define T6_VFWRADDR_S 8 2269321936Shselasky#define T6_VFWRADDR_M 0xffU 2270321936Shselasky#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S) 2271321936Shselasky#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M) 2272321936Shselasky 2273321936Shselasky#define TP_RSS_CONFIG_CNG_A 0x7e04 2274321936Shselasky#define TP_RSS_SECRET_KEY0_A 0x40 2275321936Shselasky#define TP_RSS_PF0_CONFIG_A 0x30 2276321936Shselasky#define TP_RSS_PF_MAP_A 0x38 2277321936Shselasky#define TP_RSS_PF_MSK_A 0x39 2278321936Shselasky 2279321936Shselasky#define PF1LKPIDX_S 3 2280321936Shselasky 2281321936Shselasky#define PF0LKPIDX_M 0x7U 2282321936Shselasky 2283321936Shselasky#define PF1MSKSIZE_S 4 2284321936Shselasky#define PF1MSKSIZE_M 0xfU 2285321936Shselasky 2286321936Shselasky#define CHNCOUNT3_S 31 2287321936Shselasky#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S) 2288321936Shselasky#define CHNCOUNT3_F CHNCOUNT3_V(1U) 2289321936Shselasky 2290321936Shselasky#define CHNCOUNT2_S 30 2291321936Shselasky#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S) 2292321936Shselasky#define CHNCOUNT2_F CHNCOUNT2_V(1U) 2293321936Shselasky 2294321936Shselasky#define CHNCOUNT1_S 29 2295321936Shselasky#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S) 2296321936Shselasky#define CHNCOUNT1_F CHNCOUNT1_V(1U) 2297321936Shselasky 2298321936Shselasky#define CHNCOUNT0_S 28 2299321936Shselasky#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S) 2300321936Shselasky#define CHNCOUNT0_F CHNCOUNT0_V(1U) 2301321936Shselasky 2302321936Shselasky#define CHNUNDFLOW3_S 27 2303321936Shselasky#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S) 2304321936Shselasky#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U) 2305321936Shselasky 2306321936Shselasky#define CHNUNDFLOW2_S 26 2307321936Shselasky#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S) 2308321936Shselasky#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U) 2309321936Shselasky 2310321936Shselasky#define CHNUNDFLOW1_S 25 2311321936Shselasky#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S) 2312321936Shselasky#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U) 2313321936Shselasky 2314321936Shselasky#define CHNUNDFLOW0_S 24 2315321936Shselasky#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S) 2316321936Shselasky#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U) 2317321936Shselasky 2318321936Shselasky#define RSTCHN3_S 19 2319321936Shselasky#define RSTCHN3_V(x) ((x) << RSTCHN3_S) 2320321936Shselasky#define RSTCHN3_F RSTCHN3_V(1U) 2321321936Shselasky 2322321936Shselasky#define RSTCHN2_S 18 2323321936Shselasky#define RSTCHN2_V(x) ((x) << RSTCHN2_S) 2324321936Shselasky#define RSTCHN2_F RSTCHN2_V(1U) 2325321936Shselasky 2326321936Shselasky#define RSTCHN1_S 17 2327321936Shselasky#define RSTCHN1_V(x) ((x) << RSTCHN1_S) 2328321936Shselasky#define RSTCHN1_F RSTCHN1_V(1U) 2329321936Shselasky 2330321936Shselasky#define RSTCHN0_S 16 2331321936Shselasky#define RSTCHN0_V(x) ((x) << RSTCHN0_S) 2332321936Shselasky#define RSTCHN0_F RSTCHN0_V(1U) 2333321936Shselasky 2334321936Shselasky#define UPDVLD_S 15 2335321936Shselasky#define UPDVLD_V(x) ((x) << UPDVLD_S) 2336321936Shselasky#define UPDVLD_F UPDVLD_V(1U) 2337321936Shselasky 2338321936Shselasky#define XOFF_S 14 2339321936Shselasky#define XOFF_V(x) ((x) << XOFF_S) 2340321936Shselasky#define XOFF_F XOFF_V(1U) 2341321936Shselasky 2342321936Shselasky#define UPDCHN3_S 13 2343321936Shselasky#define UPDCHN3_V(x) ((x) << UPDCHN3_S) 2344321936Shselasky#define UPDCHN3_F UPDCHN3_V(1U) 2345321936Shselasky 2346321936Shselasky#define UPDCHN2_S 12 2347321936Shselasky#define UPDCHN2_V(x) ((x) << UPDCHN2_S) 2348321936Shselasky#define UPDCHN2_F UPDCHN2_V(1U) 2349321936Shselasky 2350321936Shselasky#define UPDCHN1_S 11 2351321936Shselasky#define UPDCHN1_V(x) ((x) << UPDCHN1_S) 2352321936Shselasky#define UPDCHN1_F UPDCHN1_V(1U) 2353321936Shselasky 2354321936Shselasky#define UPDCHN0_S 10 2355321936Shselasky#define UPDCHN0_V(x) ((x) << UPDCHN0_S) 2356321936Shselasky#define UPDCHN0_F UPDCHN0_V(1U) 2357321936Shselasky 2358321936Shselasky#define QUEUE_S 0 2359321936Shselasky#define QUEUE_M 0x3ffU 2360321936Shselasky#define QUEUE_V(x) ((x) << QUEUE_S) 2361321936Shselasky#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M) 2362321936Shselasky 2363321936Shselasky#define MPS_TRC_INT_CAUSE_A 0x985c 2364321936Shselasky 2365321936Shselasky#define MISCPERR_S 8 2366321936Shselasky#define MISCPERR_V(x) ((x) << MISCPERR_S) 2367321936Shselasky#define MISCPERR_F MISCPERR_V(1U) 2368321936Shselasky 2369321936Shselasky#define PKTFIFO_S 4 2370321936Shselasky#define PKTFIFO_M 0xfU 2371321936Shselasky#define PKTFIFO_V(x) ((x) << PKTFIFO_S) 2372321936Shselasky 2373321936Shselasky#define FILTMEM_S 0 2374321936Shselasky#define FILTMEM_M 0xfU 2375321936Shselasky#define FILTMEM_V(x) ((x) << FILTMEM_S) 2376321936Shselasky 2377321936Shselasky#define MPS_CLS_INT_CAUSE_A 0xd028 2378321936Shselasky 2379321936Shselasky#define HASHSRAM_S 2 2380321936Shselasky#define HASHSRAM_V(x) ((x) << HASHSRAM_S) 2381321936Shselasky#define HASHSRAM_F HASHSRAM_V(1U) 2382321936Shselasky 2383321936Shselasky#define MATCHTCAM_S 1 2384321936Shselasky#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S) 2385321936Shselasky#define MATCHTCAM_F MATCHTCAM_V(1U) 2386321936Shselasky 2387321936Shselasky#define MATCHSRAM_S 0 2388321936Shselasky#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S) 2389321936Shselasky#define MATCHSRAM_F MATCHSRAM_V(1U) 2390321936Shselasky 2391321936Shselasky#define MPS_RX_PG_RSV0_A 0x11010 2392321936Shselasky#define MPS_RX_PG_RSV4_A 0x11020 2393321936Shselasky#define MPS_RX_PERR_INT_CAUSE_A 0x11074 2394321936Shselasky#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208 2395321936Shselasky#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218 2396321936Shselasky 2397321936Shselasky#define MPS_CLS_TCAM_Y_L_A 0xf000 2398321936Shselasky#define MPS_CLS_TCAM_DATA0_A 0xf000 2399321936Shselasky#define MPS_CLS_TCAM_DATA1_A 0xf004 2400321936Shselasky 2401321936Shselasky#define VIDL_S 16 2402321936Shselasky#define VIDL_M 0xffffU 2403321936Shselasky#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M) 2404321936Shselasky 2405321936Shselasky#define DATALKPTYPE_S 10 2406321936Shselasky#define DATALKPTYPE_M 0x3U 2407321936Shselasky#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M) 2408321936Shselasky 2409321936Shselasky#define DATAPORTNUM_S 12 2410321936Shselasky#define DATAPORTNUM_M 0xfU 2411321936Shselasky#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M) 2412321936Shselasky 2413321936Shselasky#define DATADIPHIT_S 8 2414321936Shselasky#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S) 2415321936Shselasky#define DATADIPHIT_F DATADIPHIT_V(1U) 2416321936Shselasky 2417321936Shselasky#define DATAVIDH2_S 7 2418321936Shselasky#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S) 2419321936Shselasky#define DATAVIDH2_F DATAVIDH2_V(1U) 2420321936Shselasky 2421321936Shselasky#define DATAVIDH1_S 0 2422321936Shselasky#define DATAVIDH1_M 0x7fU 2423321936Shselasky#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M) 2424321936Shselasky 2425321936Shselasky#define USED_S 16 2426321936Shselasky#define USED_M 0x7ffU 2427321936Shselasky#define USED_G(x) (((x) >> USED_S) & USED_M) 2428321936Shselasky 2429321936Shselasky#define ALLOC_S 0 2430321936Shselasky#define ALLOC_M 0x7ffU 2431321936Shselasky#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M) 2432321936Shselasky 2433321936Shselasky#define T5_USED_S 16 2434321936Shselasky#define T5_USED_M 0xfffU 2435321936Shselasky#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M) 2436321936Shselasky 2437321936Shselasky#define T5_ALLOC_S 0 2438321936Shselasky#define T5_ALLOC_M 0xfffU 2439321936Shselasky#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M) 2440321936Shselasky 2441321936Shselasky#define DMACH_S 0 2442321936Shselasky#define DMACH_M 0xffffU 2443321936Shselasky#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M) 2444321936Shselasky 2445321936Shselasky#define MPS_CLS_TCAM_X_L_A 0xf008 2446321936Shselasky#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008 2447321936Shselasky 2448321936Shselasky#define CTLCMDTYPE_S 31 2449321936Shselasky#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S) 2450321936Shselasky#define CTLCMDTYPE_F CTLCMDTYPE_V(1U) 2451321936Shselasky 2452321936Shselasky#define CTLTCAMSEL_S 25 2453321936Shselasky#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S) 2454321936Shselasky 2455321936Shselasky#define CTLTCAMINDEX_S 17 2456321936Shselasky#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S) 2457321936Shselasky 2458321936Shselasky#define CTLXYBITSEL_S 16 2459321936Shselasky#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S) 2460321936Shselasky 2461321936Shselasky#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16) 2462321936Shselasky#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 2463321936Shselasky 2464321936Shselasky#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16) 2465321936Shselasky#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 2466321936Shselasky 2467321936Shselasky#define MPS_CLS_SRAM_L_A 0xe000 2468321936Shselasky 2469321936Shselasky#define T6_MULTILISTEN0_S 26 2470321936Shselasky 2471321936Shselasky#define T6_SRAM_PRIO3_S 23 2472321936Shselasky#define T6_SRAM_PRIO3_M 0x7U 2473321936Shselasky#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M) 2474321936Shselasky 2475321936Shselasky#define T6_SRAM_PRIO2_S 20 2476321936Shselasky#define T6_SRAM_PRIO2_M 0x7U 2477321936Shselasky#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M) 2478321936Shselasky 2479321936Shselasky#define T6_SRAM_PRIO1_S 17 2480321936Shselasky#define T6_SRAM_PRIO1_M 0x7U 2481321936Shselasky#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M) 2482321936Shselasky 2483321936Shselasky#define T6_SRAM_PRIO0_S 14 2484321936Shselasky#define T6_SRAM_PRIO0_M 0x7U 2485321936Shselasky#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M) 2486321936Shselasky 2487321936Shselasky#define T6_SRAM_VLD_S 13 2488321936Shselasky#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S) 2489321936Shselasky#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U) 2490321936Shselasky 2491321936Shselasky#define T6_REPLICATE_S 12 2492321936Shselasky#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S) 2493321936Shselasky#define T6_REPLICATE_F T6_REPLICATE_V(1U) 2494321936Shselasky 2495321936Shselasky#define T6_PF_S 9 2496321936Shselasky#define T6_PF_M 0x7U 2497321936Shselasky#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M) 2498321936Shselasky 2499321936Shselasky#define T6_VF_VALID_S 8 2500321936Shselasky#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S) 2501321936Shselasky#define T6_VF_VALID_F T6_VF_VALID_V(1U) 2502321936Shselasky 2503321936Shselasky#define T6_VF_S 0 2504321936Shselasky#define T6_VF_M 0xffU 2505321936Shselasky#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M) 2506321936Shselasky 2507321936Shselasky#define MPS_CLS_SRAM_H_A 0xe004 2508321936Shselasky 2509321936Shselasky#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8) 2510321936Shselasky#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 2511321936Shselasky 2512321936Shselasky#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8) 2513321936Shselasky#define NUM_MPS_CLS_SRAM_H_INSTANCES 336 2514321936Shselasky 2515321936Shselasky#define MULTILISTEN0_S 25 2516321936Shselasky 2517321936Shselasky#define REPLICATE_S 11 2518321936Shselasky#define REPLICATE_V(x) ((x) << REPLICATE_S) 2519321936Shselasky#define REPLICATE_F REPLICATE_V(1U) 2520321936Shselasky 2521321936Shselasky#define PF_S 8 2522321936Shselasky#define PF_M 0x7U 2523321936Shselasky#define PF_G(x) (((x) >> PF_S) & PF_M) 2524321936Shselasky 2525321936Shselasky#define VF_VALID_S 7 2526321936Shselasky#define VF_VALID_V(x) ((x) << VF_VALID_S) 2527321936Shselasky#define VF_VALID_F VF_VALID_V(1U) 2528321936Shselasky 2529321936Shselasky#define VF_S 0 2530321936Shselasky#define VF_M 0x7fU 2531321936Shselasky#define VF_G(x) (((x) >> VF_S) & VF_M) 2532321936Shselasky 2533321936Shselasky#define SRAM_PRIO3_S 22 2534321936Shselasky#define SRAM_PRIO3_M 0x7U 2535321936Shselasky#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M) 2536321936Shselasky 2537321936Shselasky#define SRAM_PRIO2_S 19 2538321936Shselasky#define SRAM_PRIO2_M 0x7U 2539321936Shselasky#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M) 2540321936Shselasky 2541321936Shselasky#define SRAM_PRIO1_S 16 2542321936Shselasky#define SRAM_PRIO1_M 0x7U 2543321936Shselasky#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M) 2544321936Shselasky 2545321936Shselasky#define SRAM_PRIO0_S 13 2546321936Shselasky#define SRAM_PRIO0_M 0x7U 2547321936Shselasky#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M) 2548321936Shselasky 2549321936Shselasky#define SRAM_VLD_S 12 2550321936Shselasky#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S) 2551321936Shselasky#define SRAM_VLD_F SRAM_VLD_V(1U) 2552321936Shselasky 2553321936Shselasky#define PORTMAP_S 0 2554321936Shselasky#define PORTMAP_M 0xfU 2555321936Shselasky#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M) 2556321936Shselasky 2557321936Shselasky#define CPL_INTR_CAUSE_A 0x19054 2558321936Shselasky 2559321936Shselasky#define CIM_OP_MAP_PERR_S 5 2560321936Shselasky#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S) 2561321936Shselasky#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U) 2562321936Shselasky 2563321936Shselasky#define CIM_OVFL_ERROR_S 4 2564321936Shselasky#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S) 2565321936Shselasky#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U) 2566321936Shselasky 2567321936Shselasky#define TP_FRAMING_ERROR_S 3 2568321936Shselasky#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S) 2569321936Shselasky#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U) 2570321936Shselasky 2571321936Shselasky#define SGE_FRAMING_ERROR_S 2 2572321936Shselasky#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S) 2573321936Shselasky#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U) 2574321936Shselasky 2575321936Shselasky#define CIM_FRAMING_ERROR_S 1 2576321936Shselasky#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S) 2577321936Shselasky#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U) 2578321936Shselasky 2579321936Shselasky#define ZERO_SWITCH_ERROR_S 0 2580321936Shselasky#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S) 2581321936Shselasky#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U) 2582321936Shselasky 2583321936Shselasky#define SMB_INT_CAUSE_A 0x19090 2584321936Shselasky 2585321936Shselasky#define MSTTXFIFOPARINT_S 21 2586321936Shselasky#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S) 2587321936Shselasky#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U) 2588321936Shselasky 2589321936Shselasky#define MSTRXFIFOPARINT_S 20 2590321936Shselasky#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S) 2591321936Shselasky#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U) 2592321936Shselasky 2593321936Shselasky#define SLVFIFOPARINT_S 19 2594321936Shselasky#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S) 2595321936Shselasky#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U) 2596321936Shselasky 2597321936Shselasky#define ULP_RX_INT_CAUSE_A 0x19158 2598321936Shselasky#define ULP_RX_ISCSI_LLIMIT_A 0x1915c 2599321936Shselasky#define ULP_RX_ISCSI_ULIMIT_A 0x19160 2600321936Shselasky#define ULP_RX_ISCSI_TAGMASK_A 0x19164 2601321936Shselasky#define ULP_RX_ISCSI_PSZ_A 0x19168 2602321936Shselasky#define ULP_RX_TDDP_LLIMIT_A 0x1916c 2603321936Shselasky#define ULP_RX_TDDP_ULIMIT_A 0x19170 2604321936Shselasky#define ULP_RX_STAG_LLIMIT_A 0x1917c 2605321936Shselasky#define ULP_RX_STAG_ULIMIT_A 0x19180 2606321936Shselasky#define ULP_RX_RQ_LLIMIT_A 0x19184 2607321936Shselasky#define ULP_RX_RQ_ULIMIT_A 0x19188 2608321936Shselasky#define ULP_RX_PBL_LLIMIT_A 0x1918c 2609321936Shselasky#define ULP_RX_PBL_ULIMIT_A 0x19190 2610321936Shselasky#define ULP_RX_CTX_BASE_A 0x19194 2611321936Shselasky#define ULP_RX_RQUDP_LLIMIT_A 0x191a4 2612321936Shselasky#define ULP_RX_RQUDP_ULIMIT_A 0x191a8 2613321936Shselasky#define ULP_RX_LA_CTL_A 0x1923c 2614321936Shselasky#define ULP_RX_LA_RDPTR_A 0x19240 2615321936Shselasky#define ULP_RX_LA_RDDATA_A 0x19244 2616321936Shselasky#define ULP_RX_LA_WRPTR_A 0x19248 2617321936Shselasky 2618321936Shselasky#define HPZ3_S 24 2619321936Shselasky#define HPZ3_V(x) ((x) << HPZ3_S) 2620321936Shselasky 2621321936Shselasky#define HPZ2_S 16 2622321936Shselasky#define HPZ2_V(x) ((x) << HPZ2_S) 2623321936Shselasky 2624321936Shselasky#define HPZ1_S 8 2625321936Shselasky#define HPZ1_V(x) ((x) << HPZ1_S) 2626321936Shselasky 2627321936Shselasky#define HPZ0_S 0 2628321936Shselasky#define HPZ0_V(x) ((x) << HPZ0_S) 2629321936Shselasky 2630321936Shselasky#define ULP_RX_TDDP_PSZ_A 0x19178 2631321936Shselasky 2632321936Shselasky/* registers for module SF */ 2633321936Shselasky#define SF_DATA_A 0x193f8 2634321936Shselasky#define SF_OP_A 0x193fc 2635321936Shselasky 2636321936Shselasky#define SF_BUSY_S 31 2637321936Shselasky#define SF_BUSY_V(x) ((x) << SF_BUSY_S) 2638321936Shselasky#define SF_BUSY_F SF_BUSY_V(1U) 2639321936Shselasky 2640321936Shselasky#define SF_LOCK_S 4 2641321936Shselasky#define SF_LOCK_V(x) ((x) << SF_LOCK_S) 2642321936Shselasky#define SF_LOCK_F SF_LOCK_V(1U) 2643321936Shselasky 2644321936Shselasky#define SF_CONT_S 3 2645321936Shselasky#define SF_CONT_V(x) ((x) << SF_CONT_S) 2646321936Shselasky#define SF_CONT_F SF_CONT_V(1U) 2647321936Shselasky 2648321936Shselasky#define BYTECNT_S 1 2649321936Shselasky#define BYTECNT_V(x) ((x) << BYTECNT_S) 2650321936Shselasky 2651321936Shselasky#define OP_S 0 2652321936Shselasky#define OP_V(x) ((x) << OP_S) 2653321936Shselasky#define OP_F OP_V(1U) 2654321936Shselasky 2655321936Shselasky#define PL_PF_INT_CAUSE_A 0x3c0 2656321936Shselasky 2657321936Shselasky#define PFSW_S 3 2658321936Shselasky#define PFSW_V(x) ((x) << PFSW_S) 2659321936Shselasky#define PFSW_F PFSW_V(1U) 2660321936Shselasky 2661321936Shselasky#define PFCIM_S 1 2662321936Shselasky#define PFCIM_V(x) ((x) << PFCIM_S) 2663321936Shselasky#define PFCIM_F PFCIM_V(1U) 2664321936Shselasky 2665321936Shselasky#define PL_PF_INT_ENABLE_A 0x3c4 2666321936Shselasky#define PL_PF_CTL_A 0x3c8 2667321936Shselasky 2668321936Shselasky#define PL_WHOAMI_A 0x19400 2669321936Shselasky 2670321936Shselasky#define SOURCEPF_S 8 2671321936Shselasky#define SOURCEPF_M 0x7U 2672321936Shselasky#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M) 2673321936Shselasky 2674321936Shselasky#define T6_SOURCEPF_S 9 2675321936Shselasky#define T6_SOURCEPF_M 0x7U 2676321936Shselasky#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M) 2677321936Shselasky 2678321936Shselasky#define PL_INT_CAUSE_A 0x1940c 2679321936Shselasky 2680321936Shselasky#define ULP_TX_S 27 2681321936Shselasky#define ULP_TX_V(x) ((x) << ULP_TX_S) 2682321936Shselasky#define ULP_TX_F ULP_TX_V(1U) 2683321936Shselasky 2684321936Shselasky#define SGE_S 26 2685321936Shselasky#define SGE_V(x) ((x) << SGE_S) 2686321936Shselasky#define SGE_F SGE_V(1U) 2687321936Shselasky 2688321936Shselasky#define CPL_SWITCH_S 24 2689321936Shselasky#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S) 2690321936Shselasky#define CPL_SWITCH_F CPL_SWITCH_V(1U) 2691321936Shselasky 2692321936Shselasky#define ULP_RX_S 23 2693321936Shselasky#define ULP_RX_V(x) ((x) << ULP_RX_S) 2694321936Shselasky#define ULP_RX_F ULP_RX_V(1U) 2695321936Shselasky 2696321936Shselasky#define PM_RX_S 22 2697321936Shselasky#define PM_RX_V(x) ((x) << PM_RX_S) 2698321936Shselasky#define PM_RX_F PM_RX_V(1U) 2699321936Shselasky 2700321936Shselasky#define PM_TX_S 21 2701321936Shselasky#define PM_TX_V(x) ((x) << PM_TX_S) 2702321936Shselasky#define PM_TX_F PM_TX_V(1U) 2703321936Shselasky 2704321936Shselasky#define MA_S 20 2705321936Shselasky#define MA_V(x) ((x) << MA_S) 2706321936Shselasky#define MA_F MA_V(1U) 2707321936Shselasky 2708321936Shselasky#define TP_S 19 2709321936Shselasky#define TP_V(x) ((x) << TP_S) 2710321936Shselasky#define TP_F TP_V(1U) 2711321936Shselasky 2712321936Shselasky#define LE_S 18 2713321936Shselasky#define LE_V(x) ((x) << LE_S) 2714321936Shselasky#define LE_F LE_V(1U) 2715321936Shselasky 2716321936Shselasky#define EDC1_S 17 2717321936Shselasky#define EDC1_V(x) ((x) << EDC1_S) 2718321936Shselasky#define EDC1_F EDC1_V(1U) 2719321936Shselasky 2720321936Shselasky#define EDC0_S 16 2721321936Shselasky#define EDC0_V(x) ((x) << EDC0_S) 2722321936Shselasky#define EDC0_F EDC0_V(1U) 2723321936Shselasky 2724321936Shselasky#define MC_S 15 2725321936Shselasky#define MC_V(x) ((x) << MC_S) 2726321936Shselasky#define MC_F MC_V(1U) 2727321936Shselasky 2728321936Shselasky#define PCIE_S 14 2729321936Shselasky#define PCIE_V(x) ((x) << PCIE_S) 2730321936Shselasky#define PCIE_F PCIE_V(1U) 2731321936Shselasky 2732321936Shselasky#define XGMAC_KR1_S 12 2733321936Shselasky#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S) 2734321936Shselasky#define XGMAC_KR1_F XGMAC_KR1_V(1U) 2735321936Shselasky 2736321936Shselasky#define XGMAC_KR0_S 11 2737321936Shselasky#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S) 2738321936Shselasky#define XGMAC_KR0_F XGMAC_KR0_V(1U) 2739321936Shselasky 2740321936Shselasky#define XGMAC1_S 10 2741321936Shselasky#define XGMAC1_V(x) ((x) << XGMAC1_S) 2742321936Shselasky#define XGMAC1_F XGMAC1_V(1U) 2743321936Shselasky 2744321936Shselasky#define XGMAC0_S 9 2745321936Shselasky#define XGMAC0_V(x) ((x) << XGMAC0_S) 2746321936Shselasky#define XGMAC0_F XGMAC0_V(1U) 2747321936Shselasky 2748321936Shselasky#define SMB_S 8 2749321936Shselasky#define SMB_V(x) ((x) << SMB_S) 2750321936Shselasky#define SMB_F SMB_V(1U) 2751321936Shselasky 2752321936Shselasky#define SF_S 7 2753321936Shselasky#define SF_V(x) ((x) << SF_S) 2754321936Shselasky#define SF_F SF_V(1U) 2755321936Shselasky 2756321936Shselasky#define PL_S 6 2757321936Shselasky#define PL_V(x) ((x) << PL_S) 2758321936Shselasky#define PL_F PL_V(1U) 2759321936Shselasky 2760321936Shselasky#define NCSI_S 5 2761321936Shselasky#define NCSI_V(x) ((x) << NCSI_S) 2762321936Shselasky#define NCSI_F NCSI_V(1U) 2763321936Shselasky 2764321936Shselasky#define MPS_S 4 2765321936Shselasky#define MPS_V(x) ((x) << MPS_S) 2766321936Shselasky#define MPS_F MPS_V(1U) 2767321936Shselasky 2768321936Shselasky#define CIM_S 0 2769321936Shselasky#define CIM_V(x) ((x) << CIM_S) 2770321936Shselasky#define CIM_F CIM_V(1U) 2771321936Shselasky 2772321936Shselasky#define MC1_S 31 2773321936Shselasky#define MC1_V(x) ((x) << MC1_S) 2774321936Shselasky#define MC1_F MC1_V(1U) 2775321936Shselasky 2776321936Shselasky#define PL_INT_ENABLE_A 0x19410 2777321936Shselasky#define PL_INT_MAP0_A 0x19414 2778321936Shselasky#define PL_RST_A 0x19428 2779321936Shselasky 2780321936Shselasky#define PIORST_S 1 2781321936Shselasky#define PIORST_V(x) ((x) << PIORST_S) 2782321936Shselasky#define PIORST_F PIORST_V(1U) 2783321936Shselasky 2784321936Shselasky#define PIORSTMODE_S 0 2785321936Shselasky#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S) 2786321936Shselasky#define PIORSTMODE_F PIORSTMODE_V(1U) 2787321936Shselasky 2788321936Shselasky#define PL_PL_INT_CAUSE_A 0x19430 2789321936Shselasky 2790321936Shselasky#define FATALPERR_S 4 2791321936Shselasky#define FATALPERR_V(x) ((x) << FATALPERR_S) 2792321936Shselasky#define FATALPERR_F FATALPERR_V(1U) 2793321936Shselasky 2794321936Shselasky#define PERRVFID_S 0 2795321936Shselasky#define PERRVFID_V(x) ((x) << PERRVFID_S) 2796321936Shselasky#define PERRVFID_F PERRVFID_V(1U) 2797321936Shselasky 2798321936Shselasky#define PL_REV_A 0x1943c 2799321936Shselasky 2800321936Shselasky#define REV_S 0 2801321936Shselasky#define REV_M 0xfU 2802321936Shselasky#define REV_V(x) ((x) << REV_S) 2803321936Shselasky#define REV_G(x) (((x) >> REV_S) & REV_M) 2804321936Shselasky 2805321936Shselasky#define T6_UNKNOWNCMD_S 3 2806321936Shselasky#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S) 2807321936Shselasky#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U) 2808321936Shselasky 2809321936Shselasky#define T6_LIP0_S 2 2810321936Shselasky#define T6_LIP0_V(x) ((x) << T6_LIP0_S) 2811321936Shselasky#define T6_LIP0_F T6_LIP0_V(1U) 2812321936Shselasky 2813321936Shselasky#define T6_LIPMISS_S 1 2814321936Shselasky#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S) 2815321936Shselasky#define T6_LIPMISS_F T6_LIPMISS_V(1U) 2816321936Shselasky 2817321936Shselasky#define LE_DB_CONFIG_A 0x19c04 2818321936Shselasky#define LE_DB_SERVER_INDEX_A 0x19c18 2819321936Shselasky#define LE_DB_SRVR_START_INDEX_A 0x19c18 2820321936Shselasky#define LE_DB_ACT_CNT_IPV4_A 0x19c20 2821321936Shselasky#define LE_DB_ACT_CNT_IPV6_A 0x19c24 2822321936Shselasky#define LE_DB_HASH_TID_BASE_A 0x19c30 2823321936Shselasky#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30 2824321936Shselasky#define LE_DB_INT_CAUSE_A 0x19c3c 2825321936Shselasky#define LE_DB_TID_HASHBASE_A 0x19df8 2826321936Shselasky#define T6_LE_DB_HASH_TID_BASE_A 0x19df8 2827321936Shselasky 2828321936Shselasky#define HASHEN_S 20 2829321936Shselasky#define HASHEN_V(x) ((x) << HASHEN_S) 2830321936Shselasky#define HASHEN_F HASHEN_V(1U) 2831321936Shselasky 2832321936Shselasky#define ASLIPCOMPEN_S 17 2833321936Shselasky#define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S) 2834321936Shselasky#define ASLIPCOMPEN_F ASLIPCOMPEN_V(1U) 2835321936Shselasky 2836321936Shselasky#define REQQPARERR_S 16 2837321936Shselasky#define REQQPARERR_V(x) ((x) << REQQPARERR_S) 2838321936Shselasky#define REQQPARERR_F REQQPARERR_V(1U) 2839321936Shselasky 2840321936Shselasky#define UNKNOWNCMD_S 15 2841321936Shselasky#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S) 2842321936Shselasky#define UNKNOWNCMD_F UNKNOWNCMD_V(1U) 2843321936Shselasky 2844321936Shselasky#define PARITYERR_S 6 2845321936Shselasky#define PARITYERR_V(x) ((x) << PARITYERR_S) 2846321936Shselasky#define PARITYERR_F PARITYERR_V(1U) 2847321936Shselasky 2848321936Shselasky#define LIPMISS_S 5 2849321936Shselasky#define LIPMISS_V(x) ((x) << LIPMISS_S) 2850321936Shselasky#define LIPMISS_F LIPMISS_V(1U) 2851321936Shselasky 2852321936Shselasky#define LIP0_S 4 2853321936Shselasky#define LIP0_V(x) ((x) << LIP0_S) 2854321936Shselasky#define LIP0_F LIP0_V(1U) 2855321936Shselasky 2856321936Shselasky#define BASEADDR_S 3 2857321936Shselasky#define BASEADDR_M 0x1fffffffU 2858321936Shselasky#define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M) 2859321936Shselasky 2860321936Shselasky#define TCAMINTPERR_S 13 2861321936Shselasky#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S) 2862321936Shselasky#define TCAMINTPERR_F TCAMINTPERR_V(1U) 2863321936Shselasky 2864321936Shselasky#define SSRAMINTPERR_S 10 2865321936Shselasky#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S) 2866321936Shselasky#define SSRAMINTPERR_F SSRAMINTPERR_V(1U) 2867321936Shselasky 2868321936Shselasky#define NCSI_INT_CAUSE_A 0x1a0d8 2869321936Shselasky 2870321936Shselasky#define CIM_DM_PRTY_ERR_S 8 2871321936Shselasky#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S) 2872321936Shselasky#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U) 2873321936Shselasky 2874321936Shselasky#define MPS_DM_PRTY_ERR_S 7 2875321936Shselasky#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S) 2876321936Shselasky#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U) 2877321936Shselasky 2878321936Shselasky#define TXFIFO_PRTY_ERR_S 1 2879321936Shselasky#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S) 2880321936Shselasky#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U) 2881321936Shselasky 2882321936Shselasky#define RXFIFO_PRTY_ERR_S 0 2883321936Shselasky#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S) 2884321936Shselasky#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U) 2885321936Shselasky 2886321936Shselasky#define XGMAC_PORT_CFG2_A 0x1018 2887321936Shselasky 2888321936Shselasky#define PATEN_S 18 2889321936Shselasky#define PATEN_V(x) ((x) << PATEN_S) 2890321936Shselasky#define PATEN_F PATEN_V(1U) 2891321936Shselasky 2892321936Shselasky#define MAGICEN_S 17 2893321936Shselasky#define MAGICEN_V(x) ((x) << MAGICEN_S) 2894321936Shselasky#define MAGICEN_F MAGICEN_V(1U) 2895321936Shselasky 2896321936Shselasky#define XGMAC_PORT_MAGIC_MACID_LO 0x1024 2897321936Shselasky#define XGMAC_PORT_MAGIC_MACID_HI 0x1028 2898321936Shselasky 2899321936Shselasky#define XGMAC_PORT_EPIO_DATA0_A 0x10c0 2900321936Shselasky#define XGMAC_PORT_EPIO_DATA1_A 0x10c4 2901321936Shselasky#define XGMAC_PORT_EPIO_DATA2_A 0x10c8 2902321936Shselasky#define XGMAC_PORT_EPIO_DATA3_A 0x10cc 2903321936Shselasky#define XGMAC_PORT_EPIO_OP_A 0x10d0 2904321936Shselasky 2905321936Shselasky#define EPIOWR_S 8 2906321936Shselasky#define EPIOWR_V(x) ((x) << EPIOWR_S) 2907321936Shselasky#define EPIOWR_F EPIOWR_V(1U) 2908321936Shselasky 2909321936Shselasky#define ADDRESS_S 0 2910321936Shselasky#define ADDRESS_V(x) ((x) << ADDRESS_S) 2911321936Shselasky 2912321936Shselasky#define MAC_PORT_INT_CAUSE_A 0x8dc 2913321936Shselasky#define XGMAC_PORT_INT_CAUSE_A 0x10dc 2914321936Shselasky 2915321936Shselasky#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28 2916321936Shselasky 2917321936Shselasky#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30 2918321936Shselasky#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34 2919321936Shselasky 2920321936Shselasky#define TX_MOD_QUEUE_REQ_MAP_S 0 2921321936Shselasky#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S) 2922321936Shselasky 2923321936Shselasky#define TX_MODQ_WEIGHT3_S 24 2924321936Shselasky#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S) 2925321936Shselasky 2926321936Shselasky#define TX_MODQ_WEIGHT2_S 16 2927321936Shselasky#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S) 2928321936Shselasky 2929321936Shselasky#define TX_MODQ_WEIGHT1_S 8 2930321936Shselasky#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S) 2931321936Shselasky 2932321936Shselasky#define TX_MODQ_WEIGHT0_S 0 2933321936Shselasky#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S) 2934321936Shselasky 2935321936Shselasky#define TP_TX_SCHED_HDR_A 0x23 2936321936Shselasky#define TP_TX_SCHED_FIFO_A 0x24 2937321936Shselasky#define TP_TX_SCHED_PCMD_A 0x25 2938321936Shselasky 2939321936Shselasky#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 2940321936Shselasky#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 2941321936Shselasky 2942321936Shselasky#define T5_PORT0_BASE 0x30000 2943321936Shselasky#define T5_PORT_STRIDE 0x4000 2944321936Shselasky#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 2945321936Shselasky#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 2946321936Shselasky 2947321936Shselasky#define MC_0_BASE_ADDR 0x40000 2948321936Shselasky#define MC_1_BASE_ADDR 0x48000 2949321936Shselasky#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 2950321936Shselasky#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 2951321936Shselasky 2952321936Shselasky#define MC_P_BIST_CMD_A 0x41400 2953321936Shselasky#define MC_P_BIST_CMD_ADDR_A 0x41404 2954321936Shselasky#define MC_P_BIST_CMD_LEN_A 0x41408 2955321936Shselasky#define MC_P_BIST_DATA_PATTERN_A 0x4140c 2956321936Shselasky#define MC_P_BIST_STATUS_RDATA_A 0x41488 2957321936Shselasky 2958321936Shselasky#define EDC_T50_BASE_ADDR 0x50000 2959321936Shselasky 2960321936Shselasky#define EDC_H_BIST_CMD_A 0x50004 2961321936Shselasky#define EDC_H_BIST_CMD_ADDR_A 0x50008 2962321936Shselasky#define EDC_H_BIST_CMD_LEN_A 0x5000c 2963321936Shselasky#define EDC_H_BIST_DATA_PATTERN_A 0x50010 2964321936Shselasky#define EDC_H_BIST_STATUS_RDATA_A 0x50028 2965321936Shselasky 2966321936Shselasky#define EDC_H_ECC_ERR_ADDR_A 0x50084 2967321936Shselasky#define EDC_T51_BASE_ADDR 0x50800 2968321936Shselasky 2969321936Shselasky#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 2970321936Shselasky#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx) 2971321936Shselasky 2972321936Shselasky#define PL_VF_REV_A 0x4 2973321936Shselasky#define PL_VF_WHOAMI_A 0x0 2974321936Shselasky#define PL_VF_REVISION_A 0x8 2975321936Shselasky 2976321936Shselasky/* registers for module CIM */ 2977321936Shselasky#define CIM_HOST_ACC_CTRL_A 0x7b50 2978321936Shselasky#define CIM_HOST_ACC_DATA_A 0x7b54 2979321936Shselasky#define UP_UP_DBG_LA_CFG_A 0x140 2980321936Shselasky#define UP_UP_DBG_LA_DATA_A 0x144 2981321936Shselasky 2982321936Shselasky#define HOSTBUSY_S 17 2983321936Shselasky#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S) 2984321936Shselasky#define HOSTBUSY_F HOSTBUSY_V(1U) 2985321936Shselasky 2986321936Shselasky#define HOSTWRITE_S 16 2987321936Shselasky#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S) 2988321936Shselasky#define HOSTWRITE_F HOSTWRITE_V(1U) 2989321936Shselasky 2990321936Shselasky#define CIM_IBQ_DBG_CFG_A 0x7b60 2991321936Shselasky 2992321936Shselasky#define IBQDBGADDR_S 16 2993321936Shselasky#define IBQDBGADDR_M 0xfffU 2994321936Shselasky#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S) 2995321936Shselasky#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M) 2996321936Shselasky 2997321936Shselasky#define IBQDBGBUSY_S 1 2998321936Shselasky#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S) 2999321936Shselasky#define IBQDBGBUSY_F IBQDBGBUSY_V(1U) 3000321936Shselasky 3001321936Shselasky#define IBQDBGEN_S 0 3002321936Shselasky#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S) 3003321936Shselasky#define IBQDBGEN_F IBQDBGEN_V(1U) 3004321936Shselasky 3005321936Shselasky#define CIM_OBQ_DBG_CFG_A 0x7b64 3006321936Shselasky 3007321936Shselasky#define OBQDBGADDR_S 16 3008321936Shselasky#define OBQDBGADDR_M 0xfffU 3009321936Shselasky#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S) 3010321936Shselasky#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M) 3011321936Shselasky 3012321936Shselasky#define OBQDBGBUSY_S 1 3013321936Shselasky#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S) 3014321936Shselasky#define OBQDBGBUSY_F OBQDBGBUSY_V(1U) 3015321936Shselasky 3016321936Shselasky#define OBQDBGEN_S 0 3017321936Shselasky#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S) 3018321936Shselasky#define OBQDBGEN_F OBQDBGEN_V(1U) 3019321936Shselasky 3020321936Shselasky#define CIM_IBQ_DBG_DATA_A 0x7b68 3021321936Shselasky#define CIM_OBQ_DBG_DATA_A 0x7b6c 3022321936Shselasky#define CIM_DEBUGCFG_A 0x7b70 3023321936Shselasky#define CIM_DEBUGSTS_A 0x7b74 3024321936Shselasky 3025321936Shselasky#define POLADBGRDPTR_S 23 3026321936Shselasky#define POLADBGRDPTR_M 0x1ffU 3027321936Shselasky#define POLADBGRDPTR_V(x) ((x) << POLADBGRDPTR_S) 3028321936Shselasky 3029321936Shselasky#define POLADBGWRPTR_S 16 3030321936Shselasky#define POLADBGWRPTR_M 0x1ffU 3031321936Shselasky#define POLADBGWRPTR_G(x) (((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M) 3032321936Shselasky 3033321936Shselasky#define PILADBGRDPTR_S 14 3034321936Shselasky#define PILADBGRDPTR_M 0x1ffU 3035321936Shselasky#define PILADBGRDPTR_V(x) ((x) << PILADBGRDPTR_S) 3036321936Shselasky 3037321936Shselasky#define PILADBGWRPTR_S 0 3038321936Shselasky#define PILADBGWRPTR_M 0x1ffU 3039321936Shselasky#define PILADBGWRPTR_G(x) (((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M) 3040321936Shselasky 3041321936Shselasky#define LADBGEN_S 12 3042321936Shselasky#define LADBGEN_V(x) ((x) << LADBGEN_S) 3043321936Shselasky#define LADBGEN_F LADBGEN_V(1U) 3044321936Shselasky 3045321936Shselasky#define CIM_PO_LA_DEBUGDATA_A 0x7b78 3046321936Shselasky#define CIM_PI_LA_DEBUGDATA_A 0x7b7c 3047321936Shselasky#define CIM_PO_LA_MADEBUGDATA_A 0x7b80 3048321936Shselasky#define CIM_PI_LA_MADEBUGDATA_A 0x7b84 3049321936Shselasky 3050321936Shselasky#define UPDBGLARDEN_S 1 3051321936Shselasky#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S) 3052321936Shselasky#define UPDBGLARDEN_F UPDBGLARDEN_V(1U) 3053321936Shselasky 3054321936Shselasky#define UPDBGLAEN_S 0 3055321936Shselasky#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S) 3056321936Shselasky#define UPDBGLAEN_F UPDBGLAEN_V(1U) 3057321936Shselasky 3058321936Shselasky#define UPDBGLARDPTR_S 2 3059321936Shselasky#define UPDBGLARDPTR_M 0xfffU 3060321936Shselasky#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S) 3061321936Shselasky 3062321936Shselasky#define UPDBGLAWRPTR_S 16 3063321936Shselasky#define UPDBGLAWRPTR_M 0xfffU 3064321936Shselasky#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M) 3065321936Shselasky 3066321936Shselasky#define UPDBGLACAPTPCONLY_S 30 3067321936Shselasky#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S) 3068321936Shselasky#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U) 3069321936Shselasky 3070321936Shselasky#define CIM_QUEUE_CONFIG_REF_A 0x7b48 3071321936Shselasky#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c 3072321936Shselasky 3073321936Shselasky#define CIMQSIZE_S 24 3074321936Shselasky#define CIMQSIZE_M 0x3fU 3075321936Shselasky#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M) 3076321936Shselasky 3077321936Shselasky#define CIMQBASE_S 16 3078321936Shselasky#define CIMQBASE_M 0x3fU 3079321936Shselasky#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M) 3080321936Shselasky 3081321936Shselasky#define QUEFULLTHRSH_S 0 3082321936Shselasky#define QUEFULLTHRSH_M 0x1ffU 3083321936Shselasky#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M) 3084321936Shselasky 3085321936Shselasky#define UP_IBQ_0_RDADDR_A 0x10 3086321936Shselasky#define UP_IBQ_0_SHADOW_RDADDR_A 0x280 3087321936Shselasky#define UP_OBQ_0_REALADDR_A 0x104 3088321936Shselasky#define UP_OBQ_0_SHADOW_REALADDR_A 0x394 3089321936Shselasky 3090321936Shselasky#define IBQRDADDR_S 0 3091321936Shselasky#define IBQRDADDR_M 0x1fffU 3092321936Shselasky#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M) 3093321936Shselasky 3094321936Shselasky#define IBQWRADDR_S 0 3095321936Shselasky#define IBQWRADDR_M 0x1fffU 3096321936Shselasky#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M) 3097321936Shselasky 3098321936Shselasky#define QUERDADDR_S 0 3099321936Shselasky#define QUERDADDR_M 0x7fffU 3100321936Shselasky#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M) 3101321936Shselasky 3102321936Shselasky#define QUEREMFLITS_S 0 3103321936Shselasky#define QUEREMFLITS_M 0x7ffU 3104321936Shselasky#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M) 3105321936Shselasky 3106321936Shselasky#define QUEEOPCNT_S 16 3107321936Shselasky#define QUEEOPCNT_M 0xfffU 3108321936Shselasky#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M) 3109321936Shselasky 3110321936Shselasky#define QUESOPCNT_S 0 3111321936Shselasky#define QUESOPCNT_M 0xfffU 3112321936Shselasky#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M) 3113321936Shselasky 3114321936Shselasky#define OBQSELECT_S 4 3115321936Shselasky#define OBQSELECT_V(x) ((x) << OBQSELECT_S) 3116321936Shselasky#define OBQSELECT_F OBQSELECT_V(1U) 3117321936Shselasky 3118321936Shselasky#define IBQSELECT_S 3 3119321936Shselasky#define IBQSELECT_V(x) ((x) << IBQSELECT_S) 3120321936Shselasky#define IBQSELECT_F IBQSELECT_V(1U) 3121321936Shselasky 3122321936Shselasky#define QUENUMSELECT_S 0 3123321936Shselasky#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S) 3124321936Shselasky 3125321936Shselasky#endif /* __T4_REGS_H */ 3126