X86RecognizableInstr.h revision 218893 
1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the interface of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef X86RECOGNIZABLEINSTR_H
18#define X86RECOGNIZABLEINSTR_H
19
20#include "X86DisassemblerTables.h"
21
22#include "CodeGenTarget.h"
23#include "Record.h"
24
25#include "llvm/Support/DataTypes.h"
26#include "llvm/ADT/SmallVector.h"
27
28namespace llvm {
29
30namespace X86Disassembler {
31
32/// RecognizableInstr - Encapsulates all information required to decode a single
33///   instruction, as extracted from the LLVM instruction tables.  Has methods
34///   to interpret the information available in the LLVM tables, and to emit the
35///   instruction into DisassemblerTables.
36class RecognizableInstr {
37private:
38  /// The opcode of the instruction, as used in an MCInst
39  InstrUID UID;
40  /// The record from the .td files corresponding to this instruction
41  const Record* Rec;
42  /// The prefix field from the record
43  uint8_t Prefix;
44  /// The opcode field from the record; this is the opcode used in the Intel
45  /// encoding and therefore distinct from the UID
46  uint8_t Opcode;
47  /// The form field from the record
48  uint8_t Form;
49  /// The segment override field from the record
50  uint8_t SegOvr;
51  /// The hasOpSizePrefix field from the record
52  bool HasOpSizePrefix;
53  /// The hasREX_WPrefix field from the record
54  bool HasREX_WPrefix;
55  /// The hasVEX_4VPrefix field from the record
56  bool HasVEX_4VPrefix;
57  /// The hasLockPrefix field from the record
58  bool HasLockPrefix;
59  /// The isCodeGenOnly filed from the record
60  bool IsCodeGenOnly;
61
62  /// The instruction name as listed in the tables
63  std::string Name;
64  /// The AT&T AsmString for the instruction
65  std::string AsmString;
66
67  /// Indicates whether the instruction is SSE
68  bool IsSSE;
69  /// Indicates whether the instruction has FR operands - MOVs with FR operands
70  /// are typically ignored
71  bool HasFROperands;
72  /// Indicates whether the instruction should be emitted into the decode
73  /// tables; regardless, it will be emitted into the instruction info table
74  bool ShouldBeEmitted;
75
76  /// The operands of the instruction, as listed in the CodeGenInstruction.
77  /// They are not one-to-one with operands listed in the MCInst; for example,
78  /// memory operands expand to 5 operands in the MCInst
79  const std::vector<CGIOperandList::OperandInfo>* Operands;
80
81  /// The description of the instruction that is emitted into the instruction
82  /// info table
83  InstructionSpecifier* Spec;
84
85  /// insnContext - Returns the primary context in which the instruction is
86  ///   valid.
87  ///
88  /// @return - The context in which the instruction is valid.
89  InstructionContext insnContext() const;
90
91  enum filter_ret {
92    FILTER_STRONG,    // instruction has no place in the instruction tables
93    FILTER_WEAK,      // instruction may conflict, and should be eliminated if
94                      // it does
95    FILTER_NORMAL     // instruction should have high priority and generate an
96                      // error if it conflcits with any other FILTER_NORMAL
97                      // instruction
98  };
99
100  /// filter - Determines whether the instruction should be decodable.  Some
101  ///   instructions are pure intrinsics and use unencodable operands; many
102  ///   synthetic instructions are duplicates of other instructions; other
103  ///   instructions only differ in the logical way in which they are used, and
104  ///   have the same decoding.  Because these would cause decode conflicts,
105  ///   they must be filtered out.
106  ///
107  /// @return - The degree of filtering to be applied (see filter_ret).
108  filter_ret filter() const;
109
110  /// typeFromString - Translates an operand type from the string provided in
111  ///   the LLVM tables to an OperandType for use in the operand specifier.
112  ///
113  /// @param s              - The string, as extracted by calling Rec->getName()
114  ///                         on a CodeGenInstruction::OperandInfo.
115  /// @param isSSE          - Indicates whether the instruction is an SSE
116  ///                         instruction.  For SSE instructions, immediates are
117  ///                         fixed-size rather than being affected by the
118  ///                         mandatory OpSize prefix.
119  /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
120  ///                         prefix.  If it does, 32-bit register operands stay
121  ///                         32-bit regardless of the operand size.
122  /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
123  ///                         prefix.  If it does not, then 16-bit register
124  ///                         operands stay 16-bit.
125  /// @return               - The operand's type.
126  static OperandType typeFromString(const std::string& s,
127                                    bool isSSE,
128                                    bool hasREX_WPrefix,
129                                    bool hasOpSizePrefix);
130
131  /// immediateEncodingFromString - Translates an immediate encoding from the
132  ///   string provided in the LLVM tables to an OperandEncoding for use in
133  ///   the operand specifier.
134  ///
135  /// @param s                - See typeFromString().
136  /// @param hasOpSizePrefix  - Indicates whether the instruction has an OpSize
137  ///                           prefix.  If it does not, then 16-bit immediate
138  ///                           operands stay 16-bit.
139  /// @return                 - The operand's encoding.
140  static OperandEncoding immediateEncodingFromString(const std::string &s,
141                                                     bool hasOpSizePrefix);
142
143  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
144  ///   handles operands that are in the REG field of the ModR/M byte.
145  static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
146                                                      bool hasOpSizePrefix);
147
148  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
149  ///   handles operands that are in the REG field of the ModR/M byte.
150  static OperandEncoding roRegisterEncodingFromString(const std::string &s,
151                                                      bool hasOpSizePrefix);
152  static OperandEncoding memoryEncodingFromString(const std::string &s,
153                                                  bool hasOpSizePrefix);
154  static OperandEncoding relocationEncodingFromString(const std::string &s,
155                                                      bool hasOpSizePrefix);
156  static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
157                                                          bool hasOpSizePrefix);
158
159  /// handleOperand - Converts a single operand from the LLVM table format to
160  ///   the emitted table format, handling any duplicate operands it encounters
161  ///   and then one non-duplicate.
162  ///
163  /// @param optional             - Determines whether to assert that the
164  ///                               operand exists.
165  /// @param operandIndex         - The index into the generated operand table.
166  ///                               Incremented by this function one or more
167  ///                               times to reflect possible duplicate
168  ///                               operands).
169  /// @param physicalOperandIndex - The index of the current operand into the
170  ///                               set of non-duplicate ('physical') operands.
171  ///                               Incremented by this function once.
172  /// @param numPhysicalOperands  - The number of non-duplicate operands in the
173  ///                               instructions.
174  /// @param operandMapping       - The operand mapping, which has an entry for
175  ///                               each operand that indicates whether it is a
176  ///                               duplicate, and of what.
177  void handleOperand(bool optional,
178                     unsigned &operandIndex,
179                     unsigned &physicalOperandIndex,
180                     unsigned &numPhysicalOperands,
181                     unsigned *operandMapping,
182                     OperandEncoding (*encodingFromString)
183                       (const std::string&,
184                        bool hasOpSizePrefix));
185
186  /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
187  ///   filters out many instructions, at various points in decoding we
188  ///   determine that the instruction should not actually be decodable.  In
189  ///   particular, MMX MOV instructions aren't emitted, but they're only
190  ///   identified during operand parsing.
191  ///
192  /// @return - true if at this point we believe the instruction should be
193  ///   emitted; false if not.  This will return false if filter() returns false
194  ///   once emitInstructionSpecifier() has been called.
195  bool shouldBeEmitted() const {
196    return ShouldBeEmitted;
197  }
198
199  /// emitInstructionSpecifier - Loads the instruction specifier for the current
200  ///   instruction into a DisassemblerTables.
201  ///
202  /// @arg tables - The DisassemblerTables to populate with the specifier for
203  ///               the current instruction.
204  void emitInstructionSpecifier(DisassemblerTables &tables);
205
206  /// emitDecodePath - Populates the proper fields in the decode tables
207  ///   corresponding to the decode paths for this instruction.
208  ///
209  /// @arg tables - The DisassemblerTables to populate with the decode
210  ///               decode information for the current instruction.
211  void emitDecodePath(DisassemblerTables &tables) const;
212
213  /// Constructor - Initializes a RecognizableInstr with the appropriate fields
214  ///   from a CodeGenInstruction.
215  ///
216  /// @arg tables - The DisassemblerTables that the specifier will be added to.
217  /// @arg insn   - The CodeGenInstruction to extract information from.
218  /// @arg uid    - The unique ID of the current instruction.
219  RecognizableInstr(DisassemblerTables &tables,
220                    const CodeGenInstruction &insn,
221                    InstrUID uid);
222public:
223  /// processInstr - Accepts a CodeGenInstruction and loads decode information
224  ///   for it into a DisassemblerTables if appropriate.
225  ///
226  /// @arg tables - The DiassemblerTables to be populated with decode
227  ///               information.
228  /// @arg insn   - The CodeGenInstruction to be used as a source for this
229  ///               information.
230  /// @uid        - The unique ID of the instruction.
231  static void processInstr(DisassemblerTables &tables,
232                           const CodeGenInstruction &insn,
233                           InstrUID uid);
234};
235
236} // namespace X86Disassembler
237
238} // namespace llvm
239
240#endif
241