X86RecognizableInstr.cpp revision 208599 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)		\
37  MAP(F9, 42)
38
39// A clone of X86 since we can't depend on something that is generated.
40namespace X86Local {
41  enum {
42    Pseudo      = 0,
43    RawFrm      = 1,
44    AddRegFrm   = 2,
45    MRMDestReg  = 3,
46    MRMDestMem  = 4,
47    MRMSrcReg   = 5,
48    MRMSrcMem   = 6,
49    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
53    MRMInitReg  = 32,
54
55#define MAP(from, to) MRM_##from = to,
56    MRM_MAPPING
57#undef MAP
58    lastMRM
59  };
60
61  enum {
62    TB  = 1,
63    REP = 2,
64    D8 = 3, D9 = 4, DA = 5, DB = 6,
65    DC = 7, DD = 8, DE = 9, DF = 10,
66    XD = 11,  XS = 12,
67    T8 = 13,  P_TA = 14,
68    P_0F_AE = 16, P_0F_01 = 17
69  };
70}
71
72// If rows are added to the opcode extension tables, then corresponding entries
73// must be added here.
74//
75// If the row corresponds to a single byte (i.e., 8f), then add an entry for
76// that byte to ONE_BYTE_EXTENSION_TABLES.
77//
78// If the row corresponds to two bytes where the first is 0f, add an entry for
79// the second byte to TWO_BYTE_EXTENSION_TABLES.
80//
81// If the row corresponds to some other set of bytes, you will need to modify
82// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83// to the X86 TD files, except in two cases: if the first two bytes of such a
84// new combination are 0f 38 or 0f 3a, you just have to add maps called
85// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87// in RecognizableInstr::emitDecodePath().
88
89#define ONE_BYTE_EXTENSION_TABLES \
90  EXTENSION_TABLE(80)             \
91  EXTENSION_TABLE(81)             \
92  EXTENSION_TABLE(82)             \
93  EXTENSION_TABLE(83)             \
94  EXTENSION_TABLE(8f)             \
95  EXTENSION_TABLE(c0)             \
96  EXTENSION_TABLE(c1)             \
97  EXTENSION_TABLE(c6)             \
98  EXTENSION_TABLE(c7)             \
99  EXTENSION_TABLE(d0)             \
100  EXTENSION_TABLE(d1)             \
101  EXTENSION_TABLE(d2)             \
102  EXTENSION_TABLE(d3)             \
103  EXTENSION_TABLE(f6)             \
104  EXTENSION_TABLE(f7)             \
105  EXTENSION_TABLE(fe)             \
106  EXTENSION_TABLE(ff)
107
108#define TWO_BYTE_EXTENSION_TABLES \
109  EXTENSION_TABLE(00)             \
110  EXTENSION_TABLE(01)             \
111  EXTENSION_TABLE(18)             \
112  EXTENSION_TABLE(71)             \
113  EXTENSION_TABLE(72)             \
114  EXTENSION_TABLE(73)             \
115  EXTENSION_TABLE(ae)             \
116  EXTENSION_TABLE(b9)             \
117  EXTENSION_TABLE(ba)             \
118  EXTENSION_TABLE(c7)
119
120using namespace X86Disassembler;
121
122/// needsModRMForDecode - Indicates whether a particular instruction requires a
123///   ModR/M byte for the instruction to be properly decoded.  For example, a
124///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
125///   0b11.
126///
127/// @param form - The form of the instruction.
128/// @return     - true if the form implies that a ModR/M byte is required, false
129///               otherwise.
130static bool needsModRMForDecode(uint8_t form) {
131  if (form == X86Local::MRMDestReg    ||
132     form == X86Local::MRMDestMem    ||
133     form == X86Local::MRMSrcReg     ||
134     form == X86Local::MRMSrcMem     ||
135     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
137    return true;
138  else
139    return false;
140}
141
142/// isRegFormat - Indicates whether a particular form requires the Mod field of
143///   the ModR/M byte to be 0b11.
144///
145/// @param form - The form of the instruction.
146/// @return     - true if the form implies that Mod must be 0b11, false
147///               otherwise.
148static bool isRegFormat(uint8_t form) {
149  if (form == X86Local::MRMDestReg ||
150     form == X86Local::MRMSrcReg  ||
151     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
152    return true;
153  else
154    return false;
155}
156
157/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158///   Useful for switch statements and the like.
159///
160/// @param init - A reference to the BitsInit to be decoded.
161/// @return     - The field, with the first bit in the BitsInit as the lowest
162///               order bit.
163static uint8_t byteFromBitsInit(BitsInit &init) {
164  int width = init.getNumBits();
165
166  assert(width <= 8 && "Field is too large for uint8_t!");
167
168  int     index;
169  uint8_t mask = 0x01;
170
171  uint8_t ret = 0;
172
173  for (index = 0; index < width; index++) {
174    if (static_cast<BitInit*>(init.getBit(index))->getValue())
175      ret |= mask;
176
177    mask <<= 1;
178  }
179
180  return ret;
181}
182
183/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184///   name of the field.
185///
186/// @param rec  - The record from which to extract the value.
187/// @param name - The name of the field in the record.
188/// @return     - The field, as translated by byteFromBitsInit().
189static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190  BitsInit* bits = rec->getValueAsBitsInit(name);
191  return byteFromBitsInit(*bits);
192}
193
194RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195                                     const CodeGenInstruction &insn,
196                                     InstrUID uid) {
197  UID = uid;
198
199  Rec = insn.TheDef;
200  Name = Rec->getName();
201  Spec = &tables.specForUID(UID);
202
203  if (!Rec->isSubClassOf("X86Inst")) {
204    ShouldBeEmitted = false;
205    return;
206  }
207
208  Prefix   = byteFromRec(Rec, "Prefix");
209  Opcode   = byteFromRec(Rec, "Opcode");
210  Form     = byteFromRec(Rec, "FormBits");
211  SegOvr   = byteFromRec(Rec, "SegOvrBits");
212
213  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
214  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
215  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
216  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
217
218  Name      = Rec->getName();
219  AsmString = Rec->getValueAsString("AsmString");
220
221  Operands = &insn.OperandList;
222
223  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
224  HasFROperands    = false;
225
226  ShouldBeEmitted  = true;
227}
228
229void RecognizableInstr::processInstr(DisassemblerTables &tables,
230                                   const CodeGenInstruction &insn,
231                                   InstrUID uid)
232{
233  // Ignore "asm parser only" instructions.
234  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
235    return;
236
237  RecognizableInstr recogInstr(tables, insn, uid);
238
239  recogInstr.emitInstructionSpecifier(tables);
240
241  if (recogInstr.shouldBeEmitted())
242    recogInstr.emitDecodePath(tables);
243}
244
245InstructionContext RecognizableInstr::insnContext() const {
246  InstructionContext insnContext;
247
248  if (Name.find("64") != Name.npos || HasREX_WPrefix) {
249    if (HasREX_WPrefix && HasOpSizePrefix)
250      insnContext = IC_64BIT_REXW_OPSIZE;
251    else if (HasOpSizePrefix)
252      insnContext = IC_64BIT_OPSIZE;
253    else if (HasREX_WPrefix && Prefix == X86Local::XS)
254      insnContext = IC_64BIT_REXW_XS;
255    else if (HasREX_WPrefix && Prefix == X86Local::XD)
256      insnContext = IC_64BIT_REXW_XD;
257    else if (Prefix == X86Local::XD)
258      insnContext = IC_64BIT_XD;
259    else if (Prefix == X86Local::XS)
260      insnContext = IC_64BIT_XS;
261    else if (HasREX_WPrefix)
262      insnContext = IC_64BIT_REXW;
263    else
264      insnContext = IC_64BIT;
265  } else {
266    if (HasOpSizePrefix)
267      insnContext = IC_OPSIZE;
268    else if (Prefix == X86Local::XD)
269      insnContext = IC_XD;
270    else if (Prefix == X86Local::XS)
271      insnContext = IC_XS;
272    else
273      insnContext = IC;
274  }
275
276  return insnContext;
277}
278
279RecognizableInstr::filter_ret RecognizableInstr::filter() const {
280  // Filter out intrinsics
281
282  if (!Rec->isSubClassOf("X86Inst"))
283    return FILTER_STRONG;
284
285  if (Form == X86Local::Pseudo ||
286      IsCodeGenOnly)
287    return FILTER_STRONG;
288
289  if (Form == X86Local::MRMInitReg)
290    return FILTER_STRONG;
291
292
293  // Filter out instructions with a LOCK prefix;
294  //   prefer forms that do not have the prefix
295  if (HasLockPrefix)
296    return FILTER_WEAK;
297
298  // Filter out artificial instructions
299
300  if (Name.find("TAILJMP") != Name.npos    ||
301     Name.find("_Int") != Name.npos       ||
302     Name.find("_int") != Name.npos       ||
303     Name.find("Int_") != Name.npos       ||
304     Name.find("_NOREX") != Name.npos     ||
305     Name.find("_TC") != Name.npos     ||
306     Name.find("EH_RETURN") != Name.npos  ||
307     Name.find("V_SET") != Name.npos      ||
308     Name.find("LOCK_") != Name.npos      ||
309     Name.find("WIN") != Name.npos)
310    return FILTER_STRONG;
311
312  // Special cases.
313
314  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
315    return FILTER_WEAK;
316  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
317    return FILTER_WEAK;
318
319  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
320    return FILTER_WEAK;
321  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
322    return FILTER_WEAK;
323  if (Name.find("Fs") != Name.npos)
324    return FILTER_WEAK;
325  if (Name == "MOVLPDrr"          ||
326      Name == "MOVLPSrr"          ||
327      Name == "PUSHFQ"            ||
328      Name == "BSF16rr"           ||
329      Name == "BSF16rm"           ||
330      Name == "BSR16rr"           ||
331      Name == "BSR16rm"           ||
332      Name == "MOVSX16rm8"        ||
333      Name == "MOVSX16rr8"        ||
334      Name == "MOVZX16rm8"        ||
335      Name == "MOVZX16rr8"        ||
336      Name == "PUSH32i16"         ||
337      Name == "PUSH64i16"         ||
338      Name == "MOVPQI2QImr"       ||
339      Name == "MOVSDmr"           ||
340      Name == "MOVSDrm"           ||
341      Name == "MOVSSmr"           ||
342      Name == "MOVSSrm"           ||
343      Name == "MMX_MOVD64rrv164"  ||
344      Name == "CRC32m16"          ||
345      Name == "MOV64ri64i32"      ||
346      Name == "CRC32r16")
347    return FILTER_WEAK;
348
349  // Filter out instructions with segment override prefixes.
350  // They're too messy to handle now and we'll special case them if needed.
351
352  if (SegOvr)
353    return FILTER_STRONG;
354
355  // Filter out instructions that can't be printed.
356
357  if (AsmString.size() == 0)
358    return FILTER_STRONG;
359
360  // Filter out instructions with subreg operands.
361
362  if (AsmString.find("subreg") != AsmString.npos)
363    return FILTER_STRONG;
364
365  if (HasFROperands && Name.find("MOV") != Name.npos &&
366     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
367      (Name.find("to") != Name.npos)))
368    return FILTER_WEAK;
369
370  return FILTER_NORMAL;
371}
372
373void RecognizableInstr::handleOperand(
374  bool optional,
375  unsigned &operandIndex,
376  unsigned &physicalOperandIndex,
377  unsigned &numPhysicalOperands,
378  unsigned *operandMapping,
379  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
380  if (optional) {
381    if (physicalOperandIndex >= numPhysicalOperands)
382      return;
383  } else {
384    assert(physicalOperandIndex < numPhysicalOperands);
385  }
386
387  while (operandMapping[operandIndex] != operandIndex) {
388    Spec->operands[operandIndex].encoding = ENCODING_DUP;
389    Spec->operands[operandIndex].type =
390      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
391    ++operandIndex;
392  }
393
394  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
395
396  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
397                                                              HasOpSizePrefix);
398  Spec->operands[operandIndex].type = typeFromString(typeName,
399                                                      IsSSE,
400                                                      HasREX_WPrefix,
401                                                      HasOpSizePrefix);
402
403  ++operandIndex;
404  ++physicalOperandIndex;
405}
406
407void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
408  Spec->name       = Name;
409
410  if (!Rec->isSubClassOf("X86Inst"))
411    return;
412
413  switch (filter()) {
414  case FILTER_WEAK:
415    Spec->filtered = true;
416    break;
417  case FILTER_STRONG:
418    ShouldBeEmitted = false;
419    return;
420  case FILTER_NORMAL:
421    break;
422  }
423
424  Spec->insnContext = insnContext();
425
426  const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
427
428  unsigned operandIndex;
429  unsigned numOperands = OperandList.size();
430  unsigned numPhysicalOperands = 0;
431
432  // operandMapping maps from operands in OperandList to their originals.
433  // If operandMapping[i] != i, then the entry is a duplicate.
434  unsigned operandMapping[X86_MAX_OPERANDS];
435
436  bool hasFROperands = false;
437
438  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
439
440  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
441    if (OperandList[operandIndex].Constraints.size()) {
442      const CodeGenInstruction::ConstraintInfo &Constraint =
443        OperandList[operandIndex].Constraints[0];
444      if (Constraint.isTied()) {
445        operandMapping[operandIndex] = Constraint.getTiedOperand();
446      } else {
447        ++numPhysicalOperands;
448        operandMapping[operandIndex] = operandIndex;
449      }
450    } else {
451      ++numPhysicalOperands;
452      operandMapping[operandIndex] = operandIndex;
453    }
454
455    const std::string &recName = OperandList[operandIndex].Rec->getName();
456
457    if (recName.find("FR") != recName.npos)
458      hasFROperands = true;
459  }
460
461  if (hasFROperands && Name.find("MOV") != Name.npos &&
462     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
463      (Name.find("to") != Name.npos)))
464    ShouldBeEmitted = false;
465
466  if (!ShouldBeEmitted)
467    return;
468
469#define HANDLE_OPERAND(class)               \
470  handleOperand(false,                      \
471                operandIndex,               \
472                physicalOperandIndex,       \
473                numPhysicalOperands,        \
474                operandMapping,             \
475                class##EncodingFromString);
476
477#define HANDLE_OPTIONAL(class)              \
478  handleOperand(true,                       \
479                operandIndex,               \
480                physicalOperandIndex,       \
481                numPhysicalOperands,        \
482                operandMapping,             \
483                class##EncodingFromString);
484
485  // operandIndex should always be < numOperands
486  operandIndex = 0;
487  // physicalOperandIndex should always be < numPhysicalOperands
488  unsigned physicalOperandIndex = 0;
489
490  switch (Form) {
491  case X86Local::RawFrm:
492    // Operand 1 (optional) is an address or immediate.
493    // Operand 2 (optional) is an immediate.
494    assert(numPhysicalOperands <= 2 &&
495           "Unexpected number of operands for RawFrm");
496    HANDLE_OPTIONAL(relocation)
497    HANDLE_OPTIONAL(immediate)
498    break;
499  case X86Local::AddRegFrm:
500    // Operand 1 is added to the opcode.
501    // Operand 2 (optional) is an address.
502    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
503           "Unexpected number of operands for AddRegFrm");
504    HANDLE_OPERAND(opcodeModifier)
505    HANDLE_OPTIONAL(relocation)
506    break;
507  case X86Local::MRMDestReg:
508    // Operand 1 is a register operand in the R/M field.
509    // Operand 2 is a register operand in the Reg/Opcode field.
510    // Operand 3 (optional) is an immediate.
511    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
512           "Unexpected number of operands for MRMDestRegFrm");
513    HANDLE_OPERAND(rmRegister)
514    HANDLE_OPERAND(roRegister)
515    HANDLE_OPTIONAL(immediate)
516    break;
517  case X86Local::MRMDestMem:
518    // Operand 1 is a memory operand (possibly SIB-extended)
519    // Operand 2 is a register operand in the Reg/Opcode field.
520    // Operand 3 (optional) is an immediate.
521    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
522           "Unexpected number of operands for MRMDestMemFrm");
523    HANDLE_OPERAND(memory)
524    HANDLE_OPERAND(roRegister)
525    HANDLE_OPTIONAL(immediate)
526    break;
527  case X86Local::MRMSrcReg:
528    // Operand 1 is a register operand in the Reg/Opcode field.
529    // Operand 2 is a register operand in the R/M field.
530    // Operand 3 (optional) is an immediate.
531    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
532           "Unexpected number of operands for MRMSrcRegFrm");
533    HANDLE_OPERAND(roRegister)
534    HANDLE_OPERAND(rmRegister)
535    HANDLE_OPTIONAL(immediate)
536    break;
537  case X86Local::MRMSrcMem:
538    // Operand 1 is a register operand in the Reg/Opcode field.
539    // Operand 2 is a memory operand (possibly SIB-extended)
540    // Operand 3 (optional) is an immediate.
541    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
542           "Unexpected number of operands for MRMSrcMemFrm");
543    HANDLE_OPERAND(roRegister)
544    HANDLE_OPERAND(memory)
545    HANDLE_OPTIONAL(immediate)
546    break;
547  case X86Local::MRM0r:
548  case X86Local::MRM1r:
549  case X86Local::MRM2r:
550  case X86Local::MRM3r:
551  case X86Local::MRM4r:
552  case X86Local::MRM5r:
553  case X86Local::MRM6r:
554  case X86Local::MRM7r:
555    // Operand 1 is a register operand in the R/M field.
556    // Operand 2 (optional) is an immediate or relocation.
557    assert(numPhysicalOperands <= 2 &&
558           "Unexpected number of operands for MRMnRFrm");
559    HANDLE_OPTIONAL(rmRegister)
560    HANDLE_OPTIONAL(relocation)
561    break;
562  case X86Local::MRM0m:
563  case X86Local::MRM1m:
564  case X86Local::MRM2m:
565  case X86Local::MRM3m:
566  case X86Local::MRM4m:
567  case X86Local::MRM5m:
568  case X86Local::MRM6m:
569  case X86Local::MRM7m:
570    // Operand 1 is a memory operand (possibly SIB-extended)
571    // Operand 2 (optional) is an immediate or relocation.
572    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
573           "Unexpected number of operands for MRMnMFrm");
574    HANDLE_OPERAND(memory)
575    HANDLE_OPTIONAL(relocation)
576    break;
577  case X86Local::MRMInitReg:
578    // Ignored.
579    break;
580  }
581
582  #undef HANDLE_OPERAND
583  #undef HANDLE_OPTIONAL
584}
585
586void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
587  // Special cases where the LLVM tables are not complete
588
589#define MAP(from, to)                     \
590  case X86Local::MRM_##from:              \
591    filter = new ExactFilter(0x##from);   \
592    break;
593
594  OpcodeType    opcodeType  = (OpcodeType)-1;
595
596  ModRMFilter*  filter      = NULL;
597  uint8_t       opcodeToSet = 0;
598
599  switch (Prefix) {
600  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
601  case X86Local::XD:
602  case X86Local::XS:
603  case X86Local::TB:
604    opcodeType = TWOBYTE;
605
606    switch (Opcode) {
607    default:
608      if (needsModRMForDecode(Form))
609        filter = new ModFilter(isRegFormat(Form));
610      else
611        filter = new DumbFilter();
612      break;
613#define EXTENSION_TABLE(n) case 0x##n:
614    TWO_BYTE_EXTENSION_TABLES
615#undef EXTENSION_TABLE
616      switch (Form) {
617      default:
618        llvm_unreachable("Unhandled two-byte extended opcode");
619      case X86Local::MRM0r:
620      case X86Local::MRM1r:
621      case X86Local::MRM2r:
622      case X86Local::MRM3r:
623      case X86Local::MRM4r:
624      case X86Local::MRM5r:
625      case X86Local::MRM6r:
626      case X86Local::MRM7r:
627        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
628        break;
629      case X86Local::MRM0m:
630      case X86Local::MRM1m:
631      case X86Local::MRM2m:
632      case X86Local::MRM3m:
633      case X86Local::MRM4m:
634      case X86Local::MRM5m:
635      case X86Local::MRM6m:
636      case X86Local::MRM7m:
637        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
638        break;
639      MRM_MAPPING
640      } // switch (Form)
641      break;
642    } // switch (Opcode)
643    opcodeToSet = Opcode;
644    break;
645  case X86Local::T8:
646    opcodeType = THREEBYTE_38;
647    if (needsModRMForDecode(Form))
648      filter = new ModFilter(isRegFormat(Form));
649    else
650      filter = new DumbFilter();
651    opcodeToSet = Opcode;
652    break;
653  case X86Local::P_TA:
654    opcodeType = THREEBYTE_3A;
655    if (needsModRMForDecode(Form))
656      filter = new ModFilter(isRegFormat(Form));
657    else
658      filter = new DumbFilter();
659    opcodeToSet = Opcode;
660    break;
661  case X86Local::D8:
662  case X86Local::D9:
663  case X86Local::DA:
664  case X86Local::DB:
665  case X86Local::DC:
666  case X86Local::DD:
667  case X86Local::DE:
668  case X86Local::DF:
669    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
670    opcodeType = ONEBYTE;
671    if (Form == X86Local::AddRegFrm) {
672      Spec->modifierType = MODIFIER_MODRM;
673      Spec->modifierBase = Opcode;
674      filter = new AddRegEscapeFilter(Opcode);
675    } else {
676      filter = new EscapeFilter(true, Opcode);
677    }
678    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
679    break;
680  default:
681    opcodeType = ONEBYTE;
682    switch (Opcode) {
683#define EXTENSION_TABLE(n) case 0x##n:
684    ONE_BYTE_EXTENSION_TABLES
685#undef EXTENSION_TABLE
686      switch (Form) {
687      default:
688        llvm_unreachable("Fell through the cracks of a single-byte "
689                         "extended opcode");
690      case X86Local::MRM0r:
691      case X86Local::MRM1r:
692      case X86Local::MRM2r:
693      case X86Local::MRM3r:
694      case X86Local::MRM4r:
695      case X86Local::MRM5r:
696      case X86Local::MRM6r:
697      case X86Local::MRM7r:
698        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
699        break;
700      case X86Local::MRM0m:
701      case X86Local::MRM1m:
702      case X86Local::MRM2m:
703      case X86Local::MRM3m:
704      case X86Local::MRM4m:
705      case X86Local::MRM5m:
706      case X86Local::MRM6m:
707      case X86Local::MRM7m:
708        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
709        break;
710      MRM_MAPPING
711      } // switch (Form)
712      break;
713    case 0xd8:
714    case 0xd9:
715    case 0xda:
716    case 0xdb:
717    case 0xdc:
718    case 0xdd:
719    case 0xde:
720    case 0xdf:
721      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
722      break;
723    default:
724      if (needsModRMForDecode(Form))
725        filter = new ModFilter(isRegFormat(Form));
726      else
727        filter = new DumbFilter();
728      break;
729    } // switch (Opcode)
730    opcodeToSet = Opcode;
731  } // switch (Prefix)
732
733  assert(opcodeType != (OpcodeType)-1 &&
734         "Opcode type not set");
735  assert(filter && "Filter not set");
736
737  if (Form == X86Local::AddRegFrm) {
738    if(Spec->modifierType != MODIFIER_MODRM) {
739      assert(opcodeToSet < 0xf9 &&
740             "Not enough room for all ADDREG_FRM operands");
741
742      uint8_t currentOpcode;
743
744      for (currentOpcode = opcodeToSet;
745           currentOpcode < opcodeToSet + 8;
746           ++currentOpcode)
747        tables.setTableFields(opcodeType,
748                              insnContext(),
749                              currentOpcode,
750                              *filter,
751                              UID);
752
753      Spec->modifierType = MODIFIER_OPCODE;
754      Spec->modifierBase = opcodeToSet;
755    } else {
756      // modifierBase was set where MODIFIER_MODRM was set
757      tables.setTableFields(opcodeType,
758                            insnContext(),
759                            opcodeToSet,
760                            *filter,
761                            UID);
762    }
763  } else {
764    tables.setTableFields(opcodeType,
765                          insnContext(),
766                          opcodeToSet,
767                          *filter,
768                          UID);
769
770    Spec->modifierType = MODIFIER_NONE;
771    Spec->modifierBase = opcodeToSet;
772  }
773
774  delete filter;
775
776#undef MAP
777}
778
779#define TYPE(str, type) if (s == str) return type;
780OperandType RecognizableInstr::typeFromString(const std::string &s,
781                                              bool isSSE,
782                                              bool hasREX_WPrefix,
783                                              bool hasOpSizePrefix) {
784  if (isSSE) {
785    // For SSE instructions, we ignore the OpSize prefix and force operand
786    // sizes.
787    TYPE("GR16",              TYPE_R16)
788    TYPE("GR32",              TYPE_R32)
789    TYPE("GR64",              TYPE_R64)
790  }
791  if(hasREX_WPrefix) {
792    // For instructions with a REX_W prefix, a declared 32-bit register encoding
793    // is special.
794    TYPE("GR32",              TYPE_R32)
795  }
796  if(!hasOpSizePrefix) {
797    // For instructions without an OpSize prefix, a declared 16-bit register or
798    // immediate encoding is special.
799    TYPE("GR16",              TYPE_R16)
800    TYPE("i16imm",            TYPE_IMM16)
801  }
802  TYPE("i16mem",              TYPE_Mv)
803  TYPE("i16imm",              TYPE_IMMv)
804  TYPE("i16i8imm",            TYPE_IMMv)
805  TYPE("GR16",                TYPE_Rv)
806  TYPE("i32mem",              TYPE_Mv)
807  TYPE("i32imm",              TYPE_IMMv)
808  TYPE("i32i8imm",            TYPE_IMM32)
809  TYPE("GR32",                TYPE_Rv)
810  TYPE("i64mem",              TYPE_Mv)
811  TYPE("i64i32imm",           TYPE_IMM64)
812  TYPE("i64i8imm",            TYPE_IMM64)
813  TYPE("GR64",                TYPE_R64)
814  TYPE("i8mem",               TYPE_M8)
815  TYPE("i8imm",               TYPE_IMM8)
816  TYPE("GR8",                 TYPE_R8)
817  TYPE("VR128",               TYPE_XMM128)
818  TYPE("f128mem",             TYPE_M128)
819  TYPE("FR64",                TYPE_XMM64)
820  TYPE("f64mem",              TYPE_M64FP)
821  TYPE("FR32",                TYPE_XMM32)
822  TYPE("f32mem",              TYPE_M32FP)
823  TYPE("RST",                 TYPE_ST)
824  TYPE("i128mem",             TYPE_M128)
825  TYPE("i64i32imm_pcrel",     TYPE_REL64)
826  TYPE("i32imm_pcrel",        TYPE_REL32)
827  TYPE("SSECC",               TYPE_IMM3)
828  TYPE("brtarget",            TYPE_RELv)
829  TYPE("brtarget8",           TYPE_REL8)
830  TYPE("f80mem",              TYPE_M80FP)
831  TYPE("lea32mem",            TYPE_LEA)
832  TYPE("lea64_32mem",         TYPE_LEA)
833  TYPE("lea64mem",            TYPE_LEA)
834  TYPE("VR64",                TYPE_MM64)
835  TYPE("i64imm",              TYPE_IMMv)
836  TYPE("opaque32mem",         TYPE_M1616)
837  TYPE("opaque48mem",         TYPE_M1632)
838  TYPE("opaque80mem",         TYPE_M1664)
839  TYPE("opaque512mem",        TYPE_M512)
840  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
841  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
842  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
843  TYPE("offset8",             TYPE_MOFFS8)
844  TYPE("offset16",            TYPE_MOFFS16)
845  TYPE("offset32",            TYPE_MOFFS32)
846  TYPE("offset64",            TYPE_MOFFS64)
847  errs() << "Unhandled type string " << s << "\n";
848  llvm_unreachable("Unhandled type string");
849}
850#undef TYPE
851
852#define ENCODING(str, encoding) if (s == str) return encoding;
853OperandEncoding RecognizableInstr::immediateEncodingFromString
854  (const std::string &s,
855   bool hasOpSizePrefix) {
856  if(!hasOpSizePrefix) {
857    // For instructions without an OpSize prefix, a declared 16-bit register or
858    // immediate encoding is special.
859    ENCODING("i16imm",        ENCODING_IW)
860  }
861  ENCODING("i32i8imm",        ENCODING_IB)
862  ENCODING("SSECC",           ENCODING_IB)
863  ENCODING("i16imm",          ENCODING_Iv)
864  ENCODING("i16i8imm",        ENCODING_IB)
865  ENCODING("i32imm",          ENCODING_Iv)
866  ENCODING("i64i32imm",       ENCODING_ID)
867  ENCODING("i64i8imm",        ENCODING_IB)
868  ENCODING("i8imm",           ENCODING_IB)
869  errs() << "Unhandled immediate encoding " << s << "\n";
870  llvm_unreachable("Unhandled immediate encoding");
871}
872
873OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
874  (const std::string &s,
875   bool hasOpSizePrefix) {
876  ENCODING("GR16",            ENCODING_RM)
877  ENCODING("GR32",            ENCODING_RM)
878  ENCODING("GR64",            ENCODING_RM)
879  ENCODING("GR8",             ENCODING_RM)
880  ENCODING("VR128",           ENCODING_RM)
881  ENCODING("FR64",            ENCODING_RM)
882  ENCODING("FR32",            ENCODING_RM)
883  ENCODING("VR64",            ENCODING_RM)
884  errs() << "Unhandled R/M register encoding " << s << "\n";
885  llvm_unreachable("Unhandled R/M register encoding");
886}
887
888OperandEncoding RecognizableInstr::roRegisterEncodingFromString
889  (const std::string &s,
890   bool hasOpSizePrefix) {
891  ENCODING("GR16",            ENCODING_REG)
892  ENCODING("GR32",            ENCODING_REG)
893  ENCODING("GR64",            ENCODING_REG)
894  ENCODING("GR8",             ENCODING_REG)
895  ENCODING("VR128",           ENCODING_REG)
896  ENCODING("FR64",            ENCODING_REG)
897  ENCODING("FR32",            ENCODING_REG)
898  ENCODING("VR64",            ENCODING_REG)
899  ENCODING("SEGMENT_REG",     ENCODING_REG)
900  ENCODING("DEBUG_REG",       ENCODING_REG)
901  ENCODING("CONTROL_REG",     ENCODING_REG)
902  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
903  llvm_unreachable("Unhandled reg/opcode register encoding");
904}
905
906OperandEncoding RecognizableInstr::memoryEncodingFromString
907  (const std::string &s,
908   bool hasOpSizePrefix) {
909  ENCODING("i16mem",          ENCODING_RM)
910  ENCODING("i32mem",          ENCODING_RM)
911  ENCODING("i64mem",          ENCODING_RM)
912  ENCODING("i8mem",           ENCODING_RM)
913  ENCODING("f128mem",         ENCODING_RM)
914  ENCODING("f64mem",          ENCODING_RM)
915  ENCODING("f32mem",          ENCODING_RM)
916  ENCODING("i128mem",         ENCODING_RM)
917  ENCODING("f80mem",          ENCODING_RM)
918  ENCODING("lea32mem",        ENCODING_RM)
919  ENCODING("lea64_32mem",     ENCODING_RM)
920  ENCODING("lea64mem",        ENCODING_RM)
921  ENCODING("opaque32mem",     ENCODING_RM)
922  ENCODING("opaque48mem",     ENCODING_RM)
923  ENCODING("opaque80mem",     ENCODING_RM)
924  ENCODING("opaque512mem",    ENCODING_RM)
925  errs() << "Unhandled memory encoding " << s << "\n";
926  llvm_unreachable("Unhandled memory encoding");
927}
928
929OperandEncoding RecognizableInstr::relocationEncodingFromString
930  (const std::string &s,
931   bool hasOpSizePrefix) {
932  if(!hasOpSizePrefix) {
933    // For instructions without an OpSize prefix, a declared 16-bit register or
934    // immediate encoding is special.
935    ENCODING("i16imm",        ENCODING_IW)
936  }
937  ENCODING("i16imm",          ENCODING_Iv)
938  ENCODING("i16i8imm",        ENCODING_IB)
939  ENCODING("i32imm",          ENCODING_Iv)
940  ENCODING("i32i8imm",        ENCODING_IB)
941  ENCODING("i64i32imm",       ENCODING_ID)
942  ENCODING("i64i8imm",        ENCODING_IB)
943  ENCODING("i8imm",           ENCODING_IB)
944  ENCODING("i64i32imm_pcrel", ENCODING_ID)
945  ENCODING("i32imm_pcrel",    ENCODING_ID)
946  ENCODING("brtarget",        ENCODING_Iv)
947  ENCODING("brtarget8",       ENCODING_IB)
948  ENCODING("i64imm",          ENCODING_IO)
949  ENCODING("offset8",         ENCODING_Ia)
950  ENCODING("offset16",        ENCODING_Ia)
951  ENCODING("offset32",        ENCODING_Ia)
952  ENCODING("offset64",        ENCODING_Ia)
953  errs() << "Unhandled relocation encoding " << s << "\n";
954  llvm_unreachable("Unhandled relocation encoding");
955}
956
957OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
958  (const std::string &s,
959   bool hasOpSizePrefix) {
960  ENCODING("RST",             ENCODING_I)
961  ENCODING("GR32",            ENCODING_Rv)
962  ENCODING("GR64",            ENCODING_RO)
963  ENCODING("GR16",            ENCODING_Rv)
964  ENCODING("GR8",             ENCODING_RB)
965  errs() << "Unhandled opcode modifier encoding " << s << "\n";
966  llvm_unreachable("Unhandled opcode modifier encoding");
967}
968#undef ENCODING
969