X86RecognizableInstr.cpp revision 201360 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27// A clone of X86 since we can't depend on something that is generated.
28namespace X86Local {
29  enum {
30    Pseudo      = 0,
31    RawFrm      = 1,
32    AddRegFrm   = 2,
33    MRMDestReg  = 3,
34    MRMDestMem  = 4,
35    MRMSrcReg   = 5,
36    MRMSrcMem   = 6,
37    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
38    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
39    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
40    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
41    MRMInitReg  = 32
42  };
43
44  enum {
45    TB  = 1,
46    REP = 2,
47    D8 = 3, D9 = 4, DA = 5, DB = 6,
48    DC = 7, DD = 8, DE = 9, DF = 10,
49    XD = 11,  XS = 12,
50    T8 = 13,  TA = 14
51  };
52}
53
54#define ONE_BYTE_EXTENSION_TABLES \
55  EXTENSION_TABLE(80)             \
56  EXTENSION_TABLE(81)             \
57  EXTENSION_TABLE(82)             \
58  EXTENSION_TABLE(83)             \
59  EXTENSION_TABLE(8f)             \
60  EXTENSION_TABLE(c0)             \
61  EXTENSION_TABLE(c1)             \
62  EXTENSION_TABLE(c6)             \
63  EXTENSION_TABLE(c7)             \
64  EXTENSION_TABLE(d0)             \
65  EXTENSION_TABLE(d1)             \
66  EXTENSION_TABLE(d2)             \
67  EXTENSION_TABLE(d3)             \
68  EXTENSION_TABLE(f6)             \
69  EXTENSION_TABLE(f7)             \
70  EXTENSION_TABLE(fe)             \
71  EXTENSION_TABLE(ff)
72
73#define TWO_BYTE_EXTENSION_TABLES \
74  EXTENSION_TABLE(00)             \
75  EXTENSION_TABLE(01)             \
76  EXTENSION_TABLE(18)             \
77  EXTENSION_TABLE(71)             \
78  EXTENSION_TABLE(72)             \
79  EXTENSION_TABLE(73)             \
80  EXTENSION_TABLE(ae)             \
81  EXTENSION_TABLE(b9)             \
82  EXTENSION_TABLE(ba)             \
83  EXTENSION_TABLE(c7)
84
85#define TWO_BYTE_FULL_EXTENSION_TABLES \
86  EXTENSION_TABLE(01)
87
88
89using namespace X86Disassembler;
90
91/// needsModRMForDecode - Indicates whether a particular instruction requires a
92///   ModR/M byte for the instruction to be properly decoded.  For example, a
93///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
94///   0b11.
95///
96/// @param form - The form of the instruction.
97/// @return     - true if the form implies that a ModR/M byte is required, false
98///               otherwise.
99static bool needsModRMForDecode(uint8_t form) {
100  if (form == X86Local::MRMDestReg    ||
101     form == X86Local::MRMDestMem    ||
102     form == X86Local::MRMSrcReg     ||
103     form == X86Local::MRMSrcMem     ||
104     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
105     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
106    return true;
107  else
108    return false;
109}
110
111/// isRegFormat - Indicates whether a particular form requires the Mod field of
112///   the ModR/M byte to be 0b11.
113///
114/// @param form - The form of the instruction.
115/// @return     - true if the form implies that Mod must be 0b11, false
116///               otherwise.
117static bool isRegFormat(uint8_t form) {
118  if (form == X86Local::MRMDestReg ||
119     form == X86Local::MRMSrcReg  ||
120     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
121    return true;
122  else
123    return false;
124}
125
126/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
127///   Useful for switch statements and the like.
128///
129/// @param init - A reference to the BitsInit to be decoded.
130/// @return     - The field, with the first bit in the BitsInit as the lowest
131///               order bit.
132static uint8_t byteFromBitsInit(BitsInit &init) {
133  int width = init.getNumBits();
134
135  assert(width <= 8 && "Field is too large for uint8_t!");
136
137  int     index;
138  uint8_t mask = 0x01;
139
140  uint8_t ret = 0;
141
142  for (index = 0; index < width; index++) {
143    if (static_cast<BitInit*>(init.getBit(index))->getValue())
144      ret |= mask;
145
146    mask <<= 1;
147  }
148
149  return ret;
150}
151
152/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
153///   name of the field.
154///
155/// @param rec  - The record from which to extract the value.
156/// @param name - The name of the field in the record.
157/// @return     - The field, as translated by byteFromBitsInit().
158static uint8_t byteFromRec(const Record* rec, const std::string &name) {
159  BitsInit* bits = rec->getValueAsBitsInit(name);
160  return byteFromBitsInit(*bits);
161}
162
163RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
164                                     const CodeGenInstruction &insn,
165                                     InstrUID uid) {
166  UID = uid;
167
168  Rec = insn.TheDef;
169  Name = Rec->getName();
170  Spec = &tables.specForUID(UID);
171
172  if (!Rec->isSubClassOf("X86Inst")) {
173    ShouldBeEmitted = false;
174    return;
175  }
176
177  Prefix   = byteFromRec(Rec, "Prefix");
178  Opcode   = byteFromRec(Rec, "Opcode");
179  Form     = byteFromRec(Rec, "FormBits");
180  SegOvr   = byteFromRec(Rec, "SegOvrBits");
181
182  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
183  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
184  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
185  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
186
187  Name      = Rec->getName();
188  AsmString = Rec->getValueAsString("AsmString");
189
190  Operands = &insn.OperandList;
191
192  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
193  HasFROperands    = false;
194
195  ShouldBeEmitted  = true;
196}
197
198void RecognizableInstr::processInstr(DisassemblerTables &tables,
199                                   const CodeGenInstruction &insn,
200                                   InstrUID uid)
201{
202  RecognizableInstr recogInstr(tables, insn, uid);
203
204  recogInstr.emitInstructionSpecifier(tables);
205
206  if (recogInstr.shouldBeEmitted())
207    recogInstr.emitDecodePath(tables);
208}
209
210InstructionContext RecognizableInstr::insnContext() const {
211  InstructionContext insnContext;
212
213  if (Name.find("64") != Name.npos || HasREX_WPrefix) {
214    if (HasREX_WPrefix && HasOpSizePrefix)
215      insnContext = IC_64BIT_REXW_OPSIZE;
216    else if (HasOpSizePrefix)
217      insnContext = IC_64BIT_OPSIZE;
218    else if (HasREX_WPrefix && Prefix == X86Local::XS)
219      insnContext = IC_64BIT_REXW_XS;
220    else if (HasREX_WPrefix && Prefix == X86Local::XD)
221      insnContext = IC_64BIT_REXW_XD;
222    else if (Prefix == X86Local::XD)
223      insnContext = IC_64BIT_XD;
224    else if (Prefix == X86Local::XS)
225      insnContext = IC_64BIT_XS;
226    else if (HasREX_WPrefix)
227      insnContext = IC_64BIT_REXW;
228    else
229      insnContext = IC_64BIT;
230  } else {
231    if (HasOpSizePrefix)
232      insnContext = IC_OPSIZE;
233    else if (Prefix == X86Local::XD)
234      insnContext = IC_XD;
235    else if (Prefix == X86Local::XS)
236      insnContext = IC_XS;
237    else
238      insnContext = IC;
239  }
240
241  return insnContext;
242}
243
244RecognizableInstr::filter_ret RecognizableInstr::filter() const {
245  // Filter out intrinsics
246
247  if (!Rec->isSubClassOf("X86Inst"))
248    return FILTER_STRONG;
249
250  if (Form == X86Local::Pseudo ||
251      IsCodeGenOnly)
252    return FILTER_STRONG;
253
254  // Filter out instructions with a LOCK prefix;
255  //   prefer forms that do not have the prefix
256  if (HasLockPrefix)
257    return FILTER_WEAK;
258
259  // Filter out artificial instructions
260
261  if (Name.find("TAILJMP") != Name.npos    ||
262     Name.find("_Int") != Name.npos       ||
263     Name.find("_int") != Name.npos       ||
264     Name.find("Int_") != Name.npos       ||
265     Name.find("_NOREX") != Name.npos     ||
266     Name.find("EH_RETURN") != Name.npos  ||
267     Name.find("V_SET") != Name.npos      ||
268     Name.find("LOCK_") != Name.npos      ||
269     Name.find("WIN") != Name.npos)
270    return FILTER_STRONG;
271
272  // Special cases.
273
274  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
275    return FILTER_WEAK;
276  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
277    return FILTER_WEAK;
278
279  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
280    return FILTER_WEAK;
281  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
282    return FILTER_WEAK;
283  if (Name.find("Fs") != Name.npos)
284    return FILTER_WEAK;
285  if (Name == "MOVLPDrr"          ||
286      Name == "MOVLPSrr"          ||
287      Name == "PUSHFQ"            ||
288      Name == "BSF16rr"           ||
289      Name == "BSF16rm"           ||
290      Name == "BSR16rr"           ||
291      Name == "BSR16rm"           ||
292      Name == "MOVSX16rm8"        ||
293      Name == "MOVSX16rr8"        ||
294      Name == "MOVZX16rm8"        ||
295      Name == "MOVZX16rr8"        ||
296      Name == "PUSH32i16"         ||
297      Name == "PUSH64i16"         ||
298      Name == "MOVPQI2QImr"       ||
299      Name == "MOVSDmr"           ||
300      Name == "MOVSDrm"           ||
301      Name == "MOVSSmr"           ||
302      Name == "MOVSSrm"           ||
303      Name == "MMX_MOVD64rrv164"  ||
304      Name == "CRC32m16"          ||
305      Name == "MOV64ri64i32"      ||
306      Name == "CRC32r16")
307    return FILTER_WEAK;
308
309  // Filter out instructions with segment override prefixes.
310  // They're too messy to handle now and we'll special case them if needed.
311
312  if (SegOvr)
313    return FILTER_STRONG;
314
315  // Filter out instructions that can't be printed.
316
317  if (AsmString.size() == 0)
318    return FILTER_STRONG;
319
320  // Filter out instructions with subreg operands.
321
322  if (AsmString.find("subreg") != AsmString.npos)
323    return FILTER_STRONG;
324
325  assert(Form != X86Local::MRMInitReg &&
326         "FORMAT_MRMINITREG instruction not skipped");
327
328  if (HasFROperands && Name.find("MOV") != Name.npos &&
329     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
330      (Name.find("to") != Name.npos)))
331    return FILTER_WEAK;
332
333  return FILTER_NORMAL;
334}
335
336void RecognizableInstr::handleOperand(
337  bool optional,
338  unsigned &operandIndex,
339  unsigned &physicalOperandIndex,
340  unsigned &numPhysicalOperands,
341  unsigned *operandMapping,
342  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
343  if (optional) {
344    if (physicalOperandIndex >= numPhysicalOperands)
345      return;
346  } else {
347    assert(physicalOperandIndex < numPhysicalOperands);
348  }
349
350  while (operandMapping[operandIndex] != operandIndex) {
351    Spec->operands[operandIndex].encoding = ENCODING_DUP;
352    Spec->operands[operandIndex].type =
353      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
354    ++operandIndex;
355  }
356
357  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
358
359  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
360                                                              HasOpSizePrefix);
361  Spec->operands[operandIndex].type = typeFromString(typeName,
362                                                      IsSSE,
363                                                      HasREX_WPrefix,
364                                                      HasOpSizePrefix);
365
366  ++operandIndex;
367  ++physicalOperandIndex;
368}
369
370void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
371  Spec->name       = Name;
372
373  if (!Rec->isSubClassOf("X86Inst"))
374    return;
375
376  switch (filter()) {
377  case FILTER_WEAK:
378    Spec->filtered = true;
379    break;
380  case FILTER_STRONG:
381    ShouldBeEmitted = false;
382    return;
383  case FILTER_NORMAL:
384    break;
385  }
386
387  Spec->insnContext = insnContext();
388
389  const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
390
391  unsigned operandIndex;
392  unsigned numOperands = OperandList.size();
393  unsigned numPhysicalOperands = 0;
394
395  // operandMapping maps from operands in OperandList to their originals.
396  // If operandMapping[i] != i, then the entry is a duplicate.
397  unsigned operandMapping[X86_MAX_OPERANDS];
398
399  bool hasFROperands = false;
400
401  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
402
403  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
404    if (OperandList[operandIndex].Constraints.size()) {
405      const std::string &constraint = OperandList[operandIndex].Constraints[0];
406      std::string::size_type tiedToPos;
407
408      if ((tiedToPos = constraint.find(" << 16) | (1 << TOI::TIED_TO))")) !=
409         constraint.npos) {
410        tiedToPos--;
411        operandMapping[operandIndex] = constraint[tiedToPos] - '0';
412      } else {
413        ++numPhysicalOperands;
414        operandMapping[operandIndex] = operandIndex;
415      }
416    } else {
417      ++numPhysicalOperands;
418      operandMapping[operandIndex] = operandIndex;
419    }
420
421    const std::string &recName = OperandList[operandIndex].Rec->getName();
422
423    if (recName.find("FR") != recName.npos)
424      hasFROperands = true;
425  }
426
427  if (hasFROperands && Name.find("MOV") != Name.npos &&
428     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
429      (Name.find("to") != Name.npos)))
430    ShouldBeEmitted = false;
431
432  if (!ShouldBeEmitted)
433    return;
434
435#define HANDLE_OPERAND(class)               \
436  handleOperand(false,                      \
437                operandIndex,               \
438                physicalOperandIndex,       \
439                numPhysicalOperands,        \
440                operandMapping,             \
441                class##EncodingFromString);
442
443#define HANDLE_OPTIONAL(class)              \
444  handleOperand(true,                       \
445                operandIndex,               \
446                physicalOperandIndex,       \
447                numPhysicalOperands,        \
448                operandMapping,             \
449                class##EncodingFromString);
450
451  // operandIndex should always be < numOperands
452  operandIndex = 0;
453  // physicalOperandIndex should always be < numPhysicalOperands
454  unsigned physicalOperandIndex = 0;
455
456  switch (Form) {
457  case X86Local::RawFrm:
458    // Operand 1 (optional) is an address or immediate.
459    // Operand 2 (optional) is an immediate.
460    assert(numPhysicalOperands <= 2 &&
461           "Unexpected number of operands for RawFrm");
462    HANDLE_OPTIONAL(relocation)
463    HANDLE_OPTIONAL(immediate)
464    break;
465  case X86Local::AddRegFrm:
466    // Operand 1 is added to the opcode.
467    // Operand 2 (optional) is an address.
468    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
469           "Unexpected number of operands for AddRegFrm");
470    HANDLE_OPERAND(opcodeModifier)
471    HANDLE_OPTIONAL(relocation)
472    break;
473  case X86Local::MRMDestReg:
474    // Operand 1 is a register operand in the R/M field.
475    // Operand 2 is a register operand in the Reg/Opcode field.
476    // Operand 3 (optional) is an immediate.
477    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
478           "Unexpected number of operands for MRMDestRegFrm");
479    HANDLE_OPERAND(rmRegister)
480    HANDLE_OPERAND(roRegister)
481    HANDLE_OPTIONAL(immediate)
482    break;
483  case X86Local::MRMDestMem:
484    // Operand 1 is a memory operand (possibly SIB-extended)
485    // Operand 2 is a register operand in the Reg/Opcode field.
486    // Operand 3 (optional) is an immediate.
487    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
488           "Unexpected number of operands for MRMDestMemFrm");
489    HANDLE_OPERAND(memory)
490    HANDLE_OPERAND(roRegister)
491    HANDLE_OPTIONAL(immediate)
492    break;
493  case X86Local::MRMSrcReg:
494    // Operand 1 is a register operand in the Reg/Opcode field.
495    // Operand 2 is a register operand in the R/M field.
496    // Operand 3 (optional) is an immediate.
497    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
498           "Unexpected number of operands for MRMSrcRegFrm");
499    HANDLE_OPERAND(roRegister)
500    HANDLE_OPERAND(rmRegister)
501    HANDLE_OPTIONAL(immediate)
502    break;
503  case X86Local::MRMSrcMem:
504    // Operand 1 is a register operand in the Reg/Opcode field.
505    // Operand 2 is a memory operand (possibly SIB-extended)
506    // Operand 3 (optional) is an immediate.
507    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
508           "Unexpected number of operands for MRMSrcMemFrm");
509    HANDLE_OPERAND(roRegister)
510    HANDLE_OPERAND(memory)
511    HANDLE_OPTIONAL(immediate)
512    break;
513  case X86Local::MRM0r:
514  case X86Local::MRM1r:
515  case X86Local::MRM2r:
516  case X86Local::MRM3r:
517  case X86Local::MRM4r:
518  case X86Local::MRM5r:
519  case X86Local::MRM6r:
520  case X86Local::MRM7r:
521    // Operand 1 is a register operand in the R/M field.
522    // Operand 2 (optional) is an immediate or relocation.
523    assert(numPhysicalOperands <= 2 &&
524           "Unexpected number of operands for MRMnRFrm");
525    HANDLE_OPTIONAL(rmRegister)
526    HANDLE_OPTIONAL(relocation)
527    break;
528  case X86Local::MRM0m:
529  case X86Local::MRM1m:
530  case X86Local::MRM2m:
531  case X86Local::MRM3m:
532  case X86Local::MRM4m:
533  case X86Local::MRM5m:
534  case X86Local::MRM6m:
535  case X86Local::MRM7m:
536    // Operand 1 is a memory operand (possibly SIB-extended)
537    // Operand 2 (optional) is an immediate or relocation.
538    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
539           "Unexpected number of operands for MRMnMFrm");
540    HANDLE_OPERAND(memory)
541    HANDLE_OPTIONAL(relocation)
542    break;
543  case X86Local::MRMInitReg:
544    // Ignored.
545    break;
546  }
547
548  #undef HANDLE_OPERAND
549  #undef HANDLE_OPTIONAL
550}
551
552void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
553  // Special cases where the LLVM tables are not complete
554
555#define EXACTCASE(class, name, lastbyte)         \
556  if (Name == name) {                           \
557    tables.setTableFields(class,                 \
558                          insnContext(),         \
559                          Opcode,               \
560                          ExactFilter(lastbyte), \
561                          UID);                 \
562    Spec->modifierBase = Opcode;               \
563    return;                                      \
564  }
565
566  EXACTCASE(TWOBYTE, "MONITOR",  0xc8)
567  EXACTCASE(TWOBYTE, "MWAIT",    0xc9)
568  EXACTCASE(TWOBYTE, "SWPGS",    0xf8)
569  EXACTCASE(TWOBYTE, "INVEPT",   0x80)
570  EXACTCASE(TWOBYTE, "INVVPID",  0x81)
571  EXACTCASE(TWOBYTE, "VMCALL",   0xc1)
572  EXACTCASE(TWOBYTE, "VMLAUNCH", 0xc2)
573  EXACTCASE(TWOBYTE, "VMRESUME", 0xc3)
574  EXACTCASE(TWOBYTE, "VMXOFF",   0xc4)
575
576  if (Name == "INVLPG") {
577    tables.setTableFields(TWOBYTE,
578                          insnContext(),
579                          Opcode,
580                          ExtendedFilter(false, 7),
581                          UID);
582    Spec->modifierBase = Opcode;
583    return;
584  }
585
586  OpcodeType    opcodeType  = (OpcodeType)-1;
587
588  ModRMFilter*  filter      = NULL;
589  uint8_t       opcodeToSet = 0;
590
591  switch (Prefix) {
592  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
593  case X86Local::XD:
594  case X86Local::XS:
595  case X86Local::TB:
596    opcodeType = TWOBYTE;
597
598    switch (Opcode) {
599#define EXTENSION_TABLE(n) case 0x##n:
600    TWO_BYTE_EXTENSION_TABLES
601#undef EXTENSION_TABLE
602      switch (Form) {
603      default:
604        llvm_unreachable("Unhandled two-byte extended opcode");
605      case X86Local::MRM0r:
606      case X86Local::MRM1r:
607      case X86Local::MRM2r:
608      case X86Local::MRM3r:
609      case X86Local::MRM4r:
610      case X86Local::MRM5r:
611      case X86Local::MRM6r:
612      case X86Local::MRM7r:
613        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
614        break;
615      case X86Local::MRM0m:
616      case X86Local::MRM1m:
617      case X86Local::MRM2m:
618      case X86Local::MRM3m:
619      case X86Local::MRM4m:
620      case X86Local::MRM5m:
621      case X86Local::MRM6m:
622      case X86Local::MRM7m:
623        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
624        break;
625      } // switch (Form)
626      break;
627    default:
628      if (needsModRMForDecode(Form))
629        filter = new ModFilter(isRegFormat(Form));
630      else
631        filter = new DumbFilter();
632
633      break;
634    } // switch (opcode)
635    opcodeToSet = Opcode;
636    break;
637  case X86Local::T8:
638    opcodeType = THREEBYTE_38;
639    if (needsModRMForDecode(Form))
640      filter = new ModFilter(isRegFormat(Form));
641    else
642      filter = new DumbFilter();
643    opcodeToSet = Opcode;
644    break;
645  case X86Local::TA:
646    opcodeType = THREEBYTE_3A;
647    if (needsModRMForDecode(Form))
648      filter = new ModFilter(isRegFormat(Form));
649    else
650      filter = new DumbFilter();
651    opcodeToSet = Opcode;
652    break;
653  case X86Local::D8:
654  case X86Local::D9:
655  case X86Local::DA:
656  case X86Local::DB:
657  case X86Local::DC:
658  case X86Local::DD:
659  case X86Local::DE:
660  case X86Local::DF:
661    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
662    opcodeType = ONEBYTE;
663    if (Form == X86Local::AddRegFrm) {
664      Spec->modifierType = MODIFIER_MODRM;
665      Spec->modifierBase = Opcode;
666      filter = new AddRegEscapeFilter(Opcode);
667    } else {
668      filter = new EscapeFilter(true, Opcode);
669    }
670    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
671    break;
672  default:
673    opcodeType = ONEBYTE;
674    switch (Opcode) {
675#define EXTENSION_TABLE(n) case 0x##n:
676    ONE_BYTE_EXTENSION_TABLES
677#undef EXTENSION_TABLE
678      switch (Form) {
679      default:
680        llvm_unreachable("Fell through the cracks of a single-byte "
681                         "extended opcode");
682      case X86Local::MRM0r:
683      case X86Local::MRM1r:
684      case X86Local::MRM2r:
685      case X86Local::MRM3r:
686      case X86Local::MRM4r:
687      case X86Local::MRM5r:
688      case X86Local::MRM6r:
689      case X86Local::MRM7r:
690        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
691        break;
692      case X86Local::MRM0m:
693      case X86Local::MRM1m:
694      case X86Local::MRM2m:
695      case X86Local::MRM3m:
696      case X86Local::MRM4m:
697      case X86Local::MRM5m:
698      case X86Local::MRM6m:
699      case X86Local::MRM7m:
700        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
701        break;
702      } // switch (Form)
703      break;
704    case 0xd8:
705    case 0xd9:
706    case 0xda:
707    case 0xdb:
708    case 0xdc:
709    case 0xdd:
710    case 0xde:
711    case 0xdf:
712      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
713      break;
714    default:
715      if (needsModRMForDecode(Form))
716        filter = new ModFilter(isRegFormat(Form));
717      else
718        filter = new DumbFilter();
719      break;
720    } // switch (Opcode)
721    opcodeToSet = Opcode;
722  } // switch (Prefix)
723
724  assert(opcodeType != (OpcodeType)-1 &&
725         "Opcode type not set");
726  assert(filter && "Filter not set");
727
728  if (Form == X86Local::AddRegFrm) {
729    if(Spec->modifierType != MODIFIER_MODRM) {
730      assert(opcodeToSet < 0xf9 &&
731             "Not enough room for all ADDREG_FRM operands");
732
733      uint8_t currentOpcode;
734
735      for (currentOpcode = opcodeToSet;
736           currentOpcode < opcodeToSet + 8;
737           ++currentOpcode)
738        tables.setTableFields(opcodeType,
739                              insnContext(),
740                              currentOpcode,
741                              *filter,
742                              UID);
743
744      Spec->modifierType = MODIFIER_OPCODE;
745      Spec->modifierBase = opcodeToSet;
746    } else {
747      // modifierBase was set where MODIFIER_MODRM was set
748      tables.setTableFields(opcodeType,
749                            insnContext(),
750                            opcodeToSet,
751                            *filter,
752                            UID);
753    }
754  } else {
755    tables.setTableFields(opcodeType,
756                          insnContext(),
757                          opcodeToSet,
758                          *filter,
759                          UID);
760
761    Spec->modifierType = MODIFIER_NONE;
762    Spec->modifierBase = opcodeToSet;
763  }
764
765  delete filter;
766}
767
768#define TYPE(str, type) if (s == str) return type;
769OperandType RecognizableInstr::typeFromString(const std::string &s,
770                                              bool isSSE,
771                                              bool hasREX_WPrefix,
772                                              bool hasOpSizePrefix) {
773  if (isSSE) {
774    // For SSE instructions, we ignore the OpSize prefix and force operand
775    // sizes.
776    TYPE("GR16",              TYPE_R16)
777    TYPE("GR32",              TYPE_R32)
778    TYPE("GR64",              TYPE_R64)
779  }
780  if(hasREX_WPrefix) {
781    // For instructions with a REX_W prefix, a declared 32-bit register encoding
782    // is special.
783    TYPE("GR32",              TYPE_R32)
784  }
785  if(!hasOpSizePrefix) {
786    // For instructions without an OpSize prefix, a declared 16-bit register or
787    // immediate encoding is special.
788    TYPE("GR16",              TYPE_R16)
789    TYPE("i16imm",            TYPE_IMM16)
790  }
791  TYPE("i16mem",              TYPE_Mv)
792  TYPE("i16imm",              TYPE_IMMv)
793  TYPE("i16i8imm",            TYPE_IMMv)
794  TYPE("GR16",                TYPE_Rv)
795  TYPE("i32mem",              TYPE_Mv)
796  TYPE("i32imm",              TYPE_IMMv)
797  TYPE("i32i8imm",            TYPE_IMM32)
798  TYPE("GR32",                TYPE_Rv)
799  TYPE("i64mem",              TYPE_Mv)
800  TYPE("i64i32imm",           TYPE_IMM64)
801  TYPE("i64i8imm",            TYPE_IMM64)
802  TYPE("GR64",                TYPE_R64)
803  TYPE("i8mem",               TYPE_M8)
804  TYPE("i8imm",               TYPE_IMM8)
805  TYPE("GR8",                 TYPE_R8)
806  TYPE("VR128",               TYPE_XMM128)
807  TYPE("f128mem",             TYPE_M128)
808  TYPE("FR64",                TYPE_XMM64)
809  TYPE("f64mem",              TYPE_M64FP)
810  TYPE("FR32",                TYPE_XMM32)
811  TYPE("f32mem",              TYPE_M32FP)
812  TYPE("RST",                 TYPE_ST)
813  TYPE("i128mem",             TYPE_M128)
814  TYPE("i64i32imm_pcrel",     TYPE_REL64)
815  TYPE("i32imm_pcrel",        TYPE_REL32)
816  TYPE("SSECC",               TYPE_IMM8)
817  TYPE("brtarget",            TYPE_RELv)
818  TYPE("brtarget8",           TYPE_REL8)
819  TYPE("f80mem",              TYPE_M80FP)
820  TYPE("lea32mem",            TYPE_LEA)
821  TYPE("lea64_32mem",         TYPE_LEA)
822  TYPE("lea64mem",            TYPE_LEA)
823  TYPE("VR64",                TYPE_MM64)
824  TYPE("i64imm",              TYPE_IMMv)
825  TYPE("opaque32mem",         TYPE_M1616)
826  TYPE("opaque48mem",         TYPE_M1632)
827  TYPE("opaque80mem",         TYPE_M1664)
828  TYPE("opaque512mem",        TYPE_M512)
829  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
830  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
831  TYPE("CONTROL_REG_32",      TYPE_CR32)
832  TYPE("CONTROL_REG_64",      TYPE_CR64)
833  TYPE("offset8",             TYPE_MOFFS8)
834  TYPE("offset16",            TYPE_MOFFS16)
835  TYPE("offset32",            TYPE_MOFFS32)
836  TYPE("offset64",            TYPE_MOFFS64)
837  errs() << "Unhandled type string " << s << "\n";
838  llvm_unreachable("Unhandled type string");
839}
840#undef TYPE
841
842#define ENCODING(str, encoding) if (s == str) return encoding;
843OperandEncoding RecognizableInstr::immediateEncodingFromString
844  (const std::string &s,
845   bool hasOpSizePrefix) {
846  if(!hasOpSizePrefix) {
847    // For instructions without an OpSize prefix, a declared 16-bit register or
848    // immediate encoding is special.
849    ENCODING("i16imm",        ENCODING_IW)
850  }
851  ENCODING("i32i8imm",        ENCODING_IB)
852  ENCODING("SSECC",           ENCODING_IB)
853  ENCODING("i16imm",          ENCODING_Iv)
854  ENCODING("i16i8imm",        ENCODING_IB)
855  ENCODING("i32imm",          ENCODING_Iv)
856  ENCODING("i64i32imm",       ENCODING_ID)
857  ENCODING("i64i8imm",        ENCODING_IB)
858  ENCODING("i8imm",           ENCODING_IB)
859  errs() << "Unhandled immediate encoding " << s << "\n";
860  llvm_unreachable("Unhandled immediate encoding");
861}
862
863OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
864  (const std::string &s,
865   bool hasOpSizePrefix) {
866  ENCODING("GR16",            ENCODING_RM)
867  ENCODING("GR32",            ENCODING_RM)
868  ENCODING("GR64",            ENCODING_RM)
869  ENCODING("GR8",             ENCODING_RM)
870  ENCODING("VR128",           ENCODING_RM)
871  ENCODING("FR64",            ENCODING_RM)
872  ENCODING("FR32",            ENCODING_RM)
873  ENCODING("VR64",            ENCODING_RM)
874  errs() << "Unhandled R/M register encoding " << s << "\n";
875  llvm_unreachable("Unhandled R/M register encoding");
876}
877
878OperandEncoding RecognizableInstr::roRegisterEncodingFromString
879  (const std::string &s,
880   bool hasOpSizePrefix) {
881  ENCODING("GR16",            ENCODING_REG)
882  ENCODING("GR32",            ENCODING_REG)
883  ENCODING("GR64",            ENCODING_REG)
884  ENCODING("GR8",             ENCODING_REG)
885  ENCODING("VR128",           ENCODING_REG)
886  ENCODING("FR64",            ENCODING_REG)
887  ENCODING("FR32",            ENCODING_REG)
888  ENCODING("VR64",            ENCODING_REG)
889  ENCODING("SEGMENT_REG",     ENCODING_REG)
890  ENCODING("DEBUG_REG",       ENCODING_REG)
891  ENCODING("CONTROL_REG_32",  ENCODING_REG)
892  ENCODING("CONTROL_REG_64",  ENCODING_REG)
893  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
894  llvm_unreachable("Unhandled reg/opcode register encoding");
895}
896
897OperandEncoding RecognizableInstr::memoryEncodingFromString
898  (const std::string &s,
899   bool hasOpSizePrefix) {
900  ENCODING("i16mem",          ENCODING_RM)
901  ENCODING("i32mem",          ENCODING_RM)
902  ENCODING("i64mem",          ENCODING_RM)
903  ENCODING("i8mem",           ENCODING_RM)
904  ENCODING("f128mem",         ENCODING_RM)
905  ENCODING("f64mem",          ENCODING_RM)
906  ENCODING("f32mem",          ENCODING_RM)
907  ENCODING("i128mem",         ENCODING_RM)
908  ENCODING("f80mem",          ENCODING_RM)
909  ENCODING("lea32mem",        ENCODING_RM)
910  ENCODING("lea64_32mem",     ENCODING_RM)
911  ENCODING("lea64mem",        ENCODING_RM)
912  ENCODING("opaque32mem",     ENCODING_RM)
913  ENCODING("opaque48mem",     ENCODING_RM)
914  ENCODING("opaque80mem",     ENCODING_RM)
915  ENCODING("opaque512mem",    ENCODING_RM)
916  errs() << "Unhandled memory encoding " << s << "\n";
917  llvm_unreachable("Unhandled memory encoding");
918}
919
920OperandEncoding RecognizableInstr::relocationEncodingFromString
921  (const std::string &s,
922   bool hasOpSizePrefix) {
923  if(!hasOpSizePrefix) {
924    // For instructions without an OpSize prefix, a declared 16-bit register or
925    // immediate encoding is special.
926    ENCODING("i16imm",        ENCODING_IW)
927  }
928  ENCODING("i16imm",          ENCODING_Iv)
929  ENCODING("i16i8imm",        ENCODING_IB)
930  ENCODING("i32imm",          ENCODING_Iv)
931  ENCODING("i32i8imm",        ENCODING_IB)
932  ENCODING("i64i32imm",       ENCODING_ID)
933  ENCODING("i64i8imm",        ENCODING_IB)
934  ENCODING("i8imm",           ENCODING_IB)
935  ENCODING("i64i32imm_pcrel", ENCODING_ID)
936  ENCODING("i32imm_pcrel",    ENCODING_ID)
937  ENCODING("brtarget",        ENCODING_Iv)
938  ENCODING("brtarget8",       ENCODING_IB)
939  ENCODING("i64imm",          ENCODING_IO)
940  ENCODING("offset8",         ENCODING_Ia)
941  ENCODING("offset16",        ENCODING_Ia)
942  ENCODING("offset32",        ENCODING_Ia)
943  ENCODING("offset64",        ENCODING_Ia)
944  errs() << "Unhandled relocation encoding " << s << "\n";
945  llvm_unreachable("Unhandled relocation encoding");
946}
947
948OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
949  (const std::string &s,
950   bool hasOpSizePrefix) {
951  ENCODING("RST",             ENCODING_I)
952  ENCODING("GR32",            ENCODING_Rv)
953  ENCODING("GR64",            ENCODING_RO)
954  ENCODING("GR16",            ENCODING_Rv)
955  ENCODING("GR8",             ENCODING_RB)
956  errs() << "Unhandled opcode modifier encoding " << s << "\n";
957  llvm_unreachable("Unhandled opcode modifier encoding");
958}
959#undef ENCODING
960