X86RecognizableInstr.cpp revision 226633
1201360Srdivacky//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2201360Srdivacky// 3201360Srdivacky// The LLVM Compiler Infrastructure 4201360Srdivacky// 5201360Srdivacky// This file is distributed under the University of Illinois Open Source 6201360Srdivacky// License. See LICENSE.TXT for details. 7201360Srdivacky// 8201360Srdivacky//===----------------------------------------------------------------------===// 9201360Srdivacky// 10201360Srdivacky// This file is part of the X86 Disassembler Emitter. 11201360Srdivacky// It contains the implementation of a single recognizable instruction. 12201360Srdivacky// Documentation for the disassembler emitter in general can be found in 13201360Srdivacky// X86DisasemblerEmitter.h. 14201360Srdivacky// 15201360Srdivacky//===----------------------------------------------------------------------===// 16201360Srdivacky 17201360Srdivacky#include "X86DisassemblerShared.h" 18201360Srdivacky#include "X86RecognizableInstr.h" 19201360Srdivacky#include "X86ModRMFilters.h" 20201360Srdivacky 21201360Srdivacky#include "llvm/Support/ErrorHandling.h" 22201360Srdivacky 23201360Srdivacky#include <string> 24201360Srdivacky 25201360Srdivackyusing namespace llvm; 26201360Srdivacky 27203954Srdivacky#define MRM_MAPPING \ 28203954Srdivacky MAP(C1, 33) \ 29203954Srdivacky MAP(C2, 34) \ 30203954Srdivacky MAP(C3, 35) \ 31203954Srdivacky MAP(C4, 36) \ 32203954Srdivacky MAP(C8, 37) \ 33203954Srdivacky MAP(C9, 38) \ 34203954Srdivacky MAP(E8, 39) \ 35203954Srdivacky MAP(F0, 40) \ 36210299Sed MAP(F8, 41) \ 37219077Sdim MAP(F9, 42) \ 38219077Sdim MAP(D0, 45) \ 39219077Sdim MAP(D1, 46) 40203954Srdivacky 41201360Srdivacky// A clone of X86 since we can't depend on something that is generated. 42201360Srdivackynamespace X86Local { 43201360Srdivacky enum { 44201360Srdivacky Pseudo = 0, 45201360Srdivacky RawFrm = 1, 46201360Srdivacky AddRegFrm = 2, 47201360Srdivacky MRMDestReg = 3, 48201360Srdivacky MRMDestMem = 4, 49201360Srdivacky MRMSrcReg = 5, 50201360Srdivacky MRMSrcMem = 6, 51201360Srdivacky MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 52201360Srdivacky MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 53201360Srdivacky MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 54201360Srdivacky MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 55203954Srdivacky MRMInitReg = 32, 56203954Srdivacky#define MAP(from, to) MRM_##from = to, 57203954Srdivacky MRM_MAPPING 58203954Srdivacky#undef MAP 59218893Sdim RawFrmImm8 = 43, 60218893Sdim RawFrmImm16 = 44, 61203954Srdivacky lastMRM 62201360Srdivacky }; 63201360Srdivacky 64201360Srdivacky enum { 65201360Srdivacky TB = 1, 66201360Srdivacky REP = 2, 67201360Srdivacky D8 = 3, D9 = 4, DA = 5, DB = 6, 68201360Srdivacky DC = 7, DD = 8, DE = 9, DF = 10, 69201360Srdivacky XD = 11, XS = 12, 70203954Srdivacky T8 = 13, P_TA = 14, 71226633Sdim A6 = 15, A7 = 16, TF = 17 72201360Srdivacky }; 73201360Srdivacky} 74203954Srdivacky 75203954Srdivacky// If rows are added to the opcode extension tables, then corresponding entries 76203954Srdivacky// must be added here. 77203954Srdivacky// 78203954Srdivacky// If the row corresponds to a single byte (i.e., 8f), then add an entry for 79203954Srdivacky// that byte to ONE_BYTE_EXTENSION_TABLES. 80203954Srdivacky// 81203954Srdivacky// If the row corresponds to two bytes where the first is 0f, add an entry for 82203954Srdivacky// the second byte to TWO_BYTE_EXTENSION_TABLES. 83203954Srdivacky// 84203954Srdivacky// If the row corresponds to some other set of bytes, you will need to modify 85203954Srdivacky// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes 86203954Srdivacky// to the X86 TD files, except in two cases: if the first two bytes of such a 87203954Srdivacky// new combination are 0f 38 or 0f 3a, you just have to add maps called 88203954Srdivacky// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a 89203954Srdivacky// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line 90203954Srdivacky// in RecognizableInstr::emitDecodePath(). 91203954Srdivacky 92201360Srdivacky#define ONE_BYTE_EXTENSION_TABLES \ 93201360Srdivacky EXTENSION_TABLE(80) \ 94201360Srdivacky EXTENSION_TABLE(81) \ 95201360Srdivacky EXTENSION_TABLE(82) \ 96201360Srdivacky EXTENSION_TABLE(83) \ 97201360Srdivacky EXTENSION_TABLE(8f) \ 98201360Srdivacky EXTENSION_TABLE(c0) \ 99201360Srdivacky EXTENSION_TABLE(c1) \ 100201360Srdivacky EXTENSION_TABLE(c6) \ 101201360Srdivacky EXTENSION_TABLE(c7) \ 102201360Srdivacky EXTENSION_TABLE(d0) \ 103201360Srdivacky EXTENSION_TABLE(d1) \ 104201360Srdivacky EXTENSION_TABLE(d2) \ 105201360Srdivacky EXTENSION_TABLE(d3) \ 106201360Srdivacky EXTENSION_TABLE(f6) \ 107201360Srdivacky EXTENSION_TABLE(f7) \ 108201360Srdivacky EXTENSION_TABLE(fe) \ 109201360Srdivacky EXTENSION_TABLE(ff) 110201360Srdivacky 111201360Srdivacky#define TWO_BYTE_EXTENSION_TABLES \ 112201360Srdivacky EXTENSION_TABLE(00) \ 113201360Srdivacky EXTENSION_TABLE(01) \ 114201360Srdivacky EXTENSION_TABLE(18) \ 115201360Srdivacky EXTENSION_TABLE(71) \ 116201360Srdivacky EXTENSION_TABLE(72) \ 117201360Srdivacky EXTENSION_TABLE(73) \ 118201360Srdivacky EXTENSION_TABLE(ae) \ 119201360Srdivacky EXTENSION_TABLE(ba) \ 120201360Srdivacky EXTENSION_TABLE(c7) 121201360Srdivacky 122201360Srdivackyusing namespace X86Disassembler; 123201360Srdivacky 124201360Srdivacky/// needsModRMForDecode - Indicates whether a particular instruction requires a 125201360Srdivacky/// ModR/M byte for the instruction to be properly decoded. For example, a 126201360Srdivacky/// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to 127201360Srdivacky/// 0b11. 128201360Srdivacky/// 129201360Srdivacky/// @param form - The form of the instruction. 130201360Srdivacky/// @return - true if the form implies that a ModR/M byte is required, false 131201360Srdivacky/// otherwise. 132201360Srdivackystatic bool needsModRMForDecode(uint8_t form) { 133201360Srdivacky if (form == X86Local::MRMDestReg || 134201360Srdivacky form == X86Local::MRMDestMem || 135201360Srdivacky form == X86Local::MRMSrcReg || 136201360Srdivacky form == X86Local::MRMSrcMem || 137201360Srdivacky (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || 138201360Srdivacky (form >= X86Local::MRM0m && form <= X86Local::MRM7m)) 139201360Srdivacky return true; 140201360Srdivacky else 141201360Srdivacky return false; 142201360Srdivacky} 143201360Srdivacky 144201360Srdivacky/// isRegFormat - Indicates whether a particular form requires the Mod field of 145201360Srdivacky/// the ModR/M byte to be 0b11. 146201360Srdivacky/// 147201360Srdivacky/// @param form - The form of the instruction. 148201360Srdivacky/// @return - true if the form implies that Mod must be 0b11, false 149201360Srdivacky/// otherwise. 150201360Srdivackystatic bool isRegFormat(uint8_t form) { 151201360Srdivacky if (form == X86Local::MRMDestReg || 152201360Srdivacky form == X86Local::MRMSrcReg || 153201360Srdivacky (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) 154201360Srdivacky return true; 155201360Srdivacky else 156201360Srdivacky return false; 157201360Srdivacky} 158201360Srdivacky 159201360Srdivacky/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 160201360Srdivacky/// Useful for switch statements and the like. 161201360Srdivacky/// 162201360Srdivacky/// @param init - A reference to the BitsInit to be decoded. 163201360Srdivacky/// @return - The field, with the first bit in the BitsInit as the lowest 164201360Srdivacky/// order bit. 165201360Srdivackystatic uint8_t byteFromBitsInit(BitsInit &init) { 166201360Srdivacky int width = init.getNumBits(); 167201360Srdivacky 168201360Srdivacky assert(width <= 8 && "Field is too large for uint8_t!"); 169201360Srdivacky 170201360Srdivacky int index; 171201360Srdivacky uint8_t mask = 0x01; 172201360Srdivacky 173201360Srdivacky uint8_t ret = 0; 174201360Srdivacky 175201360Srdivacky for (index = 0; index < width; index++) { 176201360Srdivacky if (static_cast<BitInit*>(init.getBit(index))->getValue()) 177201360Srdivacky ret |= mask; 178201360Srdivacky 179201360Srdivacky mask <<= 1; 180201360Srdivacky } 181201360Srdivacky 182201360Srdivacky return ret; 183201360Srdivacky} 184201360Srdivacky 185201360Srdivacky/// byteFromRec - Extract a value at most 8 bits in with from a Record given the 186201360Srdivacky/// name of the field. 187201360Srdivacky/// 188201360Srdivacky/// @param rec - The record from which to extract the value. 189201360Srdivacky/// @param name - The name of the field in the record. 190201360Srdivacky/// @return - The field, as translated by byteFromBitsInit(). 191201360Srdivackystatic uint8_t byteFromRec(const Record* rec, const std::string &name) { 192201360Srdivacky BitsInit* bits = rec->getValueAsBitsInit(name); 193201360Srdivacky return byteFromBitsInit(*bits); 194201360Srdivacky} 195201360Srdivacky 196201360SrdivackyRecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 197201360Srdivacky const CodeGenInstruction &insn, 198201360Srdivacky InstrUID uid) { 199201360Srdivacky UID = uid; 200201360Srdivacky 201201360Srdivacky Rec = insn.TheDef; 202201360Srdivacky Name = Rec->getName(); 203201360Srdivacky Spec = &tables.specForUID(UID); 204201360Srdivacky 205201360Srdivacky if (!Rec->isSubClassOf("X86Inst")) { 206201360Srdivacky ShouldBeEmitted = false; 207201360Srdivacky return; 208201360Srdivacky } 209201360Srdivacky 210201360Srdivacky Prefix = byteFromRec(Rec, "Prefix"); 211201360Srdivacky Opcode = byteFromRec(Rec, "Opcode"); 212201360Srdivacky Form = byteFromRec(Rec, "FormBits"); 213201360Srdivacky SegOvr = byteFromRec(Rec, "SegOvrBits"); 214201360Srdivacky 215201360Srdivacky HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); 216201360Srdivacky HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 217221345Sdim HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix"); 218210299Sed HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); 219221345Sdim HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 220226633Sdim IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 221201360Srdivacky HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); 222201360Srdivacky IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 223201360Srdivacky 224201360Srdivacky Name = Rec->getName(); 225201360Srdivacky AsmString = Rec->getValueAsString("AsmString"); 226201360Srdivacky 227218893Sdim Operands = &insn.Operands.OperandList; 228201360Srdivacky 229226633Sdim IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || 230226633Sdim (Name.find("CRC32") != Name.npos); 231221345Sdim HasFROperands = hasFROperands(); 232221345Sdim HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); 233201360Srdivacky 234224145Sdim // Check for 64-bit inst which does not require REX 235226633Sdim Is32Bit = false; 236224145Sdim Is64Bit = false; 237224145Sdim // FIXME: Is there some better way to check for In64BitMode? 238224145Sdim std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 239224145Sdim for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 240226633Sdim if (Predicates[i]->getName().find("32Bit") != Name.npos) { 241226633Sdim Is32Bit = true; 242226633Sdim break; 243226633Sdim } 244224145Sdim if (Predicates[i]->getName().find("64Bit") != Name.npos) { 245224145Sdim Is64Bit = true; 246224145Sdim break; 247224145Sdim } 248224145Sdim } 249224145Sdim // FIXME: These instructions aren't marked as 64-bit in any way 250224145Sdim Is64Bit |= Rec->getName() == "JMP64pcrel32" || 251224145Sdim Rec->getName() == "MASKMOVDQU64" || 252224145Sdim Rec->getName() == "POPFS64" || 253224145Sdim Rec->getName() == "POPGS64" || 254224145Sdim Rec->getName() == "PUSHFS64" || 255224145Sdim Rec->getName() == "PUSHGS64" || 256224145Sdim Rec->getName() == "REX64_PREFIX" || 257224145Sdim Rec->getName().find("VMREAD64") != Name.npos || 258224145Sdim Rec->getName().find("VMWRITE64") != Name.npos || 259226633Sdim Rec->getName().find("INVEPT64") != Name.npos || 260226633Sdim Rec->getName().find("INVVPID64") != Name.npos || 261224145Sdim Rec->getName().find("MOV64") != Name.npos || 262224145Sdim Rec->getName().find("PUSH64") != Name.npos || 263224145Sdim Rec->getName().find("POP64") != Name.npos; 264224145Sdim 265201360Srdivacky ShouldBeEmitted = true; 266201360Srdivacky} 267201360Srdivacky 268201360Srdivackyvoid RecognizableInstr::processInstr(DisassemblerTables &tables, 269226633Sdim const CodeGenInstruction &insn, 270201360Srdivacky InstrUID uid) 271201360Srdivacky{ 272208599Srdivacky // Ignore "asm parser only" instructions. 273208599Srdivacky if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 274208599Srdivacky return; 275208599Srdivacky 276201360Srdivacky RecognizableInstr recogInstr(tables, insn, uid); 277201360Srdivacky 278201360Srdivacky recogInstr.emitInstructionSpecifier(tables); 279201360Srdivacky 280201360Srdivacky if (recogInstr.shouldBeEmitted()) 281201360Srdivacky recogInstr.emitDecodePath(tables); 282201360Srdivacky} 283201360Srdivacky 284201360SrdivackyInstructionContext RecognizableInstr::insnContext() const { 285201360Srdivacky InstructionContext insnContext; 286201360Srdivacky 287221345Sdim if (HasVEX_4VPrefix || HasVEXPrefix) { 288226633Sdim if (HasVEX_LPrefix && HasVEX_WPrefix) 289226633Sdim llvm_unreachable("Don't support VEX.L and VEX.W together"); 290226633Sdim else if (HasOpSizePrefix && HasVEX_LPrefix) 291221345Sdim insnContext = IC_VEX_L_OPSIZE; 292221345Sdim else if (HasOpSizePrefix && HasVEX_WPrefix) 293221345Sdim insnContext = IC_VEX_W_OPSIZE; 294221345Sdim else if (HasOpSizePrefix) 295221345Sdim insnContext = IC_VEX_OPSIZE; 296221345Sdim else if (HasVEX_LPrefix && Prefix == X86Local::XS) 297221345Sdim insnContext = IC_VEX_L_XS; 298221345Sdim else if (HasVEX_LPrefix && Prefix == X86Local::XD) 299221345Sdim insnContext = IC_VEX_L_XD; 300221345Sdim else if (HasVEX_WPrefix && Prefix == X86Local::XS) 301221345Sdim insnContext = IC_VEX_W_XS; 302221345Sdim else if (HasVEX_WPrefix && Prefix == X86Local::XD) 303221345Sdim insnContext = IC_VEX_W_XD; 304221345Sdim else if (HasVEX_WPrefix) 305221345Sdim insnContext = IC_VEX_W; 306221345Sdim else if (HasVEX_LPrefix) 307221345Sdim insnContext = IC_VEX_L; 308221345Sdim else if (Prefix == X86Local::XD) 309221345Sdim insnContext = IC_VEX_XD; 310221345Sdim else if (Prefix == X86Local::XS) 311221345Sdim insnContext = IC_VEX_XS; 312221345Sdim else 313221345Sdim insnContext = IC_VEX; 314224145Sdim } else if (Is64Bit || HasREX_WPrefix) { 315201360Srdivacky if (HasREX_WPrefix && HasOpSizePrefix) 316201360Srdivacky insnContext = IC_64BIT_REXW_OPSIZE; 317226633Sdim else if (HasOpSizePrefix && 318226633Sdim (Prefix == X86Local::XD || Prefix == X86Local::TF)) 319226633Sdim insnContext = IC_64BIT_XD_OPSIZE; 320226633Sdim else if (HasOpSizePrefix && Prefix == X86Local::XS) 321226633Sdim insnContext = IC_64BIT_XS_OPSIZE; 322201360Srdivacky else if (HasOpSizePrefix) 323201360Srdivacky insnContext = IC_64BIT_OPSIZE; 324201360Srdivacky else if (HasREX_WPrefix && Prefix == X86Local::XS) 325201360Srdivacky insnContext = IC_64BIT_REXW_XS; 326226633Sdim else if (HasREX_WPrefix && 327226633Sdim (Prefix == X86Local::XD || Prefix == X86Local::TF)) 328201360Srdivacky insnContext = IC_64BIT_REXW_XD; 329226633Sdim else if (Prefix == X86Local::XD || Prefix == X86Local::TF) 330201360Srdivacky insnContext = IC_64BIT_XD; 331201360Srdivacky else if (Prefix == X86Local::XS) 332201360Srdivacky insnContext = IC_64BIT_XS; 333201360Srdivacky else if (HasREX_WPrefix) 334201360Srdivacky insnContext = IC_64BIT_REXW; 335201360Srdivacky else 336201360Srdivacky insnContext = IC_64BIT; 337201360Srdivacky } else { 338226633Sdim if (HasOpSizePrefix && 339226633Sdim (Prefix == X86Local::XD || Prefix == X86Local::TF)) 340226633Sdim insnContext = IC_XD_OPSIZE; 341226633Sdim else if (HasOpSizePrefix && Prefix == X86Local::XS) 342226633Sdim insnContext = IC_XS_OPSIZE; 343226633Sdim else if (HasOpSizePrefix) 344201360Srdivacky insnContext = IC_OPSIZE; 345226633Sdim else if (Prefix == X86Local::XD || Prefix == X86Local::TF) 346201360Srdivacky insnContext = IC_XD; 347226633Sdim else if (Prefix == X86Local::XS || Prefix == X86Local::REP) 348201360Srdivacky insnContext = IC_XS; 349201360Srdivacky else 350201360Srdivacky insnContext = IC; 351201360Srdivacky } 352201360Srdivacky 353201360Srdivacky return insnContext; 354201360Srdivacky} 355201360Srdivacky 356201360SrdivackyRecognizableInstr::filter_ret RecognizableInstr::filter() const { 357221345Sdim /////////////////// 358221345Sdim // FILTER_STRONG 359221345Sdim // 360221345Sdim 361201360Srdivacky // Filter out intrinsics 362201360Srdivacky 363201360Srdivacky if (!Rec->isSubClassOf("X86Inst")) 364201360Srdivacky return FILTER_STRONG; 365201360Srdivacky 366201360Srdivacky if (Form == X86Local::Pseudo || 367226633Sdim (IsCodeGenOnly && Name.find("_REV") == Name.npos)) 368201360Srdivacky return FILTER_STRONG; 369201360Srdivacky 370204642Srdivacky if (Form == X86Local::MRMInitReg) 371204642Srdivacky return FILTER_STRONG; 372221345Sdim 373221345Sdim 374221345Sdim // Filter out artificial instructions 375221345Sdim 376221345Sdim if (Name.find("TAILJMP") != Name.npos || 377221345Sdim Name.find("_Int") != Name.npos || 378221345Sdim Name.find("_int") != Name.npos || 379221345Sdim Name.find("Int_") != Name.npos || 380221345Sdim Name.find("_NOREX") != Name.npos || 381221345Sdim Name.find("_TC") != Name.npos || 382221345Sdim Name.find("EH_RETURN") != Name.npos || 383221345Sdim Name.find("V_SET") != Name.npos || 384221345Sdim Name.find("LOCK_") != Name.npos || 385221345Sdim Name.find("WIN") != Name.npos || 386221345Sdim Name.find("_AVX") != Name.npos || 387221345Sdim Name.find("2SDL") != Name.npos) 388221345Sdim return FILTER_STRONG; 389221345Sdim 390221345Sdim // Filter out instructions with segment override prefixes. 391221345Sdim // They're too messy to handle now and we'll special case them if needed. 392221345Sdim 393221345Sdim if (SegOvr) 394221345Sdim return FILTER_STRONG; 395221345Sdim 396221345Sdim // Filter out instructions that can't be printed. 397221345Sdim 398221345Sdim if (AsmString.size() == 0) 399221345Sdim return FILTER_STRONG; 400221345Sdim 401221345Sdim // Filter out instructions with subreg operands. 402221345Sdim 403221345Sdim if (AsmString.find("subreg") != AsmString.npos) 404221345Sdim return FILTER_STRONG; 405221345Sdim 406221345Sdim ///////////////// 407221345Sdim // FILTER_WEAK 408221345Sdim // 409221345Sdim 410221345Sdim 411201360Srdivacky // Filter out instructions with a LOCK prefix; 412201360Srdivacky // prefer forms that do not have the prefix 413201360Srdivacky if (HasLockPrefix) 414201360Srdivacky return FILTER_WEAK; 415201360Srdivacky 416221345Sdim // Filter out alternate forms of AVX instructions 417221345Sdim if (Name.find("_alt") != Name.npos || 418221345Sdim Name.find("XrYr") != Name.npos || 419226633Sdim (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || 420221345Sdim Name.find("_64mr") != Name.npos || 421221345Sdim Name.find("Xrr") != Name.npos || 422221345Sdim Name.find("rr64") != Name.npos) 423221345Sdim return FILTER_WEAK; 424221345Sdim 425221345Sdim if (Name == "VMASKMOVDQU64" || 426221345Sdim Name == "VEXTRACTPSrr64" || 427221345Sdim Name == "VMOVQd64rr" || 428221345Sdim Name == "VMOVQs64rr") 429221345Sdim return FILTER_WEAK; 430201360Srdivacky 431201360Srdivacky // Special cases. 432218893Sdim 433201360Srdivacky if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") 434201360Srdivacky return FILTER_WEAK; 435201360Srdivacky if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") 436201360Srdivacky return FILTER_WEAK; 437201360Srdivacky 438201360Srdivacky if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) 439201360Srdivacky return FILTER_WEAK; 440201360Srdivacky if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos) 441201360Srdivacky return FILTER_WEAK; 442201360Srdivacky if (Name.find("Fs") != Name.npos) 443201360Srdivacky return FILTER_WEAK; 444201360Srdivacky if (Name == "MOVLPDrr" || 445201360Srdivacky Name == "MOVLPSrr" || 446201360Srdivacky Name == "PUSHFQ" || 447201360Srdivacky Name == "BSF16rr" || 448201360Srdivacky Name == "BSF16rm" || 449201360Srdivacky Name == "BSR16rr" || 450201360Srdivacky Name == "BSR16rm" || 451201360Srdivacky Name == "MOVSX16rm8" || 452201360Srdivacky Name == "MOVSX16rr8" || 453201360Srdivacky Name == "MOVZX16rm8" || 454201360Srdivacky Name == "MOVZX16rr8" || 455201360Srdivacky Name == "PUSH32i16" || 456201360Srdivacky Name == "PUSH64i16" || 457201360Srdivacky Name == "MOVPQI2QImr" || 458221345Sdim Name == "VMOVPQI2QImr" || 459201360Srdivacky Name == "MOVSDmr" || 460201360Srdivacky Name == "MOVSDrm" || 461201360Srdivacky Name == "MOVSSmr" || 462201360Srdivacky Name == "MOVSSrm" || 463201360Srdivacky Name == "MMX_MOVD64rrv164" || 464201360Srdivacky Name == "CRC32m16" || 465201360Srdivacky Name == "MOV64ri64i32" || 466201360Srdivacky Name == "CRC32r16") 467201360Srdivacky return FILTER_WEAK; 468201360Srdivacky 469201360Srdivacky if (HasFROperands && Name.find("MOV") != Name.npos && 470201360Srdivacky ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 471201360Srdivacky (Name.find("to") != Name.npos))) 472201360Srdivacky return FILTER_WEAK; 473201360Srdivacky 474201360Srdivacky return FILTER_NORMAL; 475201360Srdivacky} 476221345Sdim 477221345Sdimbool RecognizableInstr::hasFROperands() const { 478221345Sdim const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 479221345Sdim unsigned numOperands = OperandList.size(); 480221345Sdim 481221345Sdim for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 482221345Sdim const std::string &recName = OperandList[operandIndex].Rec->getName(); 483221345Sdim 484221345Sdim if (recName.find("FR") != recName.npos) 485221345Sdim return true; 486221345Sdim } 487221345Sdim return false; 488221345Sdim} 489221345Sdim 490221345Sdimbool RecognizableInstr::has256BitOperands() const { 491221345Sdim const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 492221345Sdim unsigned numOperands = OperandList.size(); 493221345Sdim 494221345Sdim for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 495221345Sdim const std::string &recName = OperandList[operandIndex].Rec->getName(); 496221345Sdim 497221345Sdim if (!recName.compare("VR256") || !recName.compare("f256mem")) { 498221345Sdim return true; 499221345Sdim } 500221345Sdim } 501221345Sdim return false; 502221345Sdim} 503201360Srdivacky 504201360Srdivackyvoid RecognizableInstr::handleOperand( 505201360Srdivacky bool optional, 506201360Srdivacky unsigned &operandIndex, 507201360Srdivacky unsigned &physicalOperandIndex, 508201360Srdivacky unsigned &numPhysicalOperands, 509201360Srdivacky unsigned *operandMapping, 510201360Srdivacky OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) { 511201360Srdivacky if (optional) { 512201360Srdivacky if (physicalOperandIndex >= numPhysicalOperands) 513201360Srdivacky return; 514201360Srdivacky } else { 515201360Srdivacky assert(physicalOperandIndex < numPhysicalOperands); 516201360Srdivacky } 517201360Srdivacky 518201360Srdivacky while (operandMapping[operandIndex] != operandIndex) { 519201360Srdivacky Spec->operands[operandIndex].encoding = ENCODING_DUP; 520201360Srdivacky Spec->operands[operandIndex].type = 521201360Srdivacky (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 522201360Srdivacky ++operandIndex; 523201360Srdivacky } 524201360Srdivacky 525201360Srdivacky const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 526221345Sdim 527201360Srdivacky Spec->operands[operandIndex].encoding = encodingFromString(typeName, 528201360Srdivacky HasOpSizePrefix); 529201360Srdivacky Spec->operands[operandIndex].type = typeFromString(typeName, 530221345Sdim IsSSE, 531221345Sdim HasREX_WPrefix, 532221345Sdim HasOpSizePrefix); 533201360Srdivacky 534201360Srdivacky ++operandIndex; 535201360Srdivacky ++physicalOperandIndex; 536201360Srdivacky} 537201360Srdivacky 538201360Srdivackyvoid RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { 539201360Srdivacky Spec->name = Name; 540201360Srdivacky 541201360Srdivacky if (!Rec->isSubClassOf("X86Inst")) 542201360Srdivacky return; 543201360Srdivacky 544201360Srdivacky switch (filter()) { 545201360Srdivacky case FILTER_WEAK: 546201360Srdivacky Spec->filtered = true; 547201360Srdivacky break; 548201360Srdivacky case FILTER_STRONG: 549201360Srdivacky ShouldBeEmitted = false; 550201360Srdivacky return; 551201360Srdivacky case FILTER_NORMAL: 552201360Srdivacky break; 553201360Srdivacky } 554201360Srdivacky 555201360Srdivacky Spec->insnContext = insnContext(); 556201360Srdivacky 557218893Sdim const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 558201360Srdivacky 559201360Srdivacky unsigned operandIndex; 560201360Srdivacky unsigned numOperands = OperandList.size(); 561201360Srdivacky unsigned numPhysicalOperands = 0; 562201360Srdivacky 563201360Srdivacky // operandMapping maps from operands in OperandList to their originals. 564201360Srdivacky // If operandMapping[i] != i, then the entry is a duplicate. 565201360Srdivacky unsigned operandMapping[X86_MAX_OPERANDS]; 566201360Srdivacky 567201360Srdivacky bool hasFROperands = false; 568201360Srdivacky 569201360Srdivacky assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 570201360Srdivacky 571201360Srdivacky for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 572201360Srdivacky if (OperandList[operandIndex].Constraints.size()) { 573218893Sdim const CGIOperandList::ConstraintInfo &Constraint = 574203954Srdivacky OperandList[operandIndex].Constraints[0]; 575203954Srdivacky if (Constraint.isTied()) { 576203954Srdivacky operandMapping[operandIndex] = Constraint.getTiedOperand(); 577201360Srdivacky } else { 578201360Srdivacky ++numPhysicalOperands; 579201360Srdivacky operandMapping[operandIndex] = operandIndex; 580201360Srdivacky } 581201360Srdivacky } else { 582201360Srdivacky ++numPhysicalOperands; 583201360Srdivacky operandMapping[operandIndex] = operandIndex; 584201360Srdivacky } 585201360Srdivacky 586201360Srdivacky const std::string &recName = OperandList[operandIndex].Rec->getName(); 587201360Srdivacky 588201360Srdivacky if (recName.find("FR") != recName.npos) 589201360Srdivacky hasFROperands = true; 590201360Srdivacky } 591201360Srdivacky 592201360Srdivacky if (hasFROperands && Name.find("MOV") != Name.npos && 593201360Srdivacky ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 594201360Srdivacky (Name.find("to") != Name.npos))) 595201360Srdivacky ShouldBeEmitted = false; 596201360Srdivacky 597201360Srdivacky if (!ShouldBeEmitted) 598201360Srdivacky return; 599201360Srdivacky 600201360Srdivacky#define HANDLE_OPERAND(class) \ 601201360Srdivacky handleOperand(false, \ 602201360Srdivacky operandIndex, \ 603201360Srdivacky physicalOperandIndex, \ 604201360Srdivacky numPhysicalOperands, \ 605201360Srdivacky operandMapping, \ 606201360Srdivacky class##EncodingFromString); 607201360Srdivacky 608201360Srdivacky#define HANDLE_OPTIONAL(class) \ 609201360Srdivacky handleOperand(true, \ 610201360Srdivacky operandIndex, \ 611201360Srdivacky physicalOperandIndex, \ 612201360Srdivacky numPhysicalOperands, \ 613201360Srdivacky operandMapping, \ 614201360Srdivacky class##EncodingFromString); 615201360Srdivacky 616201360Srdivacky // operandIndex should always be < numOperands 617201360Srdivacky operandIndex = 0; 618201360Srdivacky // physicalOperandIndex should always be < numPhysicalOperands 619201360Srdivacky unsigned physicalOperandIndex = 0; 620201360Srdivacky 621201360Srdivacky switch (Form) { 622201360Srdivacky case X86Local::RawFrm: 623201360Srdivacky // Operand 1 (optional) is an address or immediate. 624201360Srdivacky // Operand 2 (optional) is an immediate. 625201360Srdivacky assert(numPhysicalOperands <= 2 && 626201360Srdivacky "Unexpected number of operands for RawFrm"); 627201360Srdivacky HANDLE_OPTIONAL(relocation) 628201360Srdivacky HANDLE_OPTIONAL(immediate) 629201360Srdivacky break; 630201360Srdivacky case X86Local::AddRegFrm: 631201360Srdivacky // Operand 1 is added to the opcode. 632201360Srdivacky // Operand 2 (optional) is an address. 633201360Srdivacky assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 634201360Srdivacky "Unexpected number of operands for AddRegFrm"); 635201360Srdivacky HANDLE_OPERAND(opcodeModifier) 636201360Srdivacky HANDLE_OPTIONAL(relocation) 637201360Srdivacky break; 638201360Srdivacky case X86Local::MRMDestReg: 639201360Srdivacky // Operand 1 is a register operand in the R/M field. 640201360Srdivacky // Operand 2 is a register operand in the Reg/Opcode field. 641226633Sdim // - In AVX, there is a register operand in the VEX.vvvv field here - 642201360Srdivacky // Operand 3 (optional) is an immediate. 643226633Sdim if (HasVEX_4VPrefix) 644226633Sdim assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 645226633Sdim "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 646226633Sdim else 647226633Sdim assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 648226633Sdim "Unexpected number of operands for MRMDestRegFrm"); 649226633Sdim 650201360Srdivacky HANDLE_OPERAND(rmRegister) 651226633Sdim 652226633Sdim if (HasVEX_4VPrefix) 653226633Sdim // FIXME: In AVX, the register below becomes the one encoded 654226633Sdim // in ModRMVEX and the one above the one in the VEX.VVVV field 655226633Sdim HANDLE_OPERAND(vvvvRegister) 656226633Sdim 657201360Srdivacky HANDLE_OPERAND(roRegister) 658201360Srdivacky HANDLE_OPTIONAL(immediate) 659201360Srdivacky break; 660201360Srdivacky case X86Local::MRMDestMem: 661201360Srdivacky // Operand 1 is a memory operand (possibly SIB-extended) 662201360Srdivacky // Operand 2 is a register operand in the Reg/Opcode field. 663226633Sdim // - In AVX, there is a register operand in the VEX.vvvv field here - 664201360Srdivacky // Operand 3 (optional) is an immediate. 665226633Sdim if (HasVEX_4VPrefix) 666226633Sdim assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 667226633Sdim "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 668226633Sdim else 669226633Sdim assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 670226633Sdim "Unexpected number of operands for MRMDestMemFrm"); 671201360Srdivacky HANDLE_OPERAND(memory) 672226633Sdim 673226633Sdim if (HasVEX_4VPrefix) 674226633Sdim // FIXME: In AVX, the register below becomes the one encoded 675226633Sdim // in ModRMVEX and the one above the one in the VEX.VVVV field 676226633Sdim HANDLE_OPERAND(vvvvRegister) 677226633Sdim 678201360Srdivacky HANDLE_OPERAND(roRegister) 679201360Srdivacky HANDLE_OPTIONAL(immediate) 680201360Srdivacky break; 681201360Srdivacky case X86Local::MRMSrcReg: 682201360Srdivacky // Operand 1 is a register operand in the Reg/Opcode field. 683201360Srdivacky // Operand 2 is a register operand in the R/M field. 684221345Sdim // - In AVX, there is a register operand in the VEX.vvvv field here - 685201360Srdivacky // Operand 3 (optional) is an immediate. 686210299Sed 687210299Sed if (HasVEX_4VPrefix) 688221345Sdim assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 689221345Sdim "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 690221345Sdim else 691221345Sdim assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 692221345Sdim "Unexpected number of operands for MRMSrcRegFrm"); 693221345Sdim 694221345Sdim HANDLE_OPERAND(roRegister) 695221345Sdim 696221345Sdim if (HasVEX_4VPrefix) 697210299Sed // FIXME: In AVX, the register below becomes the one encoded 698210299Sed // in ModRMVEX and the one above the one in the VEX.VVVV field 699221345Sdim HANDLE_OPERAND(vvvvRegister) 700221345Sdim 701221345Sdim HANDLE_OPERAND(rmRegister) 702221345Sdim HANDLE_OPTIONAL(immediate) 703201360Srdivacky break; 704201360Srdivacky case X86Local::MRMSrcMem: 705201360Srdivacky // Operand 1 is a register operand in the Reg/Opcode field. 706201360Srdivacky // Operand 2 is a memory operand (possibly SIB-extended) 707221345Sdim // - In AVX, there is a register operand in the VEX.vvvv field here - 708201360Srdivacky // Operand 3 (optional) is an immediate. 709221345Sdim 710221345Sdim if (HasVEX_4VPrefix) 711221345Sdim assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 712221345Sdim "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 713221345Sdim else 714221345Sdim assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 715221345Sdim "Unexpected number of operands for MRMSrcMemFrm"); 716221345Sdim 717201360Srdivacky HANDLE_OPERAND(roRegister) 718210299Sed 719210299Sed if (HasVEX_4VPrefix) 720210299Sed // FIXME: In AVX, the register below becomes the one encoded 721210299Sed // in ModRMVEX and the one above the one in the VEX.VVVV field 722221345Sdim HANDLE_OPERAND(vvvvRegister) 723210299Sed 724201360Srdivacky HANDLE_OPERAND(memory) 725201360Srdivacky HANDLE_OPTIONAL(immediate) 726201360Srdivacky break; 727201360Srdivacky case X86Local::MRM0r: 728201360Srdivacky case X86Local::MRM1r: 729201360Srdivacky case X86Local::MRM2r: 730201360Srdivacky case X86Local::MRM3r: 731201360Srdivacky case X86Local::MRM4r: 732201360Srdivacky case X86Local::MRM5r: 733201360Srdivacky case X86Local::MRM6r: 734201360Srdivacky case X86Local::MRM7r: 735201360Srdivacky // Operand 1 is a register operand in the R/M field. 736201360Srdivacky // Operand 2 (optional) is an immediate or relocation. 737221345Sdim if (HasVEX_4VPrefix) 738221345Sdim assert(numPhysicalOperands <= 3 && 739221345Sdim "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 740221345Sdim else 741221345Sdim assert(numPhysicalOperands <= 2 && 742221345Sdim "Unexpected number of operands for MRMnRFrm"); 743221345Sdim if (HasVEX_4VPrefix) 744221345Sdim HANDLE_OPERAND(vvvvRegister); 745201360Srdivacky HANDLE_OPTIONAL(rmRegister) 746201360Srdivacky HANDLE_OPTIONAL(relocation) 747201360Srdivacky break; 748201360Srdivacky case X86Local::MRM0m: 749201360Srdivacky case X86Local::MRM1m: 750201360Srdivacky case X86Local::MRM2m: 751201360Srdivacky case X86Local::MRM3m: 752201360Srdivacky case X86Local::MRM4m: 753201360Srdivacky case X86Local::MRM5m: 754201360Srdivacky case X86Local::MRM6m: 755201360Srdivacky case X86Local::MRM7m: 756201360Srdivacky // Operand 1 is a memory operand (possibly SIB-extended) 757201360Srdivacky // Operand 2 (optional) is an immediate or relocation. 758201360Srdivacky assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 759201360Srdivacky "Unexpected number of operands for MRMnMFrm"); 760201360Srdivacky HANDLE_OPERAND(memory) 761201360Srdivacky HANDLE_OPTIONAL(relocation) 762201360Srdivacky break; 763218893Sdim case X86Local::RawFrmImm8: 764218893Sdim // operand 1 is a 16-bit immediate 765218893Sdim // operand 2 is an 8-bit immediate 766218893Sdim assert(numPhysicalOperands == 2 && 767218893Sdim "Unexpected number of operands for X86Local::RawFrmImm8"); 768218893Sdim HANDLE_OPERAND(immediate) 769218893Sdim HANDLE_OPERAND(immediate) 770218893Sdim break; 771218893Sdim case X86Local::RawFrmImm16: 772218893Sdim // operand 1 is a 16-bit immediate 773218893Sdim // operand 2 is a 16-bit immediate 774218893Sdim HANDLE_OPERAND(immediate) 775218893Sdim HANDLE_OPERAND(immediate) 776218893Sdim break; 777201360Srdivacky case X86Local::MRMInitReg: 778201360Srdivacky // Ignored. 779201360Srdivacky break; 780201360Srdivacky } 781201360Srdivacky 782201360Srdivacky #undef HANDLE_OPERAND 783201360Srdivacky #undef HANDLE_OPTIONAL 784201360Srdivacky} 785201360Srdivacky 786201360Srdivackyvoid RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 787201360Srdivacky // Special cases where the LLVM tables are not complete 788201360Srdivacky 789203954Srdivacky#define MAP(from, to) \ 790203954Srdivacky case X86Local::MRM_##from: \ 791203954Srdivacky filter = new ExactFilter(0x##from); \ 792203954Srdivacky break; 793201360Srdivacky 794201360Srdivacky OpcodeType opcodeType = (OpcodeType)-1; 795201360Srdivacky 796201360Srdivacky ModRMFilter* filter = NULL; 797201360Srdivacky uint8_t opcodeToSet = 0; 798201360Srdivacky 799201360Srdivacky switch (Prefix) { 800201360Srdivacky // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f 801201360Srdivacky case X86Local::XD: 802201360Srdivacky case X86Local::XS: 803201360Srdivacky case X86Local::TB: 804201360Srdivacky opcodeType = TWOBYTE; 805201360Srdivacky 806201360Srdivacky switch (Opcode) { 807203954Srdivacky default: 808203954Srdivacky if (needsModRMForDecode(Form)) 809203954Srdivacky filter = new ModFilter(isRegFormat(Form)); 810203954Srdivacky else 811203954Srdivacky filter = new DumbFilter(); 812203954Srdivacky break; 813201360Srdivacky#define EXTENSION_TABLE(n) case 0x##n: 814201360Srdivacky TWO_BYTE_EXTENSION_TABLES 815201360Srdivacky#undef EXTENSION_TABLE 816201360Srdivacky switch (Form) { 817201360Srdivacky default: 818201360Srdivacky llvm_unreachable("Unhandled two-byte extended opcode"); 819201360Srdivacky case X86Local::MRM0r: 820201360Srdivacky case X86Local::MRM1r: 821201360Srdivacky case X86Local::MRM2r: 822201360Srdivacky case X86Local::MRM3r: 823201360Srdivacky case X86Local::MRM4r: 824201360Srdivacky case X86Local::MRM5r: 825201360Srdivacky case X86Local::MRM6r: 826201360Srdivacky case X86Local::MRM7r: 827201360Srdivacky filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 828201360Srdivacky break; 829201360Srdivacky case X86Local::MRM0m: 830201360Srdivacky case X86Local::MRM1m: 831201360Srdivacky case X86Local::MRM2m: 832201360Srdivacky case X86Local::MRM3m: 833201360Srdivacky case X86Local::MRM4m: 834201360Srdivacky case X86Local::MRM5m: 835201360Srdivacky case X86Local::MRM6m: 836201360Srdivacky case X86Local::MRM7m: 837201360Srdivacky filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 838201360Srdivacky break; 839203954Srdivacky MRM_MAPPING 840201360Srdivacky } // switch (Form) 841201360Srdivacky break; 842203954Srdivacky } // switch (Opcode) 843201360Srdivacky opcodeToSet = Opcode; 844201360Srdivacky break; 845201360Srdivacky case X86Local::T8: 846226633Sdim case X86Local::TF: 847201360Srdivacky opcodeType = THREEBYTE_38; 848201360Srdivacky if (needsModRMForDecode(Form)) 849201360Srdivacky filter = new ModFilter(isRegFormat(Form)); 850201360Srdivacky else 851201360Srdivacky filter = new DumbFilter(); 852201360Srdivacky opcodeToSet = Opcode; 853201360Srdivacky break; 854203954Srdivacky case X86Local::P_TA: 855201360Srdivacky opcodeType = THREEBYTE_3A; 856201360Srdivacky if (needsModRMForDecode(Form)) 857201360Srdivacky filter = new ModFilter(isRegFormat(Form)); 858201360Srdivacky else 859201360Srdivacky filter = new DumbFilter(); 860201360Srdivacky opcodeToSet = Opcode; 861201360Srdivacky break; 862221345Sdim case X86Local::A6: 863221345Sdim opcodeType = THREEBYTE_A6; 864221345Sdim if (needsModRMForDecode(Form)) 865221345Sdim filter = new ModFilter(isRegFormat(Form)); 866221345Sdim else 867221345Sdim filter = new DumbFilter(); 868221345Sdim opcodeToSet = Opcode; 869221345Sdim break; 870221345Sdim case X86Local::A7: 871221345Sdim opcodeType = THREEBYTE_A7; 872221345Sdim if (needsModRMForDecode(Form)) 873221345Sdim filter = new ModFilter(isRegFormat(Form)); 874221345Sdim else 875221345Sdim filter = new DumbFilter(); 876221345Sdim opcodeToSet = Opcode; 877221345Sdim break; 878201360Srdivacky case X86Local::D8: 879201360Srdivacky case X86Local::D9: 880201360Srdivacky case X86Local::DA: 881201360Srdivacky case X86Local::DB: 882201360Srdivacky case X86Local::DC: 883201360Srdivacky case X86Local::DD: 884201360Srdivacky case X86Local::DE: 885201360Srdivacky case X86Local::DF: 886201360Srdivacky assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); 887201360Srdivacky opcodeType = ONEBYTE; 888201360Srdivacky if (Form == X86Local::AddRegFrm) { 889201360Srdivacky Spec->modifierType = MODIFIER_MODRM; 890201360Srdivacky Spec->modifierBase = Opcode; 891201360Srdivacky filter = new AddRegEscapeFilter(Opcode); 892201360Srdivacky } else { 893201360Srdivacky filter = new EscapeFilter(true, Opcode); 894201360Srdivacky } 895201360Srdivacky opcodeToSet = 0xd8 + (Prefix - X86Local::D8); 896201360Srdivacky break; 897226633Sdim case X86Local::REP: 898201360Srdivacky default: 899201360Srdivacky opcodeType = ONEBYTE; 900201360Srdivacky switch (Opcode) { 901201360Srdivacky#define EXTENSION_TABLE(n) case 0x##n: 902201360Srdivacky ONE_BYTE_EXTENSION_TABLES 903201360Srdivacky#undef EXTENSION_TABLE 904201360Srdivacky switch (Form) { 905201360Srdivacky default: 906201360Srdivacky llvm_unreachable("Fell through the cracks of a single-byte " 907201360Srdivacky "extended opcode"); 908201360Srdivacky case X86Local::MRM0r: 909201360Srdivacky case X86Local::MRM1r: 910201360Srdivacky case X86Local::MRM2r: 911201360Srdivacky case X86Local::MRM3r: 912201360Srdivacky case X86Local::MRM4r: 913201360Srdivacky case X86Local::MRM5r: 914201360Srdivacky case X86Local::MRM6r: 915201360Srdivacky case X86Local::MRM7r: 916201360Srdivacky filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 917201360Srdivacky break; 918201360Srdivacky case X86Local::MRM0m: 919201360Srdivacky case X86Local::MRM1m: 920201360Srdivacky case X86Local::MRM2m: 921201360Srdivacky case X86Local::MRM3m: 922201360Srdivacky case X86Local::MRM4m: 923201360Srdivacky case X86Local::MRM5m: 924201360Srdivacky case X86Local::MRM6m: 925201360Srdivacky case X86Local::MRM7m: 926201360Srdivacky filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 927201360Srdivacky break; 928203954Srdivacky MRM_MAPPING 929201360Srdivacky } // switch (Form) 930201360Srdivacky break; 931201360Srdivacky case 0xd8: 932201360Srdivacky case 0xd9: 933201360Srdivacky case 0xda: 934201360Srdivacky case 0xdb: 935201360Srdivacky case 0xdc: 936201360Srdivacky case 0xdd: 937201360Srdivacky case 0xde: 938201360Srdivacky case 0xdf: 939201360Srdivacky filter = new EscapeFilter(false, Form - X86Local::MRM0m); 940201360Srdivacky break; 941201360Srdivacky default: 942201360Srdivacky if (needsModRMForDecode(Form)) 943201360Srdivacky filter = new ModFilter(isRegFormat(Form)); 944201360Srdivacky else 945201360Srdivacky filter = new DumbFilter(); 946201360Srdivacky break; 947201360Srdivacky } // switch (Opcode) 948201360Srdivacky opcodeToSet = Opcode; 949201360Srdivacky } // switch (Prefix) 950201360Srdivacky 951201360Srdivacky assert(opcodeType != (OpcodeType)-1 && 952201360Srdivacky "Opcode type not set"); 953201360Srdivacky assert(filter && "Filter not set"); 954201360Srdivacky 955201360Srdivacky if (Form == X86Local::AddRegFrm) { 956201360Srdivacky if(Spec->modifierType != MODIFIER_MODRM) { 957201360Srdivacky assert(opcodeToSet < 0xf9 && 958201360Srdivacky "Not enough room for all ADDREG_FRM operands"); 959201360Srdivacky 960201360Srdivacky uint8_t currentOpcode; 961201360Srdivacky 962201360Srdivacky for (currentOpcode = opcodeToSet; 963201360Srdivacky currentOpcode < opcodeToSet + 8; 964201360Srdivacky ++currentOpcode) 965201360Srdivacky tables.setTableFields(opcodeType, 966201360Srdivacky insnContext(), 967201360Srdivacky currentOpcode, 968201360Srdivacky *filter, 969226633Sdim UID, Is32Bit, IgnoresVEX_L); 970201360Srdivacky 971201360Srdivacky Spec->modifierType = MODIFIER_OPCODE; 972201360Srdivacky Spec->modifierBase = opcodeToSet; 973201360Srdivacky } else { 974201360Srdivacky // modifierBase was set where MODIFIER_MODRM was set 975201360Srdivacky tables.setTableFields(opcodeType, 976201360Srdivacky insnContext(), 977201360Srdivacky opcodeToSet, 978201360Srdivacky *filter, 979226633Sdim UID, Is32Bit, IgnoresVEX_L); 980201360Srdivacky } 981201360Srdivacky } else { 982201360Srdivacky tables.setTableFields(opcodeType, 983201360Srdivacky insnContext(), 984201360Srdivacky opcodeToSet, 985201360Srdivacky *filter, 986226633Sdim UID, Is32Bit, IgnoresVEX_L); 987201360Srdivacky 988201360Srdivacky Spec->modifierType = MODIFIER_NONE; 989201360Srdivacky Spec->modifierBase = opcodeToSet; 990201360Srdivacky } 991201360Srdivacky 992201360Srdivacky delete filter; 993203954Srdivacky 994203954Srdivacky#undef MAP 995201360Srdivacky} 996201360Srdivacky 997201360Srdivacky#define TYPE(str, type) if (s == str) return type; 998201360SrdivackyOperandType RecognizableInstr::typeFromString(const std::string &s, 999201360Srdivacky bool isSSE, 1000201360Srdivacky bool hasREX_WPrefix, 1001201360Srdivacky bool hasOpSizePrefix) { 1002201360Srdivacky if (isSSE) { 1003201360Srdivacky // For SSE instructions, we ignore the OpSize prefix and force operand 1004201360Srdivacky // sizes. 1005201360Srdivacky TYPE("GR16", TYPE_R16) 1006201360Srdivacky TYPE("GR32", TYPE_R32) 1007201360Srdivacky TYPE("GR64", TYPE_R64) 1008201360Srdivacky } 1009201360Srdivacky if(hasREX_WPrefix) { 1010201360Srdivacky // For instructions with a REX_W prefix, a declared 32-bit register encoding 1011201360Srdivacky // is special. 1012201360Srdivacky TYPE("GR32", TYPE_R32) 1013201360Srdivacky } 1014201360Srdivacky if(!hasOpSizePrefix) { 1015201360Srdivacky // For instructions without an OpSize prefix, a declared 16-bit register or 1016201360Srdivacky // immediate encoding is special. 1017201360Srdivacky TYPE("GR16", TYPE_R16) 1018201360Srdivacky TYPE("i16imm", TYPE_IMM16) 1019201360Srdivacky } 1020201360Srdivacky TYPE("i16mem", TYPE_Mv) 1021201360Srdivacky TYPE("i16imm", TYPE_IMMv) 1022201360Srdivacky TYPE("i16i8imm", TYPE_IMMv) 1023201360Srdivacky TYPE("GR16", TYPE_Rv) 1024201360Srdivacky TYPE("i32mem", TYPE_Mv) 1025201360Srdivacky TYPE("i32imm", TYPE_IMMv) 1026201360Srdivacky TYPE("i32i8imm", TYPE_IMM32) 1027226633Sdim TYPE("u32u8imm", TYPE_IMM32) 1028201360Srdivacky TYPE("GR32", TYPE_Rv) 1029201360Srdivacky TYPE("i64mem", TYPE_Mv) 1030201360Srdivacky TYPE("i64i32imm", TYPE_IMM64) 1031201360Srdivacky TYPE("i64i8imm", TYPE_IMM64) 1032201360Srdivacky TYPE("GR64", TYPE_R64) 1033201360Srdivacky TYPE("i8mem", TYPE_M8) 1034201360Srdivacky TYPE("i8imm", TYPE_IMM8) 1035201360Srdivacky TYPE("GR8", TYPE_R8) 1036201360Srdivacky TYPE("VR128", TYPE_XMM128) 1037201360Srdivacky TYPE("f128mem", TYPE_M128) 1038218893Sdim TYPE("f256mem", TYPE_M256) 1039201360Srdivacky TYPE("FR64", TYPE_XMM64) 1040201360Srdivacky TYPE("f64mem", TYPE_M64FP) 1041218893Sdim TYPE("sdmem", TYPE_M64FP) 1042201360Srdivacky TYPE("FR32", TYPE_XMM32) 1043201360Srdivacky TYPE("f32mem", TYPE_M32FP) 1044218893Sdim TYPE("ssmem", TYPE_M32FP) 1045201360Srdivacky TYPE("RST", TYPE_ST) 1046201360Srdivacky TYPE("i128mem", TYPE_M128) 1047221345Sdim TYPE("i256mem", TYPE_M256) 1048201360Srdivacky TYPE("i64i32imm_pcrel", TYPE_REL64) 1049210299Sed TYPE("i16imm_pcrel", TYPE_REL16) 1050201360Srdivacky TYPE("i32imm_pcrel", TYPE_REL32) 1051207618Srdivacky TYPE("SSECC", TYPE_IMM3) 1052201360Srdivacky TYPE("brtarget", TYPE_RELv) 1053218893Sdim TYPE("uncondbrtarget", TYPE_RELv) 1054201360Srdivacky TYPE("brtarget8", TYPE_REL8) 1055201360Srdivacky TYPE("f80mem", TYPE_M80FP) 1056201360Srdivacky TYPE("lea32mem", TYPE_LEA) 1057201360Srdivacky TYPE("lea64_32mem", TYPE_LEA) 1058201360Srdivacky TYPE("lea64mem", TYPE_LEA) 1059201360Srdivacky TYPE("VR64", TYPE_MM64) 1060201360Srdivacky TYPE("i64imm", TYPE_IMMv) 1061201360Srdivacky TYPE("opaque32mem", TYPE_M1616) 1062201360Srdivacky TYPE("opaque48mem", TYPE_M1632) 1063201360Srdivacky TYPE("opaque80mem", TYPE_M1664) 1064201360Srdivacky TYPE("opaque512mem", TYPE_M512) 1065201360Srdivacky TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1066201360Srdivacky TYPE("DEBUG_REG", TYPE_DEBUGREG) 1067208599Srdivacky TYPE("CONTROL_REG", TYPE_CONTROLREG) 1068201360Srdivacky TYPE("offset8", TYPE_MOFFS8) 1069201360Srdivacky TYPE("offset16", TYPE_MOFFS16) 1070201360Srdivacky TYPE("offset32", TYPE_MOFFS32) 1071201360Srdivacky TYPE("offset64", TYPE_MOFFS64) 1072221345Sdim TYPE("VR256", TYPE_XMM256) 1073226633Sdim TYPE("GR16_NOAX", TYPE_Rv) 1074226633Sdim TYPE("GR32_NOAX", TYPE_Rv) 1075226633Sdim TYPE("GR64_NOAX", TYPE_R64) 1076201360Srdivacky errs() << "Unhandled type string " << s << "\n"; 1077201360Srdivacky llvm_unreachable("Unhandled type string"); 1078201360Srdivacky} 1079201360Srdivacky#undef TYPE 1080201360Srdivacky 1081201360Srdivacky#define ENCODING(str, encoding) if (s == str) return encoding; 1082201360SrdivackyOperandEncoding RecognizableInstr::immediateEncodingFromString 1083201360Srdivacky (const std::string &s, 1084201360Srdivacky bool hasOpSizePrefix) { 1085201360Srdivacky if(!hasOpSizePrefix) { 1086201360Srdivacky // For instructions without an OpSize prefix, a declared 16-bit register or 1087201360Srdivacky // immediate encoding is special. 1088201360Srdivacky ENCODING("i16imm", ENCODING_IW) 1089201360Srdivacky } 1090201360Srdivacky ENCODING("i32i8imm", ENCODING_IB) 1091226633Sdim ENCODING("u32u8imm", ENCODING_IB) 1092201360Srdivacky ENCODING("SSECC", ENCODING_IB) 1093201360Srdivacky ENCODING("i16imm", ENCODING_Iv) 1094201360Srdivacky ENCODING("i16i8imm", ENCODING_IB) 1095201360Srdivacky ENCODING("i32imm", ENCODING_Iv) 1096201360Srdivacky ENCODING("i64i32imm", ENCODING_ID) 1097201360Srdivacky ENCODING("i64i8imm", ENCODING_IB) 1098201360Srdivacky ENCODING("i8imm", ENCODING_IB) 1099221345Sdim // This is not a typo. Instructions like BLENDVPD put 1100221345Sdim // register IDs in 8-bit immediates nowadays. 1101221345Sdim ENCODING("VR256", ENCODING_IB) 1102221345Sdim ENCODING("VR128", ENCODING_IB) 1103201360Srdivacky errs() << "Unhandled immediate encoding " << s << "\n"; 1104201360Srdivacky llvm_unreachable("Unhandled immediate encoding"); 1105201360Srdivacky} 1106201360Srdivacky 1107201360SrdivackyOperandEncoding RecognizableInstr::rmRegisterEncodingFromString 1108201360Srdivacky (const std::string &s, 1109201360Srdivacky bool hasOpSizePrefix) { 1110201360Srdivacky ENCODING("GR16", ENCODING_RM) 1111201360Srdivacky ENCODING("GR32", ENCODING_RM) 1112201360Srdivacky ENCODING("GR64", ENCODING_RM) 1113201360Srdivacky ENCODING("GR8", ENCODING_RM) 1114201360Srdivacky ENCODING("VR128", ENCODING_RM) 1115201360Srdivacky ENCODING("FR64", ENCODING_RM) 1116201360Srdivacky ENCODING("FR32", ENCODING_RM) 1117201360Srdivacky ENCODING("VR64", ENCODING_RM) 1118221345Sdim ENCODING("VR256", ENCODING_RM) 1119201360Srdivacky errs() << "Unhandled R/M register encoding " << s << "\n"; 1120201360Srdivacky llvm_unreachable("Unhandled R/M register encoding"); 1121201360Srdivacky} 1122201360Srdivacky 1123201360SrdivackyOperandEncoding RecognizableInstr::roRegisterEncodingFromString 1124201360Srdivacky (const std::string &s, 1125201360Srdivacky bool hasOpSizePrefix) { 1126201360Srdivacky ENCODING("GR16", ENCODING_REG) 1127201360Srdivacky ENCODING("GR32", ENCODING_REG) 1128201360Srdivacky ENCODING("GR64", ENCODING_REG) 1129201360Srdivacky ENCODING("GR8", ENCODING_REG) 1130201360Srdivacky ENCODING("VR128", ENCODING_REG) 1131201360Srdivacky ENCODING("FR64", ENCODING_REG) 1132201360Srdivacky ENCODING("FR32", ENCODING_REG) 1133201360Srdivacky ENCODING("VR64", ENCODING_REG) 1134201360Srdivacky ENCODING("SEGMENT_REG", ENCODING_REG) 1135201360Srdivacky ENCODING("DEBUG_REG", ENCODING_REG) 1136208599Srdivacky ENCODING("CONTROL_REG", ENCODING_REG) 1137221345Sdim ENCODING("VR256", ENCODING_REG) 1138201360Srdivacky errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1139201360Srdivacky llvm_unreachable("Unhandled reg/opcode register encoding"); 1140201360Srdivacky} 1141201360Srdivacky 1142221345SdimOperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString 1143221345Sdim (const std::string &s, 1144221345Sdim bool hasOpSizePrefix) { 1145226633Sdim ENCODING("GR32", ENCODING_VVVV) 1146226633Sdim ENCODING("GR64", ENCODING_VVVV) 1147221345Sdim ENCODING("FR32", ENCODING_VVVV) 1148221345Sdim ENCODING("FR64", ENCODING_VVVV) 1149221345Sdim ENCODING("VR128", ENCODING_VVVV) 1150221345Sdim ENCODING("VR256", ENCODING_VVVV) 1151221345Sdim errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1152221345Sdim llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1153221345Sdim} 1154221345Sdim 1155201360SrdivackyOperandEncoding RecognizableInstr::memoryEncodingFromString 1156201360Srdivacky (const std::string &s, 1157201360Srdivacky bool hasOpSizePrefix) { 1158201360Srdivacky ENCODING("i16mem", ENCODING_RM) 1159201360Srdivacky ENCODING("i32mem", ENCODING_RM) 1160201360Srdivacky ENCODING("i64mem", ENCODING_RM) 1161201360Srdivacky ENCODING("i8mem", ENCODING_RM) 1162218893Sdim ENCODING("ssmem", ENCODING_RM) 1163218893Sdim ENCODING("sdmem", ENCODING_RM) 1164201360Srdivacky ENCODING("f128mem", ENCODING_RM) 1165218893Sdim ENCODING("f256mem", ENCODING_RM) 1166201360Srdivacky ENCODING("f64mem", ENCODING_RM) 1167201360Srdivacky ENCODING("f32mem", ENCODING_RM) 1168201360Srdivacky ENCODING("i128mem", ENCODING_RM) 1169221345Sdim ENCODING("i256mem", ENCODING_RM) 1170201360Srdivacky ENCODING("f80mem", ENCODING_RM) 1171201360Srdivacky ENCODING("lea32mem", ENCODING_RM) 1172201360Srdivacky ENCODING("lea64_32mem", ENCODING_RM) 1173201360Srdivacky ENCODING("lea64mem", ENCODING_RM) 1174201360Srdivacky ENCODING("opaque32mem", ENCODING_RM) 1175201360Srdivacky ENCODING("opaque48mem", ENCODING_RM) 1176201360Srdivacky ENCODING("opaque80mem", ENCODING_RM) 1177201360Srdivacky ENCODING("opaque512mem", ENCODING_RM) 1178201360Srdivacky errs() << "Unhandled memory encoding " << s << "\n"; 1179201360Srdivacky llvm_unreachable("Unhandled memory encoding"); 1180201360Srdivacky} 1181201360Srdivacky 1182201360SrdivackyOperandEncoding RecognizableInstr::relocationEncodingFromString 1183201360Srdivacky (const std::string &s, 1184201360Srdivacky bool hasOpSizePrefix) { 1185201360Srdivacky if(!hasOpSizePrefix) { 1186201360Srdivacky // For instructions without an OpSize prefix, a declared 16-bit register or 1187201360Srdivacky // immediate encoding is special. 1188201360Srdivacky ENCODING("i16imm", ENCODING_IW) 1189201360Srdivacky } 1190201360Srdivacky ENCODING("i16imm", ENCODING_Iv) 1191201360Srdivacky ENCODING("i16i8imm", ENCODING_IB) 1192201360Srdivacky ENCODING("i32imm", ENCODING_Iv) 1193201360Srdivacky ENCODING("i32i8imm", ENCODING_IB) 1194201360Srdivacky ENCODING("i64i32imm", ENCODING_ID) 1195201360Srdivacky ENCODING("i64i8imm", ENCODING_IB) 1196201360Srdivacky ENCODING("i8imm", ENCODING_IB) 1197201360Srdivacky ENCODING("i64i32imm_pcrel", ENCODING_ID) 1198210299Sed ENCODING("i16imm_pcrel", ENCODING_IW) 1199201360Srdivacky ENCODING("i32imm_pcrel", ENCODING_ID) 1200201360Srdivacky ENCODING("brtarget", ENCODING_Iv) 1201201360Srdivacky ENCODING("brtarget8", ENCODING_IB) 1202201360Srdivacky ENCODING("i64imm", ENCODING_IO) 1203201360Srdivacky ENCODING("offset8", ENCODING_Ia) 1204201360Srdivacky ENCODING("offset16", ENCODING_Ia) 1205201360Srdivacky ENCODING("offset32", ENCODING_Ia) 1206201360Srdivacky ENCODING("offset64", ENCODING_Ia) 1207201360Srdivacky errs() << "Unhandled relocation encoding " << s << "\n"; 1208201360Srdivacky llvm_unreachable("Unhandled relocation encoding"); 1209201360Srdivacky} 1210201360Srdivacky 1211201360SrdivackyOperandEncoding RecognizableInstr::opcodeModifierEncodingFromString 1212201360Srdivacky (const std::string &s, 1213201360Srdivacky bool hasOpSizePrefix) { 1214201360Srdivacky ENCODING("RST", ENCODING_I) 1215201360Srdivacky ENCODING("GR32", ENCODING_Rv) 1216201360Srdivacky ENCODING("GR64", ENCODING_RO) 1217201360Srdivacky ENCODING("GR16", ENCODING_Rv) 1218201360Srdivacky ENCODING("GR8", ENCODING_RB) 1219226633Sdim ENCODING("GR16_NOAX", ENCODING_Rv) 1220226633Sdim ENCODING("GR32_NOAX", ENCODING_Rv) 1221226633Sdim ENCODING("GR64_NOAX", ENCODING_RO) 1222201360Srdivacky errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1223201360Srdivacky llvm_unreachable("Unhandled opcode modifier encoding"); 1224201360Srdivacky} 1225201360Srdivacky#undef ENCODING 1226