X86RecognizableInstr.cpp revision 207618 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)		\
37  MAP(F9, 42)
38
39// A clone of X86 since we can't depend on something that is generated.
40namespace X86Local {
41  enum {
42    Pseudo      = 0,
43    RawFrm      = 1,
44    AddRegFrm   = 2,
45    MRMDestReg  = 3,
46    MRMDestMem  = 4,
47    MRMSrcReg   = 5,
48    MRMSrcMem   = 6,
49    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
53    MRMInitReg  = 32,
54
55#define MAP(from, to) MRM_##from = to,
56    MRM_MAPPING
57#undef MAP
58    lastMRM
59  };
60
61  enum {
62    TB  = 1,
63    REP = 2,
64    D8 = 3, D9 = 4, DA = 5, DB = 6,
65    DC = 7, DD = 8, DE = 9, DF = 10,
66    XD = 11,  XS = 12,
67    T8 = 13,  P_TA = 14,
68    P_0F_AE = 16, P_0F_01 = 17
69  };
70}
71
72// If rows are added to the opcode extension tables, then corresponding entries
73// must be added here.
74//
75// If the row corresponds to a single byte (i.e., 8f), then add an entry for
76// that byte to ONE_BYTE_EXTENSION_TABLES.
77//
78// If the row corresponds to two bytes where the first is 0f, add an entry for
79// the second byte to TWO_BYTE_EXTENSION_TABLES.
80//
81// If the row corresponds to some other set of bytes, you will need to modify
82// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83// to the X86 TD files, except in two cases: if the first two bytes of such a
84// new combination are 0f 38 or 0f 3a, you just have to add maps called
85// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87// in RecognizableInstr::emitDecodePath().
88
89#define ONE_BYTE_EXTENSION_TABLES \
90  EXTENSION_TABLE(80)             \
91  EXTENSION_TABLE(81)             \
92  EXTENSION_TABLE(82)             \
93  EXTENSION_TABLE(83)             \
94  EXTENSION_TABLE(8f)             \
95  EXTENSION_TABLE(c0)             \
96  EXTENSION_TABLE(c1)             \
97  EXTENSION_TABLE(c6)             \
98  EXTENSION_TABLE(c7)             \
99  EXTENSION_TABLE(d0)             \
100  EXTENSION_TABLE(d1)             \
101  EXTENSION_TABLE(d2)             \
102  EXTENSION_TABLE(d3)             \
103  EXTENSION_TABLE(f6)             \
104  EXTENSION_TABLE(f7)             \
105  EXTENSION_TABLE(fe)             \
106  EXTENSION_TABLE(ff)
107
108#define TWO_BYTE_EXTENSION_TABLES \
109  EXTENSION_TABLE(00)             \
110  EXTENSION_TABLE(01)             \
111  EXTENSION_TABLE(18)             \
112  EXTENSION_TABLE(71)             \
113  EXTENSION_TABLE(72)             \
114  EXTENSION_TABLE(73)             \
115  EXTENSION_TABLE(ae)             \
116  EXTENSION_TABLE(b9)             \
117  EXTENSION_TABLE(ba)             \
118  EXTENSION_TABLE(c7)
119
120using namespace X86Disassembler;
121
122/// needsModRMForDecode - Indicates whether a particular instruction requires a
123///   ModR/M byte for the instruction to be properly decoded.  For example, a
124///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
125///   0b11.
126///
127/// @param form - The form of the instruction.
128/// @return     - true if the form implies that a ModR/M byte is required, false
129///               otherwise.
130static bool needsModRMForDecode(uint8_t form) {
131  if (form == X86Local::MRMDestReg    ||
132     form == X86Local::MRMDestMem    ||
133     form == X86Local::MRMSrcReg     ||
134     form == X86Local::MRMSrcMem     ||
135     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
137    return true;
138  else
139    return false;
140}
141
142/// isRegFormat - Indicates whether a particular form requires the Mod field of
143///   the ModR/M byte to be 0b11.
144///
145/// @param form - The form of the instruction.
146/// @return     - true if the form implies that Mod must be 0b11, false
147///               otherwise.
148static bool isRegFormat(uint8_t form) {
149  if (form == X86Local::MRMDestReg ||
150     form == X86Local::MRMSrcReg  ||
151     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
152    return true;
153  else
154    return false;
155}
156
157/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158///   Useful for switch statements and the like.
159///
160/// @param init - A reference to the BitsInit to be decoded.
161/// @return     - The field, with the first bit in the BitsInit as the lowest
162///               order bit.
163static uint8_t byteFromBitsInit(BitsInit &init) {
164  int width = init.getNumBits();
165
166  assert(width <= 8 && "Field is too large for uint8_t!");
167
168  int     index;
169  uint8_t mask = 0x01;
170
171  uint8_t ret = 0;
172
173  for (index = 0; index < width; index++) {
174    if (static_cast<BitInit*>(init.getBit(index))->getValue())
175      ret |= mask;
176
177    mask <<= 1;
178  }
179
180  return ret;
181}
182
183/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184///   name of the field.
185///
186/// @param rec  - The record from which to extract the value.
187/// @param name - The name of the field in the record.
188/// @return     - The field, as translated by byteFromBitsInit().
189static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190  BitsInit* bits = rec->getValueAsBitsInit(name);
191  return byteFromBitsInit(*bits);
192}
193
194RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195                                     const CodeGenInstruction &insn,
196                                     InstrUID uid) {
197  UID = uid;
198
199  Rec = insn.TheDef;
200  Name = Rec->getName();
201  Spec = &tables.specForUID(UID);
202
203  if (!Rec->isSubClassOf("X86Inst")) {
204    ShouldBeEmitted = false;
205    return;
206  }
207
208  Prefix   = byteFromRec(Rec, "Prefix");
209  Opcode   = byteFromRec(Rec, "Opcode");
210  Form     = byteFromRec(Rec, "FormBits");
211  SegOvr   = byteFromRec(Rec, "SegOvrBits");
212
213  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
214  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
215  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
216  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
217
218  Name      = Rec->getName();
219  AsmString = Rec->getValueAsString("AsmString");
220
221  Operands = &insn.OperandList;
222
223  IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
224  HasFROperands    = false;
225
226  ShouldBeEmitted  = true;
227}
228
229void RecognizableInstr::processInstr(DisassemblerTables &tables,
230                                   const CodeGenInstruction &insn,
231                                   InstrUID uid)
232{
233  RecognizableInstr recogInstr(tables, insn, uid);
234
235  recogInstr.emitInstructionSpecifier(tables);
236
237  if (recogInstr.shouldBeEmitted())
238    recogInstr.emitDecodePath(tables);
239}
240
241InstructionContext RecognizableInstr::insnContext() const {
242  InstructionContext insnContext;
243
244  if (Name.find("64") != Name.npos || HasREX_WPrefix) {
245    if (HasREX_WPrefix && HasOpSizePrefix)
246      insnContext = IC_64BIT_REXW_OPSIZE;
247    else if (HasOpSizePrefix)
248      insnContext = IC_64BIT_OPSIZE;
249    else if (HasREX_WPrefix && Prefix == X86Local::XS)
250      insnContext = IC_64BIT_REXW_XS;
251    else if (HasREX_WPrefix && Prefix == X86Local::XD)
252      insnContext = IC_64BIT_REXW_XD;
253    else if (Prefix == X86Local::XD)
254      insnContext = IC_64BIT_XD;
255    else if (Prefix == X86Local::XS)
256      insnContext = IC_64BIT_XS;
257    else if (HasREX_WPrefix)
258      insnContext = IC_64BIT_REXW;
259    else
260      insnContext = IC_64BIT;
261  } else {
262    if (HasOpSizePrefix)
263      insnContext = IC_OPSIZE;
264    else if (Prefix == X86Local::XD)
265      insnContext = IC_XD;
266    else if (Prefix == X86Local::XS)
267      insnContext = IC_XS;
268    else
269      insnContext = IC;
270  }
271
272  return insnContext;
273}
274
275RecognizableInstr::filter_ret RecognizableInstr::filter() const {
276  // Filter out intrinsics
277
278  if (!Rec->isSubClassOf("X86Inst"))
279    return FILTER_STRONG;
280
281  if (Form == X86Local::Pseudo ||
282      IsCodeGenOnly)
283    return FILTER_STRONG;
284
285  if (Form == X86Local::MRMInitReg)
286    return FILTER_STRONG;
287
288
289  // Filter out instructions with a LOCK prefix;
290  //   prefer forms that do not have the prefix
291  if (HasLockPrefix)
292    return FILTER_WEAK;
293
294  // Filter out artificial instructions
295
296  if (Name.find("TAILJMP") != Name.npos    ||
297     Name.find("_Int") != Name.npos       ||
298     Name.find("_int") != Name.npos       ||
299     Name.find("Int_") != Name.npos       ||
300     Name.find("_NOREX") != Name.npos     ||
301     Name.find("_TC") != Name.npos     ||
302     Name.find("EH_RETURN") != Name.npos  ||
303     Name.find("V_SET") != Name.npos      ||
304     Name.find("LOCK_") != Name.npos      ||
305     Name.find("WIN") != Name.npos)
306    return FILTER_STRONG;
307
308  // Special cases.
309
310  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
311    return FILTER_WEAK;
312  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
313    return FILTER_WEAK;
314
315  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
316    return FILTER_WEAK;
317  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
318    return FILTER_WEAK;
319  if (Name.find("Fs") != Name.npos)
320    return FILTER_WEAK;
321  if (Name == "MOVLPDrr"          ||
322      Name == "MOVLPSrr"          ||
323      Name == "PUSHFQ"            ||
324      Name == "BSF16rr"           ||
325      Name == "BSF16rm"           ||
326      Name == "BSR16rr"           ||
327      Name == "BSR16rm"           ||
328      Name == "MOVSX16rm8"        ||
329      Name == "MOVSX16rr8"        ||
330      Name == "MOVZX16rm8"        ||
331      Name == "MOVZX16rr8"        ||
332      Name == "PUSH32i16"         ||
333      Name == "PUSH64i16"         ||
334      Name == "MOVPQI2QImr"       ||
335      Name == "MOVSDmr"           ||
336      Name == "MOVSDrm"           ||
337      Name == "MOVSSmr"           ||
338      Name == "MOVSSrm"           ||
339      Name == "MMX_MOVD64rrv164"  ||
340      Name == "CRC32m16"          ||
341      Name == "MOV64ri64i32"      ||
342      Name == "CRC32r16")
343    return FILTER_WEAK;
344
345  // Filter out instructions with segment override prefixes.
346  // They're too messy to handle now and we'll special case them if needed.
347
348  if (SegOvr)
349    return FILTER_STRONG;
350
351  // Filter out instructions that can't be printed.
352
353  if (AsmString.size() == 0)
354    return FILTER_STRONG;
355
356  // Filter out instructions with subreg operands.
357
358  if (AsmString.find("subreg") != AsmString.npos)
359    return FILTER_STRONG;
360
361  if (HasFROperands && Name.find("MOV") != Name.npos &&
362     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
363      (Name.find("to") != Name.npos)))
364    return FILTER_WEAK;
365
366  return FILTER_NORMAL;
367}
368
369void RecognizableInstr::handleOperand(
370  bool optional,
371  unsigned &operandIndex,
372  unsigned &physicalOperandIndex,
373  unsigned &numPhysicalOperands,
374  unsigned *operandMapping,
375  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
376  if (optional) {
377    if (physicalOperandIndex >= numPhysicalOperands)
378      return;
379  } else {
380    assert(physicalOperandIndex < numPhysicalOperands);
381  }
382
383  while (operandMapping[operandIndex] != operandIndex) {
384    Spec->operands[operandIndex].encoding = ENCODING_DUP;
385    Spec->operands[operandIndex].type =
386      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
387    ++operandIndex;
388  }
389
390  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
391
392  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
393                                                              HasOpSizePrefix);
394  Spec->operands[operandIndex].type = typeFromString(typeName,
395                                                      IsSSE,
396                                                      HasREX_WPrefix,
397                                                      HasOpSizePrefix);
398
399  ++operandIndex;
400  ++physicalOperandIndex;
401}
402
403void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
404  Spec->name       = Name;
405
406  if (!Rec->isSubClassOf("X86Inst"))
407    return;
408
409  switch (filter()) {
410  case FILTER_WEAK:
411    Spec->filtered = true;
412    break;
413  case FILTER_STRONG:
414    ShouldBeEmitted = false;
415    return;
416  case FILTER_NORMAL:
417    break;
418  }
419
420  Spec->insnContext = insnContext();
421
422  const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
423
424  unsigned operandIndex;
425  unsigned numOperands = OperandList.size();
426  unsigned numPhysicalOperands = 0;
427
428  // operandMapping maps from operands in OperandList to their originals.
429  // If operandMapping[i] != i, then the entry is a duplicate.
430  unsigned operandMapping[X86_MAX_OPERANDS];
431
432  bool hasFROperands = false;
433
434  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
435
436  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
437    if (OperandList[operandIndex].Constraints.size()) {
438      const CodeGenInstruction::ConstraintInfo &Constraint =
439        OperandList[operandIndex].Constraints[0];
440      if (Constraint.isTied()) {
441        operandMapping[operandIndex] = Constraint.getTiedOperand();
442      } else {
443        ++numPhysicalOperands;
444        operandMapping[operandIndex] = operandIndex;
445      }
446    } else {
447      ++numPhysicalOperands;
448      operandMapping[operandIndex] = operandIndex;
449    }
450
451    const std::string &recName = OperandList[operandIndex].Rec->getName();
452
453    if (recName.find("FR") != recName.npos)
454      hasFROperands = true;
455  }
456
457  if (hasFROperands && Name.find("MOV") != Name.npos &&
458     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
459      (Name.find("to") != Name.npos)))
460    ShouldBeEmitted = false;
461
462  if (!ShouldBeEmitted)
463    return;
464
465#define HANDLE_OPERAND(class)               \
466  handleOperand(false,                      \
467                operandIndex,               \
468                physicalOperandIndex,       \
469                numPhysicalOperands,        \
470                operandMapping,             \
471                class##EncodingFromString);
472
473#define HANDLE_OPTIONAL(class)              \
474  handleOperand(true,                       \
475                operandIndex,               \
476                physicalOperandIndex,       \
477                numPhysicalOperands,        \
478                operandMapping,             \
479                class##EncodingFromString);
480
481  // operandIndex should always be < numOperands
482  operandIndex = 0;
483  // physicalOperandIndex should always be < numPhysicalOperands
484  unsigned physicalOperandIndex = 0;
485
486  switch (Form) {
487  case X86Local::RawFrm:
488    // Operand 1 (optional) is an address or immediate.
489    // Operand 2 (optional) is an immediate.
490    assert(numPhysicalOperands <= 2 &&
491           "Unexpected number of operands for RawFrm");
492    HANDLE_OPTIONAL(relocation)
493    HANDLE_OPTIONAL(immediate)
494    break;
495  case X86Local::AddRegFrm:
496    // Operand 1 is added to the opcode.
497    // Operand 2 (optional) is an address.
498    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
499           "Unexpected number of operands for AddRegFrm");
500    HANDLE_OPERAND(opcodeModifier)
501    HANDLE_OPTIONAL(relocation)
502    break;
503  case X86Local::MRMDestReg:
504    // Operand 1 is a register operand in the R/M field.
505    // Operand 2 is a register operand in the Reg/Opcode field.
506    // Operand 3 (optional) is an immediate.
507    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
508           "Unexpected number of operands for MRMDestRegFrm");
509    HANDLE_OPERAND(rmRegister)
510    HANDLE_OPERAND(roRegister)
511    HANDLE_OPTIONAL(immediate)
512    break;
513  case X86Local::MRMDestMem:
514    // Operand 1 is a memory operand (possibly SIB-extended)
515    // Operand 2 is a register operand in the Reg/Opcode field.
516    // Operand 3 (optional) is an immediate.
517    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
518           "Unexpected number of operands for MRMDestMemFrm");
519    HANDLE_OPERAND(memory)
520    HANDLE_OPERAND(roRegister)
521    HANDLE_OPTIONAL(immediate)
522    break;
523  case X86Local::MRMSrcReg:
524    // Operand 1 is a register operand in the Reg/Opcode field.
525    // Operand 2 is a register operand in the R/M field.
526    // Operand 3 (optional) is an immediate.
527    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
528           "Unexpected number of operands for MRMSrcRegFrm");
529    HANDLE_OPERAND(roRegister)
530    HANDLE_OPERAND(rmRegister)
531    HANDLE_OPTIONAL(immediate)
532    break;
533  case X86Local::MRMSrcMem:
534    // Operand 1 is a register operand in the Reg/Opcode field.
535    // Operand 2 is a memory operand (possibly SIB-extended)
536    // Operand 3 (optional) is an immediate.
537    assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
538           "Unexpected number of operands for MRMSrcMemFrm");
539    HANDLE_OPERAND(roRegister)
540    HANDLE_OPERAND(memory)
541    HANDLE_OPTIONAL(immediate)
542    break;
543  case X86Local::MRM0r:
544  case X86Local::MRM1r:
545  case X86Local::MRM2r:
546  case X86Local::MRM3r:
547  case X86Local::MRM4r:
548  case X86Local::MRM5r:
549  case X86Local::MRM6r:
550  case X86Local::MRM7r:
551    // Operand 1 is a register operand in the R/M field.
552    // Operand 2 (optional) is an immediate or relocation.
553    assert(numPhysicalOperands <= 2 &&
554           "Unexpected number of operands for MRMnRFrm");
555    HANDLE_OPTIONAL(rmRegister)
556    HANDLE_OPTIONAL(relocation)
557    break;
558  case X86Local::MRM0m:
559  case X86Local::MRM1m:
560  case X86Local::MRM2m:
561  case X86Local::MRM3m:
562  case X86Local::MRM4m:
563  case X86Local::MRM5m:
564  case X86Local::MRM6m:
565  case X86Local::MRM7m:
566    // Operand 1 is a memory operand (possibly SIB-extended)
567    // Operand 2 (optional) is an immediate or relocation.
568    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
569           "Unexpected number of operands for MRMnMFrm");
570    HANDLE_OPERAND(memory)
571    HANDLE_OPTIONAL(relocation)
572    break;
573  case X86Local::MRMInitReg:
574    // Ignored.
575    break;
576  }
577
578  #undef HANDLE_OPERAND
579  #undef HANDLE_OPTIONAL
580}
581
582void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
583  // Special cases where the LLVM tables are not complete
584
585#define MAP(from, to)                     \
586  case X86Local::MRM_##from:              \
587    filter = new ExactFilter(0x##from);   \
588    break;
589
590  OpcodeType    opcodeType  = (OpcodeType)-1;
591
592  ModRMFilter*  filter      = NULL;
593  uint8_t       opcodeToSet = 0;
594
595  switch (Prefix) {
596  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
597  case X86Local::XD:
598  case X86Local::XS:
599  case X86Local::TB:
600    opcodeType = TWOBYTE;
601
602    switch (Opcode) {
603    default:
604      if (needsModRMForDecode(Form))
605        filter = new ModFilter(isRegFormat(Form));
606      else
607        filter = new DumbFilter();
608      break;
609#define EXTENSION_TABLE(n) case 0x##n:
610    TWO_BYTE_EXTENSION_TABLES
611#undef EXTENSION_TABLE
612      switch (Form) {
613      default:
614        llvm_unreachable("Unhandled two-byte extended opcode");
615      case X86Local::MRM0r:
616      case X86Local::MRM1r:
617      case X86Local::MRM2r:
618      case X86Local::MRM3r:
619      case X86Local::MRM4r:
620      case X86Local::MRM5r:
621      case X86Local::MRM6r:
622      case X86Local::MRM7r:
623        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
624        break;
625      case X86Local::MRM0m:
626      case X86Local::MRM1m:
627      case X86Local::MRM2m:
628      case X86Local::MRM3m:
629      case X86Local::MRM4m:
630      case X86Local::MRM5m:
631      case X86Local::MRM6m:
632      case X86Local::MRM7m:
633        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
634        break;
635      MRM_MAPPING
636      } // switch (Form)
637      break;
638    } // switch (Opcode)
639    opcodeToSet = Opcode;
640    break;
641  case X86Local::T8:
642    opcodeType = THREEBYTE_38;
643    if (needsModRMForDecode(Form))
644      filter = new ModFilter(isRegFormat(Form));
645    else
646      filter = new DumbFilter();
647    opcodeToSet = Opcode;
648    break;
649  case X86Local::P_TA:
650    opcodeType = THREEBYTE_3A;
651    if (needsModRMForDecode(Form))
652      filter = new ModFilter(isRegFormat(Form));
653    else
654      filter = new DumbFilter();
655    opcodeToSet = Opcode;
656    break;
657  case X86Local::D8:
658  case X86Local::D9:
659  case X86Local::DA:
660  case X86Local::DB:
661  case X86Local::DC:
662  case X86Local::DD:
663  case X86Local::DE:
664  case X86Local::DF:
665    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
666    opcodeType = ONEBYTE;
667    if (Form == X86Local::AddRegFrm) {
668      Spec->modifierType = MODIFIER_MODRM;
669      Spec->modifierBase = Opcode;
670      filter = new AddRegEscapeFilter(Opcode);
671    } else {
672      filter = new EscapeFilter(true, Opcode);
673    }
674    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
675    break;
676  default:
677    opcodeType = ONEBYTE;
678    switch (Opcode) {
679#define EXTENSION_TABLE(n) case 0x##n:
680    ONE_BYTE_EXTENSION_TABLES
681#undef EXTENSION_TABLE
682      switch (Form) {
683      default:
684        llvm_unreachable("Fell through the cracks of a single-byte "
685                         "extended opcode");
686      case X86Local::MRM0r:
687      case X86Local::MRM1r:
688      case X86Local::MRM2r:
689      case X86Local::MRM3r:
690      case X86Local::MRM4r:
691      case X86Local::MRM5r:
692      case X86Local::MRM6r:
693      case X86Local::MRM7r:
694        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
695        break;
696      case X86Local::MRM0m:
697      case X86Local::MRM1m:
698      case X86Local::MRM2m:
699      case X86Local::MRM3m:
700      case X86Local::MRM4m:
701      case X86Local::MRM5m:
702      case X86Local::MRM6m:
703      case X86Local::MRM7m:
704        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
705        break;
706      MRM_MAPPING
707      } // switch (Form)
708      break;
709    case 0xd8:
710    case 0xd9:
711    case 0xda:
712    case 0xdb:
713    case 0xdc:
714    case 0xdd:
715    case 0xde:
716    case 0xdf:
717      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
718      break;
719    default:
720      if (needsModRMForDecode(Form))
721        filter = new ModFilter(isRegFormat(Form));
722      else
723        filter = new DumbFilter();
724      break;
725    } // switch (Opcode)
726    opcodeToSet = Opcode;
727  } // switch (Prefix)
728
729  assert(opcodeType != (OpcodeType)-1 &&
730         "Opcode type not set");
731  assert(filter && "Filter not set");
732
733  if (Form == X86Local::AddRegFrm) {
734    if(Spec->modifierType != MODIFIER_MODRM) {
735      assert(opcodeToSet < 0xf9 &&
736             "Not enough room for all ADDREG_FRM operands");
737
738      uint8_t currentOpcode;
739
740      for (currentOpcode = opcodeToSet;
741           currentOpcode < opcodeToSet + 8;
742           ++currentOpcode)
743        tables.setTableFields(opcodeType,
744                              insnContext(),
745                              currentOpcode,
746                              *filter,
747                              UID);
748
749      Spec->modifierType = MODIFIER_OPCODE;
750      Spec->modifierBase = opcodeToSet;
751    } else {
752      // modifierBase was set where MODIFIER_MODRM was set
753      tables.setTableFields(opcodeType,
754                            insnContext(),
755                            opcodeToSet,
756                            *filter,
757                            UID);
758    }
759  } else {
760    tables.setTableFields(opcodeType,
761                          insnContext(),
762                          opcodeToSet,
763                          *filter,
764                          UID);
765
766    Spec->modifierType = MODIFIER_NONE;
767    Spec->modifierBase = opcodeToSet;
768  }
769
770  delete filter;
771
772#undef MAP
773}
774
775#define TYPE(str, type) if (s == str) return type;
776OperandType RecognizableInstr::typeFromString(const std::string &s,
777                                              bool isSSE,
778                                              bool hasREX_WPrefix,
779                                              bool hasOpSizePrefix) {
780  if (isSSE) {
781    // For SSE instructions, we ignore the OpSize prefix and force operand
782    // sizes.
783    TYPE("GR16",              TYPE_R16)
784    TYPE("GR32",              TYPE_R32)
785    TYPE("GR64",              TYPE_R64)
786  }
787  if(hasREX_WPrefix) {
788    // For instructions with a REX_W prefix, a declared 32-bit register encoding
789    // is special.
790    TYPE("GR32",              TYPE_R32)
791  }
792  if(!hasOpSizePrefix) {
793    // For instructions without an OpSize prefix, a declared 16-bit register or
794    // immediate encoding is special.
795    TYPE("GR16",              TYPE_R16)
796    TYPE("i16imm",            TYPE_IMM16)
797  }
798  TYPE("i16mem",              TYPE_Mv)
799  TYPE("i16imm",              TYPE_IMMv)
800  TYPE("i16i8imm",            TYPE_IMMv)
801  TYPE("GR16",                TYPE_Rv)
802  TYPE("i32mem",              TYPE_Mv)
803  TYPE("i32imm",              TYPE_IMMv)
804  TYPE("i32i8imm",            TYPE_IMM32)
805  TYPE("GR32",                TYPE_Rv)
806  TYPE("i64mem",              TYPE_Mv)
807  TYPE("i64i32imm",           TYPE_IMM64)
808  TYPE("i64i8imm",            TYPE_IMM64)
809  TYPE("GR64",                TYPE_R64)
810  TYPE("i8mem",               TYPE_M8)
811  TYPE("i8imm",               TYPE_IMM8)
812  TYPE("GR8",                 TYPE_R8)
813  TYPE("VR128",               TYPE_XMM128)
814  TYPE("f128mem",             TYPE_M128)
815  TYPE("FR64",                TYPE_XMM64)
816  TYPE("f64mem",              TYPE_M64FP)
817  TYPE("FR32",                TYPE_XMM32)
818  TYPE("f32mem",              TYPE_M32FP)
819  TYPE("RST",                 TYPE_ST)
820  TYPE("i128mem",             TYPE_M128)
821  TYPE("i64i32imm_pcrel",     TYPE_REL64)
822  TYPE("i32imm_pcrel",        TYPE_REL32)
823  TYPE("SSECC",               TYPE_IMM3)
824  TYPE("brtarget",            TYPE_RELv)
825  TYPE("brtarget8",           TYPE_REL8)
826  TYPE("f80mem",              TYPE_M80FP)
827  TYPE("lea32mem",            TYPE_LEA)
828  TYPE("lea64_32mem",         TYPE_LEA)
829  TYPE("lea64mem",            TYPE_LEA)
830  TYPE("VR64",                TYPE_MM64)
831  TYPE("i64imm",              TYPE_IMMv)
832  TYPE("opaque32mem",         TYPE_M1616)
833  TYPE("opaque48mem",         TYPE_M1632)
834  TYPE("opaque80mem",         TYPE_M1664)
835  TYPE("opaque512mem",        TYPE_M512)
836  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
837  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
838  TYPE("CONTROL_REG_32",      TYPE_CR32)
839  TYPE("CONTROL_REG_64",      TYPE_CR64)
840  TYPE("offset8",             TYPE_MOFFS8)
841  TYPE("offset16",            TYPE_MOFFS16)
842  TYPE("offset32",            TYPE_MOFFS32)
843  TYPE("offset64",            TYPE_MOFFS64)
844  errs() << "Unhandled type string " << s << "\n";
845  llvm_unreachable("Unhandled type string");
846}
847#undef TYPE
848
849#define ENCODING(str, encoding) if (s == str) return encoding;
850OperandEncoding RecognizableInstr::immediateEncodingFromString
851  (const std::string &s,
852   bool hasOpSizePrefix) {
853  if(!hasOpSizePrefix) {
854    // For instructions without an OpSize prefix, a declared 16-bit register or
855    // immediate encoding is special.
856    ENCODING("i16imm",        ENCODING_IW)
857  }
858  ENCODING("i32i8imm",        ENCODING_IB)
859  ENCODING("SSECC",           ENCODING_IB)
860  ENCODING("i16imm",          ENCODING_Iv)
861  ENCODING("i16i8imm",        ENCODING_IB)
862  ENCODING("i32imm",          ENCODING_Iv)
863  ENCODING("i64i32imm",       ENCODING_ID)
864  ENCODING("i64i8imm",        ENCODING_IB)
865  ENCODING("i8imm",           ENCODING_IB)
866  errs() << "Unhandled immediate encoding " << s << "\n";
867  llvm_unreachable("Unhandled immediate encoding");
868}
869
870OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
871  (const std::string &s,
872   bool hasOpSizePrefix) {
873  ENCODING("GR16",            ENCODING_RM)
874  ENCODING("GR32",            ENCODING_RM)
875  ENCODING("GR64",            ENCODING_RM)
876  ENCODING("GR8",             ENCODING_RM)
877  ENCODING("VR128",           ENCODING_RM)
878  ENCODING("FR64",            ENCODING_RM)
879  ENCODING("FR32",            ENCODING_RM)
880  ENCODING("VR64",            ENCODING_RM)
881  errs() << "Unhandled R/M register encoding " << s << "\n";
882  llvm_unreachable("Unhandled R/M register encoding");
883}
884
885OperandEncoding RecognizableInstr::roRegisterEncodingFromString
886  (const std::string &s,
887   bool hasOpSizePrefix) {
888  ENCODING("GR16",            ENCODING_REG)
889  ENCODING("GR32",            ENCODING_REG)
890  ENCODING("GR64",            ENCODING_REG)
891  ENCODING("GR8",             ENCODING_REG)
892  ENCODING("VR128",           ENCODING_REG)
893  ENCODING("FR64",            ENCODING_REG)
894  ENCODING("FR32",            ENCODING_REG)
895  ENCODING("VR64",            ENCODING_REG)
896  ENCODING("SEGMENT_REG",     ENCODING_REG)
897  ENCODING("DEBUG_REG",       ENCODING_REG)
898  ENCODING("CONTROL_REG_32",  ENCODING_REG)
899  ENCODING("CONTROL_REG_64",  ENCODING_REG)
900  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
901  llvm_unreachable("Unhandled reg/opcode register encoding");
902}
903
904OperandEncoding RecognizableInstr::memoryEncodingFromString
905  (const std::string &s,
906   bool hasOpSizePrefix) {
907  ENCODING("i16mem",          ENCODING_RM)
908  ENCODING("i32mem",          ENCODING_RM)
909  ENCODING("i64mem",          ENCODING_RM)
910  ENCODING("i8mem",           ENCODING_RM)
911  ENCODING("f128mem",         ENCODING_RM)
912  ENCODING("f64mem",          ENCODING_RM)
913  ENCODING("f32mem",          ENCODING_RM)
914  ENCODING("i128mem",         ENCODING_RM)
915  ENCODING("f80mem",          ENCODING_RM)
916  ENCODING("lea32mem",        ENCODING_RM)
917  ENCODING("lea64_32mem",     ENCODING_RM)
918  ENCODING("lea64mem",        ENCODING_RM)
919  ENCODING("opaque32mem",     ENCODING_RM)
920  ENCODING("opaque48mem",     ENCODING_RM)
921  ENCODING("opaque80mem",     ENCODING_RM)
922  ENCODING("opaque512mem",    ENCODING_RM)
923  errs() << "Unhandled memory encoding " << s << "\n";
924  llvm_unreachable("Unhandled memory encoding");
925}
926
927OperandEncoding RecognizableInstr::relocationEncodingFromString
928  (const std::string &s,
929   bool hasOpSizePrefix) {
930  if(!hasOpSizePrefix) {
931    // For instructions without an OpSize prefix, a declared 16-bit register or
932    // immediate encoding is special.
933    ENCODING("i16imm",        ENCODING_IW)
934  }
935  ENCODING("i16imm",          ENCODING_Iv)
936  ENCODING("i16i8imm",        ENCODING_IB)
937  ENCODING("i32imm",          ENCODING_Iv)
938  ENCODING("i32i8imm",        ENCODING_IB)
939  ENCODING("i64i32imm",       ENCODING_ID)
940  ENCODING("i64i8imm",        ENCODING_IB)
941  ENCODING("i8imm",           ENCODING_IB)
942  ENCODING("i64i32imm_pcrel", ENCODING_ID)
943  ENCODING("i32imm_pcrel",    ENCODING_ID)
944  ENCODING("brtarget",        ENCODING_Iv)
945  ENCODING("brtarget8",       ENCODING_IB)
946  ENCODING("i64imm",          ENCODING_IO)
947  ENCODING("offset8",         ENCODING_Ia)
948  ENCODING("offset16",        ENCODING_Ia)
949  ENCODING("offset32",        ENCODING_Ia)
950  ENCODING("offset64",        ENCODING_Ia)
951  errs() << "Unhandled relocation encoding " << s << "\n";
952  llvm_unreachable("Unhandled relocation encoding");
953}
954
955OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
956  (const std::string &s,
957   bool hasOpSizePrefix) {
958  ENCODING("RST",             ENCODING_I)
959  ENCODING("GR32",            ENCODING_Rv)
960  ENCODING("GR64",            ENCODING_RO)
961  ENCODING("GR16",            ENCODING_Rv)
962  ENCODING("GR8",             ENCODING_RB)
963  errs() << "Unhandled opcode modifier encoding " << s << "\n";
964  llvm_unreachable("Unhandled opcode modifier encoding");
965}
966#undef ENCODING
967