X86DisassemblerTables.cpp revision 276479
1//===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file is part of the X86 Disassembler Emitter. 11// It contains the implementation of the disassembler tables. 12// Documentation for the disassembler emitter in general can be found in 13// X86DisasemblerEmitter.h. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86DisassemblerTables.h" 18#include "X86DisassemblerShared.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/Support/ErrorHandling.h" 21#include "llvm/Support/Format.h" 22#include <map> 23 24using namespace llvm; 25using namespace X86Disassembler; 26 27/// stringForContext - Returns a string containing the name of a particular 28/// InstructionContext, usually for diagnostic purposes. 29/// 30/// @param insnContext - The instruction class to transform to a string. 31/// @return - A statically-allocated string constant that contains the 32/// name of the instruction class. 33static inline const char* stringForContext(InstructionContext insnContext) { 34 switch (insnContext) { 35 default: 36 llvm_unreachable("Unhandled instruction class"); 37#define ENUM_ENTRY(n, r, d) case n: return #n; break; 38#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ 39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ 40 ENUM_ENTRY(n##_KZ_B, r, d) 41 INSTRUCTION_CONTEXTS 42#undef ENUM_ENTRY 43#undef ENUM_ENTRY_K_B 44 } 45} 46 47/// stringForOperandType - Like stringForContext, but for OperandTypes. 48static inline const char* stringForOperandType(OperandType type) { 49 switch (type) { 50 default: 51 llvm_unreachable("Unhandled type"); 52#define ENUM_ENTRY(i, d) case i: return #i; 53 TYPES 54#undef ENUM_ENTRY 55 } 56} 57 58/// stringForOperandEncoding - like stringForContext, but for 59/// OperandEncodings. 60static inline const char* stringForOperandEncoding(OperandEncoding encoding) { 61 switch (encoding) { 62 default: 63 llvm_unreachable("Unhandled encoding"); 64#define ENUM_ENTRY(i, d) case i: return #i; 65 ENCODINGS 66#undef ENUM_ENTRY 67 } 68} 69 70/// inheritsFrom - Indicates whether all instructions in one class also belong 71/// to another class. 72/// 73/// @param child - The class that may be the subset 74/// @param parent - The class that may be the superset 75/// @return - True if child is a subset of parent, false otherwise. 76static inline bool inheritsFrom(InstructionContext child, 77 InstructionContext parent, 78 bool VEX_LIG = false) { 79 if (child == parent) 80 return true; 81 82 switch (parent) { 83 case IC: 84 return(inheritsFrom(child, IC_64BIT) || 85 inheritsFrom(child, IC_OPSIZE) || 86 inheritsFrom(child, IC_ADSIZE) || 87 inheritsFrom(child, IC_XD) || 88 inheritsFrom(child, IC_XS)); 89 case IC_64BIT: 90 return(inheritsFrom(child, IC_64BIT_REXW) || 91 inheritsFrom(child, IC_64BIT_OPSIZE) || 92 inheritsFrom(child, IC_64BIT_ADSIZE) || 93 inheritsFrom(child, IC_64BIT_XD) || 94 inheritsFrom(child, IC_64BIT_XS)); 95 case IC_OPSIZE: 96 return inheritsFrom(child, IC_64BIT_OPSIZE); 97 case IC_ADSIZE: 98 case IC_64BIT_ADSIZE: 99 return false; 100 case IC_XD: 101 return inheritsFrom(child, IC_64BIT_XD); 102 case IC_XS: 103 return inheritsFrom(child, IC_64BIT_XS); 104 case IC_XD_OPSIZE: 105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE); 106 case IC_XS_OPSIZE: 107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE); 108 case IC_64BIT_REXW: 109 return(inheritsFrom(child, IC_64BIT_REXW_XS) || 110 inheritsFrom(child, IC_64BIT_REXW_XD) || 111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 112 case IC_64BIT_OPSIZE: 113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE)); 114 case IC_64BIT_XD: 115 return(inheritsFrom(child, IC_64BIT_REXW_XD)); 116 case IC_64BIT_XS: 117 return(inheritsFrom(child, IC_64BIT_REXW_XS)); 118 case IC_64BIT_XD_OPSIZE: 119 case IC_64BIT_XS_OPSIZE: 120 return false; 121 case IC_64BIT_REXW_XD: 122 case IC_64BIT_REXW_XS: 123 case IC_64BIT_REXW_OPSIZE: 124 return false; 125 case IC_VEX: 126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || 127 inheritsFrom(child, IC_VEX_W) || 128 (VEX_LIG && inheritsFrom(child, IC_VEX_L)); 129 case IC_VEX_XS: 130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || 131 inheritsFrom(child, IC_VEX_W_XS) || 132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); 133 case IC_VEX_XD: 134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || 135 inheritsFrom(child, IC_VEX_W_XD) || 136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); 137 case IC_VEX_OPSIZE: 138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || 139 inheritsFrom(child, IC_VEX_W_OPSIZE) || 140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); 141 case IC_VEX_W: 142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); 143 case IC_VEX_W_XS: 144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); 145 case IC_VEX_W_XD: 146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); 147 case IC_VEX_W_OPSIZE: 148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); 149 case IC_VEX_L: 150 return inheritsFrom(child, IC_VEX_L_W); 151 case IC_VEX_L_XS: 152 return inheritsFrom(child, IC_VEX_L_W_XS); 153 case IC_VEX_L_XD: 154 return inheritsFrom(child, IC_VEX_L_W_XD); 155 case IC_VEX_L_OPSIZE: 156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE); 157 case IC_VEX_L_W: 158 case IC_VEX_L_W_XS: 159 case IC_VEX_L_W_XD: 160 case IC_VEX_L_W_OPSIZE: 161 return false; 162 case IC_EVEX: 163 return inheritsFrom(child, IC_EVEX_W) || 164 inheritsFrom(child, IC_EVEX_L_W); 165 case IC_EVEX_XS: 166 return inheritsFrom(child, IC_EVEX_W_XS) || 167 inheritsFrom(child, IC_EVEX_L_W_XS); 168 case IC_EVEX_XD: 169 return inheritsFrom(child, IC_EVEX_W_XD) || 170 inheritsFrom(child, IC_EVEX_L_W_XD); 171 case IC_EVEX_OPSIZE: 172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) || 173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE); 174 case IC_EVEX_W: 175 case IC_EVEX_W_XS: 176 case IC_EVEX_W_XD: 177 case IC_EVEX_W_OPSIZE: 178 return false; 179 case IC_EVEX_L: 180 case IC_EVEX_L_XS: 181 case IC_EVEX_L_XD: 182 case IC_EVEX_L_OPSIZE: 183 return false; 184 case IC_EVEX_L_W: 185 case IC_EVEX_L_W_XS: 186 case IC_EVEX_L_W_XD: 187 case IC_EVEX_L_W_OPSIZE: 188 return false; 189 case IC_EVEX_L2: 190 case IC_EVEX_L2_XS: 191 case IC_EVEX_L2_XD: 192 case IC_EVEX_L2_OPSIZE: 193 return false; 194 case IC_EVEX_L2_W: 195 case IC_EVEX_L2_W_XS: 196 case IC_EVEX_L2_W_XD: 197 case IC_EVEX_L2_W_OPSIZE: 198 return false; 199 case IC_EVEX_K: 200 return inheritsFrom(child, IC_EVEX_W_K) || 201 inheritsFrom(child, IC_EVEX_L_W_K); 202 case IC_EVEX_XS_K: 203 return inheritsFrom(child, IC_EVEX_W_XS_K) || 204 inheritsFrom(child, IC_EVEX_L_W_XS_K); 205 case IC_EVEX_XD_K: 206 return inheritsFrom(child, IC_EVEX_W_XD_K) || 207 inheritsFrom(child, IC_EVEX_L_W_XD_K); 208 case IC_EVEX_OPSIZE_K: 209 case IC_EVEX_OPSIZE_B: 210 return false; 211 case IC_EVEX_W_K: 212 case IC_EVEX_W_XS_K: 213 case IC_EVEX_W_XD_K: 214 case IC_EVEX_W_OPSIZE_K: 215 case IC_EVEX_W_OPSIZE_B: 216 return false; 217 case IC_EVEX_L_K: 218 case IC_EVEX_L_XS_K: 219 case IC_EVEX_L_XD_K: 220 case IC_EVEX_L_OPSIZE_K: 221 return false; 222 case IC_EVEX_W_KZ: 223 case IC_EVEX_W_XS_KZ: 224 case IC_EVEX_W_XD_KZ: 225 case IC_EVEX_W_OPSIZE_KZ: 226 return false; 227 case IC_EVEX_L_KZ: 228 case IC_EVEX_L_XS_KZ: 229 case IC_EVEX_L_XD_KZ: 230 case IC_EVEX_L_OPSIZE_KZ: 231 return false; 232 case IC_EVEX_L_W_K: 233 case IC_EVEX_L_W_XS_K: 234 case IC_EVEX_L_W_XD_K: 235 case IC_EVEX_L_W_OPSIZE_K: 236 case IC_EVEX_L_W_KZ: 237 case IC_EVEX_L_W_XS_KZ: 238 case IC_EVEX_L_W_XD_KZ: 239 case IC_EVEX_L_W_OPSIZE_KZ: 240 return false; 241 case IC_EVEX_L2_K: 242 case IC_EVEX_L2_B: 243 case IC_EVEX_L2_K_B: 244 case IC_EVEX_L2_KZ_B: 245 case IC_EVEX_L2_XS_K: 246 case IC_EVEX_L2_XS_B: 247 case IC_EVEX_L2_XD_B: 248 case IC_EVEX_L2_XD_K: 249 case IC_EVEX_L2_OPSIZE_K: 250 case IC_EVEX_L2_OPSIZE_B: 251 case IC_EVEX_L2_OPSIZE_K_B: 252 case IC_EVEX_L2_KZ: 253 case IC_EVEX_L2_XS_KZ: 254 case IC_EVEX_L2_XD_KZ: 255 case IC_EVEX_L2_OPSIZE_KZ: 256 case IC_EVEX_L2_OPSIZE_KZ_B: 257 return false; 258 case IC_EVEX_L2_W_K: 259 case IC_EVEX_L2_W_B: 260 case IC_EVEX_L2_W_XS_K: 261 case IC_EVEX_L2_W_XD_K: 262 case IC_EVEX_L2_W_XD_B: 263 case IC_EVEX_L2_W_OPSIZE_K: 264 case IC_EVEX_L2_W_OPSIZE_B: 265 case IC_EVEX_L2_W_OPSIZE_K_B: 266 case IC_EVEX_L2_W_KZ: 267 case IC_EVEX_L2_W_XS_KZ: 268 case IC_EVEX_L2_W_XD_KZ: 269 case IC_EVEX_L2_W_OPSIZE_KZ: 270 case IC_EVEX_L2_W_OPSIZE_KZ_B: 271 return false; 272 default: 273 errs() << "Unknown instruction class: " << 274 stringForContext((InstructionContext)parent) << "\n"; 275 llvm_unreachable("Unknown instruction class"); 276 } 277} 278 279/// outranks - Indicates whether, if an instruction has two different applicable 280/// classes, which class should be preferred when performing decode. This 281/// imposes a total ordering (ties are resolved toward "lower") 282/// 283/// @param upper - The class that may be preferable 284/// @param lower - The class that may be less preferable 285/// @return - True if upper is to be preferred, false otherwise. 286static inline bool outranks(InstructionContext upper, 287 InstructionContext lower) { 288 assert(upper < IC_max); 289 assert(lower < IC_max); 290 291#define ENUM_ENTRY(n, r, d) r, 292#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ 293 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ 294 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) 295 static int ranks[IC_max] = { 296 INSTRUCTION_CONTEXTS 297 }; 298#undef ENUM_ENTRY 299#undef ENUM_ENTRY_K_B 300 301 return (ranks[upper] > ranks[lower]); 302} 303 304/// getDecisionType - Determines whether a ModRM decision with 255 entries can 305/// be compacted by eliminating redundant information. 306/// 307/// @param decision - The decision to be compacted. 308/// @return - The compactest available representation for the decision. 309static ModRMDecisionType getDecisionType(ModRMDecision &decision) { 310 bool satisfiesOneEntry = true; 311 bool satisfiesSplitRM = true; 312 bool satisfiesSplitReg = true; 313 bool satisfiesSplitMisc = true; 314 315 for (unsigned index = 0; index < 256; ++index) { 316 if (decision.instructionIDs[index] != decision.instructionIDs[0]) 317 satisfiesOneEntry = false; 318 319 if (((index & 0xc0) == 0xc0) && 320 (decision.instructionIDs[index] != decision.instructionIDs[0xc0])) 321 satisfiesSplitRM = false; 322 323 if (((index & 0xc0) != 0xc0) && 324 (decision.instructionIDs[index] != decision.instructionIDs[0x00])) 325 satisfiesSplitRM = false; 326 327 if (((index & 0xc0) == 0xc0) && 328 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8])) 329 satisfiesSplitReg = false; 330 331 if (((index & 0xc0) != 0xc0) && 332 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) 333 satisfiesSplitMisc = false; 334 } 335 336 if (satisfiesOneEntry) 337 return MODRM_ONEENTRY; 338 339 if (satisfiesSplitRM) 340 return MODRM_SPLITRM; 341 342 if (satisfiesSplitReg && satisfiesSplitMisc) 343 return MODRM_SPLITREG; 344 345 if (satisfiesSplitMisc) 346 return MODRM_SPLITMISC; 347 348 return MODRM_FULL; 349} 350 351/// stringForDecisionType - Returns a statically-allocated string corresponding 352/// to a particular decision type. 353/// 354/// @param dt - The decision type. 355/// @return - A pointer to the statically-allocated string (e.g., 356/// "MODRM_ONEENTRY" for MODRM_ONEENTRY). 357static const char* stringForDecisionType(ModRMDecisionType dt) { 358#define ENUM_ENTRY(n) case n: return #n; 359 switch (dt) { 360 default: 361 llvm_unreachable("Unknown decision type"); 362 MODRMTYPES 363 }; 364#undef ENUM_ENTRY 365} 366 367DisassemblerTables::DisassemblerTables() { 368 unsigned i; 369 370 for (i = 0; i < array_lengthof(Tables); i++) { 371 Tables[i] = new ContextDecision; 372 memset(Tables[i], 0, sizeof(ContextDecision)); 373 } 374 375 HasConflicts = false; 376} 377 378DisassemblerTables::~DisassemblerTables() { 379 unsigned i; 380 381 for (i = 0; i < array_lengthof(Tables); i++) 382 delete Tables[i]; 383} 384 385void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, 386 unsigned &i1, unsigned &i2, 387 unsigned &ModRMTableNum, 388 ModRMDecision &decision) const { 389 static uint32_t sTableNumber = 0; 390 static uint32_t sEntryNumber = 1; 391 ModRMDecisionType dt = getDecisionType(decision); 392 393 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) 394 { 395 o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; 396 i2++; 397 398 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 399 o2.indent(i2) << 0 << " /* EmptyTable */\n"; 400 401 i2--; 402 o2.indent(i2) << "}"; 403 return; 404 } 405 406 std::vector<unsigned> ModRMDecision; 407 408 switch (dt) { 409 default: 410 llvm_unreachable("Unknown decision type"); 411 case MODRM_ONEENTRY: 412 ModRMDecision.push_back(decision.instructionIDs[0]); 413 break; 414 case MODRM_SPLITRM: 415 ModRMDecision.push_back(decision.instructionIDs[0x00]); 416 ModRMDecision.push_back(decision.instructionIDs[0xc0]); 417 break; 418 case MODRM_SPLITREG: 419 for (unsigned index = 0; index < 64; index += 8) 420 ModRMDecision.push_back(decision.instructionIDs[index]); 421 for (unsigned index = 0xc0; index < 256; index += 8) 422 ModRMDecision.push_back(decision.instructionIDs[index]); 423 break; 424 case MODRM_SPLITMISC: 425 for (unsigned index = 0; index < 64; index += 8) 426 ModRMDecision.push_back(decision.instructionIDs[index]); 427 for (unsigned index = 0xc0; index < 256; ++index) 428 ModRMDecision.push_back(decision.instructionIDs[index]); 429 break; 430 case MODRM_FULL: 431 for (unsigned index = 0; index < 256; ++index) 432 ModRMDecision.push_back(decision.instructionIDs[index]); 433 break; 434 } 435 436 unsigned &EntryNumber = ModRMTable[ModRMDecision]; 437 if (EntryNumber == 0) { 438 EntryNumber = ModRMTableNum; 439 440 ModRMTableNum += ModRMDecision.size(); 441 o1 << "/* Table" << EntryNumber << " */\n"; 442 i1++; 443 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), 444 E = ModRMDecision.end(); I != E; ++I) { 445 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " 446 << InstructionSpecifiers[*I].name << " */\n"; 447 } 448 i1--; 449 } 450 451 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; 452 i2++; 453 454 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; 455 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; 456 457 i2--; 458 o2.indent(i2) << "}"; 459 460 switch (dt) { 461 default: 462 llvm_unreachable("Unknown decision type"); 463 case MODRM_ONEENTRY: 464 sEntryNumber += 1; 465 break; 466 case MODRM_SPLITRM: 467 sEntryNumber += 2; 468 break; 469 case MODRM_SPLITREG: 470 sEntryNumber += 16; 471 break; 472 case MODRM_SPLITMISC: 473 sEntryNumber += 8 + 64; 474 break; 475 case MODRM_FULL: 476 sEntryNumber += 256; 477 break; 478 } 479 480 // We assume that the index can fit into uint16_t. 481 assert(sEntryNumber < 65536U && 482 "Index into ModRMDecision is too large for uint16_t!"); 483 484 ++sTableNumber; 485} 486 487void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, 488 unsigned &i1, unsigned &i2, 489 unsigned &ModRMTableNum, 490 OpcodeDecision &decision) const { 491 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; 492 i2++; 493 o2.indent(i2) << "{" << "\n"; 494 i2++; 495 496 for (unsigned index = 0; index < 256; ++index) { 497 o2.indent(i2); 498 499 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; 500 501 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, 502 decision.modRMDecisions[index]); 503 504 if (index < 255) 505 o2 << ","; 506 507 o2 << "\n"; 508 } 509 510 i2--; 511 o2.indent(i2) << "}" << "\n"; 512 i2--; 513 o2.indent(i2) << "}" << "\n"; 514} 515 516void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, 517 unsigned &i1, unsigned &i2, 518 unsigned &ModRMTableNum, 519 ContextDecision &decision, 520 const char* name) const { 521 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; 522 i2++; 523 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n"; 524 i2++; 525 526 for (unsigned index = 0; index < IC_max; ++index) { 527 o2.indent(i2) << "/* "; 528 o2 << stringForContext((InstructionContext)index); 529 o2 << " */"; 530 o2 << "\n"; 531 532 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, 533 decision.opcodeDecisions[index]); 534 535 if (index + 1 < IC_max) 536 o2 << ", "; 537 } 538 539 i2--; 540 o2.indent(i2) << "}" << "\n"; 541 i2--; 542 o2.indent(i2) << "};" << "\n"; 543} 544 545void DisassemblerTables::emitInstructionInfo(raw_ostream &o, 546 unsigned &i) const { 547 unsigned NumInstructions = InstructionSpecifiers.size(); 548 549 o << "static const struct OperandSpecifier x86OperandSets[][" 550 << X86_MAX_OPERANDS << "] = {\n"; 551 552 typedef std::vector<std::pair<const char *, const char *> > OperandListTy; 553 std::map<OperandListTy, unsigned> OperandSets; 554 555 unsigned OperandSetNum = 0; 556 for (unsigned Index = 0; Index < NumInstructions; ++Index) { 557 OperandListTy OperandList; 558 559 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 560 ++OperandIndex) { 561 const char *Encoding = 562 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] 563 .operands[OperandIndex].encoding); 564 const char *Type = 565 stringForOperandType((OperandType)InstructionSpecifiers[Index] 566 .operands[OperandIndex].type); 567 OperandList.push_back(std::make_pair(Encoding, Type)); 568 } 569 unsigned &N = OperandSets[OperandList]; 570 if (N != 0) continue; 571 572 N = ++OperandSetNum; 573 574 o << " { /* " << (OperandSetNum - 1) << " */\n"; 575 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { 576 o << " { " << OperandList[i].first << ", " 577 << OperandList[i].second << " },\n"; 578 } 579 o << " },\n"; 580 } 581 o << "};" << "\n\n"; 582 583 o.indent(i * 2) << "static const struct InstructionSpecifier "; 584 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; 585 586 i++; 587 588 for (unsigned index = 0; index < NumInstructions; ++index) { 589 o.indent(i * 2) << "{ /* " << index << " */" << "\n"; 590 i++; 591 592 OperandListTy OperandList; 593 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; 594 ++OperandIndex) { 595 const char *Encoding = 596 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] 597 .operands[OperandIndex].encoding); 598 const char *Type = 599 stringForOperandType((OperandType)InstructionSpecifiers[index] 600 .operands[OperandIndex].type); 601 OperandList.push_back(std::make_pair(Encoding, Type)); 602 } 603 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; 604 605 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; 606 o << "\n"; 607 608 i--; 609 o.indent(i * 2) << "}"; 610 611 if (index + 1 < NumInstructions) 612 o << ","; 613 614 o << "\n"; 615 } 616 617 i--; 618 o.indent(i * 2) << "};" << "\n"; 619} 620 621void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { 622 const unsigned int tableSize = 16384; 623 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR 624 "[" << tableSize << "] = {\n"; 625 i++; 626 627 for (unsigned index = 0; index < tableSize; ++index) { 628 o.indent(i * 2); 629 630 if (index & ATTR_EVEX) { 631 o << "IC_EVEX"; 632 if (index & ATTR_EVEXL2) 633 o << "_L2"; 634 else if (index & ATTR_EVEXL) 635 o << "_L"; 636 if (index & ATTR_REXW) 637 o << "_W"; 638 if (index & ATTR_OPSIZE) 639 o << "_OPSIZE"; 640 else if (index & ATTR_XD) 641 o << "_XD"; 642 else if (index & ATTR_XS) 643 o << "_XS"; 644 if (index & ATTR_EVEXKZ) 645 o << "_KZ"; 646 else if (index & ATTR_EVEXK) 647 o << "_K"; 648 if (index & ATTR_EVEXB) 649 o << "_B"; 650 } 651 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 652 o << "IC_VEX_L_W_OPSIZE"; 653 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) 654 o << "IC_VEX_L_W_XD"; 655 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) 656 o << "IC_VEX_L_W_XS"; 657 else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) 658 o << "IC_VEX_L_W"; 659 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) 660 o << "IC_VEX_L_OPSIZE"; 661 else if ((index & ATTR_VEXL) && (index & ATTR_XD)) 662 o << "IC_VEX_L_XD"; 663 else if ((index & ATTR_VEXL) && (index & ATTR_XS)) 664 o << "IC_VEX_L_XS"; 665 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) 666 o << "IC_VEX_W_OPSIZE"; 667 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) 668 o << "IC_VEX_W_XD"; 669 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) 670 o << "IC_VEX_W_XS"; 671 else if (index & ATTR_VEXL) 672 o << "IC_VEX_L"; 673 else if ((index & ATTR_VEX) && (index & ATTR_REXW)) 674 o << "IC_VEX_W"; 675 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) 676 o << "IC_VEX_OPSIZE"; 677 else if ((index & ATTR_VEX) && (index & ATTR_XD)) 678 o << "IC_VEX_XD"; 679 else if ((index & ATTR_VEX) && (index & ATTR_XS)) 680 o << "IC_VEX_XS"; 681 else if (index & ATTR_VEX) 682 o << "IC_VEX"; 683 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) 684 o << "IC_64BIT_REXW_XS"; 685 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) 686 o << "IC_64BIT_REXW_XD"; 687 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && 688 (index & ATTR_OPSIZE)) 689 o << "IC_64BIT_REXW_OPSIZE"; 690 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) 691 o << "IC_64BIT_XD_OPSIZE"; 692 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) 693 o << "IC_64BIT_XS_OPSIZE"; 694 else if ((index & ATTR_64BIT) && (index & ATTR_XS)) 695 o << "IC_64BIT_XS"; 696 else if ((index & ATTR_64BIT) && (index & ATTR_XD)) 697 o << "IC_64BIT_XD"; 698 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) 699 o << "IC_64BIT_OPSIZE"; 700 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) 701 o << "IC_64BIT_ADSIZE"; 702 else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) 703 o << "IC_64BIT_REXW"; 704 else if ((index & ATTR_64BIT)) 705 o << "IC_64BIT"; 706 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) 707 o << "IC_XS_OPSIZE"; 708 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) 709 o << "IC_XD_OPSIZE"; 710 else if (index & ATTR_XS) 711 o << "IC_XS"; 712 else if (index & ATTR_XD) 713 o << "IC_XD"; 714 else if (index & ATTR_OPSIZE) 715 o << "IC_OPSIZE"; 716 else if (index & ATTR_ADSIZE) 717 o << "IC_ADSIZE"; 718 else 719 o << "IC"; 720 721 if (index < tableSize - 1) 722 o << ","; 723 else 724 o << " "; 725 726 o << " /* " << index << " */"; 727 728 o << "\n"; 729 } 730 731 i--; 732 o.indent(i * 2) << "};" << "\n"; 733} 734 735void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, 736 unsigned &i1, unsigned &i2, 737 unsigned &ModRMTableNum) const { 738 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); 739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); 740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); 741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); 742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR); 743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR); 744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR); 745} 746 747void DisassemblerTables::emit(raw_ostream &o) const { 748 unsigned i1 = 0; 749 unsigned i2 = 0; 750 751 std::string s1; 752 std::string s2; 753 754 raw_string_ostream o1(s1); 755 raw_string_ostream o2(s2); 756 757 emitInstructionInfo(o, i2); 758 o << "\n"; 759 760 emitContextTable(o, i2); 761 o << "\n"; 762 763 unsigned ModRMTableNum = 0; 764 765 o << "static const InstrUID modRMTable[] = {\n"; 766 i1++; 767 std::vector<unsigned> EmptyTable(1, 0); 768 ModRMTable[EmptyTable] = ModRMTableNum; 769 ModRMTableNum += EmptyTable.size(); 770 o1 << "/* EmptyTable */\n"; 771 o1.indent(i1 * 2) << "0x0,\n"; 772 i1--; 773 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); 774 775 o << o1.str(); 776 o << " 0x0\n"; 777 o << "};\n"; 778 o << "\n"; 779 o << o2.str(); 780 o << "\n"; 781 o << "\n"; 782} 783 784void DisassemblerTables::setTableFields(ModRMDecision &decision, 785 const ModRMFilter &filter, 786 InstrUID uid, 787 uint8_t opcode) { 788 for (unsigned index = 0; index < 256; ++index) { 789 if (filter.accepts(index)) { 790 if (decision.instructionIDs[index] == uid) 791 continue; 792 793 if (decision.instructionIDs[index] != 0) { 794 InstructionSpecifier &newInfo = 795 InstructionSpecifiers[uid]; 796 InstructionSpecifier &previousInfo = 797 InstructionSpecifiers[decision.instructionIDs[index]]; 798 799 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the 800 // presence of the AdSize prefix. However, the disassembler doesn't 801 // care about that difference in the instruction definition; it 802 // handles 16-bit vs. 32-bit addressing for itself based purely 803 // on the 0x67 prefix and the CPU mode. So there's no need to 804 // disambiguate between them; just let them conflict/coexist. 805 if (previousInfo.name + "_16" == newInfo.name) 806 continue; 807 808 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" || 809 newInfo.name == "XCHG32ar" || 810 newInfo.name == "XCHG32ar64" || 811 newInfo.name == "XCHG64ar")) 812 continue; // special case for XCHG*ar and NOOP 813 814 if (outranks(previousInfo.insnContext, newInfo.insnContext)) 815 continue; 816 817 if (previousInfo.insnContext == newInfo.insnContext) { 818 errs() << "Error: Primary decode conflict: "; 819 errs() << newInfo.name << " would overwrite " << previousInfo.name; 820 errs() << "\n"; 821 errs() << "ModRM " << index << "\n"; 822 errs() << "Opcode " << (uint16_t)opcode << "\n"; 823 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n"; 824 HasConflicts = true; 825 } 826 } 827 828 decision.instructionIDs[index] = uid; 829 } 830 } 831} 832 833void DisassemblerTables::setTableFields(OpcodeType type, 834 InstructionContext insnContext, 835 uint8_t opcode, 836 const ModRMFilter &filter, 837 InstrUID uid, 838 bool is32bit, 839 bool ignoresVEX_L) { 840 ContextDecision &decision = *Tables[type]; 841 842 for (unsigned index = 0; index < IC_max; ++index) { 843 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT)) 844 continue; 845 846 if (inheritsFrom((InstructionContext)index, 847 InstructionSpecifiers[uid].insnContext, ignoresVEX_L)) 848 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode], 849 filter, 850 uid, 851 opcode); 852 } 853} 854