RegisterInfoEmitter.cpp revision 344779
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16239462Sdim#include "CodeGenRegisters.h" 17193323Sed#include "CodeGenTarget.h" 18341825Sdim#include "SequenceToOffsetTable.h" 19314564Sdim#include "Types.h" 20309124Sdim#include "llvm/ADT/ArrayRef.h" 21226633Sdim#include "llvm/ADT/BitVector.h" 22341825Sdim#include "llvm/ADT/STLExtras.h" 23309124Sdim#include "llvm/ADT/SetVector.h" 24309124Sdim#include "llvm/ADT/SmallVector.h" 25309124Sdim#include "llvm/ADT/SparseBitVector.h" 26234982Sdim#include "llvm/ADT/Twine.h" 27309124Sdim#include "llvm/Support/Casting.h" 28327952Sdim#include "llvm/Support/CommandLine.h" 29224145Sdim#include "llvm/Support/Format.h" 30341825Sdim#include "llvm/Support/MachineValueType.h" 31309124Sdim#include "llvm/Support/raw_ostream.h" 32239462Sdim#include "llvm/TableGen/Error.h" 33239462Sdim#include "llvm/TableGen/Record.h" 34309124Sdim#include "llvm/TableGen/SetTheory.h" 35239462Sdim#include "llvm/TableGen/TableGenBackend.h" 36195340Sed#include <algorithm> 37309124Sdim#include <cassert> 38309124Sdim#include <cstddef> 39309124Sdim#include <cstdint> 40309124Sdim#include <deque> 41309124Sdim#include <iterator> 42193323Sed#include <set> 43309124Sdim#include <string> 44239462Sdim#include <vector> 45309124Sdim 46193323Sedusing namespace llvm; 47193323Sed 48327952Sdimcl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 49327952Sdim 50327952Sdimstatic cl::opt<bool> 51327952Sdim RegisterInfoDebug("register-info-debug", cl::init(false), 52327952Sdim cl::desc("Dump register information to help debugging"), 53327952Sdim cl::cat(RegisterInfoCat)); 54327952Sdim 55239462Sdimnamespace { 56309124Sdim 57239462Sdimclass RegisterInfoEmitter { 58327952Sdim CodeGenTarget Target; 59239462Sdim RecordKeeper &Records; 60309124Sdim 61239462Sdimpublic: 62327952Sdim RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 63327952Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 64327952Sdim RegBank.computeDerivedInfo(); 65327952Sdim } 66239462Sdim 67239462Sdim // runEnums - Print out enum values for all of the registers. 68239462Sdim void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 69239462Sdim 70239462Sdim // runMCDesc - Print out MC register descriptions. 71239462Sdim void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 72239462Sdim 73239462Sdim // runTargetHeader - Emit a header fragment for the register info emitter. 74239462Sdim void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 75239462Sdim CodeGenRegBank &Bank); 76239462Sdim 77239462Sdim // runTargetDesc - Output the target register and register file descriptions. 78239462Sdim void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 79239462Sdim CodeGenRegBank &Bank); 80239462Sdim 81239462Sdim // run - Output the register file description. 82239462Sdim void run(raw_ostream &o); 83239462Sdim 84327952Sdim void debugDump(raw_ostream &OS); 85327952Sdim 86239462Sdimprivate: 87280031Sdim void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 88280031Sdim bool isCtor); 89239462Sdim void EmitRegMappingTables(raw_ostream &o, 90280031Sdim const std::deque<CodeGenRegister> &Regs, 91239462Sdim bool isCtor); 92239462Sdim void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 93239462Sdim const std::string &ClassName); 94243830Sdim void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 95243830Sdim const std::string &ClassName); 96280031Sdim void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 97280031Sdim const std::string &ClassName); 98239462Sdim}; 99239462Sdim 100309124Sdim} // end anonymous namespace 101309124Sdim 102193323Sed// runEnums - Print out enum values for all of the registers. 103234982Sdimvoid RegisterInfoEmitter::runEnums(raw_ostream &OS, 104234982Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 105280031Sdim const auto &Registers = Bank.getRegisters(); 106193323Sed 107234982Sdim // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 108234353Sdim assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 109234353Sdim 110321369Sdim StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 111193323Sed 112239462Sdim emitSourceFileHeader("Target Register Enum Values", OS); 113224145Sdim 114224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 115309124Sdim OS << "#undef GET_REGINFO_ENUM\n\n"; 116224145Sdim 117193323Sed OS << "namespace llvm {\n\n"; 118193323Sed 119226633Sdim OS << "class MCRegisterClass;\n" 120314564Sdim << "extern const MCRegisterClass " << Target.getName() 121234353Sdim << "MCRegisterClasses[];\n\n"; 122226633Sdim 123193323Sed if (!Namespace.empty()) 124193323Sed OS << "namespace " << Namespace << " {\n"; 125208599Srdivacky OS << "enum {\n NoRegister,\n"; 126193323Sed 127280031Sdim for (const auto &Reg : Registers) 128280031Sdim OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 129280031Sdim assert(Registers.size() == Registers.back().EnumValue && 130221345Sdim "Register enum value mismatch!"); 131208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 132208599Srdivacky OS << "};\n"; 133193323Sed if (!Namespace.empty()) 134309124Sdim OS << "} // end namespace " << Namespace << "\n"; 135208599Srdivacky 136280031Sdim const auto &RegisterClasses = Bank.getRegClasses(); 137224145Sdim if (!RegisterClasses.empty()) { 138234353Sdim 139234353Sdim // RegisterClass enums are stored as uint16_t in the tables. 140234353Sdim assert(RegisterClasses.size() <= 0xffff && 141234353Sdim "Too many register classes to fit in tables"); 142234353Sdim 143309124Sdim OS << "\n// Register classes\n\n"; 144208599Srdivacky if (!Namespace.empty()) 145208599Srdivacky OS << "namespace " << Namespace << " {\n"; 146224145Sdim OS << "enum {\n"; 147280031Sdim for (const auto &RC : RegisterClasses) 148280031Sdim OS << " " << RC.getName() << "RegClassID" 149280031Sdim << " = " << RC.EnumValue << ",\n"; 150224145Sdim OS << "\n };\n"; 151224145Sdim if (!Namespace.empty()) 152309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 153224145Sdim } 154224145Sdim 155261991Sdim const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 156224145Sdim // If the only definition is the default NoRegAltName, we don't need to 157224145Sdim // emit anything. 158224145Sdim if (RegAltNameIndices.size() > 1) { 159309124Sdim OS << "\n// Register alternate name indices\n\n"; 160224145Sdim if (!Namespace.empty()) 161224145Sdim OS << "namespace " << Namespace << " {\n"; 162224145Sdim OS << "enum {\n"; 163224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 164224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 165224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 166208599Srdivacky OS << "};\n"; 167208599Srdivacky if (!Namespace.empty()) 168309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 169208599Srdivacky } 170224145Sdim 171280031Sdim auto &SubRegIndices = Bank.getSubRegIndices(); 172234353Sdim if (!SubRegIndices.empty()) { 173309124Sdim OS << "\n// Subregister indices\n\n"; 174280031Sdim std::string Namespace = SubRegIndices.front().getNamespace(); 175234353Sdim if (!Namespace.empty()) 176234353Sdim OS << "namespace " << Namespace << " {\n"; 177234353Sdim OS << "enum {\n NoSubRegister,\n"; 178280031Sdim unsigned i = 0; 179280031Sdim for (const auto &Idx : SubRegIndices) 180280031Sdim OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 181239462Sdim OS << " NUM_TARGET_SUBREGS\n};\n"; 182234353Sdim if (!Namespace.empty()) 183309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 184234353Sdim } 185224145Sdim 186309124Sdim OS << "} // end namespace llvm\n\n"; 187224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 188193323Sed} 189193323Sed 190280031Sdimstatic void printInt(raw_ostream &OS, int Val) { 191280031Sdim OS << Val; 192280031Sdim} 193280031Sdim 194234353Sdimvoid RegisterInfoEmitter:: 195234353SdimEmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 196234353Sdim const std::string &ClassName) { 197234353Sdim unsigned NumRCs = RegBank.getRegClasses().size(); 198234353Sdim unsigned NumSets = RegBank.getNumRegPressureSets(); 199234353Sdim 200234353Sdim OS << "/// Get the weight in units of pressure for this register class.\n" 201234353Sdim << "const RegClassWeight &" << ClassName << "::\n" 202234353Sdim << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 203234353Sdim << " static const RegClassWeight RCWeightTable[] = {\n"; 204280031Sdim for (const auto &RC : RegBank.getRegClasses()) { 205288943Sdim const CodeGenRegister::Vec &Regs = RC.getMembers(); 206341825Sdim if (Regs.empty() || RC.Artificial) 207234353Sdim OS << " {0, 0"; 208234353Sdim else { 209234353Sdim std::vector<unsigned> RegUnits; 210341825Sdim RC.buildRegUnitSet(RegBank, RegUnits); 211234353Sdim OS << " {" << (*Regs.begin())->getWeight(RegBank) 212234353Sdim << ", " << RegBank.getRegUnitSetWeight(RegUnits); 213234353Sdim } 214234353Sdim OS << "}, \t// " << RC.getName() << "\n"; 215234353Sdim } 216280031Sdim OS << " };\n" 217234353Sdim << " return RCWeightTable[RC->getID()];\n" 218234353Sdim << "}\n\n"; 219234353Sdim 220249423Sdim // Reasonable targets (not ARMv7) have unit weight for all units, so don't 221249423Sdim // bother generating a table. 222249423Sdim bool RegUnitsHaveUnitWeight = true; 223249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 224249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 225249423Sdim if (RegBank.getRegUnit(UnitIdx).Weight > 1) 226249423Sdim RegUnitsHaveUnitWeight = false; 227249423Sdim } 228249423Sdim OS << "/// Get the weight in units of pressure for this register unit.\n" 229249423Sdim << "unsigned " << ClassName << "::\n" 230249423Sdim << "getRegUnitWeight(unsigned RegUnit) const {\n" 231249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 232249423Sdim << " && \"invalid register unit\");\n"; 233249423Sdim if (!RegUnitsHaveUnitWeight) { 234249423Sdim OS << " static const uint8_t RUWeightTable[] = {\n "; 235249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 236249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 237249423Sdim const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 238249423Sdim assert(RU.Weight < 256 && "RegUnit too heavy"); 239249423Sdim OS << RU.Weight << ", "; 240249423Sdim } 241280031Sdim OS << "};\n" 242249423Sdim << " return RUWeightTable[RegUnit];\n"; 243249423Sdim } 244249423Sdim else { 245249423Sdim OS << " // All register units have unit weight.\n" 246249423Sdim << " return 1;\n"; 247249423Sdim } 248249423Sdim OS << "}\n\n"; 249249423Sdim 250234353Sdim OS << "\n" 251234353Sdim << "// Get the number of dimensions of register pressure.\n" 252234353Sdim << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 253234353Sdim << " return " << NumSets << ";\n}\n\n"; 254234353Sdim 255239462Sdim OS << "// Get the name of this register unit pressure set.\n" 256239462Sdim << "const char *" << ClassName << "::\n" 257239462Sdim << "getRegPressureSetName(unsigned Idx) const {\n" 258288943Sdim << " static const char *const PressureNameTable[] = {\n"; 259280031Sdim unsigned MaxRegUnitWeight = 0; 260239462Sdim for (unsigned i = 0; i < NumSets; ++i ) { 261280031Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 262280031Sdim MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 263280031Sdim OS << " \"" << RegUnits.Name << "\",\n"; 264239462Sdim } 265296417Sdim OS << " };\n" 266239462Sdim << " return PressureNameTable[Idx];\n" 267239462Sdim << "}\n\n"; 268239462Sdim 269234353Sdim OS << "// Get the register unit pressure limit for this dimension.\n" 270234353Sdim << "// This limit must be adjusted dynamically for reserved registers.\n" 271234353Sdim << "unsigned " << ClassName << "::\n" 272314564Sdim << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 273314564Sdim "{\n" 274314564Sdim << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 275280031Sdim << " PressureLimitTable[] = {\n"; 276234353Sdim for (unsigned i = 0; i < NumSets; ++i ) { 277261991Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 278261991Sdim OS << " " << RegUnits.Weight << ", \t// " << i << ": " 279261991Sdim << RegUnits.Name << "\n"; 280234353Sdim } 281280031Sdim OS << " };\n" 282234353Sdim << " return PressureLimitTable[Idx];\n" 283234353Sdim << "}\n\n"; 284234353Sdim 285280031Sdim SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 286280031Sdim 287249423Sdim // This table may be larger than NumRCs if some register units needed a list 288249423Sdim // of unit sets that did not correspond to a register class. 289249423Sdim unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 290280031Sdim std::vector<std::vector<int>> PSets(NumRCUnitSets); 291280031Sdim 292280031Sdim for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 293234353Sdim ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 294280031Sdim PSets[i].reserve(PSetIDs.size()); 295234353Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 296234353Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 297280031Sdim PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 298261991Sdim } 299344779Sdim llvm::sort(PSets[i]); 300280031Sdim PSetsSeqs.add(PSets[i]); 301234353Sdim } 302249423Sdim 303280031Sdim PSetsSeqs.layout(); 304280031Sdim 305280031Sdim OS << "/// Table of pressure sets per register class or unit.\n" 306280031Sdim << "static const int RCSetsTable[] = {\n"; 307280031Sdim PSetsSeqs.emit(OS, printInt, "-1"); 308280031Sdim OS << "};\n\n"; 309280031Sdim 310249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 311249423Sdim << "register class.\n" 312249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 313249423Sdim << "const int* " << ClassName << "::\n" 314249423Sdim << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 315314564Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 316280031Sdim << " RCSetStartTable[] = {\n "; 317234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 318280031Sdim OS << PSetsSeqs.get(PSets[i]) << ","; 319234353Sdim } 320280031Sdim OS << "};\n" 321280031Sdim << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 322234353Sdim << "}\n\n"; 323249423Sdim 324249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 325249423Sdim << "register unit.\n" 326249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 327249423Sdim << "const int* " << ClassName << "::\n" 328249423Sdim << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 329249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 330249423Sdim << " && \"invalid register unit\");\n"; 331314564Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 332280031Sdim << " RUSetStartTable[] = {\n "; 333249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 334249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 335280031Sdim OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 336280031Sdim << ","; 337249423Sdim } 338280031Sdim OS << "};\n" 339280031Sdim << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 340249423Sdim << "}\n\n"; 341234353Sdim} 342234353Sdim 343344779Sdimusing DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 344344779Sdimusing DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 345344779Sdim 346344779Sdimvoid finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 347344779Sdim // Sort and unique to get a map-like vector. We want the last assignment to 348344779Sdim // match previous behaviour. 349344779Sdim std::stable_sort(DwarfRegNums.begin(), DwarfRegNums.end(), 350344779Sdim on_first<LessRecordRegister>()); 351344779Sdim // Warn about duplicate assignments. 352344779Sdim const Record *LastSeenReg = nullptr; 353344779Sdim for (const auto &X : DwarfRegNums) { 354344779Sdim const auto &Reg = X.first; 355344779Sdim // The only way LessRecordRegister can return equal is if they're the same 356344779Sdim // string. Use simple equality instead. 357344779Sdim if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 358344779Sdim PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 359344779Sdim getQualifiedName(Reg) + 360344779Sdim "specified multiple times"); 361344779Sdim LastSeenReg = Reg; 362344779Sdim } 363344779Sdim auto Last = std::unique( 364344779Sdim DwarfRegNums.begin(), DwarfRegNums.end(), 365344779Sdim [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 366344779Sdim return A.first->getName() == B.first->getName(); 367344779Sdim }); 368344779Sdim DwarfRegNums.erase(Last, DwarfRegNums.end()); 369344779Sdim} 370344779Sdim 371280031Sdimvoid RegisterInfoEmitter::EmitRegMappingTables( 372280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 373226633Sdim // Collect all information about dwarf register numbers 374344779Sdim DwarfRegNumsVecTy DwarfRegNums; 375226633Sdim 376226633Sdim // First, just pull all provided information to the map 377226633Sdim unsigned maxLength = 0; 378280031Sdim for (auto &RE : Regs) { 379280031Sdim Record *Reg = RE.TheDef; 380226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 381226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 382344779Sdim DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 383226633Sdim } 384344779Sdim finalizeDwarfRegNumsKeys(DwarfRegNums); 385226633Sdim 386226633Sdim if (!maxLength) 387226633Sdim return; 388226633Sdim 389226633Sdim // Now we know maximal length of number list. Append -1's, where needed 390344779Sdim for (DwarfRegNumsVecTy::iterator I = DwarfRegNums.begin(), 391344779Sdim E = DwarfRegNums.end(); 392344779Sdim I != E; ++I) 393226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 394226633Sdim I->second.push_back(-1); 395226633Sdim 396321369Sdim StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 397234353Sdim 398234353Sdim OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 399234353Sdim 400226633Sdim // Emit reverse information about the dwarf register numbers. 401226633Sdim for (unsigned j = 0; j < 2; ++j) { 402234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 403234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 404234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 405234353Sdim OS << i << "Dwarf2L[]"; 406234353Sdim 407234353Sdim if (!isCtor) { 408234353Sdim OS << " = {\n"; 409234353Sdim 410234353Sdim // Store the mapping sorted by the LLVM reg num so lookup can be done 411234353Sdim // with a binary search. 412234353Sdim std::map<uint64_t, Record*> Dwarf2LMap; 413344779Sdim for (DwarfRegNumsVecTy::iterator 414234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 415234353Sdim int DwarfRegNo = I->second[i]; 416234353Sdim if (DwarfRegNo < 0) 417234353Sdim continue; 418234353Sdim Dwarf2LMap[DwarfRegNo] = I->first; 419234353Sdim } 420234353Sdim 421234353Sdim for (std::map<uint64_t, Record*>::iterator 422234353Sdim I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 423234353Sdim OS << " { " << I->first << "U, " << getQualifiedName(I->second) 424234353Sdim << " },\n"; 425234353Sdim 426234353Sdim OS << "};\n"; 427234353Sdim } else { 428234353Sdim OS << ";\n"; 429234353Sdim } 430234353Sdim 431234353Sdim // We have to store the size in a const global, it's used in multiple 432234353Sdim // places. 433234353Sdim OS << "extern const unsigned " << Namespace 434234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 435234353Sdim if (!isCtor) 436280031Sdim OS << " = array_lengthof(" << Namespace 437234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 438280031Sdim << "Dwarf2L);\n\n"; 439234353Sdim else 440234353Sdim OS << ";\n\n"; 441234353Sdim } 442234353Sdim } 443234353Sdim 444280031Sdim for (auto &RE : Regs) { 445280031Sdim Record *Reg = RE.TheDef; 446234353Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 447234353Sdim if (!V || !V->getValue()) 448234353Sdim continue; 449234353Sdim 450243830Sdim DefInit *DI = cast<DefInit>(V->getValue()); 451234353Sdim Record *Alias = DI->getDef(); 452344779Sdim const auto &AliasIter = 453344779Sdim std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Alias, 454344779Sdim [](const DwarfRegNumsMapPair &A, const Record *B) { 455344779Sdim return LessRecordRegister()(A.first, B); 456344779Sdim }); 457344779Sdim assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 458344779Sdim "Expected Alias to be present in map"); 459344779Sdim const auto &RegIter = 460344779Sdim std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Reg, 461344779Sdim [](const DwarfRegNumsMapPair &A, const Record *B) { 462344779Sdim return LessRecordRegister()(A.first, B); 463344779Sdim }); 464344779Sdim assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 465344779Sdim "Expected Reg to be present in map"); 466344779Sdim RegIter->second = AliasIter->second; 467234353Sdim } 468234353Sdim 469234353Sdim // Emit information about the dwarf register numbers. 470234353Sdim for (unsigned j = 0; j < 2; ++j) { 471234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 472234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 473234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 474234353Sdim OS << i << "L2Dwarf[]"; 475234353Sdim if (!isCtor) { 476234353Sdim OS << " = {\n"; 477234353Sdim // Store the mapping sorted by the Dwarf reg num so lookup can be done 478234353Sdim // with a binary search. 479344779Sdim for (DwarfRegNumsVecTy::iterator 480234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 481234353Sdim int RegNo = I->second[i]; 482234353Sdim if (RegNo == -1) // -1 is the default value, don't emit a mapping. 483234353Sdim continue; 484234353Sdim 485234353Sdim OS << " { " << getQualifiedName(I->first) << ", " << RegNo 486234353Sdim << "U },\n"; 487234353Sdim } 488234353Sdim OS << "};\n"; 489234353Sdim } else { 490234353Sdim OS << ";\n"; 491234353Sdim } 492234353Sdim 493234353Sdim // We have to store the size in a const global, it's used in multiple 494234353Sdim // places. 495234353Sdim OS << "extern const unsigned " << Namespace 496234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 497234353Sdim if (!isCtor) 498280031Sdim OS << " = array_lengthof(" << Namespace 499280031Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 500234353Sdim else 501234353Sdim OS << ";\n\n"; 502234353Sdim } 503234353Sdim } 504234353Sdim} 505234353Sdim 506280031Sdimvoid RegisterInfoEmitter::EmitRegMapping( 507280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 508234353Sdim // Emit the initializer so the tables from EmitRegMappingTables get wired up 509234353Sdim // to the MCRegisterInfo object. 510234353Sdim unsigned maxLength = 0; 511280031Sdim for (auto &RE : Regs) { 512280031Sdim Record *Reg = RE.TheDef; 513234353Sdim maxLength = std::max((size_t)maxLength, 514234353Sdim Reg->getValueAsListOfInts("DwarfNumbers").size()); 515234353Sdim } 516234353Sdim 517234353Sdim if (!maxLength) 518234353Sdim return; 519234353Sdim 520321369Sdim StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 521234353Sdim 522234353Sdim // Emit reverse information about the dwarf register numbers. 523234353Sdim for (unsigned j = 0; j < 2; ++j) { 524226633Sdim OS << " switch ("; 525226633Sdim if (j == 0) 526226633Sdim OS << "DwarfFlavour"; 527226633Sdim else 528226633Sdim OS << "EHFlavour"; 529226633Sdim OS << ") {\n" 530226633Sdim << " default:\n" 531234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 532226633Sdim 533226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 534226633Sdim OS << " case " << i << ":\n"; 535234353Sdim OS << " "; 536234353Sdim if (!isCtor) 537234353Sdim OS << "RI->"; 538234353Sdim std::string Tmp; 539234353Sdim raw_string_ostream(Tmp) << Namespace 540234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 541234353Sdim << "Dwarf2L"; 542234353Sdim OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 543234353Sdim if (j == 0) 544226633Sdim OS << "false"; 545226633Sdim else 546226633Sdim OS << "true"; 547234353Sdim OS << ");\n"; 548226633Sdim OS << " break;\n"; 549226633Sdim } 550226633Sdim OS << " }\n"; 551226633Sdim } 552226633Sdim 553226633Sdim // Emit information about the dwarf register numbers. 554226633Sdim for (unsigned j = 0; j < 2; ++j) { 555226633Sdim OS << " switch ("; 556226633Sdim if (j == 0) 557226633Sdim OS << "DwarfFlavour"; 558226633Sdim else 559226633Sdim OS << "EHFlavour"; 560226633Sdim OS << ") {\n" 561226633Sdim << " default:\n" 562234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 563226633Sdim 564226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 565226633Sdim OS << " case " << i << ":\n"; 566234353Sdim OS << " "; 567234353Sdim if (!isCtor) 568234353Sdim OS << "RI->"; 569234353Sdim std::string Tmp; 570234353Sdim raw_string_ostream(Tmp) << Namespace 571234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 572234353Sdim << "L2Dwarf"; 573234353Sdim OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 574234353Sdim if (j == 0) 575226633Sdim OS << "false"; 576226633Sdim else 577226633Sdim OS << "true"; 578234353Sdim OS << ");\n"; 579226633Sdim OS << " break;\n"; 580226633Sdim } 581226633Sdim OS << " }\n"; 582226633Sdim } 583226633Sdim} 584226633Sdim 585226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 586226633Sdim// Width is the number of bits per hex number. 587226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 588226633Sdim const BitVector &Bits, 589226633Sdim unsigned Width) { 590226633Sdim assert(Width <= 32 && "Width too large"); 591226633Sdim unsigned Digits = (Width + 3) / 4; 592226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 593226633Sdim unsigned Value = 0; 594226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 595226633Sdim Value |= Bits.test(i + j) << j; 596226633Sdim OS << format("0x%0*x, ", Digits, Value); 597226633Sdim } 598226633Sdim} 599226633Sdim 600226633Sdim// Helper to emit a set of bits into a constant byte array. 601226633Sdimclass BitVectorEmitter { 602226633Sdim BitVector Values; 603226633Sdimpublic: 604226633Sdim void add(unsigned v) { 605226633Sdim if (v >= Values.size()) 606226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 607226633Sdim Values[v] = true; 608226633Sdim } 609226633Sdim 610226633Sdim void print(raw_ostream &OS) { 611226633Sdim printBitVectorAsHex(OS, Values, 8); 612226633Sdim } 613226633Sdim}; 614226633Sdim 615234353Sdimstatic void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 616234353Sdim OS << getEnumName(VT); 617234353Sdim} 618234353Sdim 619239462Sdimstatic void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 620239462Sdim OS << Idx->EnumValue; 621239462Sdim} 622239462Sdim 623239462Sdim// Differentially encoded register and regunit lists allow for better 624239462Sdim// compression on regular register banks. The sequence is computed from the 625239462Sdim// differential list as: 626224145Sdim// 627239462Sdim// out[0] = InitVal; 628239462Sdim// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 629239462Sdim// 630239462Sdim// The initial value depends on the specific list. The list is terminated by a 631239462Sdim// 0 differential which means we can't encode repeated elements. 632239462Sdim 633239462Sdimtypedef SmallVector<uint16_t, 4> DiffVec; 634314564Sdimtypedef SmallVector<LaneBitmask, 4> MaskVec; 635239462Sdim 636239462Sdim// Differentially encode a sequence of numbers into V. The starting value and 637239462Sdim// terminating 0 are not added to V, so it will have the same size as List. 638239462Sdimstatic 639288943SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 640239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 641239462Sdim uint16_t Val = uint16_t(InitVal); 642288943Sdim 643288943Sdim for (uint16_t Cur : List) { 644239462Sdim V.push_back(Cur - Val); 645239462Sdim Val = Cur; 646239462Sdim } 647239462Sdim return V; 648239462Sdim} 649239462Sdim 650239462Sdimtemplate<typename Iter> 651239462Sdimstatic 652239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 653239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 654239462Sdim uint16_t Val = uint16_t(InitVal); 655239462Sdim for (Iter I = Begin; I != End; ++I) { 656239462Sdim uint16_t Cur = (*I)->EnumValue; 657239462Sdim V.push_back(Cur - Val); 658239462Sdim Val = Cur; 659239462Sdim } 660239462Sdim return V; 661239462Sdim} 662239462Sdim 663239462Sdimstatic void printDiff16(raw_ostream &OS, uint16_t Val) { 664239462Sdim OS << Val; 665239462Sdim} 666239462Sdim 667314564Sdimstatic void printMask(raw_ostream &OS, LaneBitmask Val) { 668314564Sdim OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 669280031Sdim} 670280031Sdim 671243830Sdim// Try to combine Idx's compose map into Vec if it is compatible. 672243830Sdim// Return false if it's not possible. 673243830Sdimstatic bool combine(const CodeGenSubRegIndex *Idx, 674243830Sdim SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 675243830Sdim const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 676288943Sdim for (const auto &I : Map) { 677288943Sdim CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 678288943Sdim if (Entry && Entry != I.second) 679243830Sdim return false; 680243830Sdim } 681243830Sdim 682243830Sdim // All entries are compatible. Make it so. 683288943Sdim for (const auto &I : Map) { 684288943Sdim auto *&Entry = Vec[I.first->EnumValue - 1]; 685288943Sdim assert((!Entry || Entry == I.second) && 686288943Sdim "Expected EnumValue to be unique"); 687288943Sdim Entry = I.second; 688288943Sdim } 689243830Sdim return true; 690243830Sdim} 691243830Sdim 692243830Sdimvoid 693243830SdimRegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 694243830Sdim CodeGenRegBank &RegBank, 695243830Sdim const std::string &ClName) { 696280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 697243830Sdim OS << "unsigned " << ClName 698243830Sdim << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 699243830Sdim 700243830Sdim // Many sub-register indexes are composition-compatible, meaning that 701243830Sdim // 702243830Sdim // compose(IdxA, IdxB) == compose(IdxA', IdxB) 703243830Sdim // 704243830Sdim // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 705243830Sdim // The illegal entries can be use as wildcards to compress the table further. 706243830Sdim 707243830Sdim // Map each Sub-register index to a compatible table row. 708243830Sdim SmallVector<unsigned, 4> RowMap; 709243830Sdim SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 710243830Sdim 711280031Sdim auto SubRegIndicesSize = 712280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 713280031Sdim for (const auto &Idx : SubRegIndices) { 714243830Sdim unsigned Found = ~0u; 715243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 716280031Sdim if (combine(&Idx, Rows[r])) { 717243830Sdim Found = r; 718243830Sdim break; 719243830Sdim } 720243830Sdim } 721243830Sdim if (Found == ~0u) { 722243830Sdim Found = Rows.size(); 723243830Sdim Rows.resize(Found + 1); 724280031Sdim Rows.back().resize(SubRegIndicesSize); 725280031Sdim combine(&Idx, Rows.back()); 726243830Sdim } 727243830Sdim RowMap.push_back(Found); 728243830Sdim } 729243830Sdim 730243830Sdim // Output the row map if there is multiple rows. 731243830Sdim if (Rows.size() > 1) { 732314564Sdim OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 733314564Sdim << " RowMap[" << SubRegIndicesSize << "] = {\n "; 734280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 735243830Sdim OS << RowMap[i] << ", "; 736243830Sdim OS << "\n };\n"; 737243830Sdim } 738243830Sdim 739243830Sdim // Output the rows. 740314564Sdim OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 741280031Sdim << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 742243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 743243830Sdim OS << " { "; 744280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 745243830Sdim if (Rows[r][i]) 746243830Sdim OS << Rows[r][i]->EnumValue << ", "; 747243830Sdim else 748243830Sdim OS << "0, "; 749243830Sdim OS << "},\n"; 750243830Sdim } 751243830Sdim OS << " };\n\n"; 752243830Sdim 753280031Sdim OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 754280031Sdim << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 755243830Sdim if (Rows.size() > 1) 756243830Sdim OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 757243830Sdim else 758243830Sdim OS << " return Rows[0][IdxB];\n"; 759243830Sdim OS << "}\n\n"; 760243830Sdim} 761243830Sdim 762280031Sdimvoid 763280031SdimRegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 764280031Sdim CodeGenRegBank &RegBank, 765280031Sdim const std::string &ClName) { 766280031Sdim // See the comments in computeSubRegLaneMasks() for our goal here. 767280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 768280031Sdim 769280031Sdim // Create a list of Mask+Rotate operations, with equivalent entries merged. 770280031Sdim SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 771280031Sdim SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 772280031Sdim for (const auto &Idx : SubRegIndices) { 773280031Sdim const SmallVector<MaskRolPair, 1> &IdxSequence 774280031Sdim = Idx.CompositionLaneMaskTransform; 775280031Sdim 776280031Sdim unsigned Found = ~0u; 777280031Sdim unsigned SIdx = 0; 778280031Sdim unsigned NextSIdx; 779280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 780280031Sdim SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 781280031Sdim NextSIdx = SIdx + Sequence.size() + 1; 782288943Sdim if (Sequence == IdxSequence) { 783280031Sdim Found = SIdx; 784280031Sdim break; 785280031Sdim } 786280031Sdim } 787280031Sdim if (Found == ~0u) { 788280031Sdim Sequences.push_back(IdxSequence); 789280031Sdim Found = SIdx; 790280031Sdim } 791280031Sdim SubReg2SequenceIndexMap.push_back(Found); 792280031Sdim } 793280031Sdim 794280031Sdim OS << " struct MaskRolOp {\n" 795314564Sdim " LaneBitmask Mask;\n" 796280031Sdim " uint8_t RotateLeft;\n" 797280031Sdim " };\n" 798309124Sdim " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 799280031Sdim unsigned Idx = 0; 800280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 801280031Sdim OS << " "; 802280031Sdim const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 803280031Sdim for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 804280031Sdim const MaskRolPair &P = Sequence[p]; 805314564Sdim printMask(OS << "{ ", P.Mask); 806314564Sdim OS << format(", %2u }, ", P.RotateLeft); 807280031Sdim } 808314564Sdim OS << "{ LaneBitmask::getNone(), 0 }"; 809280031Sdim if (s+1 != se) 810280031Sdim OS << ", "; 811280031Sdim OS << " // Sequence " << Idx << "\n"; 812280031Sdim Idx += Sequence.size() + 1; 813280031Sdim } 814280031Sdim OS << " };\n" 815288943Sdim " static const MaskRolOp *const CompositeSequences[] = {\n"; 816280031Sdim for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 817280031Sdim OS << " "; 818280031Sdim unsigned Idx = SubReg2SequenceIndexMap[i]; 819309124Sdim OS << format("&LaneMaskComposeSequences[%u]", Idx); 820280031Sdim if (i+1 != e) 821280031Sdim OS << ","; 822280031Sdim OS << " // to " << SubRegIndices[i].getName() << "\n"; 823280031Sdim } 824280031Sdim OS << " };\n\n"; 825280031Sdim 826309124Sdim OS << "LaneBitmask " << ClName 827309124Sdim << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 828309124Sdim " const {\n" 829309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 830280031Sdim << " && \"Subregister index out of bounds\");\n" 831314564Sdim " LaneBitmask Result;\n" 832314564Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 833314564Sdim " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 834314564Sdim " if (unsigned S = Ops->RotateLeft)\n" 835314564Sdim " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 836314564Sdim " else\n" 837314564Sdim " Result |= LaneBitmask(M);\n" 838280031Sdim " }\n" 839280031Sdim " return Result;\n" 840309124Sdim "}\n\n"; 841309124Sdim 842309124Sdim OS << "LaneBitmask " << ClName 843309124Sdim << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 844309124Sdim " LaneBitmask LaneMask) const {\n" 845309124Sdim " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 846309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 847309124Sdim << " && \"Subregister index out of bounds\");\n" 848314564Sdim " LaneBitmask Result;\n" 849314564Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 850314564Sdim " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 851314564Sdim " if (unsigned S = Ops->RotateLeft)\n" 852314564Sdim " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 853314564Sdim " else\n" 854314564Sdim " Result |= LaneBitmask(M);\n" 855309124Sdim " }\n" 856309124Sdim " return Result;\n" 857309124Sdim "}\n\n"; 858280031Sdim} 859280031Sdim 860239462Sdim// 861224145Sdim// runMCDesc - Print out MC register descriptions. 862224145Sdim// 863224145Sdimvoid 864224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 865224145Sdim CodeGenRegBank &RegBank) { 866239462Sdim emitSourceFileHeader("MC Register Information", OS); 867224145Sdim 868224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 869309124Sdim OS << "#undef GET_REGINFO_MC_DESC\n\n"; 870224145Sdim 871280031Sdim const auto &Regs = RegBank.getRegisters(); 872224145Sdim 873280031Sdim auto &SubRegIndices = RegBank.getSubRegIndices(); 874261991Sdim // The lists of sub-registers and super-registers go in the same array. That 875261991Sdim // allows us to share suffixes. 876234353Sdim typedef std::vector<const CodeGenRegister*> RegVec; 877224145Sdim 878239462Sdim // Differentially encoded lists. 879239462Sdim SequenceToOffsetTable<DiffVec> DiffSeqs; 880239462Sdim SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 881239462Sdim SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 882239462Sdim SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 883239462Sdim SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 884239462Sdim 885280031Sdim // List of lane masks accompanying register unit sequences. 886280031Sdim SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 887280031Sdim SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 888280031Sdim 889239462Sdim // Keep track of sub-register names as well. These are not differentially 890239462Sdim // encoded. 891239462Sdim typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 892288943Sdim SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs; 893239462Sdim SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 894239462Sdim 895239462Sdim SequenceToOffsetTable<std::string> RegStrings; 896239462Sdim 897234353Sdim // Precompute register lists for the SequenceToOffsetTable. 898280031Sdim unsigned i = 0; 899280031Sdim for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 900280031Sdim const auto &Reg = *I; 901280031Sdim RegStrings.add(Reg.getName()); 902224145Sdim 903234353Sdim // Compute the ordered sub-register list. 904234353Sdim SetVector<const CodeGenRegister*> SR; 905280031Sdim Reg.addSubRegsPreOrder(SR, RegBank); 906280031Sdim diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 907239462Sdim DiffSeqs.add(SubRegLists[i]); 908224145Sdim 909239462Sdim // Compute the corresponding sub-register indexes. 910239462Sdim SubRegIdxVec &SRIs = SubRegIdxLists[i]; 911327952Sdim for (const CodeGenRegister *S : SR) 912327952Sdim SRIs.push_back(Reg.getSubRegIndex(S)); 913239462Sdim SubRegIdxSeqs.add(SRIs); 914239462Sdim 915234353Sdim // Super-registers are already computed. 916280031Sdim const RegVec &SuperRegList = Reg.getSuperRegs(); 917280031Sdim diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 918280031Sdim SuperRegList.end()); 919239462Sdim DiffSeqs.add(SuperRegLists[i]); 920224145Sdim 921239462Sdim // Differentially encode the register unit list, seeded by register number. 922239462Sdim // First compute a scale factor that allows more diff-lists to be reused: 923239462Sdim // 924239462Sdim // D0 -> (S0, S1) 925239462Sdim // D1 -> (S2, S3) 926239462Sdim // 927239462Sdim // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 928239462Sdim // value for the differential decoder is the register number multiplied by 929239462Sdim // the scale. 930239462Sdim // 931239462Sdim // Check the neighboring registers for arithmetic progressions. 932239462Sdim unsigned ScaleA = ~0u, ScaleB = ~0u; 933288943Sdim SparseBitVector<> RUs = Reg.getNativeRegUnits(); 934280031Sdim if (I != Regs.begin() && 935288943Sdim std::prev(I)->getNativeRegUnits().count() == RUs.count()) 936288943Sdim ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 937280031Sdim if (std::next(I) != Regs.end() && 938288943Sdim std::next(I)->getNativeRegUnits().count() == RUs.count()) 939288943Sdim ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 940239462Sdim unsigned Scale = std::min(ScaleB, ScaleA); 941239462Sdim // Default the scale to 0 if it can't be encoded in 4 bits. 942239462Sdim if (Scale >= 16) 943239462Sdim Scale = 0; 944239462Sdim RegUnitInitScale[i] = Scale; 945280031Sdim DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 946280031Sdim 947280031Sdim const auto &RUMasks = Reg.getRegUnitLaneMasks(); 948280031Sdim MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 949280031Sdim assert(LaneMaskVec.empty()); 950280031Sdim LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 951280031Sdim // Terminator mask should not be used inside of the list. 952280031Sdim#ifndef NDEBUG 953314564Sdim for (LaneBitmask M : LaneMaskVec) { 954314564Sdim assert(!M.all() && "terminator mask should not be part of the list"); 955280031Sdim } 956280031Sdim#endif 957280031Sdim LaneMaskSeqs.add(LaneMaskVec); 958224145Sdim } 959224145Sdim 960234353Sdim // Compute the final layout of the sequence table. 961239462Sdim DiffSeqs.layout(); 962280031Sdim LaneMaskSeqs.layout(); 963239462Sdim SubRegIdxSeqs.layout(); 964234353Sdim 965234353Sdim OS << "namespace llvm {\n\n"; 966234353Sdim 967234353Sdim const std::string &TargetName = Target.getName(); 968234353Sdim 969239462Sdim // Emit the shared table of differential lists. 970249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 971239462Sdim DiffSeqs.emit(OS, printDiff16); 972234353Sdim OS << "};\n\n"; 973234353Sdim 974280031Sdim // Emit the shared table of regunit lane mask sequences. 975314564Sdim OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 976314564Sdim LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 977280031Sdim OS << "};\n\n"; 978280031Sdim 979239462Sdim // Emit the table of sub-register indexes. 980239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 981239462Sdim SubRegIdxSeqs.emit(OS, printSubRegIndex); 982239462Sdim OS << "};\n\n"; 983239462Sdim 984261991Sdim // Emit the table of sub-register index sizes. 985261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 986261991Sdim << TargetName << "SubRegIdxRanges[] = {\n"; 987261991Sdim OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 988280031Sdim for (const auto &Idx : SubRegIndices) { 989280031Sdim OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 990280031Sdim << Idx.getName() << "\n"; 991261991Sdim } 992261991Sdim OS << "};\n\n"; 993261991Sdim 994239462Sdim // Emit the string table. 995239462Sdim RegStrings.layout(); 996239462Sdim OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 997239462Sdim RegStrings.emit(OS, printChar); 998239462Sdim OS << "};\n\n"; 999239462Sdim 1000234353Sdim OS << "extern const MCRegisterDesc " << TargetName 1001224145Sdim << "RegDesc[] = { // Descriptors\n"; 1002280031Sdim OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1003224145Sdim 1004234353Sdim // Emit the register descriptors now. 1005280031Sdim i = 0; 1006280031Sdim for (const auto &Reg : Regs) { 1007280031Sdim OS << " { " << RegStrings.get(Reg.getName()) << ", " 1008280031Sdim << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1009280031Sdim << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1010280031Sdim << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1011280031Sdim << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1012280031Sdim ++i; 1013224145Sdim } 1014224145Sdim OS << "};\n\n"; // End of register descriptors... 1015224145Sdim 1016239462Sdim // Emit the table of register unit roots. Each regunit has one or two root 1017239462Sdim // registers. 1018276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1019239462Sdim for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1020239462Sdim ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1021239462Sdim assert(!Roots.empty() && "All regunits must have a root register."); 1022239462Sdim assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1023239462Sdim OS << " { " << getQualifiedName(Roots.front()->TheDef); 1024239462Sdim for (unsigned r = 1; r != Roots.size(); ++r) 1025239462Sdim OS << ", " << getQualifiedName(Roots[r]->TheDef); 1026239462Sdim OS << " },\n"; 1027239462Sdim } 1028239462Sdim OS << "};\n\n"; 1029239462Sdim 1030280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1031226633Sdim 1032226633Sdim // Loop over all of the register classes... emitting each one. 1033226633Sdim OS << "namespace { // Register classes...\n"; 1034226633Sdim 1035280031Sdim SequenceToOffsetTable<std::string> RegClassStrings; 1036280031Sdim 1037226633Sdim // Emit the register enum value arrays for each RegisterClass 1038280031Sdim for (const auto &RC : RegisterClasses) { 1039226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 1040226633Sdim 1041226633Sdim // Give the register class a legal C name if it's anonymous. 1042309124Sdim const std::string &Name = RC.getName(); 1043226633Sdim 1044280031Sdim RegClassStrings.add(Name); 1045280031Sdim 1046226633Sdim // Emit the register list now. 1047226633Sdim OS << " // " << Name << " Register Class...\n" 1048276479Sdim << " const MCPhysReg " << Name 1049226633Sdim << "[] = {\n "; 1050327952Sdim for (Record *Reg : Order) { 1051226633Sdim OS << getQualifiedName(Reg) << ", "; 1052226633Sdim } 1053226633Sdim OS << "\n };\n\n"; 1054226633Sdim 1055226633Sdim OS << " // " << Name << " Bit set.\n" 1056234353Sdim << " const uint8_t " << Name 1057226633Sdim << "Bits[] = {\n "; 1058226633Sdim BitVectorEmitter BVE; 1059327952Sdim for (Record *Reg : Order) { 1060226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1061226633Sdim } 1062226633Sdim BVE.print(OS); 1063226633Sdim OS << "\n };\n\n"; 1064226633Sdim 1065226633Sdim } 1066309124Sdim OS << "} // end anonymous namespace\n\n"; 1067226633Sdim 1068280031Sdim RegClassStrings.layout(); 1069280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 1070280031Sdim RegClassStrings.emit(OS, printChar); 1071280031Sdim OS << "};\n\n"; 1072280031Sdim 1073234353Sdim OS << "extern const MCRegisterClass " << TargetName 1074234353Sdim << "MCRegisterClasses[] = {\n"; 1075226633Sdim 1076280031Sdim for (const auto &RC : RegisterClasses) { 1077321369Sdim assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1078280031Sdim OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1079280031Sdim << RegClassStrings.get(RC.getName()) << ", " 1080234353Sdim << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1081234353Sdim << RC.getQualifiedName() + "RegClassID" << ", " 1082226633Sdim << RC.CopyCost << ", " 1083309124Sdim << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1084226633Sdim } 1085226633Sdim 1086226633Sdim OS << "};\n\n"; 1087226633Sdim 1088239462Sdim EmitRegMappingTables(OS, Regs, false); 1089239462Sdim 1090239462Sdim // Emit Reg encoding table 1091239462Sdim OS << "extern const uint16_t " << TargetName; 1092239462Sdim OS << "RegEncodingTable[] = {\n"; 1093239462Sdim // Add entry for NoRegister 1094239462Sdim OS << " 0,\n"; 1095280031Sdim for (const auto &RE : Regs) { 1096280031Sdim Record *Reg = RE.TheDef; 1097239462Sdim BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1098239462Sdim uint64_t Value = 0; 1099239462Sdim for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1100243830Sdim if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1101276479Sdim Value |= (uint64_t)B->getValue() << b; 1102234353Sdim } 1103239462Sdim OS << " " << Value << ",\n"; 1104234353Sdim } 1105239462Sdim OS << "};\n"; // End of HW encoding table 1106234353Sdim 1107224145Sdim // MCRegisterInfo initialization routine. 1108224145Sdim OS << "static inline void Init" << TargetName 1109226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1110280031Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1111280031Sdim "{\n" 1112239462Sdim << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1113280031Sdim << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1114280031Sdim << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1115280031Sdim << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1116280031Sdim << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1117280031Sdim << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1118280031Sdim << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1119280031Sdim << TargetName << "SubRegIdxRanges, " << TargetName 1120280031Sdim << "RegEncodingTable);\n\n"; 1121224145Sdim 1122226633Sdim EmitRegMapping(OS, Regs, false); 1123226633Sdim 1124226633Sdim OS << "}\n\n"; 1125226633Sdim 1126309124Sdim OS << "} // end namespace llvm\n\n"; 1127224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1128224145Sdim} 1129224145Sdim 1130224145Sdimvoid 1131224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1132224145Sdim CodeGenRegBank &RegBank) { 1133239462Sdim emitSourceFileHeader("Register Information Header Fragment", OS); 1134224145Sdim 1135224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1136309124Sdim OS << "#undef GET_REGINFO_HEADER\n\n"; 1137224145Sdim 1138193323Sed const std::string &TargetName = Target.getName(); 1139193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 1140193323Sed 1141327952Sdim OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1142193323Sed 1143193323Sed OS << "namespace llvm {\n\n"; 1144193323Sed 1145288943Sdim OS << "class " << TargetName << "FrameLowering;\n\n"; 1146288943Sdim 1147193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1148226633Sdim << " explicit " << ClassName 1149327952Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1150327952Sdim << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1151239462Sdim if (!RegBank.getSubRegIndices().empty()) { 1152276479Sdim OS << " unsigned composeSubRegIndicesImpl" 1153276479Sdim << "(unsigned, unsigned) const override;\n" 1154309124Sdim << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1155309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1156309124Sdim << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1157309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1158276479Sdim << " const TargetRegisterClass *getSubClassWithSubReg" 1159276479Sdim << "(const TargetRegisterClass*, unsigned) const override;\n"; 1160239462Sdim } 1161276479Sdim OS << " const RegClassWeight &getRegClassWeight(" 1162276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1163276479Sdim << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1164276479Sdim << " unsigned getNumRegPressureSets() const override;\n" 1165276479Sdim << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1166288943Sdim << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1167288943Sdim "Idx) const override;\n" 1168276479Sdim << " const int *getRegClassPressureSets(" 1169276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1170276479Sdim << " const int *getRegUnitPressureSets(" 1171276479Sdim << "unsigned RegUnit) const override;\n" 1172288943Sdim << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1173288943Sdim << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1174288943Sdim << " /// Devirtualized TargetFrameLowering.\n" 1175288943Sdim << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1176288943Sdim << " const MachineFunction &MF);\n" 1177193323Sed << "};\n\n"; 1178193323Sed 1179280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1180193323Sed 1181193323Sed if (!RegisterClasses.empty()) { 1182280031Sdim OS << "namespace " << RegisterClasses.front().Namespace 1183193323Sed << " { // Register classes\n"; 1184221345Sdim 1185280031Sdim for (const auto &RC : RegisterClasses) { 1186224145Sdim const std::string &Name = RC.getName(); 1187193323Sed 1188193323Sed // Output the extern for the instance. 1189234353Sdim OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1190193323Sed } 1191309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1192193323Sed } 1193309124Sdim OS << "} // end namespace llvm\n\n"; 1194224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 1195193323Sed} 1196193323Sed 1197224145Sdim// 1198224145Sdim// runTargetDesc - Output the target register and register file descriptions. 1199224145Sdim// 1200224145Sdimvoid 1201224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1202224145Sdim CodeGenRegBank &RegBank){ 1203239462Sdim emitSourceFileHeader("Target Register and Register Classes Information", OS); 1204193323Sed 1205224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1206309124Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1207193323Sed 1208193323Sed OS << "namespace llvm {\n\n"; 1209193323Sed 1210226633Sdim // Get access to MCRegisterClass data. 1211234353Sdim OS << "extern const MCRegisterClass " << Target.getName() 1212234353Sdim << "MCRegisterClasses[];\n"; 1213226633Sdim 1214223017Sdim // Start out by emitting each of the register classes. 1215280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1216280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 1217193323Sed 1218223017Sdim // Collect all registers belonging to any allocatable class. 1219223017Sdim std::set<Record*> AllocatableRegs; 1220223017Sdim 1221226633Sdim // Collect allocatable registers. 1222280031Sdim for (const auto &RC : RegisterClasses) { 1223224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 1224193323Sed 1225223017Sdim if (RC.Allocatable) 1226224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 1227226633Sdim } 1228223017Sdim 1229327952Sdim const CodeGenHwModes &CGH = Target.getHwModes(); 1230327952Sdim unsigned NumModes = CGH.getNumModeIds(); 1231327952Sdim 1232234353Sdim // Build a shared array of value types. 1233327952Sdim SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1234327952Sdim for (unsigned M = 0; M < NumModes; ++M) { 1235327952Sdim for (const auto &RC : RegisterClasses) { 1236327952Sdim std::vector<MVT::SimpleValueType> S; 1237327952Sdim for (const ValueTypeByHwMode &VVT : RC.VTs) 1238327952Sdim S.push_back(VVT.get(M).SimpleTy); 1239327952Sdim VTSeqs.add(S); 1240327952Sdim } 1241327952Sdim } 1242234353Sdim VTSeqs.layout(); 1243234353Sdim OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1244234353Sdim VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1245234353Sdim OS << "};\n"; 1246221345Sdim 1247243830Sdim // Emit SubRegIndex names, skipping 0. 1248243830Sdim OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1249280031Sdim 1250280031Sdim for (const auto &Idx : SubRegIndices) { 1251280031Sdim OS << Idx.getName(); 1252280031Sdim OS << "\", \""; 1253239462Sdim } 1254239462Sdim OS << "\" };\n\n"; 1255239462Sdim 1256243830Sdim // Emit SubRegIndex lane masks, including 0. 1257321369Sdim OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1258321369Sdim "LaneBitmask::getAll(),\n"; 1259280031Sdim for (const auto &Idx : SubRegIndices) { 1260314564Sdim printMask(OS << " ", Idx.LaneMask); 1261314564Sdim OS << ", // " << Idx.getName() << '\n'; 1262243830Sdim } 1263243830Sdim OS << " };\n\n"; 1264243830Sdim 1265239462Sdim OS << "\n"; 1266239462Sdim 1267193323Sed // Now that all of the structs have been emitted, emit the instances. 1268193323Sed if (!RegisterClasses.empty()) { 1269327952Sdim OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1270327952Sdim << " = {\n"; 1271327952Sdim for (unsigned M = 0; M < NumModes; ++M) { 1272327952Sdim unsigned EV = 0; 1273327952Sdim OS << " // Mode = " << M << " ("; 1274327952Sdim if (M == 0) 1275327952Sdim OS << "Default"; 1276327952Sdim else 1277327952Sdim OS << CGH.getMode(M).Name; 1278327952Sdim OS << ")\n"; 1279327952Sdim for (const auto &RC : RegisterClasses) { 1280327952Sdim assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); 1281327952Sdim (void)EV; 1282327952Sdim const RegSizeInfo &RI = RC.RSI.get(M); 1283327952Sdim OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1284327952Sdim << RI.SpillAlignment; 1285327952Sdim std::vector<MVT::SimpleValueType> VTs; 1286327952Sdim for (const ValueTypeByHwMode &VVT : RC.VTs) 1287327952Sdim VTs.push_back(VVT.get(M).SimpleTy); 1288327952Sdim OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1289327952Sdim << RC.getName() << '\n'; 1290327952Sdim } 1291327952Sdim } 1292327952Sdim OS << "};\n"; 1293327952Sdim 1294327952Sdim 1295234353Sdim OS << "\nstatic const TargetRegisterClass *const " 1296276479Sdim << "NullRegClasses[] = { nullptr };\n\n"; 1297226633Sdim 1298239462Sdim // Emit register class bit mask tables. The first bit mask emitted for a 1299239462Sdim // register class, RC, is the set of sub-classes, including RC itself. 1300239462Sdim // 1301239462Sdim // If RC has super-registers, also create a list of subreg indices and bit 1302239462Sdim // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1303239462Sdim // SuperRC, that satisfies: 1304239462Sdim // 1305239462Sdim // For all SuperReg in SuperRC: SuperReg:Idx in RC 1306239462Sdim // 1307239462Sdim // The 0-terminated list of subreg indices starts at: 1308239462Sdim // 1309239462Sdim // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1310239462Sdim // 1311239462Sdim // The corresponding bitmasks follow the sub-class mask in memory. Each 1312239462Sdim // mask has RCMaskWords uint32_t entries. 1313239462Sdim // 1314239462Sdim // Every bit mask present in the list has at least one bit set. 1315193323Sed 1316239462Sdim // Compress the sub-reg index lists. 1317239462Sdim typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1318239462Sdim SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1319288943Sdim SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs; 1320239462Sdim BitVector MaskBV(RegisterClasses.size()); 1321193323Sed 1322280031Sdim for (const auto &RC : RegisterClasses) { 1323321369Sdim OS << "static const uint32_t " << RC.getName() 1324321369Sdim << "SubClassMask[] = {\n "; 1325239462Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1326193323Sed 1327239462Sdim // Emit super-reg class masks for any relevant SubRegIndices that can 1328239462Sdim // project into RC. 1329280031Sdim IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1330280031Sdim for (auto &Idx : SubRegIndices) { 1331239462Sdim MaskBV.reset(); 1332280031Sdim RC.getSuperRegClasses(&Idx, MaskBV); 1333239462Sdim if (MaskBV.none()) 1334239462Sdim continue; 1335280031Sdim SRIList.push_back(&Idx); 1336239462Sdim OS << "\n "; 1337239462Sdim printBitVectorAsHex(OS, MaskBV, 32); 1338280031Sdim OS << "// " << Idx.getName(); 1339239462Sdim } 1340239462Sdim SuperRegIdxSeqs.add(SRIList); 1341234353Sdim OS << "\n};\n\n"; 1342193323Sed } 1343193323Sed 1344239462Sdim OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1345239462Sdim SuperRegIdxSeqs.layout(); 1346239462Sdim SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1347239462Sdim OS << "};\n\n"; 1348239462Sdim 1349226633Sdim // Emit NULL terminated super-class lists. 1350280031Sdim for (const auto &RC : RegisterClasses) { 1351226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1352193323Sed 1353226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 1354226633Sdim if (Supers.empty()) 1355226633Sdim continue; 1356193323Sed 1357234353Sdim OS << "static const TargetRegisterClass *const " 1358226633Sdim << RC.getName() << "Superclasses[] = {\n"; 1359280031Sdim for (const auto *Super : Supers) 1360280031Sdim OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1361276479Sdim OS << " nullptr\n};\n\n"; 1362193323Sed } 1363193323Sed 1364224145Sdim // Emit methods. 1365280031Sdim for (const auto &RC : RegisterClasses) { 1366224145Sdim if (!RC.AltOrderSelect.empty()) { 1367224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 1368224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 1369234353Sdim << RC.AltOrderSelect << "}\n\n" 1370249423Sdim << "static ArrayRef<MCPhysReg> " << RC.getName() 1371234353Sdim << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1372224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1373224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 1374234353Sdim if (!Elems.empty()) { 1375249423Sdim OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1376234353Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 1377234353Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1378234353Sdim OS << " };\n"; 1379234353Sdim } 1380224145Sdim } 1381226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 1382234353Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1383249423Sdim << " const ArrayRef<MCPhysReg> Order[] = {\n" 1384226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1385224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1386234353Sdim if (RC.getOrder(oi).empty()) 1387249423Sdim OS << "),\n ArrayRef<MCPhysReg>("; 1388234353Sdim else 1389234353Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 1390224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 1391224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1392224145Sdim << ");\n return Order[Select];\n}\n"; 1393280031Sdim } 1394193323Sed } 1395221345Sdim 1396234353Sdim // Now emit the actual value-initialized register class instances. 1397280031Sdim OS << "\nnamespace " << RegisterClasses.front().Namespace 1398234353Sdim << " { // Register class instances\n"; 1399234353Sdim 1400280031Sdim for (const auto &RC : RegisterClasses) { 1401280031Sdim OS << " extern const TargetRegisterClass " << RC.getName() 1402280031Sdim << "RegClass = {\n " << '&' << Target.getName() 1403280031Sdim << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1404327952Sdim << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1405314564Sdim << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1406314564Sdim printMask(OS, RC.LaneMask); 1407314564Sdim OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1408288943Sdim << (RC.HasDisjunctSubRegs?"true":"false") 1409309124Sdim << ", /* HasDisjunctSubRegs */\n " 1410309124Sdim << (RC.CoveredBySubRegs?"true":"false") 1411309124Sdim << ", /* CoveredBySubRegs */\n "; 1412234353Sdim if (RC.getSuperClasses().empty()) 1413234353Sdim OS << "NullRegClasses,\n "; 1414234353Sdim else 1415234353Sdim OS << RC.getName() << "Superclasses,\n "; 1416234353Sdim if (RC.AltOrderSelect.empty()) 1417276479Sdim OS << "nullptr\n"; 1418234353Sdim else 1419234353Sdim OS << RC.getName() << "GetRawAllocationOrder\n"; 1420234353Sdim OS << " };\n\n"; 1421234353Sdim } 1422234353Sdim 1423309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1424193323Sed } 1425193323Sed 1426193323Sed OS << "\nnamespace {\n"; 1427193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1428280031Sdim for (const auto &RC : RegisterClasses) 1429280031Sdim OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1430193323Sed OS << " };\n"; 1431309124Sdim OS << "} // end anonymous namespace\n"; 1432193323Sed 1433224145Sdim // Emit extra information about registers. 1434224145Sdim const std::string &TargetName = Target.getName(); 1435234353Sdim OS << "\nstatic const TargetRegisterInfoDesc " 1436234353Sdim << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1437309124Sdim OS << " { 0, false },\n"; 1438221345Sdim 1439280031Sdim const auto &Regs = RegBank.getRegisters(); 1440280031Sdim for (const auto &Reg : Regs) { 1441234353Sdim OS << " { "; 1442224145Sdim OS << Reg.CostPerUse << ", " 1443309124Sdim << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1444309124Sdim << " },\n"; 1445193323Sed } 1446234353Sdim OS << "};\n"; // End of register descriptors... 1447208599Srdivacky 1448224145Sdim 1449314564Sdim std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1450193323Sed 1451280031Sdim auto SubRegIndicesSize = 1452280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1453280031Sdim 1454280031Sdim if (!SubRegIndices.empty()) { 1455243830Sdim emitComposeSubRegIndices(OS, RegBank, ClassName); 1456280031Sdim emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1457280031Sdim } 1458210299Sed 1459226633Sdim // Emit getSubClassWithSubReg. 1460239462Sdim if (!SubRegIndices.empty()) { 1461239462Sdim OS << "const TargetRegisterClass *" << ClassName 1462239462Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1463239462Sdim << " const {\n"; 1464226633Sdim // Use the smallest type that can hold a regclass ID with room for a 1465226633Sdim // sentinel. 1466226633Sdim if (RegisterClasses.size() < UINT8_MAX) 1467226633Sdim OS << " static const uint8_t Table["; 1468226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 1469226633Sdim OS << " static const uint16_t Table["; 1470226633Sdim else 1471243830Sdim PrintFatalError("Too many register classes."); 1472280031Sdim OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1473280031Sdim for (const auto &RC : RegisterClasses) { 1474226633Sdim OS << " {\t// " << RC.getName() << "\n"; 1475280031Sdim for (auto &Idx : SubRegIndices) { 1476280031Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1477280031Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1478226633Sdim << " -> " << SRC->getName() << "\n"; 1479226633Sdim else 1480280031Sdim OS << " 0,\t// " << Idx.getName() << "\n"; 1481226633Sdim } 1482226633Sdim OS << " },\n"; 1483226633Sdim } 1484226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 1485226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 1486280031Sdim << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1487226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 1488276479Sdim << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1489226633Sdim } 1490226633Sdim 1491234353Sdim EmitRegUnitPressure(OS, RegBank, ClassName); 1492234353Sdim 1493193323Sed // Emit the constructor of the class... 1494234353Sdim OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1495249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1496314564Sdim OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1497239462Sdim OS << "extern const char " << TargetName << "RegStrings[];\n"; 1498280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1499276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1500239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1501261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1502261991Sdim << TargetName << "SubRegIdxRanges[];\n"; 1503239462Sdim OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1504224145Sdim 1505234353Sdim EmitRegMappingTables(OS, Regs, true); 1506234353Sdim 1507234353Sdim OS << ClassName << "::\n" << ClassName 1508327952Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1509327952Sdim " unsigned PC, unsigned HwMode)\n" 1510224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1511327952Sdim << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1512327952Sdim << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1513327952Sdim << " "; 1514314564Sdim printMask(OS, RegBank.CoveringLanes); 1515327952Sdim OS << ", RegClassInfos, HwMode) {\n" 1516280031Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1517280031Sdim << ", RA, PC,\n " << TargetName 1518234353Sdim << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1519239462Sdim << " " << TargetName << "RegUnitRoots,\n" 1520239462Sdim << " " << RegBank.getNumNativeRegUnits() << ",\n" 1521239462Sdim << " " << TargetName << "RegDiffLists,\n" 1522280031Sdim << " " << TargetName << "LaneMaskLists,\n" 1523239462Sdim << " " << TargetName << "RegStrings,\n" 1524280031Sdim << " " << TargetName << "RegClassStrings,\n" 1525239462Sdim << " " << TargetName << "SubRegIdxLists,\n" 1526280031Sdim << " " << SubRegIndicesSize + 1 << ",\n" 1527261991Sdim << " " << TargetName << "SubRegIdxRanges,\n" 1528239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 1529193323Sed 1530226633Sdim EmitRegMapping(OS, Regs, true); 1531193323Sed 1532226633Sdim OS << "}\n\n"; 1533193323Sed 1534234353Sdim // Emit CalleeSavedRegs information. 1535234353Sdim std::vector<Record*> CSRSets = 1536234353Sdim Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1537234353Sdim for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1538234353Sdim Record *CSRSet = CSRSets[i]; 1539234353Sdim const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1540234353Sdim assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1541234353Sdim 1542234353Sdim // Emit the *_SaveList list of callee-saved registers. 1543249423Sdim OS << "static const MCPhysReg " << CSRSet->getName() 1544234353Sdim << "_SaveList[] = { "; 1545234353Sdim for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1546234353Sdim OS << getQualifiedName((*Regs)[r]) << ", "; 1547234353Sdim OS << "0 };\n"; 1548234353Sdim 1549234353Sdim // Emit the *_RegMask bit mask of call-preserved registers. 1550261991Sdim BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1551261991Sdim 1552261991Sdim // Check for an optional OtherPreserved set. 1553261991Sdim // Add those registers to RegMask, but not to SaveList. 1554261991Sdim if (DagInit *OPDag = 1555261991Sdim dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1556261991Sdim SetTheory::RecSet OPSet; 1557261991Sdim RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1558261991Sdim Covered |= RegBank.computeCoveredRegisters( 1559261991Sdim ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1560261991Sdim } 1561261991Sdim 1562234353Sdim OS << "static const uint32_t " << CSRSet->getName() 1563234353Sdim << "_RegMask[] = { "; 1564261991Sdim printBitVectorAsHex(OS, Covered, 32); 1565234353Sdim OS << "};\n"; 1566234353Sdim } 1567234353Sdim OS << "\n\n"; 1568234353Sdim 1569288943Sdim OS << "ArrayRef<const uint32_t *> " << ClassName 1570288943Sdim << "::getRegMasks() const {\n"; 1571296417Sdim if (!CSRSets.empty()) { 1572296417Sdim OS << " static const uint32_t *const Masks[] = {\n"; 1573296417Sdim for (Record *CSRSet : CSRSets) 1574296417Sdim OS << " " << CSRSet->getName() << "_RegMask,\n"; 1575296417Sdim OS << " };\n"; 1576296417Sdim OS << " return makeArrayRef(Masks);\n"; 1577296417Sdim } else { 1578296417Sdim OS << " return None;\n"; 1579296417Sdim } 1580288943Sdim OS << "}\n\n"; 1581288943Sdim 1582288943Sdim OS << "ArrayRef<const char *> " << ClassName 1583288943Sdim << "::getRegMaskNames() const {\n"; 1584296417Sdim if (!CSRSets.empty()) { 1585296417Sdim OS << " static const char *const Names[] = {\n"; 1586296417Sdim for (Record *CSRSet : CSRSets) 1587296417Sdim OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1588296417Sdim OS << " };\n"; 1589296417Sdim OS << " return makeArrayRef(Names);\n"; 1590296417Sdim } else { 1591296417Sdim OS << " return None;\n"; 1592296417Sdim } 1593288943Sdim OS << "}\n\n"; 1594288943Sdim 1595296417Sdim OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1596296417Sdim << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1597288943Sdim << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1598288943Sdim << " MF.getSubtarget().getFrameLowering());\n" 1599288943Sdim << "}\n\n"; 1600288943Sdim 1601309124Sdim OS << "} // end namespace llvm\n\n"; 1602224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1603193323Sed} 1604224145Sdim 1605224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 1606224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1607224145Sdim runEnums(OS, Target, RegBank); 1608224145Sdim runMCDesc(OS, Target, RegBank); 1609224145Sdim runTargetHeader(OS, Target, RegBank); 1610224145Sdim runTargetDesc(OS, Target, RegBank); 1611327952Sdim 1612327952Sdim if (RegisterInfoDebug) 1613327952Sdim debugDump(errs()); 1614224145Sdim} 1615239462Sdim 1616327952Sdimvoid RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1617327952Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1618327952Sdim const CodeGenHwModes &CGH = Target.getHwModes(); 1619327952Sdim unsigned NumModes = CGH.getNumModeIds(); 1620327952Sdim auto getModeName = [CGH] (unsigned M) -> StringRef { 1621327952Sdim if (M == 0) 1622327952Sdim return "Default"; 1623327952Sdim return CGH.getMode(M).Name; 1624327952Sdim }; 1625327952Sdim 1626327952Sdim for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1627327952Sdim OS << "RegisterClass " << RC.getName() << ":\n"; 1628327952Sdim OS << "\tSpillSize: {"; 1629327952Sdim for (unsigned M = 0; M != NumModes; ++M) 1630327952Sdim OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1631327952Sdim OS << " }\n\tSpillAlignment: {"; 1632327952Sdim for (unsigned M = 0; M != NumModes; ++M) 1633327952Sdim OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1634327952Sdim OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1635327952Sdim OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1636327952Sdim OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1637327952Sdim OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1638327952Sdim OS << "\tRegs:"; 1639327952Sdim for (const CodeGenRegister *R : RC.getMembers()) { 1640327952Sdim OS << " " << R->getName(); 1641327952Sdim } 1642327952Sdim OS << '\n'; 1643327952Sdim OS << "\tSubClasses:"; 1644327952Sdim const BitVector &SubClasses = RC.getSubClasses(); 1645327952Sdim for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1646327952Sdim if (!SubClasses.test(SRC.EnumValue)) 1647327952Sdim continue; 1648327952Sdim OS << " " << SRC.getName(); 1649327952Sdim } 1650327952Sdim OS << '\n'; 1651327952Sdim OS << "\tSuperClasses:"; 1652327952Sdim for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1653327952Sdim OS << " " << SRC->getName(); 1654327952Sdim } 1655327952Sdim OS << '\n'; 1656327952Sdim } 1657327952Sdim 1658327952Sdim for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1659327952Sdim OS << "SubRegIndex " << SRI.getName() << ":\n"; 1660327952Sdim OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1661327952Sdim OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1662327952Sdim } 1663327952Sdim 1664327952Sdim for (const CodeGenRegister &R : RegBank.getRegisters()) { 1665327952Sdim OS << "Register " << R.getName() << ":\n"; 1666327952Sdim OS << "\tCostPerUse: " << R.CostPerUse << '\n'; 1667327952Sdim OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1668327952Sdim OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1669327952Sdim for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1670327952Sdim OS << "\tSubReg " << P.first->getName() 1671327952Sdim << " = " << P.second->getName() << '\n'; 1672327952Sdim } 1673327952Sdim } 1674327952Sdim} 1675327952Sdim 1676239462Sdimnamespace llvm { 1677239462Sdim 1678239462Sdimvoid EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1679239462Sdim RegisterInfoEmitter(RK).run(OS); 1680239462Sdim} 1681239462Sdim 1682309124Sdim} // end namespace llvm 1683