RegisterInfoEmitter.cpp revision 309124
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16239462Sdim#include "CodeGenRegisters.h" 17193323Sed#include "CodeGenTarget.h" 18234353Sdim#include "SequenceToOffsetTable.h" 19309124Sdim#include "llvm/ADT/ArrayRef.h" 20226633Sdim#include "llvm/ADT/BitVector.h" 21309124Sdim#include "llvm/ADT/SetVector.h" 22309124Sdim#include "llvm/ADT/SmallVector.h" 23309124Sdim#include "llvm/ADT/SparseBitVector.h" 24239462Sdim#include "llvm/ADT/STLExtras.h" 25234982Sdim#include "llvm/ADT/Twine.h" 26309124Sdim#include "llvm/CodeGen/MachineValueType.h" 27309124Sdim#include "llvm/Support/Casting.h" 28224145Sdim#include "llvm/Support/Format.h" 29309124Sdim#include "llvm/Support/raw_ostream.h" 30239462Sdim#include "llvm/TableGen/Error.h" 31239462Sdim#include "llvm/TableGen/Record.h" 32309124Sdim#include "llvm/TableGen/SetTheory.h" 33239462Sdim#include "llvm/TableGen/TableGenBackend.h" 34195340Sed#include <algorithm> 35309124Sdim#include <cassert> 36309124Sdim#include <cstddef> 37309124Sdim#include <cstdint> 38309124Sdim#include <deque> 39309124Sdim#include <iterator> 40193323Sed#include <set> 41309124Sdim#include <string> 42239462Sdim#include <vector> 43309124Sdim 44193323Sedusing namespace llvm; 45193323Sed 46239462Sdimnamespace { 47309124Sdim 48239462Sdimclass RegisterInfoEmitter { 49239462Sdim RecordKeeper &Records; 50309124Sdim 51239462Sdimpublic: 52239462Sdim RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 53239462Sdim 54239462Sdim // runEnums - Print out enum values for all of the registers. 55239462Sdim void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 56239462Sdim 57239462Sdim // runMCDesc - Print out MC register descriptions. 58239462Sdim void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 59239462Sdim 60239462Sdim // runTargetHeader - Emit a header fragment for the register info emitter. 61239462Sdim void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 62239462Sdim CodeGenRegBank &Bank); 63239462Sdim 64239462Sdim // runTargetDesc - Output the target register and register file descriptions. 65239462Sdim void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 66239462Sdim CodeGenRegBank &Bank); 67239462Sdim 68239462Sdim // run - Output the register file description. 69239462Sdim void run(raw_ostream &o); 70239462Sdim 71239462Sdimprivate: 72280031Sdim void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 73280031Sdim bool isCtor); 74239462Sdim void EmitRegMappingTables(raw_ostream &o, 75280031Sdim const std::deque<CodeGenRegister> &Regs, 76239462Sdim bool isCtor); 77239462Sdim void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 78239462Sdim const std::string &ClassName); 79243830Sdim void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 80243830Sdim const std::string &ClassName); 81280031Sdim void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 82280031Sdim const std::string &ClassName); 83239462Sdim}; 84239462Sdim 85309124Sdim} // end anonymous namespace 86309124Sdim 87193323Sed// runEnums - Print out enum values for all of the registers. 88234982Sdimvoid RegisterInfoEmitter::runEnums(raw_ostream &OS, 89234982Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 90280031Sdim const auto &Registers = Bank.getRegisters(); 91193323Sed 92234982Sdim // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 93234353Sdim assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 94234353Sdim 95280031Sdim std::string Namespace = 96280031Sdim Registers.front().TheDef->getValueAsString("Namespace"); 97193323Sed 98239462Sdim emitSourceFileHeader("Target Register Enum Values", OS); 99224145Sdim 100224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 101309124Sdim OS << "#undef GET_REGINFO_ENUM\n\n"; 102224145Sdim 103193323Sed OS << "namespace llvm {\n\n"; 104193323Sed 105226633Sdim OS << "class MCRegisterClass;\n" 106234353Sdim << "extern const MCRegisterClass " << Namespace 107234353Sdim << "MCRegisterClasses[];\n\n"; 108226633Sdim 109193323Sed if (!Namespace.empty()) 110193323Sed OS << "namespace " << Namespace << " {\n"; 111208599Srdivacky OS << "enum {\n NoRegister,\n"; 112193323Sed 113280031Sdim for (const auto &Reg : Registers) 114280031Sdim OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 115280031Sdim assert(Registers.size() == Registers.back().EnumValue && 116221345Sdim "Register enum value mismatch!"); 117208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 118208599Srdivacky OS << "};\n"; 119193323Sed if (!Namespace.empty()) 120309124Sdim OS << "} // end namespace " << Namespace << "\n"; 121208599Srdivacky 122280031Sdim const auto &RegisterClasses = Bank.getRegClasses(); 123224145Sdim if (!RegisterClasses.empty()) { 124234353Sdim 125234353Sdim // RegisterClass enums are stored as uint16_t in the tables. 126234353Sdim assert(RegisterClasses.size() <= 0xffff && 127234353Sdim "Too many register classes to fit in tables"); 128234353Sdim 129309124Sdim OS << "\n// Register classes\n\n"; 130208599Srdivacky if (!Namespace.empty()) 131208599Srdivacky OS << "namespace " << Namespace << " {\n"; 132224145Sdim OS << "enum {\n"; 133280031Sdim for (const auto &RC : RegisterClasses) 134280031Sdim OS << " " << RC.getName() << "RegClassID" 135280031Sdim << " = " << RC.EnumValue << ",\n"; 136224145Sdim OS << "\n };\n"; 137224145Sdim if (!Namespace.empty()) 138309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 139224145Sdim } 140224145Sdim 141261991Sdim const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 142224145Sdim // If the only definition is the default NoRegAltName, we don't need to 143224145Sdim // emit anything. 144224145Sdim if (RegAltNameIndices.size() > 1) { 145309124Sdim OS << "\n// Register alternate name indices\n\n"; 146224145Sdim if (!Namespace.empty()) 147224145Sdim OS << "namespace " << Namespace << " {\n"; 148224145Sdim OS << "enum {\n"; 149224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 150224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 151224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 152208599Srdivacky OS << "};\n"; 153208599Srdivacky if (!Namespace.empty()) 154309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 155208599Srdivacky } 156224145Sdim 157280031Sdim auto &SubRegIndices = Bank.getSubRegIndices(); 158234353Sdim if (!SubRegIndices.empty()) { 159309124Sdim OS << "\n// Subregister indices\n\n"; 160280031Sdim std::string Namespace = SubRegIndices.front().getNamespace(); 161234353Sdim if (!Namespace.empty()) 162234353Sdim OS << "namespace " << Namespace << " {\n"; 163234353Sdim OS << "enum {\n NoSubRegister,\n"; 164280031Sdim unsigned i = 0; 165280031Sdim for (const auto &Idx : SubRegIndices) 166280031Sdim OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 167239462Sdim OS << " NUM_TARGET_SUBREGS\n};\n"; 168234353Sdim if (!Namespace.empty()) 169309124Sdim OS << "} // end namespace " << Namespace << "\n\n"; 170234353Sdim } 171224145Sdim 172309124Sdim OS << "} // end namespace llvm\n\n"; 173224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 174193323Sed} 175193323Sed 176280031Sdimstatic void printInt(raw_ostream &OS, int Val) { 177280031Sdim OS << Val; 178280031Sdim} 179280031Sdim 180280031Sdimstatic const char *getMinimalTypeForRange(uint64_t Range) { 181280031Sdim assert(Range < 0xFFFFFFFFULL && "Enum too large"); 182280031Sdim if (Range > 0xFFFF) 183280031Sdim return "uint32_t"; 184280031Sdim if (Range > 0xFF) 185280031Sdim return "uint16_t"; 186280031Sdim return "uint8_t"; 187280031Sdim} 188280031Sdim 189234353Sdimvoid RegisterInfoEmitter:: 190234353SdimEmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 191234353Sdim const std::string &ClassName) { 192234353Sdim unsigned NumRCs = RegBank.getRegClasses().size(); 193234353Sdim unsigned NumSets = RegBank.getNumRegPressureSets(); 194234353Sdim 195234353Sdim OS << "/// Get the weight in units of pressure for this register class.\n" 196234353Sdim << "const RegClassWeight &" << ClassName << "::\n" 197234353Sdim << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 198234353Sdim << " static const RegClassWeight RCWeightTable[] = {\n"; 199280031Sdim for (const auto &RC : RegBank.getRegClasses()) { 200288943Sdim const CodeGenRegister::Vec &Regs = RC.getMembers(); 201234353Sdim if (Regs.empty()) 202234353Sdim OS << " {0, 0"; 203234353Sdim else { 204234353Sdim std::vector<unsigned> RegUnits; 205234353Sdim RC.buildRegUnitSet(RegUnits); 206234353Sdim OS << " {" << (*Regs.begin())->getWeight(RegBank) 207234353Sdim << ", " << RegBank.getRegUnitSetWeight(RegUnits); 208234353Sdim } 209234353Sdim OS << "}, \t// " << RC.getName() << "\n"; 210234353Sdim } 211280031Sdim OS << " };\n" 212234353Sdim << " return RCWeightTable[RC->getID()];\n" 213234353Sdim << "}\n\n"; 214234353Sdim 215249423Sdim // Reasonable targets (not ARMv7) have unit weight for all units, so don't 216249423Sdim // bother generating a table. 217249423Sdim bool RegUnitsHaveUnitWeight = true; 218249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 219249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 220249423Sdim if (RegBank.getRegUnit(UnitIdx).Weight > 1) 221249423Sdim RegUnitsHaveUnitWeight = false; 222249423Sdim } 223249423Sdim OS << "/// Get the weight in units of pressure for this register unit.\n" 224249423Sdim << "unsigned " << ClassName << "::\n" 225249423Sdim << "getRegUnitWeight(unsigned RegUnit) const {\n" 226249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 227249423Sdim << " && \"invalid register unit\");\n"; 228249423Sdim if (!RegUnitsHaveUnitWeight) { 229249423Sdim OS << " static const uint8_t RUWeightTable[] = {\n "; 230249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 231249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 232249423Sdim const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 233249423Sdim assert(RU.Weight < 256 && "RegUnit too heavy"); 234249423Sdim OS << RU.Weight << ", "; 235249423Sdim } 236280031Sdim OS << "};\n" 237249423Sdim << " return RUWeightTable[RegUnit];\n"; 238249423Sdim } 239249423Sdim else { 240249423Sdim OS << " // All register units have unit weight.\n" 241249423Sdim << " return 1;\n"; 242249423Sdim } 243249423Sdim OS << "}\n\n"; 244249423Sdim 245234353Sdim OS << "\n" 246234353Sdim << "// Get the number of dimensions of register pressure.\n" 247234353Sdim << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 248234353Sdim << " return " << NumSets << ";\n}\n\n"; 249234353Sdim 250239462Sdim OS << "// Get the name of this register unit pressure set.\n" 251239462Sdim << "const char *" << ClassName << "::\n" 252239462Sdim << "getRegPressureSetName(unsigned Idx) const {\n" 253288943Sdim << " static const char *const PressureNameTable[] = {\n"; 254280031Sdim unsigned MaxRegUnitWeight = 0; 255239462Sdim for (unsigned i = 0; i < NumSets; ++i ) { 256280031Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 257280031Sdim MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 258280031Sdim OS << " \"" << RegUnits.Name << "\",\n"; 259239462Sdim } 260296417Sdim OS << " };\n" 261239462Sdim << " return PressureNameTable[Idx];\n" 262239462Sdim << "}\n\n"; 263239462Sdim 264234353Sdim OS << "// Get the register unit pressure limit for this dimension.\n" 265234353Sdim << "// This limit must be adjusted dynamically for reserved registers.\n" 266234353Sdim << "unsigned " << ClassName << "::\n" 267288943Sdim << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {\n" 268280031Sdim << " static const " << getMinimalTypeForRange(MaxRegUnitWeight) 269280031Sdim << " PressureLimitTable[] = {\n"; 270234353Sdim for (unsigned i = 0; i < NumSets; ++i ) { 271261991Sdim const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 272261991Sdim OS << " " << RegUnits.Weight << ", \t// " << i << ": " 273261991Sdim << RegUnits.Name << "\n"; 274234353Sdim } 275280031Sdim OS << " };\n" 276234353Sdim << " return PressureLimitTable[Idx];\n" 277234353Sdim << "}\n\n"; 278234353Sdim 279280031Sdim SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 280280031Sdim 281249423Sdim // This table may be larger than NumRCs if some register units needed a list 282249423Sdim // of unit sets that did not correspond to a register class. 283249423Sdim unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 284280031Sdim std::vector<std::vector<int>> PSets(NumRCUnitSets); 285280031Sdim 286280031Sdim for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 287234353Sdim ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 288280031Sdim PSets[i].reserve(PSetIDs.size()); 289234353Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 290234353Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 291280031Sdim PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 292261991Sdim } 293280031Sdim std::sort(PSets[i].begin(), PSets[i].end()); 294280031Sdim PSetsSeqs.add(PSets[i]); 295234353Sdim } 296249423Sdim 297280031Sdim PSetsSeqs.layout(); 298280031Sdim 299280031Sdim OS << "/// Table of pressure sets per register class or unit.\n" 300280031Sdim << "static const int RCSetsTable[] = {\n"; 301280031Sdim PSetsSeqs.emit(OS, printInt, "-1"); 302280031Sdim OS << "};\n\n"; 303280031Sdim 304249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 305249423Sdim << "register class.\n" 306249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 307249423Sdim << "const int* " << ClassName << "::\n" 308249423Sdim << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 309280031Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) 310280031Sdim << " RCSetStartTable[] = {\n "; 311234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 312280031Sdim OS << PSetsSeqs.get(PSets[i]) << ","; 313234353Sdim } 314280031Sdim OS << "};\n" 315280031Sdim << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 316234353Sdim << "}\n\n"; 317249423Sdim 318249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 319249423Sdim << "register unit.\n" 320249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 321249423Sdim << "const int* " << ClassName << "::\n" 322249423Sdim << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 323249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 324249423Sdim << " && \"invalid register unit\");\n"; 325280031Sdim OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) 326280031Sdim << " RUSetStartTable[] = {\n "; 327249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 328249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 329280031Sdim OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 330280031Sdim << ","; 331249423Sdim } 332280031Sdim OS << "};\n" 333280031Sdim << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 334249423Sdim << "}\n\n"; 335234353Sdim} 336234353Sdim 337280031Sdimvoid RegisterInfoEmitter::EmitRegMappingTables( 338280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 339226633Sdim // Collect all information about dwarf register numbers 340261991Sdim typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy; 341226633Sdim DwarfRegNumsMapTy DwarfRegNums; 342226633Sdim 343226633Sdim // First, just pull all provided information to the map 344226633Sdim unsigned maxLength = 0; 345280031Sdim for (auto &RE : Regs) { 346280031Sdim Record *Reg = RE.TheDef; 347226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 348226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 349226633Sdim if (DwarfRegNums.count(Reg)) 350234982Sdim PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 351234982Sdim getQualifiedName(Reg) + "specified multiple times"); 352226633Sdim DwarfRegNums[Reg] = RegNums; 353226633Sdim } 354226633Sdim 355226633Sdim if (!maxLength) 356226633Sdim return; 357226633Sdim 358226633Sdim // Now we know maximal length of number list. Append -1's, where needed 359226633Sdim for (DwarfRegNumsMapTy::iterator 360226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 361226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 362226633Sdim I->second.push_back(-1); 363226633Sdim 364280031Sdim std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 365234353Sdim 366234353Sdim OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 367234353Sdim 368226633Sdim // Emit reverse information about the dwarf register numbers. 369226633Sdim for (unsigned j = 0; j < 2; ++j) { 370234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 371234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 372234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 373234353Sdim OS << i << "Dwarf2L[]"; 374234353Sdim 375234353Sdim if (!isCtor) { 376234353Sdim OS << " = {\n"; 377234353Sdim 378234353Sdim // Store the mapping sorted by the LLVM reg num so lookup can be done 379234353Sdim // with a binary search. 380234353Sdim std::map<uint64_t, Record*> Dwarf2LMap; 381234353Sdim for (DwarfRegNumsMapTy::iterator 382234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 383234353Sdim int DwarfRegNo = I->second[i]; 384234353Sdim if (DwarfRegNo < 0) 385234353Sdim continue; 386234353Sdim Dwarf2LMap[DwarfRegNo] = I->first; 387234353Sdim } 388234353Sdim 389234353Sdim for (std::map<uint64_t, Record*>::iterator 390234353Sdim I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 391234353Sdim OS << " { " << I->first << "U, " << getQualifiedName(I->second) 392234353Sdim << " },\n"; 393234353Sdim 394234353Sdim OS << "};\n"; 395234353Sdim } else { 396234353Sdim OS << ";\n"; 397234353Sdim } 398234353Sdim 399234353Sdim // We have to store the size in a const global, it's used in multiple 400234353Sdim // places. 401234353Sdim OS << "extern const unsigned " << Namespace 402234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 403234353Sdim if (!isCtor) 404280031Sdim OS << " = array_lengthof(" << Namespace 405234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 406280031Sdim << "Dwarf2L);\n\n"; 407234353Sdim else 408234353Sdim OS << ";\n\n"; 409234353Sdim } 410234353Sdim } 411234353Sdim 412280031Sdim for (auto &RE : Regs) { 413280031Sdim Record *Reg = RE.TheDef; 414234353Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 415234353Sdim if (!V || !V->getValue()) 416234353Sdim continue; 417234353Sdim 418243830Sdim DefInit *DI = cast<DefInit>(V->getValue()); 419234353Sdim Record *Alias = DI->getDef(); 420234353Sdim DwarfRegNums[Reg] = DwarfRegNums[Alias]; 421234353Sdim } 422234353Sdim 423234353Sdim // Emit information about the dwarf register numbers. 424234353Sdim for (unsigned j = 0; j < 2; ++j) { 425234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 426234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 427234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 428234353Sdim OS << i << "L2Dwarf[]"; 429234353Sdim if (!isCtor) { 430234353Sdim OS << " = {\n"; 431234353Sdim // Store the mapping sorted by the Dwarf reg num so lookup can be done 432234353Sdim // with a binary search. 433234353Sdim for (DwarfRegNumsMapTy::iterator 434234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 435234353Sdim int RegNo = I->second[i]; 436234353Sdim if (RegNo == -1) // -1 is the default value, don't emit a mapping. 437234353Sdim continue; 438234353Sdim 439234353Sdim OS << " { " << getQualifiedName(I->first) << ", " << RegNo 440234353Sdim << "U },\n"; 441234353Sdim } 442234353Sdim OS << "};\n"; 443234353Sdim } else { 444234353Sdim OS << ";\n"; 445234353Sdim } 446234353Sdim 447234353Sdim // We have to store the size in a const global, it's used in multiple 448234353Sdim // places. 449234353Sdim OS << "extern const unsigned " << Namespace 450234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 451234353Sdim if (!isCtor) 452280031Sdim OS << " = array_lengthof(" << Namespace 453280031Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 454234353Sdim else 455234353Sdim OS << ";\n\n"; 456234353Sdim } 457234353Sdim } 458234353Sdim} 459234353Sdim 460280031Sdimvoid RegisterInfoEmitter::EmitRegMapping( 461280031Sdim raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 462234353Sdim // Emit the initializer so the tables from EmitRegMappingTables get wired up 463234353Sdim // to the MCRegisterInfo object. 464234353Sdim unsigned maxLength = 0; 465280031Sdim for (auto &RE : Regs) { 466280031Sdim Record *Reg = RE.TheDef; 467234353Sdim maxLength = std::max((size_t)maxLength, 468234353Sdim Reg->getValueAsListOfInts("DwarfNumbers").size()); 469234353Sdim } 470234353Sdim 471234353Sdim if (!maxLength) 472234353Sdim return; 473234353Sdim 474280031Sdim std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 475234353Sdim 476234353Sdim // Emit reverse information about the dwarf register numbers. 477234353Sdim for (unsigned j = 0; j < 2; ++j) { 478226633Sdim OS << " switch ("; 479226633Sdim if (j == 0) 480226633Sdim OS << "DwarfFlavour"; 481226633Sdim else 482226633Sdim OS << "EHFlavour"; 483226633Sdim OS << ") {\n" 484226633Sdim << " default:\n" 485234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 486226633Sdim 487226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 488226633Sdim OS << " case " << i << ":\n"; 489234353Sdim OS << " "; 490234353Sdim if (!isCtor) 491234353Sdim OS << "RI->"; 492234353Sdim std::string Tmp; 493234353Sdim raw_string_ostream(Tmp) << Namespace 494234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 495234353Sdim << "Dwarf2L"; 496234353Sdim OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 497234353Sdim if (j == 0) 498226633Sdim OS << "false"; 499226633Sdim else 500226633Sdim OS << "true"; 501234353Sdim OS << ");\n"; 502226633Sdim OS << " break;\n"; 503226633Sdim } 504226633Sdim OS << " }\n"; 505226633Sdim } 506226633Sdim 507226633Sdim // Emit information about the dwarf register numbers. 508226633Sdim for (unsigned j = 0; j < 2; ++j) { 509226633Sdim OS << " switch ("; 510226633Sdim if (j == 0) 511226633Sdim OS << "DwarfFlavour"; 512226633Sdim else 513226633Sdim OS << "EHFlavour"; 514226633Sdim OS << ") {\n" 515226633Sdim << " default:\n" 516234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 517226633Sdim 518226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 519226633Sdim OS << " case " << i << ":\n"; 520234353Sdim OS << " "; 521234353Sdim if (!isCtor) 522234353Sdim OS << "RI->"; 523234353Sdim std::string Tmp; 524234353Sdim raw_string_ostream(Tmp) << Namespace 525234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 526234353Sdim << "L2Dwarf"; 527234353Sdim OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 528234353Sdim if (j == 0) 529226633Sdim OS << "false"; 530226633Sdim else 531226633Sdim OS << "true"; 532234353Sdim OS << ");\n"; 533226633Sdim OS << " break;\n"; 534226633Sdim } 535226633Sdim OS << " }\n"; 536226633Sdim } 537226633Sdim} 538226633Sdim 539226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 540226633Sdim// Width is the number of bits per hex number. 541226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 542226633Sdim const BitVector &Bits, 543226633Sdim unsigned Width) { 544226633Sdim assert(Width <= 32 && "Width too large"); 545226633Sdim unsigned Digits = (Width + 3) / 4; 546226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 547226633Sdim unsigned Value = 0; 548226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 549226633Sdim Value |= Bits.test(i + j) << j; 550226633Sdim OS << format("0x%0*x, ", Digits, Value); 551226633Sdim } 552226633Sdim} 553226633Sdim 554226633Sdim// Helper to emit a set of bits into a constant byte array. 555226633Sdimclass BitVectorEmitter { 556226633Sdim BitVector Values; 557226633Sdimpublic: 558226633Sdim void add(unsigned v) { 559226633Sdim if (v >= Values.size()) 560226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 561226633Sdim Values[v] = true; 562226633Sdim } 563226633Sdim 564226633Sdim void print(raw_ostream &OS) { 565226633Sdim printBitVectorAsHex(OS, Values, 8); 566226633Sdim } 567226633Sdim}; 568226633Sdim 569234353Sdimstatic void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 570234353Sdim OS << getEnumName(VT); 571234353Sdim} 572234353Sdim 573239462Sdimstatic void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 574239462Sdim OS << Idx->EnumValue; 575239462Sdim} 576239462Sdim 577239462Sdim// Differentially encoded register and regunit lists allow for better 578239462Sdim// compression on regular register banks. The sequence is computed from the 579239462Sdim// differential list as: 580224145Sdim// 581239462Sdim// out[0] = InitVal; 582239462Sdim// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 583239462Sdim// 584239462Sdim// The initial value depends on the specific list. The list is terminated by a 585239462Sdim// 0 differential which means we can't encode repeated elements. 586239462Sdim 587239462Sdimtypedef SmallVector<uint16_t, 4> DiffVec; 588280031Sdimtypedef SmallVector<unsigned, 4> MaskVec; 589239462Sdim 590239462Sdim// Differentially encode a sequence of numbers into V. The starting value and 591239462Sdim// terminating 0 are not added to V, so it will have the same size as List. 592239462Sdimstatic 593288943SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 594239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 595239462Sdim uint16_t Val = uint16_t(InitVal); 596288943Sdim 597288943Sdim for (uint16_t Cur : List) { 598239462Sdim V.push_back(Cur - Val); 599239462Sdim Val = Cur; 600239462Sdim } 601239462Sdim return V; 602239462Sdim} 603239462Sdim 604239462Sdimtemplate<typename Iter> 605239462Sdimstatic 606239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 607239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 608239462Sdim uint16_t Val = uint16_t(InitVal); 609239462Sdim for (Iter I = Begin; I != End; ++I) { 610239462Sdim uint16_t Cur = (*I)->EnumValue; 611239462Sdim V.push_back(Cur - Val); 612239462Sdim Val = Cur; 613239462Sdim } 614239462Sdim return V; 615239462Sdim} 616239462Sdim 617239462Sdimstatic void printDiff16(raw_ostream &OS, uint16_t Val) { 618239462Sdim OS << Val; 619239462Sdim} 620239462Sdim 621280031Sdimstatic void printMask(raw_ostream &OS, unsigned Val) { 622280031Sdim OS << format("0x%08X", Val); 623280031Sdim} 624280031Sdim 625243830Sdim// Try to combine Idx's compose map into Vec if it is compatible. 626243830Sdim// Return false if it's not possible. 627243830Sdimstatic bool combine(const CodeGenSubRegIndex *Idx, 628243830Sdim SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 629243830Sdim const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 630288943Sdim for (const auto &I : Map) { 631288943Sdim CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 632288943Sdim if (Entry && Entry != I.second) 633243830Sdim return false; 634243830Sdim } 635243830Sdim 636243830Sdim // All entries are compatible. Make it so. 637288943Sdim for (const auto &I : Map) { 638288943Sdim auto *&Entry = Vec[I.first->EnumValue - 1]; 639288943Sdim assert((!Entry || Entry == I.second) && 640288943Sdim "Expected EnumValue to be unique"); 641288943Sdim Entry = I.second; 642288943Sdim } 643243830Sdim return true; 644243830Sdim} 645243830Sdim 646243830Sdimvoid 647243830SdimRegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 648243830Sdim CodeGenRegBank &RegBank, 649243830Sdim const std::string &ClName) { 650280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 651243830Sdim OS << "unsigned " << ClName 652243830Sdim << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 653243830Sdim 654243830Sdim // Many sub-register indexes are composition-compatible, meaning that 655243830Sdim // 656243830Sdim // compose(IdxA, IdxB) == compose(IdxA', IdxB) 657243830Sdim // 658243830Sdim // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 659243830Sdim // The illegal entries can be use as wildcards to compress the table further. 660243830Sdim 661243830Sdim // Map each Sub-register index to a compatible table row. 662243830Sdim SmallVector<unsigned, 4> RowMap; 663243830Sdim SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 664243830Sdim 665280031Sdim auto SubRegIndicesSize = 666280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 667280031Sdim for (const auto &Idx : SubRegIndices) { 668243830Sdim unsigned Found = ~0u; 669243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 670280031Sdim if (combine(&Idx, Rows[r])) { 671243830Sdim Found = r; 672243830Sdim break; 673243830Sdim } 674243830Sdim } 675243830Sdim if (Found == ~0u) { 676243830Sdim Found = Rows.size(); 677243830Sdim Rows.resize(Found + 1); 678280031Sdim Rows.back().resize(SubRegIndicesSize); 679280031Sdim combine(&Idx, Rows.back()); 680243830Sdim } 681243830Sdim RowMap.push_back(Found); 682243830Sdim } 683243830Sdim 684243830Sdim // Output the row map if there is multiple rows. 685243830Sdim if (Rows.size() > 1) { 686280031Sdim OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap[" 687280031Sdim << SubRegIndicesSize << "] = {\n "; 688280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 689243830Sdim OS << RowMap[i] << ", "; 690243830Sdim OS << "\n };\n"; 691243830Sdim } 692243830Sdim 693243830Sdim // Output the rows. 694280031Sdim OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1) 695280031Sdim << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 696243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 697243830Sdim OS << " { "; 698280031Sdim for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 699243830Sdim if (Rows[r][i]) 700243830Sdim OS << Rows[r][i]->EnumValue << ", "; 701243830Sdim else 702243830Sdim OS << "0, "; 703243830Sdim OS << "},\n"; 704243830Sdim } 705243830Sdim OS << " };\n\n"; 706243830Sdim 707280031Sdim OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 708280031Sdim << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 709243830Sdim if (Rows.size() > 1) 710243830Sdim OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 711243830Sdim else 712243830Sdim OS << " return Rows[0][IdxB];\n"; 713243830Sdim OS << "}\n\n"; 714243830Sdim} 715243830Sdim 716280031Sdimvoid 717280031SdimRegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 718280031Sdim CodeGenRegBank &RegBank, 719280031Sdim const std::string &ClName) { 720280031Sdim // See the comments in computeSubRegLaneMasks() for our goal here. 721280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 722280031Sdim 723280031Sdim // Create a list of Mask+Rotate operations, with equivalent entries merged. 724280031Sdim SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 725280031Sdim SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 726280031Sdim for (const auto &Idx : SubRegIndices) { 727280031Sdim const SmallVector<MaskRolPair, 1> &IdxSequence 728280031Sdim = Idx.CompositionLaneMaskTransform; 729280031Sdim 730280031Sdim unsigned Found = ~0u; 731280031Sdim unsigned SIdx = 0; 732280031Sdim unsigned NextSIdx; 733280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 734280031Sdim SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 735280031Sdim NextSIdx = SIdx + Sequence.size() + 1; 736288943Sdim if (Sequence == IdxSequence) { 737280031Sdim Found = SIdx; 738280031Sdim break; 739280031Sdim } 740280031Sdim } 741280031Sdim if (Found == ~0u) { 742280031Sdim Sequences.push_back(IdxSequence); 743280031Sdim Found = SIdx; 744280031Sdim } 745280031Sdim SubReg2SequenceIndexMap.push_back(Found); 746280031Sdim } 747280031Sdim 748280031Sdim OS << " struct MaskRolOp {\n" 749280031Sdim " unsigned Mask;\n" 750280031Sdim " uint8_t RotateLeft;\n" 751280031Sdim " };\n" 752309124Sdim " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 753280031Sdim unsigned Idx = 0; 754280031Sdim for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 755280031Sdim OS << " "; 756280031Sdim const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 757280031Sdim for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 758280031Sdim const MaskRolPair &P = Sequence[p]; 759280031Sdim OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft); 760280031Sdim } 761280031Sdim OS << "{ 0, 0 }"; 762280031Sdim if (s+1 != se) 763280031Sdim OS << ", "; 764280031Sdim OS << " // Sequence " << Idx << "\n"; 765280031Sdim Idx += Sequence.size() + 1; 766280031Sdim } 767280031Sdim OS << " };\n" 768288943Sdim " static const MaskRolOp *const CompositeSequences[] = {\n"; 769280031Sdim for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 770280031Sdim OS << " "; 771280031Sdim unsigned Idx = SubReg2SequenceIndexMap[i]; 772309124Sdim OS << format("&LaneMaskComposeSequences[%u]", Idx); 773280031Sdim if (i+1 != e) 774280031Sdim OS << ","; 775280031Sdim OS << " // to " << SubRegIndices[i].getName() << "\n"; 776280031Sdim } 777280031Sdim OS << " };\n\n"; 778280031Sdim 779309124Sdim OS << "LaneBitmask " << ClName 780309124Sdim << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 781309124Sdim " const {\n" 782309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 783280031Sdim << " && \"Subregister index out of bounds\");\n" 784309124Sdim " LaneBitmask Result = 0;\n" 785280031Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)" 786280031Sdim " {\n" 787309124Sdim " LaneBitmask Masked = LaneMask & Ops->Mask;\n" 788280031Sdim " Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n" 789280031Sdim " Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n" 790280031Sdim " }\n" 791280031Sdim " return Result;\n" 792309124Sdim "}\n\n"; 793309124Sdim 794309124Sdim OS << "LaneBitmask " << ClName 795309124Sdim << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 796309124Sdim " LaneBitmask LaneMask) const {\n" 797309124Sdim " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 798309124Sdim " --IdxA; assert(IdxA < " << SubRegIndices.size() 799309124Sdim << " && \"Subregister index out of bounds\");\n" 800309124Sdim " LaneBitmask Result = 0;\n" 801309124Sdim " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)" 802309124Sdim " {\n" 803309124Sdim " LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) |\n" 804309124Sdim " ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF);\n" 805309124Sdim " Result |= Rotated & Ops->Mask;\n" 806309124Sdim " }\n" 807309124Sdim " return Result;\n" 808309124Sdim "}\n\n"; 809280031Sdim} 810280031Sdim 811239462Sdim// 812224145Sdim// runMCDesc - Print out MC register descriptions. 813224145Sdim// 814224145Sdimvoid 815224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 816224145Sdim CodeGenRegBank &RegBank) { 817239462Sdim emitSourceFileHeader("MC Register Information", OS); 818224145Sdim 819224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 820309124Sdim OS << "#undef GET_REGINFO_MC_DESC\n\n"; 821224145Sdim 822280031Sdim const auto &Regs = RegBank.getRegisters(); 823224145Sdim 824280031Sdim auto &SubRegIndices = RegBank.getSubRegIndices(); 825261991Sdim // The lists of sub-registers and super-registers go in the same array. That 826261991Sdim // allows us to share suffixes. 827234353Sdim typedef std::vector<const CodeGenRegister*> RegVec; 828224145Sdim 829239462Sdim // Differentially encoded lists. 830239462Sdim SequenceToOffsetTable<DiffVec> DiffSeqs; 831239462Sdim SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 832239462Sdim SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 833239462Sdim SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 834239462Sdim SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 835239462Sdim 836280031Sdim // List of lane masks accompanying register unit sequences. 837280031Sdim SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 838280031Sdim SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 839280031Sdim 840239462Sdim // Keep track of sub-register names as well. These are not differentially 841239462Sdim // encoded. 842239462Sdim typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 843288943Sdim SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs; 844239462Sdim SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 845239462Sdim 846239462Sdim SequenceToOffsetTable<std::string> RegStrings; 847239462Sdim 848234353Sdim // Precompute register lists for the SequenceToOffsetTable. 849280031Sdim unsigned i = 0; 850280031Sdim for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 851280031Sdim const auto &Reg = *I; 852280031Sdim RegStrings.add(Reg.getName()); 853224145Sdim 854234353Sdim // Compute the ordered sub-register list. 855234353Sdim SetVector<const CodeGenRegister*> SR; 856280031Sdim Reg.addSubRegsPreOrder(SR, RegBank); 857280031Sdim diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 858239462Sdim DiffSeqs.add(SubRegLists[i]); 859224145Sdim 860239462Sdim // Compute the corresponding sub-register indexes. 861239462Sdim SubRegIdxVec &SRIs = SubRegIdxLists[i]; 862239462Sdim for (unsigned j = 0, je = SR.size(); j != je; ++j) 863280031Sdim SRIs.push_back(Reg.getSubRegIndex(SR[j])); 864239462Sdim SubRegIdxSeqs.add(SRIs); 865239462Sdim 866234353Sdim // Super-registers are already computed. 867280031Sdim const RegVec &SuperRegList = Reg.getSuperRegs(); 868280031Sdim diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 869280031Sdim SuperRegList.end()); 870239462Sdim DiffSeqs.add(SuperRegLists[i]); 871224145Sdim 872239462Sdim // Differentially encode the register unit list, seeded by register number. 873239462Sdim // First compute a scale factor that allows more diff-lists to be reused: 874239462Sdim // 875239462Sdim // D0 -> (S0, S1) 876239462Sdim // D1 -> (S2, S3) 877239462Sdim // 878239462Sdim // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 879239462Sdim // value for the differential decoder is the register number multiplied by 880239462Sdim // the scale. 881239462Sdim // 882239462Sdim // Check the neighboring registers for arithmetic progressions. 883239462Sdim unsigned ScaleA = ~0u, ScaleB = ~0u; 884288943Sdim SparseBitVector<> RUs = Reg.getNativeRegUnits(); 885280031Sdim if (I != Regs.begin() && 886288943Sdim std::prev(I)->getNativeRegUnits().count() == RUs.count()) 887288943Sdim ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 888280031Sdim if (std::next(I) != Regs.end() && 889288943Sdim std::next(I)->getNativeRegUnits().count() == RUs.count()) 890288943Sdim ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 891239462Sdim unsigned Scale = std::min(ScaleB, ScaleA); 892239462Sdim // Default the scale to 0 if it can't be encoded in 4 bits. 893239462Sdim if (Scale >= 16) 894239462Sdim Scale = 0; 895239462Sdim RegUnitInitScale[i] = Scale; 896280031Sdim DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 897280031Sdim 898280031Sdim const auto &RUMasks = Reg.getRegUnitLaneMasks(); 899280031Sdim MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 900280031Sdim assert(LaneMaskVec.empty()); 901280031Sdim LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 902280031Sdim // Terminator mask should not be used inside of the list. 903280031Sdim#ifndef NDEBUG 904280031Sdim for (unsigned M : LaneMaskVec) { 905280031Sdim assert(M != ~0u && "terminator mask should not be part of the list"); 906280031Sdim } 907280031Sdim#endif 908280031Sdim LaneMaskSeqs.add(LaneMaskVec); 909224145Sdim } 910224145Sdim 911234353Sdim // Compute the final layout of the sequence table. 912239462Sdim DiffSeqs.layout(); 913280031Sdim LaneMaskSeqs.layout(); 914239462Sdim SubRegIdxSeqs.layout(); 915234353Sdim 916234353Sdim OS << "namespace llvm {\n\n"; 917234353Sdim 918234353Sdim const std::string &TargetName = Target.getName(); 919234353Sdim 920239462Sdim // Emit the shared table of differential lists. 921249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 922239462Sdim DiffSeqs.emit(OS, printDiff16); 923234353Sdim OS << "};\n\n"; 924234353Sdim 925280031Sdim // Emit the shared table of regunit lane mask sequences. 926280031Sdim OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n"; 927280031Sdim LaneMaskSeqs.emit(OS, printMask, "~0u"); 928280031Sdim OS << "};\n\n"; 929280031Sdim 930239462Sdim // Emit the table of sub-register indexes. 931239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 932239462Sdim SubRegIdxSeqs.emit(OS, printSubRegIndex); 933239462Sdim OS << "};\n\n"; 934239462Sdim 935261991Sdim // Emit the table of sub-register index sizes. 936261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 937261991Sdim << TargetName << "SubRegIdxRanges[] = {\n"; 938261991Sdim OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 939280031Sdim for (const auto &Idx : SubRegIndices) { 940280031Sdim OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 941280031Sdim << Idx.getName() << "\n"; 942261991Sdim } 943261991Sdim OS << "};\n\n"; 944261991Sdim 945239462Sdim // Emit the string table. 946239462Sdim RegStrings.layout(); 947239462Sdim OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 948239462Sdim RegStrings.emit(OS, printChar); 949239462Sdim OS << "};\n\n"; 950239462Sdim 951234353Sdim OS << "extern const MCRegisterDesc " << TargetName 952224145Sdim << "RegDesc[] = { // Descriptors\n"; 953280031Sdim OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 954224145Sdim 955234353Sdim // Emit the register descriptors now. 956280031Sdim i = 0; 957280031Sdim for (const auto &Reg : Regs) { 958280031Sdim OS << " { " << RegStrings.get(Reg.getName()) << ", " 959280031Sdim << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 960280031Sdim << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 961280031Sdim << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 962280031Sdim << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 963280031Sdim ++i; 964224145Sdim } 965224145Sdim OS << "};\n\n"; // End of register descriptors... 966224145Sdim 967239462Sdim // Emit the table of register unit roots. Each regunit has one or two root 968239462Sdim // registers. 969276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 970239462Sdim for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 971239462Sdim ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 972239462Sdim assert(!Roots.empty() && "All regunits must have a root register."); 973239462Sdim assert(Roots.size() <= 2 && "More than two roots not supported yet."); 974239462Sdim OS << " { " << getQualifiedName(Roots.front()->TheDef); 975239462Sdim for (unsigned r = 1; r != Roots.size(); ++r) 976239462Sdim OS << ", " << getQualifiedName(Roots[r]->TheDef); 977239462Sdim OS << " },\n"; 978239462Sdim } 979239462Sdim OS << "};\n\n"; 980239462Sdim 981280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 982226633Sdim 983226633Sdim // Loop over all of the register classes... emitting each one. 984226633Sdim OS << "namespace { // Register classes...\n"; 985226633Sdim 986280031Sdim SequenceToOffsetTable<std::string> RegClassStrings; 987280031Sdim 988226633Sdim // Emit the register enum value arrays for each RegisterClass 989280031Sdim for (const auto &RC : RegisterClasses) { 990226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 991226633Sdim 992226633Sdim // Give the register class a legal C name if it's anonymous. 993309124Sdim const std::string &Name = RC.getName(); 994226633Sdim 995280031Sdim RegClassStrings.add(Name); 996280031Sdim 997226633Sdim // Emit the register list now. 998226633Sdim OS << " // " << Name << " Register Class...\n" 999276479Sdim << " const MCPhysReg " << Name 1000226633Sdim << "[] = {\n "; 1001226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 1002226633Sdim Record *Reg = Order[i]; 1003226633Sdim OS << getQualifiedName(Reg) << ", "; 1004226633Sdim } 1005226633Sdim OS << "\n };\n\n"; 1006226633Sdim 1007226633Sdim OS << " // " << Name << " Bit set.\n" 1008234353Sdim << " const uint8_t " << Name 1009226633Sdim << "Bits[] = {\n "; 1010226633Sdim BitVectorEmitter BVE; 1011226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 1012226633Sdim Record *Reg = Order[i]; 1013226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1014226633Sdim } 1015226633Sdim BVE.print(OS); 1016226633Sdim OS << "\n };\n\n"; 1017226633Sdim 1018226633Sdim } 1019309124Sdim OS << "} // end anonymous namespace\n\n"; 1020226633Sdim 1021280031Sdim RegClassStrings.layout(); 1022280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 1023280031Sdim RegClassStrings.emit(OS, printChar); 1024280031Sdim OS << "};\n\n"; 1025280031Sdim 1026234353Sdim OS << "extern const MCRegisterClass " << TargetName 1027234353Sdim << "MCRegisterClasses[] = {\n"; 1028226633Sdim 1029280031Sdim for (const auto &RC : RegisterClasses) { 1030234353Sdim // Asserts to make sure values will fit in table assuming types from 1031234353Sdim // MCRegisterInfo.h 1032234353Sdim assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); 1033234353Sdim assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); 1034234353Sdim assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); 1035234353Sdim 1036280031Sdim OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1037280031Sdim << RegClassStrings.get(RC.getName()) << ", " 1038234353Sdim << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1039234353Sdim << RC.getQualifiedName() + "RegClassID" << ", " 1040226633Sdim << RC.SpillSize/8 << ", " 1041226633Sdim << RC.SpillAlignment/8 << ", " 1042226633Sdim << RC.CopyCost << ", " 1043309124Sdim << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1044226633Sdim } 1045226633Sdim 1046226633Sdim OS << "};\n\n"; 1047226633Sdim 1048239462Sdim EmitRegMappingTables(OS, Regs, false); 1049239462Sdim 1050239462Sdim // Emit Reg encoding table 1051239462Sdim OS << "extern const uint16_t " << TargetName; 1052239462Sdim OS << "RegEncodingTable[] = {\n"; 1053239462Sdim // Add entry for NoRegister 1054239462Sdim OS << " 0,\n"; 1055280031Sdim for (const auto &RE : Regs) { 1056280031Sdim Record *Reg = RE.TheDef; 1057239462Sdim BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1058239462Sdim uint64_t Value = 0; 1059239462Sdim for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1060243830Sdim if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1061276479Sdim Value |= (uint64_t)B->getValue() << b; 1062234353Sdim } 1063239462Sdim OS << " " << Value << ",\n"; 1064234353Sdim } 1065239462Sdim OS << "};\n"; // End of HW encoding table 1066234353Sdim 1067224145Sdim // MCRegisterInfo initialization routine. 1068224145Sdim OS << "static inline void Init" << TargetName 1069226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1070280031Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1071280031Sdim "{\n" 1072239462Sdim << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1073280031Sdim << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1074280031Sdim << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1075280031Sdim << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1076280031Sdim << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1077280031Sdim << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1078280031Sdim << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1079280031Sdim << TargetName << "SubRegIdxRanges, " << TargetName 1080280031Sdim << "RegEncodingTable);\n\n"; 1081224145Sdim 1082226633Sdim EmitRegMapping(OS, Regs, false); 1083226633Sdim 1084226633Sdim OS << "}\n\n"; 1085226633Sdim 1086309124Sdim OS << "} // end namespace llvm\n\n"; 1087224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1088224145Sdim} 1089224145Sdim 1090224145Sdimvoid 1091224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1092224145Sdim CodeGenRegBank &RegBank) { 1093239462Sdim emitSourceFileHeader("Register Information Header Fragment", OS); 1094224145Sdim 1095224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1096309124Sdim OS << "#undef GET_REGINFO_HEADER\n\n"; 1097224145Sdim 1098193323Sed const std::string &TargetName = Target.getName(); 1099193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 1100193323Sed 1101234353Sdim OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; 1102193323Sed 1103193323Sed OS << "namespace llvm {\n\n"; 1104193323Sed 1105288943Sdim OS << "class " << TargetName << "FrameLowering;\n\n"; 1106288943Sdim 1107193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1108226633Sdim << " explicit " << ClassName 1109296417Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"; 1110239462Sdim if (!RegBank.getSubRegIndices().empty()) { 1111276479Sdim OS << " unsigned composeSubRegIndicesImpl" 1112276479Sdim << "(unsigned, unsigned) const override;\n" 1113309124Sdim << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1114309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1115309124Sdim << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1116309124Sdim << "(unsigned, LaneBitmask) const override;\n" 1117276479Sdim << " const TargetRegisterClass *getSubClassWithSubReg" 1118276479Sdim << "(const TargetRegisterClass*, unsigned) const override;\n"; 1119239462Sdim } 1120276479Sdim OS << " const RegClassWeight &getRegClassWeight(" 1121276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1122276479Sdim << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1123276479Sdim << " unsigned getNumRegPressureSets() const override;\n" 1124276479Sdim << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1125288943Sdim << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1126288943Sdim "Idx) const override;\n" 1127276479Sdim << " const int *getRegClassPressureSets(" 1128276479Sdim << "const TargetRegisterClass *RC) const override;\n" 1129276479Sdim << " const int *getRegUnitPressureSets(" 1130276479Sdim << "unsigned RegUnit) const override;\n" 1131288943Sdim << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1132288943Sdim << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1133288943Sdim << " /// Devirtualized TargetFrameLowering.\n" 1134288943Sdim << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1135288943Sdim << " const MachineFunction &MF);\n" 1136193323Sed << "};\n\n"; 1137193323Sed 1138280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1139193323Sed 1140193323Sed if (!RegisterClasses.empty()) { 1141280031Sdim OS << "namespace " << RegisterClasses.front().Namespace 1142193323Sed << " { // Register classes\n"; 1143221345Sdim 1144280031Sdim for (const auto &RC : RegisterClasses) { 1145224145Sdim const std::string &Name = RC.getName(); 1146193323Sed 1147193323Sed // Output the extern for the instance. 1148234353Sdim OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1149193323Sed } 1150309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1151193323Sed } 1152309124Sdim OS << "} // end namespace llvm\n\n"; 1153224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 1154193323Sed} 1155193323Sed 1156224145Sdim// 1157224145Sdim// runTargetDesc - Output the target register and register file descriptions. 1158224145Sdim// 1159224145Sdimvoid 1160224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1161224145Sdim CodeGenRegBank &RegBank){ 1162239462Sdim emitSourceFileHeader("Target Register and Register Classes Information", OS); 1163193323Sed 1164224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1165309124Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1166193323Sed 1167193323Sed OS << "namespace llvm {\n\n"; 1168193323Sed 1169226633Sdim // Get access to MCRegisterClass data. 1170234353Sdim OS << "extern const MCRegisterClass " << Target.getName() 1171234353Sdim << "MCRegisterClasses[];\n"; 1172226633Sdim 1173223017Sdim // Start out by emitting each of the register classes. 1174280031Sdim const auto &RegisterClasses = RegBank.getRegClasses(); 1175280031Sdim const auto &SubRegIndices = RegBank.getSubRegIndices(); 1176193323Sed 1177223017Sdim // Collect all registers belonging to any allocatable class. 1178223017Sdim std::set<Record*> AllocatableRegs; 1179223017Sdim 1180226633Sdim // Collect allocatable registers. 1181280031Sdim for (const auto &RC : RegisterClasses) { 1182224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 1183193323Sed 1184223017Sdim if (RC.Allocatable) 1185224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 1186226633Sdim } 1187223017Sdim 1188234353Sdim // Build a shared array of value types. 1189249423Sdim SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; 1190280031Sdim for (const auto &RC : RegisterClasses) 1191280031Sdim VTSeqs.add(RC.VTs); 1192234353Sdim VTSeqs.layout(); 1193234353Sdim OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1194234353Sdim VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1195234353Sdim OS << "};\n"; 1196221345Sdim 1197243830Sdim // Emit SubRegIndex names, skipping 0. 1198243830Sdim OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1199280031Sdim 1200280031Sdim for (const auto &Idx : SubRegIndices) { 1201280031Sdim OS << Idx.getName(); 1202280031Sdim OS << "\", \""; 1203239462Sdim } 1204239462Sdim OS << "\" };\n\n"; 1205239462Sdim 1206243830Sdim // Emit SubRegIndex lane masks, including 0. 1207243830Sdim OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; 1208280031Sdim for (const auto &Idx : SubRegIndices) { 1209280031Sdim OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n'; 1210243830Sdim } 1211243830Sdim OS << " };\n\n"; 1212243830Sdim 1213239462Sdim OS << "\n"; 1214239462Sdim 1215193323Sed // Now that all of the structs have been emitted, emit the instances. 1216193323Sed if (!RegisterClasses.empty()) { 1217234353Sdim OS << "\nstatic const TargetRegisterClass *const " 1218276479Sdim << "NullRegClasses[] = { nullptr };\n\n"; 1219226633Sdim 1220239462Sdim // Emit register class bit mask tables. The first bit mask emitted for a 1221239462Sdim // register class, RC, is the set of sub-classes, including RC itself. 1222239462Sdim // 1223239462Sdim // If RC has super-registers, also create a list of subreg indices and bit 1224239462Sdim // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1225239462Sdim // SuperRC, that satisfies: 1226239462Sdim // 1227239462Sdim // For all SuperReg in SuperRC: SuperReg:Idx in RC 1228239462Sdim // 1229239462Sdim // The 0-terminated list of subreg indices starts at: 1230239462Sdim // 1231239462Sdim // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1232239462Sdim // 1233239462Sdim // The corresponding bitmasks follow the sub-class mask in memory. Each 1234239462Sdim // mask has RCMaskWords uint32_t entries. 1235239462Sdim // 1236239462Sdim // Every bit mask present in the list has at least one bit set. 1237193323Sed 1238239462Sdim // Compress the sub-reg index lists. 1239239462Sdim typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1240239462Sdim SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1241288943Sdim SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs; 1242239462Sdim BitVector MaskBV(RegisterClasses.size()); 1243193323Sed 1244280031Sdim for (const auto &RC : RegisterClasses) { 1245239462Sdim OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; 1246239462Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1247193323Sed 1248239462Sdim // Emit super-reg class masks for any relevant SubRegIndices that can 1249239462Sdim // project into RC. 1250280031Sdim IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1251280031Sdim for (auto &Idx : SubRegIndices) { 1252239462Sdim MaskBV.reset(); 1253280031Sdim RC.getSuperRegClasses(&Idx, MaskBV); 1254239462Sdim if (MaskBV.none()) 1255239462Sdim continue; 1256280031Sdim SRIList.push_back(&Idx); 1257239462Sdim OS << "\n "; 1258239462Sdim printBitVectorAsHex(OS, MaskBV, 32); 1259280031Sdim OS << "// " << Idx.getName(); 1260239462Sdim } 1261239462Sdim SuperRegIdxSeqs.add(SRIList); 1262234353Sdim OS << "\n};\n\n"; 1263193323Sed } 1264193323Sed 1265239462Sdim OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1266239462Sdim SuperRegIdxSeqs.layout(); 1267239462Sdim SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1268239462Sdim OS << "};\n\n"; 1269239462Sdim 1270226633Sdim // Emit NULL terminated super-class lists. 1271280031Sdim for (const auto &RC : RegisterClasses) { 1272226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1273193323Sed 1274226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 1275226633Sdim if (Supers.empty()) 1276226633Sdim continue; 1277193323Sed 1278234353Sdim OS << "static const TargetRegisterClass *const " 1279226633Sdim << RC.getName() << "Superclasses[] = {\n"; 1280280031Sdim for (const auto *Super : Supers) 1281280031Sdim OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1282276479Sdim OS << " nullptr\n};\n\n"; 1283193323Sed } 1284193323Sed 1285224145Sdim // Emit methods. 1286280031Sdim for (const auto &RC : RegisterClasses) { 1287224145Sdim if (!RC.AltOrderSelect.empty()) { 1288224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 1289224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 1290234353Sdim << RC.AltOrderSelect << "}\n\n" 1291249423Sdim << "static ArrayRef<MCPhysReg> " << RC.getName() 1292234353Sdim << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1293224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1294224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 1295234353Sdim if (!Elems.empty()) { 1296249423Sdim OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1297234353Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 1298234353Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1299234353Sdim OS << " };\n"; 1300234353Sdim } 1301224145Sdim } 1302226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 1303234353Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1304249423Sdim << " const ArrayRef<MCPhysReg> Order[] = {\n" 1305226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1306224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1307234353Sdim if (RC.getOrder(oi).empty()) 1308249423Sdim OS << "),\n ArrayRef<MCPhysReg>("; 1309234353Sdim else 1310234353Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 1311224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 1312224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1313224145Sdim << ");\n return Order[Select];\n}\n"; 1314280031Sdim } 1315193323Sed } 1316221345Sdim 1317234353Sdim // Now emit the actual value-initialized register class instances. 1318280031Sdim OS << "\nnamespace " << RegisterClasses.front().Namespace 1319234353Sdim << " { // Register class instances\n"; 1320234353Sdim 1321280031Sdim for (const auto &RC : RegisterClasses) { 1322280031Sdim OS << " extern const TargetRegisterClass " << RC.getName() 1323280031Sdim << "RegClass = {\n " << '&' << Target.getName() 1324280031Sdim << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1325280031Sdim << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName() 1326280031Sdim << "SubClassMask,\n SuperRegIdxSeqs + " 1327280031Sdim << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n " 1328288943Sdim << format("0x%08x,\n ", RC.LaneMask) 1329288943Sdim << (unsigned)RC.AllocationPriority << ",\n " 1330288943Sdim << (RC.HasDisjunctSubRegs?"true":"false") 1331309124Sdim << ", /* HasDisjunctSubRegs */\n " 1332309124Sdim << (RC.CoveredBySubRegs?"true":"false") 1333309124Sdim << ", /* CoveredBySubRegs */\n "; 1334234353Sdim if (RC.getSuperClasses().empty()) 1335234353Sdim OS << "NullRegClasses,\n "; 1336234353Sdim else 1337234353Sdim OS << RC.getName() << "Superclasses,\n "; 1338234353Sdim if (RC.AltOrderSelect.empty()) 1339276479Sdim OS << "nullptr\n"; 1340234353Sdim else 1341234353Sdim OS << RC.getName() << "GetRawAllocationOrder\n"; 1342234353Sdim OS << " };\n\n"; 1343234353Sdim } 1344234353Sdim 1345309124Sdim OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1346193323Sed } 1347193323Sed 1348193323Sed OS << "\nnamespace {\n"; 1349193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1350280031Sdim for (const auto &RC : RegisterClasses) 1351280031Sdim OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1352193323Sed OS << " };\n"; 1353309124Sdim OS << "} // end anonymous namespace\n"; 1354193323Sed 1355224145Sdim // Emit extra information about registers. 1356224145Sdim const std::string &TargetName = Target.getName(); 1357234353Sdim OS << "\nstatic const TargetRegisterInfoDesc " 1358234353Sdim << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1359309124Sdim OS << " { 0, false },\n"; 1360221345Sdim 1361280031Sdim const auto &Regs = RegBank.getRegisters(); 1362280031Sdim for (const auto &Reg : Regs) { 1363234353Sdim OS << " { "; 1364224145Sdim OS << Reg.CostPerUse << ", " 1365309124Sdim << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1366309124Sdim << " },\n"; 1367193323Sed } 1368234353Sdim OS << "};\n"; // End of register descriptors... 1369208599Srdivacky 1370224145Sdim 1371193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 1372193323Sed 1373280031Sdim auto SubRegIndicesSize = 1374280031Sdim std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1375280031Sdim 1376280031Sdim if (!SubRegIndices.empty()) { 1377243830Sdim emitComposeSubRegIndices(OS, RegBank, ClassName); 1378280031Sdim emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1379280031Sdim } 1380210299Sed 1381226633Sdim // Emit getSubClassWithSubReg. 1382239462Sdim if (!SubRegIndices.empty()) { 1383239462Sdim OS << "const TargetRegisterClass *" << ClassName 1384239462Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1385239462Sdim << " const {\n"; 1386226633Sdim // Use the smallest type that can hold a regclass ID with room for a 1387226633Sdim // sentinel. 1388226633Sdim if (RegisterClasses.size() < UINT8_MAX) 1389226633Sdim OS << " static const uint8_t Table["; 1390226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 1391226633Sdim OS << " static const uint16_t Table["; 1392226633Sdim else 1393243830Sdim PrintFatalError("Too many register classes."); 1394280031Sdim OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1395280031Sdim for (const auto &RC : RegisterClasses) { 1396226633Sdim OS << " {\t// " << RC.getName() << "\n"; 1397280031Sdim for (auto &Idx : SubRegIndices) { 1398280031Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1399280031Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1400226633Sdim << " -> " << SRC->getName() << "\n"; 1401226633Sdim else 1402280031Sdim OS << " 0,\t// " << Idx.getName() << "\n"; 1403226633Sdim } 1404226633Sdim OS << " },\n"; 1405226633Sdim } 1406226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 1407226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 1408280031Sdim << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1409226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 1410276479Sdim << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1411226633Sdim } 1412226633Sdim 1413234353Sdim EmitRegUnitPressure(OS, RegBank, ClassName); 1414234353Sdim 1415193323Sed // Emit the constructor of the class... 1416234353Sdim OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1417249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1418280031Sdim OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n"; 1419239462Sdim OS << "extern const char " << TargetName << "RegStrings[];\n"; 1420280031Sdim OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1421276479Sdim OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1422239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1423261991Sdim OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1424261991Sdim << TargetName << "SubRegIdxRanges[];\n"; 1425239462Sdim OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1426224145Sdim 1427234353Sdim EmitRegMappingTables(OS, Regs, true); 1428234353Sdim 1429234353Sdim OS << ClassName << "::\n" << ClassName 1430249423Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" 1431224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1432208599Srdivacky << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 1433261991Sdim << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x"; 1434261991Sdim OS.write_hex(RegBank.CoveringLanes); 1435261991Sdim OS << ") {\n" 1436280031Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1437280031Sdim << ", RA, PC,\n " << TargetName 1438234353Sdim << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1439239462Sdim << " " << TargetName << "RegUnitRoots,\n" 1440239462Sdim << " " << RegBank.getNumNativeRegUnits() << ",\n" 1441239462Sdim << " " << TargetName << "RegDiffLists,\n" 1442280031Sdim << " " << TargetName << "LaneMaskLists,\n" 1443239462Sdim << " " << TargetName << "RegStrings,\n" 1444280031Sdim << " " << TargetName << "RegClassStrings,\n" 1445239462Sdim << " " << TargetName << "SubRegIdxLists,\n" 1446280031Sdim << " " << SubRegIndicesSize + 1 << ",\n" 1447261991Sdim << " " << TargetName << "SubRegIdxRanges,\n" 1448239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 1449193323Sed 1450226633Sdim EmitRegMapping(OS, Regs, true); 1451193323Sed 1452226633Sdim OS << "}\n\n"; 1453193323Sed 1454234353Sdim // Emit CalleeSavedRegs information. 1455234353Sdim std::vector<Record*> CSRSets = 1456234353Sdim Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1457234353Sdim for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1458234353Sdim Record *CSRSet = CSRSets[i]; 1459234353Sdim const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1460234353Sdim assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1461234353Sdim 1462234353Sdim // Emit the *_SaveList list of callee-saved registers. 1463249423Sdim OS << "static const MCPhysReg " << CSRSet->getName() 1464234353Sdim << "_SaveList[] = { "; 1465234353Sdim for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1466234353Sdim OS << getQualifiedName((*Regs)[r]) << ", "; 1467234353Sdim OS << "0 };\n"; 1468234353Sdim 1469234353Sdim // Emit the *_RegMask bit mask of call-preserved registers. 1470261991Sdim BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1471261991Sdim 1472261991Sdim // Check for an optional OtherPreserved set. 1473261991Sdim // Add those registers to RegMask, but not to SaveList. 1474261991Sdim if (DagInit *OPDag = 1475261991Sdim dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1476261991Sdim SetTheory::RecSet OPSet; 1477261991Sdim RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1478261991Sdim Covered |= RegBank.computeCoveredRegisters( 1479261991Sdim ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1480261991Sdim } 1481261991Sdim 1482234353Sdim OS << "static const uint32_t " << CSRSet->getName() 1483234353Sdim << "_RegMask[] = { "; 1484261991Sdim printBitVectorAsHex(OS, Covered, 32); 1485234353Sdim OS << "};\n"; 1486234353Sdim } 1487234353Sdim OS << "\n\n"; 1488234353Sdim 1489288943Sdim OS << "ArrayRef<const uint32_t *> " << ClassName 1490288943Sdim << "::getRegMasks() const {\n"; 1491296417Sdim if (!CSRSets.empty()) { 1492296417Sdim OS << " static const uint32_t *const Masks[] = {\n"; 1493296417Sdim for (Record *CSRSet : CSRSets) 1494296417Sdim OS << " " << CSRSet->getName() << "_RegMask,\n"; 1495296417Sdim OS << " };\n"; 1496296417Sdim OS << " return makeArrayRef(Masks);\n"; 1497296417Sdim } else { 1498296417Sdim OS << " return None;\n"; 1499296417Sdim } 1500288943Sdim OS << "}\n\n"; 1501288943Sdim 1502288943Sdim OS << "ArrayRef<const char *> " << ClassName 1503288943Sdim << "::getRegMaskNames() const {\n"; 1504296417Sdim if (!CSRSets.empty()) { 1505296417Sdim OS << " static const char *const Names[] = {\n"; 1506296417Sdim for (Record *CSRSet : CSRSets) 1507296417Sdim OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1508296417Sdim OS << " };\n"; 1509296417Sdim OS << " return makeArrayRef(Names);\n"; 1510296417Sdim } else { 1511296417Sdim OS << " return None;\n"; 1512296417Sdim } 1513288943Sdim OS << "}\n\n"; 1514288943Sdim 1515296417Sdim OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1516296417Sdim << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1517288943Sdim << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1518288943Sdim << " MF.getSubtarget().getFrameLowering());\n" 1519288943Sdim << "}\n\n"; 1520288943Sdim 1521309124Sdim OS << "} // end namespace llvm\n\n"; 1522224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1523193323Sed} 1524224145Sdim 1525224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 1526224145Sdim CodeGenTarget Target(Records); 1527224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1528224145Sdim RegBank.computeDerivedInfo(); 1529224145Sdim 1530224145Sdim runEnums(OS, Target, RegBank); 1531224145Sdim runMCDesc(OS, Target, RegBank); 1532224145Sdim runTargetHeader(OS, Target, RegBank); 1533224145Sdim runTargetDesc(OS, Target, RegBank); 1534224145Sdim} 1535239462Sdim 1536239462Sdimnamespace llvm { 1537239462Sdim 1538239462Sdimvoid EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1539239462Sdim RegisterInfoEmitter(RK).run(OS); 1540239462Sdim} 1541239462Sdim 1542309124Sdim} // end namespace llvm 1543