RegisterInfoEmitter.cpp revision 249423
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16239462Sdim#include "CodeGenRegisters.h" 17193323Sed#include "CodeGenTarget.h" 18234353Sdim#include "SequenceToOffsetTable.h" 19226633Sdim#include "llvm/ADT/BitVector.h" 20239462Sdim#include "llvm/ADT/STLExtras.h" 21193323Sed#include "llvm/ADT/StringExtras.h" 22234982Sdim#include "llvm/ADT/Twine.h" 23224145Sdim#include "llvm/Support/Format.h" 24239462Sdim#include "llvm/TableGen/Error.h" 25239462Sdim#include "llvm/TableGen/Record.h" 26239462Sdim#include "llvm/TableGen/TableGenBackend.h" 27195340Sed#include <algorithm> 28193323Sed#include <set> 29239462Sdim#include <vector> 30193323Sedusing namespace llvm; 31193323Sed 32239462Sdimnamespace { 33239462Sdimclass RegisterInfoEmitter { 34239462Sdim RecordKeeper &Records; 35239462Sdimpublic: 36239462Sdim RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 37239462Sdim 38239462Sdim // runEnums - Print out enum values for all of the registers. 39239462Sdim void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 40239462Sdim 41239462Sdim // runMCDesc - Print out MC register descriptions. 42239462Sdim void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 43239462Sdim 44239462Sdim // runTargetHeader - Emit a header fragment for the register info emitter. 45239462Sdim void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 46239462Sdim CodeGenRegBank &Bank); 47239462Sdim 48239462Sdim // runTargetDesc - Output the target register and register file descriptions. 49239462Sdim void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 50239462Sdim CodeGenRegBank &Bank); 51239462Sdim 52239462Sdim // run - Output the register file description. 53239462Sdim void run(raw_ostream &o); 54239462Sdim 55239462Sdimprivate: 56239462Sdim void EmitRegMapping(raw_ostream &o, 57239462Sdim const std::vector<CodeGenRegister*> &Regs, bool isCtor); 58239462Sdim void EmitRegMappingTables(raw_ostream &o, 59239462Sdim const std::vector<CodeGenRegister*> &Regs, 60239462Sdim bool isCtor); 61239462Sdim void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target); 62239462Sdim 63239462Sdim void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 64239462Sdim const std::string &ClassName); 65243830Sdim void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 66243830Sdim const std::string &ClassName); 67239462Sdim}; 68239462Sdim} // End anonymous namespace 69239462Sdim 70193323Sed// runEnums - Print out enum values for all of the registers. 71234982Sdimvoid RegisterInfoEmitter::runEnums(raw_ostream &OS, 72234982Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 73224145Sdim const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 74193323Sed 75234982Sdim // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 76234353Sdim assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 77234353Sdim 78224145Sdim std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 79193323Sed 80239462Sdim emitSourceFileHeader("Target Register Enum Values", OS); 81224145Sdim 82224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 83224145Sdim OS << "#undef GET_REGINFO_ENUM\n"; 84224145Sdim 85193323Sed OS << "namespace llvm {\n\n"; 86193323Sed 87226633Sdim OS << "class MCRegisterClass;\n" 88234353Sdim << "extern const MCRegisterClass " << Namespace 89234353Sdim << "MCRegisterClasses[];\n\n"; 90226633Sdim 91193323Sed if (!Namespace.empty()) 92193323Sed OS << "namespace " << Namespace << " {\n"; 93208599Srdivacky OS << "enum {\n NoRegister,\n"; 94193323Sed 95193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) 96224145Sdim OS << " " << Registers[i]->getName() << " = " << 97224145Sdim Registers[i]->EnumValue << ",\n"; 98224145Sdim assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 99221345Sdim "Register enum value mismatch!"); 100208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 101208599Srdivacky OS << "};\n"; 102193323Sed if (!Namespace.empty()) 103193323Sed OS << "}\n"; 104208599Srdivacky 105226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); 106224145Sdim if (!RegisterClasses.empty()) { 107234353Sdim 108234353Sdim // RegisterClass enums are stored as uint16_t in the tables. 109234353Sdim assert(RegisterClasses.size() <= 0xffff && 110234353Sdim "Too many register classes to fit in tables"); 111234353Sdim 112224145Sdim OS << "\n// Register classes\n"; 113208599Srdivacky if (!Namespace.empty()) 114208599Srdivacky OS << "namespace " << Namespace << " {\n"; 115224145Sdim OS << "enum {\n"; 116224145Sdim for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 117224145Sdim if (i) OS << ",\n"; 118226633Sdim OS << " " << RegisterClasses[i]->getName() << "RegClassID"; 119224145Sdim OS << " = " << i; 120224145Sdim } 121224145Sdim OS << "\n };\n"; 122224145Sdim if (!Namespace.empty()) 123224145Sdim OS << "}\n"; 124224145Sdim } 125224145Sdim 126224145Sdim const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 127224145Sdim // If the only definition is the default NoRegAltName, we don't need to 128224145Sdim // emit anything. 129224145Sdim if (RegAltNameIndices.size() > 1) { 130224145Sdim OS << "\n// Register alternate name indices\n"; 131224145Sdim if (!Namespace.empty()) 132224145Sdim OS << "namespace " << Namespace << " {\n"; 133224145Sdim OS << "enum {\n"; 134224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 135224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 136224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 137208599Srdivacky OS << "};\n"; 138208599Srdivacky if (!Namespace.empty()) 139208599Srdivacky OS << "}\n"; 140208599Srdivacky } 141224145Sdim 142234353Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices(); 143234353Sdim if (!SubRegIndices.empty()) { 144234353Sdim OS << "\n// Subregister indices\n"; 145234353Sdim std::string Namespace = 146234353Sdim SubRegIndices[0]->getNamespace(); 147234353Sdim if (!Namespace.empty()) 148234353Sdim OS << "namespace " << Namespace << " {\n"; 149234353Sdim OS << "enum {\n NoSubRegister,\n"; 150239462Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 151234353Sdim OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 152239462Sdim OS << " NUM_TARGET_SUBREGS\n};\n"; 153234353Sdim if (!Namespace.empty()) 154234353Sdim OS << "}\n"; 155234353Sdim } 156224145Sdim 157193323Sed OS << "} // End llvm namespace \n"; 158224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 159193323Sed} 160193323Sed 161234353Sdimvoid RegisterInfoEmitter:: 162234353SdimEmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 163234353Sdim const std::string &ClassName) { 164234353Sdim unsigned NumRCs = RegBank.getRegClasses().size(); 165234353Sdim unsigned NumSets = RegBank.getNumRegPressureSets(); 166234353Sdim 167234353Sdim OS << "/// Get the weight in units of pressure for this register class.\n" 168234353Sdim << "const RegClassWeight &" << ClassName << "::\n" 169234353Sdim << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 170234353Sdim << " static const RegClassWeight RCWeightTable[] = {\n"; 171234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 172234353Sdim const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; 173234353Sdim const CodeGenRegister::Set &Regs = RC.getMembers(); 174234353Sdim if (Regs.empty()) 175234353Sdim OS << " {0, 0"; 176234353Sdim else { 177234353Sdim std::vector<unsigned> RegUnits; 178234353Sdim RC.buildRegUnitSet(RegUnits); 179234353Sdim OS << " {" << (*Regs.begin())->getWeight(RegBank) 180234353Sdim << ", " << RegBank.getRegUnitSetWeight(RegUnits); 181234353Sdim } 182234353Sdim OS << "}, \t// " << RC.getName() << "\n"; 183234353Sdim } 184234353Sdim OS << " {0, 0} };\n" 185234353Sdim << " return RCWeightTable[RC->getID()];\n" 186234353Sdim << "}\n\n"; 187234353Sdim 188249423Sdim // Reasonable targets (not ARMv7) have unit weight for all units, so don't 189249423Sdim // bother generating a table. 190249423Sdim bool RegUnitsHaveUnitWeight = true; 191249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 192249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 193249423Sdim if (RegBank.getRegUnit(UnitIdx).Weight > 1) 194249423Sdim RegUnitsHaveUnitWeight = false; 195249423Sdim } 196249423Sdim OS << "/// Get the weight in units of pressure for this register unit.\n" 197249423Sdim << "unsigned " << ClassName << "::\n" 198249423Sdim << "getRegUnitWeight(unsigned RegUnit) const {\n" 199249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 200249423Sdim << " && \"invalid register unit\");\n"; 201249423Sdim if (!RegUnitsHaveUnitWeight) { 202249423Sdim OS << " static const uint8_t RUWeightTable[] = {\n "; 203249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 204249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 205249423Sdim const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 206249423Sdim assert(RU.Weight < 256 && "RegUnit too heavy"); 207249423Sdim OS << RU.Weight << ", "; 208249423Sdim } 209249423Sdim OS << "0 };\n" 210249423Sdim << " return RUWeightTable[RegUnit];\n"; 211249423Sdim } 212249423Sdim else { 213249423Sdim OS << " // All register units have unit weight.\n" 214249423Sdim << " return 1;\n"; 215249423Sdim } 216249423Sdim OS << "}\n\n"; 217249423Sdim 218234353Sdim OS << "\n" 219234353Sdim << "// Get the number of dimensions of register pressure.\n" 220234353Sdim << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 221234353Sdim << " return " << NumSets << ";\n}\n\n"; 222234353Sdim 223239462Sdim OS << "// Get the name of this register unit pressure set.\n" 224239462Sdim << "const char *" << ClassName << "::\n" 225239462Sdim << "getRegPressureSetName(unsigned Idx) const {\n" 226239462Sdim << " static const char *PressureNameTable[] = {\n"; 227239462Sdim for (unsigned i = 0; i < NumSets; ++i ) { 228239462Sdim OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n"; 229239462Sdim } 230239462Sdim OS << " 0 };\n" 231239462Sdim << " return PressureNameTable[Idx];\n" 232239462Sdim << "}\n\n"; 233239462Sdim 234234353Sdim OS << "// Get the register unit pressure limit for this dimension.\n" 235234353Sdim << "// This limit must be adjusted dynamically for reserved registers.\n" 236234353Sdim << "unsigned " << ClassName << "::\n" 237234353Sdim << "getRegPressureSetLimit(unsigned Idx) const {\n" 238234353Sdim << " static const unsigned PressureLimitTable[] = {\n"; 239234353Sdim for (unsigned i = 0; i < NumSets; ++i ) { 240234353Sdim const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i); 241234353Sdim OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units) 242239462Sdim << ", \t// " << i << ": " << RegUnits.Name << "\n"; 243234353Sdim } 244234353Sdim OS << " 0 };\n" 245234353Sdim << " return PressureLimitTable[Idx];\n" 246234353Sdim << "}\n\n"; 247234353Sdim 248249423Sdim // This table may be larger than NumRCs if some register units needed a list 249249423Sdim // of unit sets that did not correspond to a register class. 250249423Sdim unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 251249423Sdim OS << "/// Table of pressure sets per register class or unit.\n" 252249423Sdim << "static const int RCSetsTable[] = {\n "; 253249423Sdim std::vector<unsigned> RCSetStarts(NumRCUnitSets); 254249423Sdim for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) { 255234353Sdim RCSetStarts[i] = StartIdx; 256234353Sdim ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 257234353Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 258234353Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 259234353Sdim OS << *PSetI << ", "; 260234353Sdim ++StartIdx; 261234353Sdim } 262249423Sdim OS << "-1, \t// #" << RCSetStarts[i] << " "; 263249423Sdim if (i < NumRCs) 264249423Sdim OS << RegBank.getRegClasses()[i]->getName(); 265249423Sdim else { 266249423Sdim OS << "inferred"; 267249423Sdim for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 268249423Sdim PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 269249423Sdim OS << "~" << RegBank.getRegPressureSet(*PSetI).Name; 270249423Sdim } 271249423Sdim } 272249423Sdim OS << "\n "; 273234353Sdim ++StartIdx; 274234353Sdim } 275249423Sdim OS << "-1 };\n\n"; 276249423Sdim 277249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 278249423Sdim << "register class.\n" 279249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 280249423Sdim << "const int* " << ClassName << "::\n" 281249423Sdim << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 282234353Sdim OS << " static const unsigned RCSetStartTable[] = {\n "; 283234353Sdim for (unsigned i = 0, e = NumRCs; i != e; ++i) { 284234353Sdim OS << RCSetStarts[i] << ","; 285234353Sdim } 286234353Sdim OS << "0 };\n" 287234353Sdim << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 288234353Sdim << " return &RCSetsTable[SetListStart];\n" 289234353Sdim << "}\n\n"; 290249423Sdim 291249423Sdim OS << "/// Get the dimensions of register pressure impacted by this " 292249423Sdim << "register unit.\n" 293249423Sdim << "/// Returns a -1 terminated array of pressure set IDs\n" 294249423Sdim << "const int* " << ClassName << "::\n" 295249423Sdim << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 296249423Sdim << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 297249423Sdim << " && \"invalid register unit\");\n"; 298249423Sdim OS << " static const unsigned RUSetStartTable[] = {\n "; 299249423Sdim for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 300249423Sdim UnitIdx < UnitEnd; ++UnitIdx) { 301249423Sdim OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ","; 302249423Sdim } 303249423Sdim OS << "0 };\n" 304249423Sdim << " unsigned SetListStart = RUSetStartTable[RegUnit];\n" 305249423Sdim << " return &RCSetsTable[SetListStart];\n" 306249423Sdim << "}\n\n"; 307234353Sdim} 308234353Sdim 309226633Sdimvoid 310234353SdimRegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, 311234353Sdim const std::vector<CodeGenRegister*> &Regs, 312234353Sdim bool isCtor) { 313226633Sdim // Collect all information about dwarf register numbers 314226633Sdim typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 315226633Sdim DwarfRegNumsMapTy DwarfRegNums; 316226633Sdim 317226633Sdim // First, just pull all provided information to the map 318226633Sdim unsigned maxLength = 0; 319226633Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 320226633Sdim Record *Reg = Regs[i]->TheDef; 321226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 322226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 323226633Sdim if (DwarfRegNums.count(Reg)) 324234982Sdim PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 325234982Sdim getQualifiedName(Reg) + "specified multiple times"); 326226633Sdim DwarfRegNums[Reg] = RegNums; 327226633Sdim } 328226633Sdim 329226633Sdim if (!maxLength) 330226633Sdim return; 331226633Sdim 332226633Sdim // Now we know maximal length of number list. Append -1's, where needed 333226633Sdim for (DwarfRegNumsMapTy::iterator 334226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 335226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 336226633Sdim I->second.push_back(-1); 337226633Sdim 338234353Sdim std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 339234353Sdim 340234353Sdim OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 341234353Sdim 342226633Sdim // Emit reverse information about the dwarf register numbers. 343226633Sdim for (unsigned j = 0; j < 2; ++j) { 344234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 345234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 346234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 347234353Sdim OS << i << "Dwarf2L[]"; 348234353Sdim 349234353Sdim if (!isCtor) { 350234353Sdim OS << " = {\n"; 351234353Sdim 352234353Sdim // Store the mapping sorted by the LLVM reg num so lookup can be done 353234353Sdim // with a binary search. 354234353Sdim std::map<uint64_t, Record*> Dwarf2LMap; 355234353Sdim for (DwarfRegNumsMapTy::iterator 356234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 357234353Sdim int DwarfRegNo = I->second[i]; 358234353Sdim if (DwarfRegNo < 0) 359234353Sdim continue; 360234353Sdim Dwarf2LMap[DwarfRegNo] = I->first; 361234353Sdim } 362234353Sdim 363234353Sdim for (std::map<uint64_t, Record*>::iterator 364234353Sdim I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 365234353Sdim OS << " { " << I->first << "U, " << getQualifiedName(I->second) 366234353Sdim << " },\n"; 367234353Sdim 368234353Sdim OS << "};\n"; 369234353Sdim } else { 370234353Sdim OS << ";\n"; 371234353Sdim } 372234353Sdim 373234353Sdim // We have to store the size in a const global, it's used in multiple 374234353Sdim // places. 375234353Sdim OS << "extern const unsigned " << Namespace 376234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 377234353Sdim if (!isCtor) 378234353Sdim OS << " = sizeof(" << Namespace 379234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 380234353Sdim << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 381234353Sdim else 382234353Sdim OS << ";\n\n"; 383234353Sdim } 384234353Sdim } 385234353Sdim 386234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 387234353Sdim Record *Reg = Regs[i]->TheDef; 388234353Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 389234353Sdim if (!V || !V->getValue()) 390234353Sdim continue; 391234353Sdim 392243830Sdim DefInit *DI = cast<DefInit>(V->getValue()); 393234353Sdim Record *Alias = DI->getDef(); 394234353Sdim DwarfRegNums[Reg] = DwarfRegNums[Alias]; 395234353Sdim } 396234353Sdim 397234353Sdim // Emit information about the dwarf register numbers. 398234353Sdim for (unsigned j = 0; j < 2; ++j) { 399234353Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 400234353Sdim OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 401234353Sdim OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 402234353Sdim OS << i << "L2Dwarf[]"; 403234353Sdim if (!isCtor) { 404234353Sdim OS << " = {\n"; 405234353Sdim // Store the mapping sorted by the Dwarf reg num so lookup can be done 406234353Sdim // with a binary search. 407234353Sdim for (DwarfRegNumsMapTy::iterator 408234353Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 409234353Sdim int RegNo = I->second[i]; 410234353Sdim if (RegNo == -1) // -1 is the default value, don't emit a mapping. 411234353Sdim continue; 412234353Sdim 413234353Sdim OS << " { " << getQualifiedName(I->first) << ", " << RegNo 414234353Sdim << "U },\n"; 415234353Sdim } 416234353Sdim OS << "};\n"; 417234353Sdim } else { 418234353Sdim OS << ";\n"; 419234353Sdim } 420234353Sdim 421234353Sdim // We have to store the size in a const global, it's used in multiple 422234353Sdim // places. 423234353Sdim OS << "extern const unsigned " << Namespace 424234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 425234353Sdim if (!isCtor) 426234353Sdim OS << " = sizeof(" << Namespace 427234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 428234353Sdim << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 429234353Sdim else 430234353Sdim OS << ";\n\n"; 431234353Sdim } 432234353Sdim } 433234353Sdim} 434234353Sdim 435234353Sdimvoid 436234353SdimRegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 437234353Sdim const std::vector<CodeGenRegister*> &Regs, 438234353Sdim bool isCtor) { 439234353Sdim // Emit the initializer so the tables from EmitRegMappingTables get wired up 440234353Sdim // to the MCRegisterInfo object. 441234353Sdim unsigned maxLength = 0; 442234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 443234353Sdim Record *Reg = Regs[i]->TheDef; 444234353Sdim maxLength = std::max((size_t)maxLength, 445234353Sdim Reg->getValueAsListOfInts("DwarfNumbers").size()); 446234353Sdim } 447234353Sdim 448234353Sdim if (!maxLength) 449234353Sdim return; 450234353Sdim 451234353Sdim std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 452234353Sdim 453234353Sdim // Emit reverse information about the dwarf register numbers. 454234353Sdim for (unsigned j = 0; j < 2; ++j) { 455226633Sdim OS << " switch ("; 456226633Sdim if (j == 0) 457226633Sdim OS << "DwarfFlavour"; 458226633Sdim else 459226633Sdim OS << "EHFlavour"; 460226633Sdim OS << ") {\n" 461226633Sdim << " default:\n" 462234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 463226633Sdim 464226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 465226633Sdim OS << " case " << i << ":\n"; 466234353Sdim OS << " "; 467234353Sdim if (!isCtor) 468234353Sdim OS << "RI->"; 469234353Sdim std::string Tmp; 470234353Sdim raw_string_ostream(Tmp) << Namespace 471234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 472234353Sdim << "Dwarf2L"; 473234353Sdim OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 474234353Sdim if (j == 0) 475226633Sdim OS << "false"; 476226633Sdim else 477226633Sdim OS << "true"; 478234353Sdim OS << ");\n"; 479226633Sdim OS << " break;\n"; 480226633Sdim } 481226633Sdim OS << " }\n"; 482226633Sdim } 483226633Sdim 484226633Sdim // Emit information about the dwarf register numbers. 485226633Sdim for (unsigned j = 0; j < 2; ++j) { 486226633Sdim OS << " switch ("; 487226633Sdim if (j == 0) 488226633Sdim OS << "DwarfFlavour"; 489226633Sdim else 490226633Sdim OS << "EHFlavour"; 491226633Sdim OS << ") {\n" 492226633Sdim << " default:\n" 493234353Sdim << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 494226633Sdim 495226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 496226633Sdim OS << " case " << i << ":\n"; 497234353Sdim OS << " "; 498234353Sdim if (!isCtor) 499234353Sdim OS << "RI->"; 500234353Sdim std::string Tmp; 501234353Sdim raw_string_ostream(Tmp) << Namespace 502234353Sdim << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 503234353Sdim << "L2Dwarf"; 504234353Sdim OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 505234353Sdim if (j == 0) 506226633Sdim OS << "false"; 507226633Sdim else 508226633Sdim OS << "true"; 509234353Sdim OS << ");\n"; 510226633Sdim OS << " break;\n"; 511226633Sdim } 512226633Sdim OS << " }\n"; 513226633Sdim } 514226633Sdim} 515226633Sdim 516226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 517226633Sdim// Width is the number of bits per hex number. 518226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 519226633Sdim const BitVector &Bits, 520226633Sdim unsigned Width) { 521226633Sdim assert(Width <= 32 && "Width too large"); 522226633Sdim unsigned Digits = (Width + 3) / 4; 523226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 524226633Sdim unsigned Value = 0; 525226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 526226633Sdim Value |= Bits.test(i + j) << j; 527226633Sdim OS << format("0x%0*x, ", Digits, Value); 528226633Sdim } 529226633Sdim} 530226633Sdim 531226633Sdim// Helper to emit a set of bits into a constant byte array. 532226633Sdimclass BitVectorEmitter { 533226633Sdim BitVector Values; 534226633Sdimpublic: 535226633Sdim void add(unsigned v) { 536226633Sdim if (v >= Values.size()) 537226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 538226633Sdim Values[v] = true; 539226633Sdim } 540226633Sdim 541226633Sdim void print(raw_ostream &OS) { 542226633Sdim printBitVectorAsHex(OS, Values, 8); 543226633Sdim } 544226633Sdim}; 545226633Sdim 546234353Sdimstatic void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 547234353Sdim OS << getEnumName(VT); 548234353Sdim} 549234353Sdim 550239462Sdimstatic void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 551239462Sdim OS << Idx->EnumValue; 552239462Sdim} 553239462Sdim 554239462Sdim// Differentially encoded register and regunit lists allow for better 555239462Sdim// compression on regular register banks. The sequence is computed from the 556239462Sdim// differential list as: 557224145Sdim// 558239462Sdim// out[0] = InitVal; 559239462Sdim// out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 560239462Sdim// 561239462Sdim// The initial value depends on the specific list. The list is terminated by a 562239462Sdim// 0 differential which means we can't encode repeated elements. 563239462Sdim 564239462Sdimtypedef SmallVector<uint16_t, 4> DiffVec; 565239462Sdim 566239462Sdim// Differentially encode a sequence of numbers into V. The starting value and 567239462Sdim// terminating 0 are not added to V, so it will have the same size as List. 568239462Sdimstatic 569239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) { 570239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 571239462Sdim uint16_t Val = uint16_t(InitVal); 572239462Sdim for (unsigned i = 0; i != List.size(); ++i) { 573239462Sdim uint16_t Cur = List[i]; 574239462Sdim V.push_back(Cur - Val); 575239462Sdim Val = Cur; 576239462Sdim } 577239462Sdim return V; 578239462Sdim} 579239462Sdim 580239462Sdimtemplate<typename Iter> 581239462Sdimstatic 582239462SdimDiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 583239462Sdim assert(V.empty() && "Clear DiffVec before diffEncode."); 584239462Sdim uint16_t Val = uint16_t(InitVal); 585239462Sdim for (Iter I = Begin; I != End; ++I) { 586239462Sdim uint16_t Cur = (*I)->EnumValue; 587239462Sdim V.push_back(Cur - Val); 588239462Sdim Val = Cur; 589239462Sdim } 590239462Sdim return V; 591239462Sdim} 592239462Sdim 593239462Sdimstatic void printDiff16(raw_ostream &OS, uint16_t Val) { 594239462Sdim OS << Val; 595239462Sdim} 596239462Sdim 597243830Sdim// Try to combine Idx's compose map into Vec if it is compatible. 598243830Sdim// Return false if it's not possible. 599243830Sdimstatic bool combine(const CodeGenSubRegIndex *Idx, 600243830Sdim SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 601243830Sdim const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 602243830Sdim for (CodeGenSubRegIndex::CompMap::const_iterator 603243830Sdim I = Map.begin(), E = Map.end(); I != E; ++I) { 604243830Sdim CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1]; 605243830Sdim if (Entry && Entry != I->second) 606243830Sdim return false; 607243830Sdim } 608243830Sdim 609243830Sdim // All entries are compatible. Make it so. 610243830Sdim for (CodeGenSubRegIndex::CompMap::const_iterator 611243830Sdim I = Map.begin(), E = Map.end(); I != E; ++I) 612243830Sdim Vec[I->first->EnumValue - 1] = I->second; 613243830Sdim return true; 614243830Sdim} 615243830Sdim 616243830Sdimstatic const char *getMinimalTypeForRange(uint64_t Range) { 617243830Sdim assert(Range < 0xFFFFFFFFULL && "Enum too large"); 618243830Sdim if (Range > 0xFFFF) 619243830Sdim return "uint32_t"; 620243830Sdim if (Range > 0xFF) 621243830Sdim return "uint16_t"; 622243830Sdim return "uint8_t"; 623243830Sdim} 624243830Sdim 625243830Sdimvoid 626243830SdimRegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 627243830Sdim CodeGenRegBank &RegBank, 628243830Sdim const std::string &ClName) { 629243830Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 630243830Sdim OS << "unsigned " << ClName 631243830Sdim << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 632243830Sdim 633243830Sdim // Many sub-register indexes are composition-compatible, meaning that 634243830Sdim // 635243830Sdim // compose(IdxA, IdxB) == compose(IdxA', IdxB) 636243830Sdim // 637243830Sdim // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 638243830Sdim // The illegal entries can be use as wildcards to compress the table further. 639243830Sdim 640243830Sdim // Map each Sub-register index to a compatible table row. 641243830Sdim SmallVector<unsigned, 4> RowMap; 642243830Sdim SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 643243830Sdim 644243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 645243830Sdim unsigned Found = ~0u; 646243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 647243830Sdim if (combine(SubRegIndices[i], Rows[r])) { 648243830Sdim Found = r; 649243830Sdim break; 650243830Sdim } 651243830Sdim } 652243830Sdim if (Found == ~0u) { 653243830Sdim Found = Rows.size(); 654243830Sdim Rows.resize(Found + 1); 655243830Sdim Rows.back().resize(SubRegIndices.size()); 656243830Sdim combine(SubRegIndices[i], Rows.back()); 657243830Sdim } 658243830Sdim RowMap.push_back(Found); 659243830Sdim } 660243830Sdim 661243830Sdim // Output the row map if there is multiple rows. 662243830Sdim if (Rows.size() > 1) { 663243830Sdim OS << " static const " << getMinimalTypeForRange(Rows.size()) 664243830Sdim << " RowMap[" << SubRegIndices.size() << "] = {\n "; 665243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 666243830Sdim OS << RowMap[i] << ", "; 667243830Sdim OS << "\n };\n"; 668243830Sdim } 669243830Sdim 670243830Sdim // Output the rows. 671243830Sdim OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1) 672243830Sdim << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n"; 673243830Sdim for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 674243830Sdim OS << " { "; 675243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 676243830Sdim if (Rows[r][i]) 677243830Sdim OS << Rows[r][i]->EnumValue << ", "; 678243830Sdim else 679243830Sdim OS << "0, "; 680243830Sdim OS << "},\n"; 681243830Sdim } 682243830Sdim OS << " };\n\n"; 683243830Sdim 684243830Sdim OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n" 685243830Sdim << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n"; 686243830Sdim if (Rows.size() > 1) 687243830Sdim OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 688243830Sdim else 689243830Sdim OS << " return Rows[0][IdxB];\n"; 690243830Sdim OS << "}\n\n"; 691243830Sdim} 692243830Sdim 693239462Sdim// 694224145Sdim// runMCDesc - Print out MC register descriptions. 695224145Sdim// 696224145Sdimvoid 697224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 698224145Sdim CodeGenRegBank &RegBank) { 699239462Sdim emitSourceFileHeader("MC Register Information", OS); 700224145Sdim 701224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 702224145Sdim OS << "#undef GET_REGINFO_MC_DESC\n"; 703224145Sdim 704234353Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 705224145Sdim 706234353Sdim // The lists of sub-registers, super-registers, and overlaps all go in the 707234353Sdim // same array. That allows us to share suffixes. 708234353Sdim typedef std::vector<const CodeGenRegister*> RegVec; 709224145Sdim 710239462Sdim // Differentially encoded lists. 711239462Sdim SequenceToOffsetTable<DiffVec> DiffSeqs; 712239462Sdim SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 713239462Sdim SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 714239462Sdim SmallVector<DiffVec, 4> OverlapLists(Regs.size()); 715239462Sdim SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 716239462Sdim SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 717239462Sdim 718239462Sdim // Keep track of sub-register names as well. These are not differentially 719239462Sdim // encoded. 720239462Sdim typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 721239462Sdim SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs; 722239462Sdim SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 723239462Sdim 724239462Sdim SequenceToOffsetTable<std::string> RegStrings; 725239462Sdim 726234353Sdim // Precompute register lists for the SequenceToOffsetTable. 727234353Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 728234353Sdim const CodeGenRegister *Reg = Regs[i]; 729224145Sdim 730239462Sdim RegStrings.add(Reg->getName()); 731239462Sdim 732234353Sdim // Compute the ordered sub-register list. 733234353Sdim SetVector<const CodeGenRegister*> SR; 734234353Sdim Reg->addSubRegsPreOrder(SR, RegBank); 735239462Sdim diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end()); 736239462Sdim DiffSeqs.add(SubRegLists[i]); 737224145Sdim 738239462Sdim // Compute the corresponding sub-register indexes. 739239462Sdim SubRegIdxVec &SRIs = SubRegIdxLists[i]; 740239462Sdim for (unsigned j = 0, je = SR.size(); j != je; ++j) 741239462Sdim SRIs.push_back(Reg->getSubRegIndex(SR[j])); 742239462Sdim SubRegIdxSeqs.add(SRIs); 743239462Sdim 744234353Sdim // Super-registers are already computed. 745234353Sdim const RegVec &SuperRegList = Reg->getSuperRegs(); 746239462Sdim diffEncode(SuperRegLists[i], Reg->EnumValue, 747239462Sdim SuperRegList.begin(), SuperRegList.end()); 748239462Sdim DiffSeqs.add(SuperRegLists[i]); 749224145Sdim 750239462Sdim // The list of overlaps doesn't need to have any particular order, and Reg 751239462Sdim // itself must be omitted. 752239462Sdim DiffVec &OverlapList = OverlapLists[i]; 753239462Sdim CodeGenRegister::Set OSet; 754239462Sdim Reg->computeOverlaps(OSet, RegBank); 755239462Sdim OSet.erase(Reg); 756239462Sdim diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end()); 757239462Sdim DiffSeqs.add(OverlapList); 758224145Sdim 759239462Sdim // Differentially encode the register unit list, seeded by register number. 760239462Sdim // First compute a scale factor that allows more diff-lists to be reused: 761239462Sdim // 762239462Sdim // D0 -> (S0, S1) 763239462Sdim // D1 -> (S2, S3) 764239462Sdim // 765239462Sdim // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 766239462Sdim // value for the differential decoder is the register number multiplied by 767239462Sdim // the scale. 768239462Sdim // 769239462Sdim // Check the neighboring registers for arithmetic progressions. 770239462Sdim unsigned ScaleA = ~0u, ScaleB = ~0u; 771239462Sdim ArrayRef<unsigned> RUs = Reg->getNativeRegUnits(); 772239462Sdim if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size()) 773239462Sdim ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front(); 774239462Sdim if (i+1 != Regs.size() && 775239462Sdim Regs[i+1]->getNativeRegUnits().size() == RUs.size()) 776239462Sdim ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front(); 777239462Sdim unsigned Scale = std::min(ScaleB, ScaleA); 778239462Sdim // Default the scale to 0 if it can't be encoded in 4 bits. 779239462Sdim if (Scale >= 16) 780239462Sdim Scale = 0; 781239462Sdim RegUnitInitScale[i] = Scale; 782239462Sdim DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs)); 783224145Sdim } 784224145Sdim 785234353Sdim // Compute the final layout of the sequence table. 786239462Sdim DiffSeqs.layout(); 787239462Sdim SubRegIdxSeqs.layout(); 788234353Sdim 789234353Sdim OS << "namespace llvm {\n\n"; 790234353Sdim 791234353Sdim const std::string &TargetName = Target.getName(); 792234353Sdim 793239462Sdim // Emit the shared table of differential lists. 794249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 795239462Sdim DiffSeqs.emit(OS, printDiff16); 796234353Sdim OS << "};\n\n"; 797234353Sdim 798239462Sdim // Emit the table of sub-register indexes. 799239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 800239462Sdim SubRegIdxSeqs.emit(OS, printSubRegIndex); 801239462Sdim OS << "};\n\n"; 802239462Sdim 803239462Sdim // Emit the string table. 804239462Sdim RegStrings.layout(); 805239462Sdim OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 806239462Sdim RegStrings.emit(OS, printChar); 807239462Sdim OS << "};\n\n"; 808239462Sdim 809234353Sdim OS << "extern const MCRegisterDesc " << TargetName 810224145Sdim << "RegDesc[] = { // Descriptors\n"; 811239462Sdim OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 812224145Sdim 813234353Sdim // Emit the register descriptors now. 814224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 815234353Sdim const CodeGenRegister *Reg = Regs[i]; 816239462Sdim OS << " { " << RegStrings.get(Reg->getName()) << ", " 817239462Sdim << DiffSeqs.get(OverlapLists[i]) << ", " 818239462Sdim << DiffSeqs.get(SubRegLists[i]) << ", " 819239462Sdim << DiffSeqs.get(SuperRegLists[i]) << ", " 820239462Sdim << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 821239462Sdim << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n"; 822224145Sdim } 823224145Sdim OS << "};\n\n"; // End of register descriptors... 824224145Sdim 825239462Sdim // Emit the table of register unit roots. Each regunit has one or two root 826239462Sdim // registers. 827239462Sdim OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n"; 828239462Sdim for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 829239462Sdim ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 830239462Sdim assert(!Roots.empty() && "All regunits must have a root register."); 831239462Sdim assert(Roots.size() <= 2 && "More than two roots not supported yet."); 832239462Sdim OS << " { " << getQualifiedName(Roots.front()->TheDef); 833239462Sdim for (unsigned r = 1; r != Roots.size(); ++r) 834239462Sdim OS << ", " << getQualifiedName(Roots[r]->TheDef); 835239462Sdim OS << " },\n"; 836239462Sdim } 837239462Sdim OS << "};\n\n"; 838239462Sdim 839226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 840226633Sdim 841226633Sdim // Loop over all of the register classes... emitting each one. 842226633Sdim OS << "namespace { // Register classes...\n"; 843226633Sdim 844226633Sdim // Emit the register enum value arrays for each RegisterClass 845226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 846226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 847226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 848226633Sdim 849226633Sdim // Give the register class a legal C name if it's anonymous. 850226633Sdim std::string Name = RC.getName(); 851226633Sdim 852226633Sdim // Emit the register list now. 853226633Sdim OS << " // " << Name << " Register Class...\n" 854234353Sdim << " const uint16_t " << Name 855226633Sdim << "[] = {\n "; 856226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 857226633Sdim Record *Reg = Order[i]; 858226633Sdim OS << getQualifiedName(Reg) << ", "; 859226633Sdim } 860226633Sdim OS << "\n };\n\n"; 861226633Sdim 862226633Sdim OS << " // " << Name << " Bit set.\n" 863234353Sdim << " const uint8_t " << Name 864226633Sdim << "Bits[] = {\n "; 865226633Sdim BitVectorEmitter BVE; 866226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 867226633Sdim Record *Reg = Order[i]; 868226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 869226633Sdim } 870226633Sdim BVE.print(OS); 871226633Sdim OS << "\n };\n\n"; 872226633Sdim 873226633Sdim } 874226633Sdim OS << "}\n\n"; 875226633Sdim 876234353Sdim OS << "extern const MCRegisterClass " << TargetName 877234353Sdim << "MCRegisterClasses[] = {\n"; 878226633Sdim 879226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 880226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 881234353Sdim 882234353Sdim // Asserts to make sure values will fit in table assuming types from 883234353Sdim // MCRegisterInfo.h 884234353Sdim assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); 885234353Sdim assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); 886234353Sdim assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); 887234353Sdim 888234353Sdim OS << " { " << '\"' << RC.getName() << "\", " 889234353Sdim << RC.getName() << ", " << RC.getName() << "Bits, " 890234353Sdim << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 891234353Sdim << RC.getQualifiedName() + "RegClassID" << ", " 892226633Sdim << RC.SpillSize/8 << ", " 893226633Sdim << RC.SpillAlignment/8 << ", " 894226633Sdim << RC.CopyCost << ", " 895234353Sdim << RC.Allocatable << " },\n"; 896226633Sdim } 897226633Sdim 898226633Sdim OS << "};\n\n"; 899226633Sdim 900234353Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 901239462Sdim 902239462Sdim EmitRegMappingTables(OS, Regs, false); 903239462Sdim 904239462Sdim // Emit Reg encoding table 905239462Sdim OS << "extern const uint16_t " << TargetName; 906239462Sdim OS << "RegEncodingTable[] = {\n"; 907239462Sdim // Add entry for NoRegister 908239462Sdim OS << " 0,\n"; 909239462Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 910239462Sdim Record *Reg = Regs[i]->TheDef; 911239462Sdim BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 912239462Sdim uint64_t Value = 0; 913239462Sdim for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 914243830Sdim if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 915239462Sdim Value |= (uint64_t)B->getValue() << b; 916234353Sdim } 917239462Sdim OS << " " << Value << ",\n"; 918234353Sdim } 919239462Sdim OS << "};\n"; // End of HW encoding table 920234353Sdim 921224145Sdim // MCRegisterInfo initialization routine. 922224145Sdim OS << "static inline void Init" << TargetName 923226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 924249423Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n" 925239462Sdim << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 926249423Sdim << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 927239462Sdim << RegisterClasses.size() << ", " 928239462Sdim << TargetName << "RegUnitRoots, " 929239462Sdim << RegBank.getNumNativeRegUnits() << ", " 930239462Sdim << TargetName << "RegDiffLists, " 931239462Sdim << TargetName << "RegStrings, " 932239462Sdim << TargetName << "SubRegIdxLists, " 933243830Sdim << (SubRegIndices.size() + 1) << ",\n" 934239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 935224145Sdim 936226633Sdim EmitRegMapping(OS, Regs, false); 937226633Sdim 938226633Sdim OS << "}\n\n"; 939226633Sdim 940224145Sdim OS << "} // End llvm namespace \n"; 941224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 942224145Sdim} 943224145Sdim 944224145Sdimvoid 945224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 946224145Sdim CodeGenRegBank &RegBank) { 947239462Sdim emitSourceFileHeader("Register Information Header Fragment", OS); 948224145Sdim 949224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 950224145Sdim OS << "#undef GET_REGINFO_HEADER\n"; 951224145Sdim 952193323Sed const std::string &TargetName = Target.getName(); 953193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 954193323Sed 955234353Sdim OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; 956193323Sed 957193323Sed OS << "namespace llvm {\n\n"; 958193323Sed 959193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 960226633Sdim << " explicit " << ClassName 961249423Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n" 962193323Sed << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 963239462Sdim << " { return false; }\n"; 964239462Sdim if (!RegBank.getSubRegIndices().empty()) { 965243830Sdim OS << " virtual unsigned composeSubRegIndicesImpl" 966243830Sdim << "(unsigned, unsigned) const;\n" 967243830Sdim << " virtual const TargetRegisterClass *" 968239462Sdim "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; 969239462Sdim } 970243830Sdim OS << " virtual const RegClassWeight &getRegClassWeight(" 971234353Sdim << "const TargetRegisterClass *RC) const;\n" 972249423Sdim << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n" 973243830Sdim << " virtual unsigned getNumRegPressureSets() const;\n" 974243830Sdim << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n" 975243830Sdim << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n" 976243830Sdim << " virtual const int *getRegClassPressureSets(" 977234353Sdim << "const TargetRegisterClass *RC) const;\n" 978249423Sdim << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n" 979193323Sed << "};\n\n"; 980193323Sed 981226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 982193323Sed 983193323Sed if (!RegisterClasses.empty()) { 984226633Sdim OS << "namespace " << RegisterClasses[0]->Namespace 985193323Sed << " { // Register classes\n"; 986221345Sdim 987193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 988226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 989224145Sdim const std::string &Name = RC.getName(); 990193323Sed 991193323Sed // Output the extern for the instance. 992234353Sdim OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 993193323Sed } 994193323Sed OS << "} // end of namespace " << TargetName << "\n\n"; 995193323Sed } 996193323Sed OS << "} // End llvm namespace \n"; 997224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 998193323Sed} 999193323Sed 1000224145Sdim// 1001224145Sdim// runTargetDesc - Output the target register and register file descriptions. 1002224145Sdim// 1003224145Sdimvoid 1004224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1005224145Sdim CodeGenRegBank &RegBank){ 1006239462Sdim emitSourceFileHeader("Target Register and Register Classes Information", OS); 1007193323Sed 1008224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1009224145Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n"; 1010193323Sed 1011193323Sed OS << "namespace llvm {\n\n"; 1012193323Sed 1013226633Sdim // Get access to MCRegisterClass data. 1014234353Sdim OS << "extern const MCRegisterClass " << Target.getName() 1015234353Sdim << "MCRegisterClasses[];\n"; 1016226633Sdim 1017223017Sdim // Start out by emitting each of the register classes. 1018226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 1019239462Sdim ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 1020193323Sed 1021223017Sdim // Collect all registers belonging to any allocatable class. 1022223017Sdim std::set<Record*> AllocatableRegs; 1023223017Sdim 1024226633Sdim // Collect allocatable registers. 1025193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1026226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1027224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 1028193323Sed 1029223017Sdim if (RC.Allocatable) 1030224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 1031226633Sdim } 1032223017Sdim 1033234353Sdim // Build a shared array of value types. 1034249423Sdim SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; 1035234353Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) 1036234353Sdim VTSeqs.add(RegisterClasses[rc]->VTs); 1037234353Sdim VTSeqs.layout(); 1038234353Sdim OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1039234353Sdim VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1040234353Sdim OS << "};\n"; 1041221345Sdim 1042243830Sdim // Emit SubRegIndex names, skipping 0. 1043243830Sdim OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1044239462Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1045239462Sdim OS << SubRegIndices[i]->getName(); 1046243830Sdim if (i + 1 != e) 1047239462Sdim OS << "\", \""; 1048239462Sdim } 1049239462Sdim OS << "\" };\n\n"; 1050239462Sdim 1051243830Sdim // Emit SubRegIndex lane masks, including 0. 1052243830Sdim OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; 1053243830Sdim for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1054243830Sdim OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) 1055243830Sdim << SubRegIndices[i]->getName() << '\n'; 1056243830Sdim } 1057243830Sdim OS << " };\n\n"; 1058243830Sdim 1059239462Sdim OS << "\n"; 1060239462Sdim 1061193323Sed // Now that all of the structs have been emitted, emit the instances. 1062193323Sed if (!RegisterClasses.empty()) { 1063234353Sdim OS << "\nstatic const TargetRegisterClass *const " 1064234353Sdim << "NullRegClasses[] = { NULL };\n\n"; 1065226633Sdim 1066239462Sdim // Emit register class bit mask tables. The first bit mask emitted for a 1067239462Sdim // register class, RC, is the set of sub-classes, including RC itself. 1068239462Sdim // 1069239462Sdim // If RC has super-registers, also create a list of subreg indices and bit 1070239462Sdim // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1071239462Sdim // SuperRC, that satisfies: 1072239462Sdim // 1073239462Sdim // For all SuperReg in SuperRC: SuperReg:Idx in RC 1074239462Sdim // 1075239462Sdim // The 0-terminated list of subreg indices starts at: 1076239462Sdim // 1077239462Sdim // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1078239462Sdim // 1079239462Sdim // The corresponding bitmasks follow the sub-class mask in memory. Each 1080239462Sdim // mask has RCMaskWords uint32_t entries. 1081239462Sdim // 1082239462Sdim // Every bit mask present in the list has at least one bit set. 1083193323Sed 1084239462Sdim // Compress the sub-reg index lists. 1085239462Sdim typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1086239462Sdim SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1087239462Sdim SequenceToOffsetTable<IdxList> SuperRegIdxSeqs; 1088239462Sdim BitVector MaskBV(RegisterClasses.size()); 1089193323Sed 1090193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1091226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1092239462Sdim OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; 1093239462Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1094193323Sed 1095239462Sdim // Emit super-reg class masks for any relevant SubRegIndices that can 1096239462Sdim // project into RC. 1097239462Sdim IdxList &SRIList = SuperRegIdxLists[rc]; 1098239462Sdim for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1099239462Sdim CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1100239462Sdim MaskBV.reset(); 1101239462Sdim RC.getSuperRegClasses(Idx, MaskBV); 1102239462Sdim if (MaskBV.none()) 1103239462Sdim continue; 1104239462Sdim SRIList.push_back(Idx); 1105239462Sdim OS << "\n "; 1106239462Sdim printBitVectorAsHex(OS, MaskBV, 32); 1107239462Sdim OS << "// " << Idx->getName(); 1108239462Sdim } 1109239462Sdim SuperRegIdxSeqs.add(SRIList); 1110234353Sdim OS << "\n};\n\n"; 1111193323Sed } 1112193323Sed 1113239462Sdim OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1114239462Sdim SuperRegIdxSeqs.layout(); 1115239462Sdim SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1116239462Sdim OS << "};\n\n"; 1117239462Sdim 1118226633Sdim // Emit NULL terminated super-class lists. 1119193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1120226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1121226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1122193323Sed 1123226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 1124226633Sdim if (Supers.empty()) 1125226633Sdim continue; 1126193323Sed 1127234353Sdim OS << "static const TargetRegisterClass *const " 1128226633Sdim << RC.getName() << "Superclasses[] = {\n"; 1129226633Sdim for (unsigned i = 0; i != Supers.size(); ++i) 1130234353Sdim OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; 1131234353Sdim OS << " NULL\n};\n\n"; 1132193323Sed } 1133193323Sed 1134224145Sdim // Emit methods. 1135193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1136226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1137224145Sdim if (!RC.AltOrderSelect.empty()) { 1138224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 1139224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 1140234353Sdim << RC.AltOrderSelect << "}\n\n" 1141249423Sdim << "static ArrayRef<MCPhysReg> " << RC.getName() 1142234353Sdim << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1143224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1144224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 1145234353Sdim if (!Elems.empty()) { 1146249423Sdim OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1147234353Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 1148234353Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1149234353Sdim OS << " };\n"; 1150234353Sdim } 1151224145Sdim } 1152226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 1153234353Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1154249423Sdim << " const ArrayRef<MCPhysReg> Order[] = {\n" 1155226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1156224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1157234353Sdim if (RC.getOrder(oi).empty()) 1158249423Sdim OS << "),\n ArrayRef<MCPhysReg>("; 1159234353Sdim else 1160234353Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 1161224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 1162224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1163224145Sdim << ");\n return Order[Select];\n}\n"; 1164224145Sdim } 1165193323Sed } 1166221345Sdim 1167234353Sdim // Now emit the actual value-initialized register class instances. 1168234353Sdim OS << "namespace " << RegisterClasses[0]->Namespace 1169234353Sdim << " { // Register class instances\n"; 1170234353Sdim 1171234353Sdim for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1172234353Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1173234353Sdim OS << " extern const TargetRegisterClass " 1174234353Sdim << RegisterClasses[i]->getName() << "RegClass = {\n " 1175234353Sdim << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() 1176234353Sdim << "RegClassID],\n " 1177234353Sdim << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " 1178239462Sdim << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1179239462Sdim << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n "; 1180234353Sdim if (RC.getSuperClasses().empty()) 1181234353Sdim OS << "NullRegClasses,\n "; 1182234353Sdim else 1183234353Sdim OS << RC.getName() << "Superclasses,\n "; 1184234353Sdim if (RC.AltOrderSelect.empty()) 1185234353Sdim OS << "0\n"; 1186234353Sdim else 1187234353Sdim OS << RC.getName() << "GetRawAllocationOrder\n"; 1188234353Sdim OS << " };\n\n"; 1189234353Sdim } 1190234353Sdim 1191193323Sed OS << "}\n"; 1192193323Sed } 1193193323Sed 1194193323Sed OS << "\nnamespace {\n"; 1195193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1196193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 1197226633Sdim OS << " &" << RegisterClasses[i]->getQualifiedName() 1198193323Sed << "RegClass,\n"; 1199193323Sed OS << " };\n"; 1200224145Sdim OS << "}\n"; // End of anonymous namespace... 1201193323Sed 1202224145Sdim // Emit extra information about registers. 1203224145Sdim const std::string &TargetName = Target.getName(); 1204234353Sdim OS << "\nstatic const TargetRegisterInfoDesc " 1205234353Sdim << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1206234353Sdim OS << " { 0, 0 },\n"; 1207221345Sdim 1208224145Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 1209193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1210224145Sdim const CodeGenRegister &Reg = *Regs[i]; 1211234353Sdim OS << " { "; 1212224145Sdim OS << Reg.CostPerUse << ", " 1213223017Sdim << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 1214193323Sed } 1215234353Sdim OS << "};\n"; // End of register descriptors... 1216208599Srdivacky 1217224145Sdim 1218193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 1219193323Sed 1220243830Sdim if (!SubRegIndices.empty()) 1221243830Sdim emitComposeSubRegIndices(OS, RegBank, ClassName); 1222210299Sed 1223226633Sdim // Emit getSubClassWithSubReg. 1224239462Sdim if (!SubRegIndices.empty()) { 1225239462Sdim OS << "const TargetRegisterClass *" << ClassName 1226239462Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1227239462Sdim << " const {\n"; 1228226633Sdim // Use the smallest type that can hold a regclass ID with room for a 1229226633Sdim // sentinel. 1230226633Sdim if (RegisterClasses.size() < UINT8_MAX) 1231226633Sdim OS << " static const uint8_t Table["; 1232226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 1233226633Sdim OS << " static const uint16_t Table["; 1234226633Sdim else 1235243830Sdim PrintFatalError("Too many register classes."); 1236226633Sdim OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; 1237226633Sdim for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { 1238226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rci]; 1239226633Sdim OS << " {\t// " << RC.getName() << "\n"; 1240226633Sdim for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1241234353Sdim CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1242226633Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 1243226633Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 1244226633Sdim << " -> " << SRC->getName() << "\n"; 1245226633Sdim else 1246226633Sdim OS << " 0,\t// " << Idx->getName() << "\n"; 1247226633Sdim } 1248226633Sdim OS << " },\n"; 1249226633Sdim } 1250226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 1251226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 1252226633Sdim << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" 1253226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 1254239462Sdim << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; 1255226633Sdim } 1256226633Sdim 1257234353Sdim EmitRegUnitPressure(OS, RegBank, ClassName); 1258234353Sdim 1259193323Sed // Emit the constructor of the class... 1260234353Sdim OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1261249423Sdim OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1262239462Sdim OS << "extern const char " << TargetName << "RegStrings[];\n"; 1263239462Sdim OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n"; 1264239462Sdim OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1265239462Sdim OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1266224145Sdim 1267234353Sdim EmitRegMappingTables(OS, Regs, true); 1268234353Sdim 1269234353Sdim OS << ClassName << "::\n" << ClassName 1270249423Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" 1271224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1272208599Srdivacky << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 1273243830Sdim << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n" 1274224145Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 1275249423Sdim << Regs.size()+1 << ", RA, PC,\n " << TargetName 1276234353Sdim << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1277239462Sdim << " " << TargetName << "RegUnitRoots,\n" 1278239462Sdim << " " << RegBank.getNumNativeRegUnits() << ",\n" 1279239462Sdim << " " << TargetName << "RegDiffLists,\n" 1280239462Sdim << " " << TargetName << "RegStrings,\n" 1281239462Sdim << " " << TargetName << "SubRegIdxLists,\n" 1282243830Sdim << " " << SubRegIndices.size() + 1 << ",\n" 1283239462Sdim << " " << TargetName << "RegEncodingTable);\n\n"; 1284193323Sed 1285226633Sdim EmitRegMapping(OS, Regs, true); 1286193323Sed 1287226633Sdim OS << "}\n\n"; 1288193323Sed 1289234353Sdim 1290234353Sdim // Emit CalleeSavedRegs information. 1291234353Sdim std::vector<Record*> CSRSets = 1292234353Sdim Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1293234353Sdim for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1294234353Sdim Record *CSRSet = CSRSets[i]; 1295234353Sdim const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1296234353Sdim assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1297234353Sdim 1298234353Sdim // Emit the *_SaveList list of callee-saved registers. 1299249423Sdim OS << "static const MCPhysReg " << CSRSet->getName() 1300234353Sdim << "_SaveList[] = { "; 1301234353Sdim for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1302234353Sdim OS << getQualifiedName((*Regs)[r]) << ", "; 1303234353Sdim OS << "0 };\n"; 1304234353Sdim 1305234353Sdim // Emit the *_RegMask bit mask of call-preserved registers. 1306234353Sdim OS << "static const uint32_t " << CSRSet->getName() 1307234353Sdim << "_RegMask[] = { "; 1308234353Sdim printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32); 1309234353Sdim OS << "};\n"; 1310234353Sdim } 1311234353Sdim OS << "\n\n"; 1312234353Sdim 1313193323Sed OS << "} // End llvm namespace \n"; 1314224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1315193323Sed} 1316224145Sdim 1317224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 1318224145Sdim CodeGenTarget Target(Records); 1319224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 1320224145Sdim RegBank.computeDerivedInfo(); 1321224145Sdim 1322224145Sdim runEnums(OS, Target, RegBank); 1323224145Sdim runMCDesc(OS, Target, RegBank); 1324224145Sdim runTargetHeader(OS, Target, RegBank); 1325224145Sdim runTargetDesc(OS, Target, RegBank); 1326224145Sdim} 1327239462Sdim 1328239462Sdimnamespace llvm { 1329239462Sdim 1330239462Sdimvoid EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1331239462Sdim RegisterInfoEmitter(RK).run(OS); 1332239462Sdim} 1333239462Sdim 1334239462Sdim} // End llvm namespace 1335