RegisterInfoEmitter.cpp revision 226633
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#include "RegisterInfoEmitter.h" 17193323Sed#include "CodeGenTarget.h" 18193323Sed#include "CodeGenRegisters.h" 19226633Sdim#include "llvm/TableGen/Record.h" 20226633Sdim#include "llvm/ADT/BitVector.h" 21193323Sed#include "llvm/ADT/StringExtras.h" 22193323Sed#include "llvm/ADT/STLExtras.h" 23224145Sdim#include "llvm/Support/Format.h" 24195340Sed#include <algorithm> 25193323Sed#include <set> 26193323Sedusing namespace llvm; 27193323Sed 28193323Sed// runEnums - Print out enum values for all of the registers. 29224145Sdimvoid 30224145SdimRegisterInfoEmitter::runEnums(raw_ostream &OS, 31224145Sdim CodeGenTarget &Target, CodeGenRegBank &Bank) { 32224145Sdim const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 33193323Sed 34224145Sdim std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 35193323Sed 36193323Sed EmitSourceFileHeader("Target Register Enum Values", OS); 37224145Sdim 38224145Sdim OS << "\n#ifdef GET_REGINFO_ENUM\n"; 39224145Sdim OS << "#undef GET_REGINFO_ENUM\n"; 40224145Sdim 41193323Sed OS << "namespace llvm {\n\n"; 42193323Sed 43226633Sdim OS << "class MCRegisterClass;\n" 44226633Sdim << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n"; 45226633Sdim 46193323Sed if (!Namespace.empty()) 47193323Sed OS << "namespace " << Namespace << " {\n"; 48208599Srdivacky OS << "enum {\n NoRegister,\n"; 49193323Sed 50193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) 51224145Sdim OS << " " << Registers[i]->getName() << " = " << 52224145Sdim Registers[i]->EnumValue << ",\n"; 53224145Sdim assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 54221345Sdim "Register enum value mismatch!"); 55208599Srdivacky OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 56208599Srdivacky OS << "};\n"; 57193323Sed if (!Namespace.empty()) 58193323Sed OS << "}\n"; 59208599Srdivacky 60226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); 61224145Sdim if (!RegisterClasses.empty()) { 62224145Sdim OS << "\n// Register classes\n"; 63208599Srdivacky if (!Namespace.empty()) 64208599Srdivacky OS << "namespace " << Namespace << " {\n"; 65224145Sdim OS << "enum {\n"; 66224145Sdim for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 67224145Sdim if (i) OS << ",\n"; 68226633Sdim OS << " " << RegisterClasses[i]->getName() << "RegClassID"; 69224145Sdim OS << " = " << i; 70224145Sdim } 71224145Sdim OS << "\n };\n"; 72224145Sdim if (!Namespace.empty()) 73224145Sdim OS << "}\n"; 74224145Sdim } 75224145Sdim 76224145Sdim const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 77224145Sdim // If the only definition is the default NoRegAltName, we don't need to 78224145Sdim // emit anything. 79224145Sdim if (RegAltNameIndices.size() > 1) { 80224145Sdim OS << "\n// Register alternate name indices\n"; 81224145Sdim if (!Namespace.empty()) 82224145Sdim OS << "namespace " << Namespace << " {\n"; 83224145Sdim OS << "enum {\n"; 84224145Sdim for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 85224145Sdim OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 86224145Sdim OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 87208599Srdivacky OS << "};\n"; 88208599Srdivacky if (!Namespace.empty()) 89208599Srdivacky OS << "}\n"; 90208599Srdivacky } 91224145Sdim 92224145Sdim 93193323Sed OS << "} // End llvm namespace \n"; 94224145Sdim OS << "#endif // GET_REGINFO_ENUM\n\n"; 95193323Sed} 96193323Sed 97226633Sdimvoid 98226633SdimRegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 99226633Sdim const std::vector<CodeGenRegister*> &Regs, 100226633Sdim bool isCtor) { 101226633Sdim 102226633Sdim // Collect all information about dwarf register numbers 103226633Sdim typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 104226633Sdim DwarfRegNumsMapTy DwarfRegNums; 105226633Sdim 106226633Sdim // First, just pull all provided information to the map 107226633Sdim unsigned maxLength = 0; 108226633Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 109226633Sdim Record *Reg = Regs[i]->TheDef; 110226633Sdim std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 111226633Sdim maxLength = std::max((size_t)maxLength, RegNums.size()); 112226633Sdim if (DwarfRegNums.count(Reg)) 113226633Sdim errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 114226633Sdim << "specified multiple times\n"; 115226633Sdim DwarfRegNums[Reg] = RegNums; 116226633Sdim } 117226633Sdim 118226633Sdim if (!maxLength) 119226633Sdim return; 120226633Sdim 121226633Sdim // Now we know maximal length of number list. Append -1's, where needed 122226633Sdim for (DwarfRegNumsMapTy::iterator 123226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 124226633Sdim for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 125226633Sdim I->second.push_back(-1); 126226633Sdim 127226633Sdim // Emit reverse information about the dwarf register numbers. 128226633Sdim for (unsigned j = 0; j < 2; ++j) { 129226633Sdim OS << " switch ("; 130226633Sdim if (j == 0) 131226633Sdim OS << "DwarfFlavour"; 132226633Sdim else 133226633Sdim OS << "EHFlavour"; 134226633Sdim OS << ") {\n" 135226633Sdim << " default:\n" 136226633Sdim << " assert(0 && \"Unknown DWARF flavour\");\n" 137226633Sdim << " break;\n"; 138226633Sdim 139226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 140226633Sdim OS << " case " << i << ":\n"; 141226633Sdim for (DwarfRegNumsMapTy::iterator 142226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 143226633Sdim int DwarfRegNo = I->second[i]; 144226633Sdim if (DwarfRegNo < 0) 145226633Sdim continue; 146226633Sdim OS << " "; 147226633Sdim if (!isCtor) 148226633Sdim OS << "RI->"; 149226633Sdim OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", " 150226633Sdim << getQualifiedName(I->first) << ", "; 151226633Sdim if (j == 0) 152226633Sdim OS << "false"; 153226633Sdim else 154226633Sdim OS << "true"; 155226633Sdim OS << " );\n"; 156226633Sdim } 157226633Sdim OS << " break;\n"; 158226633Sdim } 159226633Sdim OS << " }\n"; 160226633Sdim } 161226633Sdim 162226633Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 163226633Sdim Record *Reg = Regs[i]->TheDef; 164226633Sdim const RecordVal *V = Reg->getValue("DwarfAlias"); 165226633Sdim if (!V || !V->getValue()) 166226633Sdim continue; 167226633Sdim 168226633Sdim DefInit *DI = dynamic_cast<DefInit*>(V->getValue()); 169226633Sdim Record *Alias = DI->getDef(); 170226633Sdim DwarfRegNums[Reg] = DwarfRegNums[Alias]; 171226633Sdim } 172226633Sdim 173226633Sdim // Emit information about the dwarf register numbers. 174226633Sdim for (unsigned j = 0; j < 2; ++j) { 175226633Sdim OS << " switch ("; 176226633Sdim if (j == 0) 177226633Sdim OS << "DwarfFlavour"; 178226633Sdim else 179226633Sdim OS << "EHFlavour"; 180226633Sdim OS << ") {\n" 181226633Sdim << " default:\n" 182226633Sdim << " assert(0 && \"Unknown DWARF flavour\");\n" 183226633Sdim << " break;\n"; 184226633Sdim 185226633Sdim for (unsigned i = 0, e = maxLength; i != e; ++i) { 186226633Sdim OS << " case " << i << ":\n"; 187226633Sdim // Sort by name to get a stable order. 188226633Sdim for (DwarfRegNumsMapTy::iterator 189226633Sdim I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 190226633Sdim int RegNo = I->second[i]; 191226633Sdim OS << " "; 192226633Sdim if (!isCtor) 193226633Sdim OS << "RI->"; 194226633Sdim OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", " 195226633Sdim << RegNo << ", "; 196226633Sdim if (j == 0) 197226633Sdim OS << "false"; 198226633Sdim else 199226633Sdim OS << "true"; 200226633Sdim OS << " );\n"; 201226633Sdim } 202226633Sdim OS << " break;\n"; 203226633Sdim } 204226633Sdim OS << " }\n"; 205226633Sdim } 206226633Sdim} 207226633Sdim 208226633Sdim// Print a BitVector as a sequence of hex numbers using a little-endian mapping. 209226633Sdim// Width is the number of bits per hex number. 210226633Sdimstatic void printBitVectorAsHex(raw_ostream &OS, 211226633Sdim const BitVector &Bits, 212226633Sdim unsigned Width) { 213226633Sdim assert(Width <= 32 && "Width too large"); 214226633Sdim unsigned Digits = (Width + 3) / 4; 215226633Sdim for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 216226633Sdim unsigned Value = 0; 217226633Sdim for (unsigned j = 0; j != Width && i + j != e; ++j) 218226633Sdim Value |= Bits.test(i + j) << j; 219226633Sdim OS << format("0x%0*x, ", Digits, Value); 220226633Sdim } 221226633Sdim} 222226633Sdim 223226633Sdim// Helper to emit a set of bits into a constant byte array. 224226633Sdimclass BitVectorEmitter { 225226633Sdim BitVector Values; 226226633Sdimpublic: 227226633Sdim void add(unsigned v) { 228226633Sdim if (v >= Values.size()) 229226633Sdim Values.resize(((v/8)+1)*8); // Round up to the next byte. 230226633Sdim Values[v] = true; 231226633Sdim } 232226633Sdim 233226633Sdim void print(raw_ostream &OS) { 234226633Sdim printBitVectorAsHex(OS, Values, 8); 235226633Sdim } 236226633Sdim}; 237226633Sdim 238224145Sdim// 239224145Sdim// runMCDesc - Print out MC register descriptions. 240224145Sdim// 241224145Sdimvoid 242224145SdimRegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 243224145Sdim CodeGenRegBank &RegBank) { 244224145Sdim EmitSourceFileHeader("MC Register Information", OS); 245224145Sdim 246224145Sdim OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 247224145Sdim OS << "#undef GET_REGINFO_MC_DESC\n"; 248224145Sdim 249224145Sdim std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps; 250224145Sdim RegBank.computeOverlaps(Overlaps); 251224145Sdim 252224145Sdim OS << "namespace llvm {\n\n"; 253224145Sdim 254224145Sdim const std::string &TargetName = Target.getName(); 255224145Sdim std::string ClassName = TargetName + "GenMCRegisterInfo"; 256224145Sdim OS << "struct " << ClassName << " : public MCRegisterInfo {\n" 257224145Sdim << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; 258224145Sdim OS << "};\n"; 259224145Sdim 260224145Sdim OS << "\nnamespace {\n"; 261224145Sdim 262224145Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 263224145Sdim 264224145Sdim // Emit an overlap list for all registers. 265224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 266224145Sdim const CodeGenRegister *Reg = Regs[i]; 267224145Sdim const CodeGenRegister::Set &O = Overlaps[Reg]; 268224145Sdim // Move Reg to the front so TRI::getAliasSet can share the list. 269224145Sdim OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " 270224145Sdim << getQualifiedName(Reg->TheDef) << ", "; 271224145Sdim for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); 272224145Sdim I != E; ++I) 273224145Sdim if (*I != Reg) 274224145Sdim OS << getQualifiedName((*I)->TheDef) << ", "; 275224145Sdim OS << "0 };\n"; 276224145Sdim } 277224145Sdim 278224145Sdim // Emit the empty sub-registers list 279224145Sdim OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 280224145Sdim // Loop over all of the registers which have sub-registers, emitting the 281224145Sdim // sub-registers list to memory. 282224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 283224145Sdim const CodeGenRegister &Reg = *Regs[i]; 284224145Sdim if (Reg.getSubRegs().empty()) 285224145Sdim continue; 286224145Sdim // getSubRegs() orders by SubRegIndex. We want a topological order. 287224145Sdim SetVector<CodeGenRegister*> SR; 288224145Sdim Reg.addSubRegsPreOrder(SR); 289224145Sdim OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; 290224145Sdim for (unsigned j = 0, je = SR.size(); j != je; ++j) 291224145Sdim OS << getQualifiedName(SR[j]->TheDef) << ", "; 292224145Sdim OS << "0 };\n"; 293224145Sdim } 294224145Sdim 295224145Sdim // Emit the empty super-registers list 296224145Sdim OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 297224145Sdim // Loop over all of the registers which have super-registers, emitting the 298224145Sdim // super-registers list to memory. 299224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 300224145Sdim const CodeGenRegister &Reg = *Regs[i]; 301224145Sdim const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); 302224145Sdim if (SR.empty()) 303224145Sdim continue; 304224145Sdim OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; 305224145Sdim for (unsigned j = 0, je = SR.size(); j != je; ++j) 306224145Sdim OS << getQualifiedName(SR[j]->TheDef) << ", "; 307224145Sdim OS << "0 };\n"; 308224145Sdim } 309224145Sdim OS << "}\n"; // End of anonymous namespace... 310224145Sdim 311224145Sdim OS << "\nMCRegisterDesc " << TargetName 312224145Sdim << "RegDesc[] = { // Descriptors\n"; 313224145Sdim OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; 314224145Sdim 315224145Sdim // Now that register alias and sub-registers sets have been emitted, emit the 316224145Sdim // register descriptors now. 317224145Sdim for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 318224145Sdim const CodeGenRegister &Reg = *Regs[i]; 319224145Sdim OS << " { \""; 320224145Sdim OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; 321224145Sdim if (!Reg.getSubRegs().empty()) 322224145Sdim OS << Reg.getName() << "_SubRegsSet,\t"; 323224145Sdim else 324224145Sdim OS << "Empty_SubRegsSet,\t"; 325224145Sdim if (!Reg.getSuperRegs().empty()) 326224145Sdim OS << Reg.getName() << "_SuperRegsSet"; 327224145Sdim else 328224145Sdim OS << "Empty_SuperRegsSet"; 329224145Sdim OS << " },\n"; 330224145Sdim } 331224145Sdim OS << "};\n\n"; // End of register descriptors... 332224145Sdim 333226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 334226633Sdim 335226633Sdim // Loop over all of the register classes... emitting each one. 336226633Sdim OS << "namespace { // Register classes...\n"; 337226633Sdim 338226633Sdim // Emit the register enum value arrays for each RegisterClass 339226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 340226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 341226633Sdim ArrayRef<Record*> Order = RC.getOrder(); 342226633Sdim 343226633Sdim // Give the register class a legal C name if it's anonymous. 344226633Sdim std::string Name = RC.getName(); 345226633Sdim 346226633Sdim // Emit the register list now. 347226633Sdim OS << " // " << Name << " Register Class...\n" 348226633Sdim << " static const unsigned " << Name 349226633Sdim << "[] = {\n "; 350226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 351226633Sdim Record *Reg = Order[i]; 352226633Sdim OS << getQualifiedName(Reg) << ", "; 353226633Sdim } 354226633Sdim OS << "\n };\n\n"; 355226633Sdim 356226633Sdim OS << " // " << Name << " Bit set.\n" 357226633Sdim << " static const unsigned char " << Name 358226633Sdim << "Bits[] = {\n "; 359226633Sdim BitVectorEmitter BVE; 360226633Sdim for (unsigned i = 0, e = Order.size(); i != e; ++i) { 361226633Sdim Record *Reg = Order[i]; 362226633Sdim BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 363226633Sdim } 364226633Sdim BVE.print(OS); 365226633Sdim OS << "\n };\n\n"; 366226633Sdim 367226633Sdim } 368226633Sdim OS << "}\n\n"; 369226633Sdim 370226633Sdim OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n"; 371226633Sdim 372226633Sdim for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 373226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 374226633Sdim OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", " 375226633Sdim << '\"' << RC.getName() << "\", " 376226633Sdim << RC.SpillSize/8 << ", " 377226633Sdim << RC.SpillAlignment/8 << ", " 378226633Sdim << RC.CopyCost << ", " 379226633Sdim << RC.Allocatable << ", " 380226633Sdim << RC.getName() << ", " << RC.getName() << " + " 381226633Sdim << RC.getOrder().size() << ", " 382226633Sdim << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)" 383226633Sdim << "),\n"; 384226633Sdim } 385226633Sdim 386226633Sdim OS << "};\n\n"; 387226633Sdim 388224145Sdim // MCRegisterInfo initialization routine. 389224145Sdim OS << "static inline void Init" << TargetName 390226633Sdim << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 391226633Sdim << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n"; 392224145Sdim OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 393226633Sdim << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, " 394226633Sdim << RegisterClasses.size() << ");\n\n"; 395224145Sdim 396226633Sdim EmitRegMapping(OS, Regs, false); 397226633Sdim 398226633Sdim OS << "}\n\n"; 399226633Sdim 400226633Sdim 401224145Sdim OS << "} // End llvm namespace \n"; 402224145Sdim OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 403224145Sdim} 404224145Sdim 405224145Sdimvoid 406224145SdimRegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 407224145Sdim CodeGenRegBank &RegBank) { 408193323Sed EmitSourceFileHeader("Register Information Header Fragment", OS); 409224145Sdim 410224145Sdim OS << "\n#ifdef GET_REGINFO_HEADER\n"; 411224145Sdim OS << "#undef GET_REGINFO_HEADER\n"; 412224145Sdim 413193323Sed const std::string &TargetName = Target.getName(); 414193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 415193323Sed 416193323Sed OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 417193323Sed OS << "#include <string>\n\n"; 418193323Sed 419193323Sed OS << "namespace llvm {\n\n"; 420193323Sed 421193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 422226633Sdim << " explicit " << ClassName 423226633Sdim << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n" 424193323Sed << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 425193323Sed << " { return false; }\n" 426193323Sed << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 427199481Srdivacky << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" 428210299Sed << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" 429226633Sdim << " const TargetRegisterClass *" 430226633Sdim "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n" 431193323Sed << "};\n\n"; 432193323Sed 433224145Sdim const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 434224145Sdim if (!SubRegIndices.empty()) { 435224145Sdim OS << "\n// Subregister indices\n"; 436224145Sdim std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); 437224145Sdim if (!Namespace.empty()) 438224145Sdim OS << "namespace " << Namespace << " {\n"; 439224145Sdim OS << "enum {\n NoSubRegister,\n"; 440224145Sdim for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i) 441224145Sdim OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 442224145Sdim OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; 443224145Sdim OS << "};\n"; 444224145Sdim if (!Namespace.empty()) 445224145Sdim OS << "}\n"; 446224145Sdim } 447224145Sdim 448226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 449193323Sed 450193323Sed if (!RegisterClasses.empty()) { 451226633Sdim OS << "namespace " << RegisterClasses[0]->Namespace 452193323Sed << " { // Register classes\n"; 453221345Sdim 454193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 455226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 456224145Sdim const std::string &Name = RC.getName(); 457193323Sed 458193323Sed // Output the register class definition. 459193323Sed OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 460224145Sdim << " " << Name << "Class();\n"; 461224145Sdim if (!RC.AltOrderSelect.empty()) 462224145Sdim OS << " ArrayRef<unsigned> " 463224145Sdim "getRawAllocationOrder(const MachineFunction&) const;\n"; 464224145Sdim OS << " };\n"; 465193323Sed 466193323Sed // Output the extern for the instance. 467193323Sed OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 468193323Sed // Output the extern for the pointer to the instance (should remove). 469193323Sed OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 470193323Sed << Name << "RegClass;\n"; 471193323Sed } 472193323Sed OS << "} // end of namespace " << TargetName << "\n\n"; 473193323Sed } 474193323Sed OS << "} // End llvm namespace \n"; 475224145Sdim OS << "#endif // GET_REGINFO_HEADER\n\n"; 476193323Sed} 477193323Sed 478224145Sdim// 479224145Sdim// runTargetDesc - Output the target register and register file descriptions. 480224145Sdim// 481224145Sdimvoid 482224145SdimRegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 483224145Sdim CodeGenRegBank &RegBank){ 484224145Sdim EmitSourceFileHeader("Target Register and Register Classes Information", OS); 485193323Sed 486224145Sdim OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 487224145Sdim OS << "#undef GET_REGINFO_TARGET_DESC\n"; 488193323Sed 489193323Sed OS << "namespace llvm {\n\n"; 490193323Sed 491226633Sdim // Get access to MCRegisterClass data. 492226633Sdim OS << "extern MCRegisterClass " << Target.getName() 493226633Sdim << "MCRegisterClasses[];\n"; 494226633Sdim 495223017Sdim // Start out by emitting each of the register classes. 496226633Sdim ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 497193323Sed 498223017Sdim // Collect all registers belonging to any allocatable class. 499223017Sdim std::set<Record*> AllocatableRegs; 500223017Sdim 501226633Sdim // Collect allocatable registers. 502193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 503226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 504224145Sdim ArrayRef<Record*> Order = RC.getOrder(); 505193323Sed 506223017Sdim if (RC.Allocatable) 507224145Sdim AllocatableRegs.insert(Order.begin(), Order.end()); 508226633Sdim } 509223017Sdim 510226633Sdim OS << "namespace { // Register classes...\n"; 511221345Sdim 512193323Sed // Emit the ValueType arrays for each RegisterClass 513193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 514226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 515221345Sdim 516193323Sed // Give the register class a legal C name if it's anonymous. 517224145Sdim std::string Name = RC.getName() + "VTs"; 518221345Sdim 519193323Sed // Emit the register list now. 520221345Sdim OS << " // " << Name 521193323Sed << " Register Class Value Types...\n" 522198090Srdivacky << " static const EVT " << Name 523193323Sed << "[] = {\n "; 524193323Sed for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 525193323Sed OS << getEnumName(RC.VTs[i]) << ", "; 526193323Sed OS << "MVT::Other\n };\n\n"; 527193323Sed } 528193323Sed OS << "} // end anonymous namespace\n\n"; 529221345Sdim 530193323Sed // Now that all of the structs have been emitted, emit the instances. 531193323Sed if (!RegisterClasses.empty()) { 532226633Sdim OS << "namespace " << RegisterClasses[0]->Namespace 533193323Sed << " { // Register class instances\n"; 534193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 535226633Sdim OS << " " << RegisterClasses[i]->getName() << "Class\t" 536226633Sdim << RegisterClasses[i]->getName() << "RegClass;\n"; 537221345Sdim 538193323Sed std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 539193323Sed 540226633Sdim OS << "\n static const TargetRegisterClass* const " 541226633Sdim << "NullRegClasses[] = { NULL };\n\n"; 542226633Sdim 543223017Sdim unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); 544193323Sed 545208599Srdivacky if (NumSubRegIndices) { 546226633Sdim // Compute the super-register classes for each RegisterClass 547208599Srdivacky for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 548226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 549208599Srdivacky for (DenseMap<Record*,Record*>::const_iterator 550208599Srdivacky i = RC.SubRegClasses.begin(), 551208599Srdivacky e = RC.SubRegClasses.end(); i != e; ++i) { 552208599Srdivacky // Find the register class number of i->second for SuperRegClassMap. 553226633Sdim const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second); 554226633Sdim assert(RC2 && "Invalid register class in SubRegClasses"); 555226633Sdim SuperRegClassMap[RC2->EnumValue].insert(rc); 556208599Srdivacky } 557193323Sed } 558193323Sed 559208599Srdivacky // Emit the super-register classes for each RegisterClass 560208599Srdivacky for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 561226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 562193323Sed 563208599Srdivacky // Give the register class a legal C name if it's anonymous. 564226633Sdim std::string Name = RC.getName(); 565193323Sed 566208599Srdivacky OS << " // " << Name 567208599Srdivacky << " Super-register Classes...\n" 568208599Srdivacky << " static const TargetRegisterClass* const " 569208599Srdivacky << Name << "SuperRegClasses[] = {\n "; 570193323Sed 571208599Srdivacky bool Empty = true; 572208599Srdivacky std::map<unsigned, std::set<unsigned> >::iterator I = 573208599Srdivacky SuperRegClassMap.find(rc); 574208599Srdivacky if (I != SuperRegClassMap.end()) { 575208599Srdivacky for (std::set<unsigned>::iterator II = I->second.begin(), 576208599Srdivacky EE = I->second.end(); II != EE; ++II) { 577226633Sdim const CodeGenRegisterClass &RC2 = *RegisterClasses[*II]; 578208599Srdivacky if (!Empty) 579208599Srdivacky OS << ", "; 580226633Sdim OS << "&" << RC2.getQualifiedName() << "RegClass"; 581208599Srdivacky Empty = false; 582208599Srdivacky } 583208599Srdivacky } 584193323Sed 585208599Srdivacky OS << (!Empty ? ", " : "") << "NULL"; 586208599Srdivacky OS << "\n };\n\n"; 587193323Sed } 588193323Sed } 589193323Sed 590193323Sed // Emit the sub-classes array for each RegisterClass 591193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 592226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 593193323Sed 594193323Sed // Give the register class a legal C name if it's anonymous. 595226633Sdim std::string Name = RC.getName(); 596193323Sed 597226633Sdim OS << " static const unsigned " << Name << "SubclassMask[] = { "; 598226633Sdim printBitVectorAsHex(OS, RC.getSubClasses(), 32); 599226633Sdim OS << "};\n\n"; 600193323Sed } 601193323Sed 602226633Sdim // Emit NULL terminated super-class lists. 603193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 604226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 605226633Sdim ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 606193323Sed 607226633Sdim // Skip classes without supers. We can reuse NullRegClasses. 608226633Sdim if (Supers.empty()) 609226633Sdim continue; 610193323Sed 611226633Sdim OS << " static const TargetRegisterClass* const " 612226633Sdim << RC.getName() << "Superclasses[] = {\n"; 613226633Sdim for (unsigned i = 0; i != Supers.size(); ++i) 614226633Sdim OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; 615226633Sdim OS << " NULL\n };\n\n"; 616193323Sed } 617193323Sed 618224145Sdim // Emit methods. 619193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 620226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[i]; 621221345Sdim OS << RC.getName() << "Class::" << RC.getName() 622226633Sdim << "Class() : TargetRegisterClass(&" 623226633Sdim << Target.getName() << "MCRegisterClasses[" 624226633Sdim << RC.getName() + "RegClassID" << "], " 625193323Sed << RC.getName() + "VTs" << ", " 626226633Sdim << RC.getName() + "SubclassMask" << ", "; 627226633Sdim if (RC.getSuperClasses().empty()) 628226633Sdim OS << "NullRegClasses, "; 629226633Sdim else 630226633Sdim OS << RC.getName() + "Superclasses, "; 631226633Sdim OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) 632226633Sdim << "RegClasses" 633193323Sed << ") {}\n"; 634224145Sdim if (!RC.AltOrderSelect.empty()) { 635224145Sdim OS << "\nstatic inline unsigned " << RC.getName() 636224145Sdim << "AltOrderSelect(const MachineFunction &MF) {" 637224145Sdim << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> " 638224145Sdim << RC.getName() << "Class::" 639224145Sdim << "getRawAllocationOrder(const MachineFunction &MF) const {\n"; 640224145Sdim for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 641224145Sdim ArrayRef<Record*> Elems = RC.getOrder(oi); 642224145Sdim OS << " static const unsigned AltOrder" << oi << "[] = {"; 643224145Sdim for (unsigned elem = 0; elem != Elems.size(); ++elem) 644224145Sdim OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 645224145Sdim OS << " };\n"; 646224145Sdim } 647226633Sdim OS << " const MCRegisterClass &MCR = " << Target.getName() 648226633Sdim << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];" 649226633Sdim << " static const ArrayRef<unsigned> Order[] = {\n" 650226633Sdim << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 651224145Sdim for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 652226633Sdim OS << "),\n makeArrayRef(AltOrder" << oi; 653224145Sdim OS << ")\n };\n const unsigned Select = " << RC.getName() 654224145Sdim << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 655224145Sdim << ");\n return Order[Select];\n}\n"; 656224145Sdim } 657193323Sed } 658221345Sdim 659193323Sed OS << "}\n"; 660193323Sed } 661193323Sed 662193323Sed OS << "\nnamespace {\n"; 663193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 664193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 665226633Sdim OS << " &" << RegisterClasses[i]->getQualifiedName() 666193323Sed << "RegClass,\n"; 667193323Sed OS << " };\n"; 668224145Sdim OS << "}\n"; // End of anonymous namespace... 669193323Sed 670224145Sdim // Emit extra information about registers. 671224145Sdim const std::string &TargetName = Target.getName(); 672224145Sdim OS << "\n static const TargetRegisterInfoDesc " 673224145Sdim << TargetName << "RegInfoDesc[] = " 674224145Sdim << "{ // Extra Descriptors\n"; 675224145Sdim OS << " { 0, 0 },\n"; 676221345Sdim 677224145Sdim const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 678193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 679224145Sdim const CodeGenRegister &Reg = *Regs[i]; 680224145Sdim OS << " { "; 681224145Sdim OS << Reg.CostPerUse << ", " 682223017Sdim << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 683193323Sed } 684193323Sed OS << " };\n"; // End of register descriptors... 685208599Srdivacky 686224145Sdim 687223017Sdim // Calculate the mapping of subregister+index pairs to physical registers. 688223017Sdim // This will also create further anonymous indexes. 689223017Sdim unsigned NamedIndices = RegBank.getNumNamedIndices(); 690223017Sdim 691208599Srdivacky // Emit SubRegIndex names, skipping 0 692223017Sdim const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 693224145Sdim OS << "\n static const char *const " << TargetName 694224145Sdim << "SubRegIndexTable[] = { \""; 695208599Srdivacky for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 696208599Srdivacky OS << SubRegIndices[i]->getName(); 697208599Srdivacky if (i+1 != e) 698208599Srdivacky OS << "\", \""; 699208599Srdivacky } 700208599Srdivacky OS << "\" };\n\n"; 701223017Sdim 702223017Sdim // Emit names of the anonymus subreg indexes. 703223017Sdim if (SubRegIndices.size() > NamedIndices) { 704223017Sdim OS << " enum {"; 705223017Sdim for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { 706223017Sdim OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; 707223017Sdim if (i+1 != e) 708223017Sdim OS << ','; 709223017Sdim } 710223017Sdim OS << "\n };\n\n"; 711223017Sdim } 712224145Sdim OS << "\n"; 713193323Sed 714193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 715193323Sed 716193323Sed // Emit the subregister + index mapping function based on the information 717193323Sed // calculated above. 718208599Srdivacky OS << "unsigned " << ClassName 719193323Sed << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 720193323Sed << " switch (RegNo) {\n" 721193323Sed << " default:\n return 0;\n"; 722208599Srdivacky for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 723224145Sdim const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 724208599Srdivacky if (SRM.empty()) 725208599Srdivacky continue; 726224145Sdim OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 727193323Sed OS << " switch (Index) {\n"; 728193323Sed OS << " default: return 0;\n"; 729223017Sdim for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 730210299Sed ie = SRM.end(); ii != ie; ++ii) 731208599Srdivacky OS << " case " << getQualifiedName(ii->first) 732223017Sdim << ": return " << getQualifiedName(ii->second->TheDef) << ";\n"; 733193323Sed OS << " };\n" << " break;\n"; 734193323Sed } 735193323Sed OS << " };\n"; 736193323Sed OS << " return 0;\n"; 737193323Sed OS << "}\n\n"; 738199481Srdivacky 739208599Srdivacky OS << "unsigned " << ClassName 740199481Srdivacky << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n" 741199481Srdivacky << " switch (RegNo) {\n" 742199481Srdivacky << " default:\n return 0;\n"; 743208599Srdivacky for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 744224145Sdim const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 745208599Srdivacky if (SRM.empty()) 746208599Srdivacky continue; 747224145Sdim OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 748223017Sdim for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 749210299Sed ie = SRM.end(); ii != ie; ++ii) 750223017Sdim OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) 751208599Srdivacky << ") return " << getQualifiedName(ii->first) << ";\n"; 752199481Srdivacky OS << " return 0;\n"; 753199481Srdivacky } 754199481Srdivacky OS << " };\n"; 755199481Srdivacky OS << " return 0;\n"; 756199481Srdivacky OS << "}\n\n"; 757210299Sed 758210299Sed // Emit composeSubRegIndices 759210299Sed OS << "unsigned " << ClassName 760210299Sed << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" 761210299Sed << " switch (IdxA) {\n" 762210299Sed << " default:\n return IdxB;\n"; 763210299Sed for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 764210299Sed bool Open = false; 765210299Sed for (unsigned j = 0; j != e; ++j) { 766223017Sdim if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i], 767223017Sdim SubRegIndices[j])) { 768210299Sed if (!Open) { 769210299Sed OS << " case " << getQualifiedName(SubRegIndices[i]) 770210299Sed << ": switch(IdxB) {\n default: return IdxB;\n"; 771210299Sed Open = true; 772210299Sed } 773210299Sed OS << " case " << getQualifiedName(SubRegIndices[j]) 774210299Sed << ": return " << getQualifiedName(Comp) << ";\n"; 775210299Sed } 776210299Sed } 777210299Sed if (Open) 778210299Sed OS << " }\n"; 779210299Sed } 780210299Sed OS << " }\n}\n\n"; 781210299Sed 782226633Sdim // Emit getSubClassWithSubReg. 783226633Sdim OS << "const TargetRegisterClass *" << ClassName 784226633Sdim << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 785226633Sdim " const {\n"; 786226633Sdim if (SubRegIndices.empty()) { 787226633Sdim OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n" 788226633Sdim << " return RC;\n"; 789226633Sdim } else { 790226633Sdim // Use the smallest type that can hold a regclass ID with room for a 791226633Sdim // sentinel. 792226633Sdim if (RegisterClasses.size() < UINT8_MAX) 793226633Sdim OS << " static const uint8_t Table["; 794226633Sdim else if (RegisterClasses.size() < UINT16_MAX) 795226633Sdim OS << " static const uint16_t Table["; 796226633Sdim else 797226633Sdim throw "Too many register classes."; 798226633Sdim OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; 799226633Sdim for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { 800226633Sdim const CodeGenRegisterClass &RC = *RegisterClasses[rci]; 801226633Sdim OS << " {\t// " << RC.getName() << "\n"; 802226633Sdim for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 803226633Sdim Record *Idx = SubRegIndices[sri]; 804226633Sdim if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 805226633Sdim OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 806226633Sdim << " -> " << SRC->getName() << "\n"; 807226633Sdim else 808226633Sdim OS << " 0,\t// " << Idx->getName() << "\n"; 809226633Sdim } 810226633Sdim OS << " },\n"; 811226633Sdim } 812226633Sdim OS << " };\n assert(RC && \"Missing regclass\");\n" 813226633Sdim << " if (!Idx) return RC;\n --Idx;\n" 814226633Sdim << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" 815226633Sdim << " unsigned TV = Table[RC->getID()][Idx];\n" 816226633Sdim << " return TV ? getRegClass(TV - 1) : 0;\n"; 817226633Sdim } 818226633Sdim OS << "}\n\n"; 819226633Sdim 820193323Sed // Emit the constructor of the class... 821224145Sdim OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n"; 822224145Sdim 823193323Sed OS << ClassName << "::" << ClassName 824226633Sdim << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n" 825224145Sdim << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 826208599Srdivacky << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 827224145Sdim << " " << TargetName << "SubRegIndexTable) {\n" 828224145Sdim << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 829226633Sdim << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, " 830226633Sdim << RegisterClasses.size() << ");\n\n"; 831193323Sed 832226633Sdim EmitRegMapping(OS, Regs, true); 833193323Sed 834226633Sdim OS << "}\n\n"; 835193323Sed 836193323Sed OS << "} // End llvm namespace \n"; 837224145Sdim OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 838193323Sed} 839224145Sdim 840224145Sdimvoid RegisterInfoEmitter::run(raw_ostream &OS) { 841224145Sdim CodeGenTarget Target(Records); 842224145Sdim CodeGenRegBank &RegBank = Target.getRegBank(); 843224145Sdim RegBank.computeDerivedInfo(); 844224145Sdim 845224145Sdim runEnums(OS, Target, RegBank); 846224145Sdim runMCDesc(OS, Target, RegBank); 847224145Sdim runTargetHeader(OS, Target, RegBank); 848224145Sdim runTargetDesc(OS, Target, RegBank); 849224145Sdim} 850