RegisterInfoEmitter.cpp revision 195340
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#include "RegisterInfoEmitter.h" 17193323Sed#include "CodeGenTarget.h" 18193323Sed#include "CodeGenRegisters.h" 19193323Sed#include "Record.h" 20193323Sed#include "llvm/ADT/StringExtras.h" 21193323Sed#include "llvm/ADT/STLExtras.h" 22195340Sed#include <algorithm> 23193323Sed#include <set> 24193323Sedusing namespace llvm; 25193323Sed 26193323Sed// runEnums - Print out enum values for all of the registers. 27195340Sedvoid RegisterInfoEmitter::runEnums(raw_ostream &OS) { 28193323Sed CodeGenTarget Target; 29193323Sed const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 30193323Sed 31193323Sed std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 32193323Sed 33193323Sed EmitSourceFileHeader("Target Register Enum Values", OS); 34193323Sed OS << "namespace llvm {\n\n"; 35193323Sed 36193323Sed if (!Namespace.empty()) 37193323Sed OS << "namespace " << Namespace << " {\n"; 38193323Sed OS << " enum {\n NoRegister,\n"; 39193323Sed 40193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) 41193323Sed OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; 42193323Sed OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 43193323Sed OS << " };\n"; 44193323Sed if (!Namespace.empty()) 45193323Sed OS << "}\n"; 46193323Sed OS << "} // End llvm namespace \n"; 47193323Sed} 48193323Sed 49195340Sedvoid RegisterInfoEmitter::runHeader(raw_ostream &OS) { 50193323Sed EmitSourceFileHeader("Register Information Header Fragment", OS); 51193323Sed CodeGenTarget Target; 52193323Sed const std::string &TargetName = Target.getName(); 53193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 54193323Sed 55193323Sed OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 56193323Sed OS << "#include <string>\n\n"; 57193323Sed 58193323Sed OS << "namespace llvm {\n\n"; 59193323Sed 60193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 61193323Sed << " explicit " << ClassName 62193323Sed << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 63193323Sed << " virtual int getDwarfRegNumFull(unsigned RegNum, " 64193323Sed << "unsigned Flavour) const;\n" 65193323Sed << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" 66193323Sed << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 67193323Sed << " { return false; }\n" 68193323Sed << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 69193323Sed << "};\n\n"; 70193323Sed 71193323Sed const std::vector<CodeGenRegisterClass> &RegisterClasses = 72193323Sed Target.getRegisterClasses(); 73193323Sed 74193323Sed if (!RegisterClasses.empty()) { 75193323Sed OS << "namespace " << RegisterClasses[0].Namespace 76193323Sed << " { // Register classes\n"; 77193323Sed 78193323Sed OS << " enum {\n"; 79193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 80193323Sed if (i) OS << ",\n"; 81193323Sed OS << " " << RegisterClasses[i].getName() << "RegClassID"; 82193323Sed OS << " = " << (i+1); 83193323Sed } 84193323Sed OS << "\n };\n\n"; 85193323Sed 86193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 87193323Sed const std::string &Name = RegisterClasses[i].getName(); 88193323Sed 89193323Sed // Output the register class definition. 90193323Sed OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 91193323Sed << " " << Name << "Class();\n" 92193323Sed << RegisterClasses[i].MethodProtos << " };\n"; 93193323Sed 94193323Sed // Output the extern for the instance. 95193323Sed OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 96193323Sed // Output the extern for the pointer to the instance (should remove). 97193323Sed OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 98193323Sed << Name << "RegClass;\n"; 99193323Sed } 100193323Sed OS << "} // end of namespace " << TargetName << "\n\n"; 101193323Sed } 102193323Sed OS << "} // End llvm namespace \n"; 103193323Sed} 104193323Sed 105193323Sedbool isSubRegisterClass(const CodeGenRegisterClass &RC, 106193323Sed std::set<Record*> &RegSet) { 107193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 108193323Sed Record *Reg = RC.Elements[i]; 109193323Sed if (!RegSet.count(Reg)) 110193323Sed return false; 111193323Sed } 112193323Sed return true; 113193323Sed} 114193323Sed 115193323Sedstatic void addSuperReg(Record *R, Record *S, 116193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 117193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 118193323Sed std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 119193323Sed if (R == S) { 120195340Sed errs() << "Error: recursive sub-register relationship between" 121195340Sed << " register " << getQualifiedName(R) 122195340Sed << " and its sub-registers?\n"; 123193323Sed abort(); 124193323Sed } 125193323Sed if (!SuperRegs[R].insert(S).second) 126193323Sed return; 127193323Sed SubRegs[S].insert(R); 128193323Sed Aliases[R].insert(S); 129193323Sed Aliases[S].insert(R); 130193323Sed if (SuperRegs.count(S)) 131193323Sed for (std::set<Record*>::iterator I = SuperRegs[S].begin(), 132193323Sed E = SuperRegs[S].end(); I != E; ++I) 133193323Sed addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 134193323Sed} 135193323Sed 136193323Sedstatic void addSubSuperReg(Record *R, Record *S, 137193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 138193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 139193323Sed std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 140193323Sed if (R == S) { 141195340Sed errs() << "Error: recursive sub-register relationship between" 142195340Sed << " register " << getQualifiedName(R) 143195340Sed << " and its sub-registers?\n"; 144193323Sed abort(); 145193323Sed } 146193323Sed 147193323Sed if (!SubRegs[R].insert(S).second) 148193323Sed return; 149193323Sed addSuperReg(S, R, SubRegs, SuperRegs, Aliases); 150193323Sed Aliases[R].insert(S); 151193323Sed Aliases[S].insert(R); 152193323Sed if (SubRegs.count(S)) 153193323Sed for (std::set<Record*>::iterator I = SubRegs[S].begin(), 154193323Sed E = SubRegs[S].end(); I != E; ++I) 155193323Sed addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 156193323Sed} 157193323Sed 158193323Sedclass RegisterSorter { 159193323Sedprivate: 160193323Sed std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs; 161193323Sed 162193323Sedpublic: 163193323Sed RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS) 164193323Sed : RegisterSubRegs(RS) {}; 165193323Sed 166193323Sed bool operator()(Record *RegA, Record *RegB) { 167193323Sed // B is sub-register of A. 168193323Sed return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); 169193323Sed } 170193323Sed}; 171193323Sed 172193323Sed// RegisterInfoEmitter::run - Main register file description emitter. 173193323Sed// 174195340Sedvoid RegisterInfoEmitter::run(raw_ostream &OS) { 175193323Sed CodeGenTarget Target; 176193323Sed EmitSourceFileHeader("Register Information Source Fragment", OS); 177193323Sed 178193323Sed OS << "namespace llvm {\n\n"; 179193323Sed 180193323Sed // Start out by emitting each of the register classes... to do this, we build 181193323Sed // a set of registers which belong to a register class, this is to ensure that 182193323Sed // each register is only in a single register class. 183193323Sed // 184193323Sed const std::vector<CodeGenRegisterClass> &RegisterClasses = 185193323Sed Target.getRegisterClasses(); 186193323Sed 187193323Sed // Loop over all of the register classes... emitting each one. 188193323Sed OS << "namespace { // Register classes...\n"; 189193323Sed 190193323Sed // RegClassesBelongedTo - Keep track of which register classes each reg 191193323Sed // belongs to. 192193323Sed std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo; 193193323Sed 194193323Sed // Emit the register enum value arrays for each RegisterClass 195193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 196193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 197193323Sed 198193323Sed // Give the register class a legal C name if it's anonymous. 199193323Sed std::string Name = RC.TheDef->getName(); 200193323Sed 201193323Sed // Emit the register list now. 202193323Sed OS << " // " << Name << " Register Class...\n" 203193323Sed << " static const unsigned " << Name 204193323Sed << "[] = {\n "; 205193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 206193323Sed Record *Reg = RC.Elements[i]; 207193323Sed OS << getQualifiedName(Reg) << ", "; 208193323Sed 209193323Sed // Keep track of which regclasses this register is in. 210193323Sed RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); 211193323Sed } 212193323Sed OS << "\n };\n\n"; 213193323Sed } 214193323Sed 215193323Sed // Emit the ValueType arrays for each RegisterClass 216193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 217193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 218193323Sed 219193323Sed // Give the register class a legal C name if it's anonymous. 220193323Sed std::string Name = RC.TheDef->getName() + "VTs"; 221193323Sed 222193323Sed // Emit the register list now. 223193323Sed OS << " // " << Name 224193323Sed << " Register Class Value Types...\n" 225193323Sed << " static const MVT " << Name 226193323Sed << "[] = {\n "; 227193323Sed for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 228193323Sed OS << getEnumName(RC.VTs[i]) << ", "; 229193323Sed OS << "MVT::Other\n };\n\n"; 230193323Sed } 231193323Sed OS << "} // end anonymous namespace\n\n"; 232193323Sed 233193323Sed // Now that all of the structs have been emitted, emit the instances. 234193323Sed if (!RegisterClasses.empty()) { 235193323Sed OS << "namespace " << RegisterClasses[0].Namespace 236193323Sed << " { // Register class instances\n"; 237193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 238193323Sed OS << " " << RegisterClasses[i].getName() << "Class\t" 239193323Sed << RegisterClasses[i].getName() << "RegClass;\n"; 240193323Sed 241193323Sed std::map<unsigned, std::set<unsigned> > SuperClassMap; 242193323Sed std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 243193323Sed OS << "\n"; 244193323Sed 245193323Sed // Emit the sub-register classes for each RegisterClass 246193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 247193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 248193323Sed 249193323Sed // Give the register class a legal C name if it's anonymous. 250193323Sed std::string Name = RC.TheDef->getName(); 251193323Sed 252193323Sed OS << " // " << Name 253193323Sed << " Sub-register Classes...\n" 254193323Sed << " static const TargetRegisterClass* const " 255193323Sed << Name << "SubRegClasses [] = {\n "; 256193323Sed 257193323Sed bool Empty = true; 258193323Sed 259193323Sed for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size(); 260193323Sed subrc != subrcMax; ++subrc) { 261193323Sed unsigned rc2 = 0, e2 = RegisterClasses.size(); 262193323Sed for (; rc2 != e2; ++rc2) { 263193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 264193323Sed if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) { 265193323Sed if (!Empty) 266193323Sed OS << ", "; 267193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 268193323Sed Empty = false; 269193323Sed 270193323Sed std::map<unsigned, std::set<unsigned> >::iterator SCMI = 271193323Sed SuperRegClassMap.find(rc2); 272193323Sed if (SCMI == SuperRegClassMap.end()) { 273193323Sed SuperRegClassMap.insert(std::make_pair(rc2, 274193323Sed std::set<unsigned>())); 275193323Sed SCMI = SuperRegClassMap.find(rc2); 276193323Sed } 277193323Sed SCMI->second.insert(rc); 278193323Sed break; 279193323Sed } 280193323Sed } 281193323Sed if (rc2 == e2) 282193323Sed throw "Register Class member '" + 283193323Sed RC.SubRegClasses[subrc]->getName() + 284193323Sed "' is not a valid RegisterClass!"; 285193323Sed } 286193323Sed 287193323Sed OS << (!Empty ? ", " : "") << "NULL"; 288193323Sed OS << "\n };\n\n"; 289193323Sed } 290193323Sed 291193323Sed // Emit the super-register classes for each RegisterClass 292193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 293193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 294193323Sed 295193323Sed // Give the register class a legal C name if it's anonymous. 296193323Sed std::string Name = RC.TheDef->getName(); 297193323Sed 298193323Sed OS << " // " << Name 299193323Sed << " Super-register Classes...\n" 300193323Sed << " static const TargetRegisterClass* const " 301193323Sed << Name << "SuperRegClasses [] = {\n "; 302193323Sed 303193323Sed bool Empty = true; 304193323Sed std::map<unsigned, std::set<unsigned> >::iterator I = 305193323Sed SuperRegClassMap.find(rc); 306193323Sed if (I != SuperRegClassMap.end()) { 307193323Sed for (std::set<unsigned>::iterator II = I->second.begin(), 308193323Sed EE = I->second.end(); II != EE; ++II) { 309193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 310193323Sed if (!Empty) 311193323Sed OS << ", "; 312193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 313193323Sed Empty = false; 314193323Sed } 315193323Sed } 316193323Sed 317193323Sed OS << (!Empty ? ", " : "") << "NULL"; 318193323Sed OS << "\n };\n\n"; 319193323Sed } 320193323Sed 321193323Sed // Emit the sub-classes array for each RegisterClass 322193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 323193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 324193323Sed 325193323Sed // Give the register class a legal C name if it's anonymous. 326193323Sed std::string Name = RC.TheDef->getName(); 327193323Sed 328193323Sed std::set<Record*> RegSet; 329193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 330193323Sed Record *Reg = RC.Elements[i]; 331193323Sed RegSet.insert(Reg); 332193323Sed } 333193323Sed 334193323Sed OS << " // " << Name 335193323Sed << " Register Class sub-classes...\n" 336193323Sed << " static const TargetRegisterClass* const " 337193323Sed << Name << "Subclasses [] = {\n "; 338193323Sed 339193323Sed bool Empty = true; 340193323Sed for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 341193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 342193323Sed 343193323Sed // RC2 is a sub-class of RC if it is a valid replacement for any 344193323Sed // instruction operand where an RC register is required. It must satisfy 345193323Sed // these conditions: 346193323Sed // 347193323Sed // 1. All RC2 registers are also in RC. 348193323Sed // 2. The RC2 spill size must not be smaller that the RC spill size. 349193323Sed // 3. RC2 spill alignment must be compatible with RC. 350193323Sed // 351193323Sed // Sub-classes are used to determine if a virtual register can be used 352193323Sed // as an instruction operand, or if it must be copied first. 353193323Sed 354193323Sed if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || 355193323Sed (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) || 356193323Sed RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) 357193323Sed continue; 358193323Sed 359193323Sed if (!Empty) OS << ", "; 360193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 361193323Sed Empty = false; 362193323Sed 363193323Sed std::map<unsigned, std::set<unsigned> >::iterator SCMI = 364193323Sed SuperClassMap.find(rc2); 365193323Sed if (SCMI == SuperClassMap.end()) { 366193323Sed SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 367193323Sed SCMI = SuperClassMap.find(rc2); 368193323Sed } 369193323Sed SCMI->second.insert(rc); 370193323Sed } 371193323Sed 372193323Sed OS << (!Empty ? ", " : "") << "NULL"; 373193323Sed OS << "\n };\n\n"; 374193323Sed } 375193323Sed 376193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 377193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 378193323Sed 379193323Sed // Give the register class a legal C name if it's anonymous. 380193323Sed std::string Name = RC.TheDef->getName(); 381193323Sed 382193323Sed OS << " // " << Name 383193323Sed << " Register Class super-classes...\n" 384193323Sed << " static const TargetRegisterClass* const " 385193323Sed << Name << "Superclasses [] = {\n "; 386193323Sed 387193323Sed bool Empty = true; 388193323Sed std::map<unsigned, std::set<unsigned> >::iterator I = 389193323Sed SuperClassMap.find(rc); 390193323Sed if (I != SuperClassMap.end()) { 391193323Sed for (std::set<unsigned>::iterator II = I->second.begin(), 392193323Sed EE = I->second.end(); II != EE; ++II) { 393193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 394193323Sed if (!Empty) OS << ", "; 395193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 396193323Sed Empty = false; 397193323Sed } 398193323Sed } 399193323Sed 400193323Sed OS << (!Empty ? ", " : "") << "NULL"; 401193323Sed OS << "\n };\n\n"; 402193323Sed } 403193323Sed 404193323Sed 405193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 406193323Sed const CodeGenRegisterClass &RC = RegisterClasses[i]; 407193323Sed OS << RC.MethodBodies << "\n"; 408193323Sed OS << RC.getName() << "Class::" << RC.getName() 409193323Sed << "Class() : TargetRegisterClass(" 410193323Sed << RC.getName() + "RegClassID" << ", " 411193323Sed << '\"' << RC.getName() << "\", " 412193323Sed << RC.getName() + "VTs" << ", " 413193323Sed << RC.getName() + "Subclasses" << ", " 414193323Sed << RC.getName() + "Superclasses" << ", " 415193323Sed << RC.getName() + "SubRegClasses" << ", " 416193323Sed << RC.getName() + "SuperRegClasses" << ", " 417193323Sed << RC.SpillSize/8 << ", " 418193323Sed << RC.SpillAlignment/8 << ", " 419193323Sed << RC.CopyCost << ", " 420193323Sed << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() 421193323Sed << ") {}\n"; 422193323Sed } 423193323Sed 424193323Sed OS << "}\n"; 425193323Sed } 426193323Sed 427193323Sed OS << "\nnamespace {\n"; 428193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 429193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 430193323Sed OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 431193323Sed << "RegClass,\n"; 432193323Sed OS << " };\n"; 433193323Sed 434193323Sed // Emit register sub-registers / super-registers, aliases... 435193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs; 436193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs; 437193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases; 438193323Sed std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors; 439193323Sed typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 440193323Sed DwarfRegNumsMapTy DwarfRegNums; 441193323Sed 442193323Sed const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 443193323Sed 444193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 445193323Sed Record *R = Regs[i].TheDef; 446193323Sed std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); 447193323Sed // Add information that R aliases all of the elements in the list... and 448193323Sed // that everything in the list aliases R. 449193323Sed for (unsigned j = 0, e = LI.size(); j != e; ++j) { 450193323Sed Record *Reg = LI[j]; 451193323Sed if (RegisterAliases[R].count(Reg)) 452195340Sed errs() << "Warning: register alias between " << getQualifiedName(R) 453195340Sed << " and " << getQualifiedName(Reg) 454195340Sed << " specified multiple times!\n"; 455193323Sed RegisterAliases[R].insert(Reg); 456193323Sed 457193323Sed if (RegisterAliases[Reg].count(R)) 458195340Sed errs() << "Warning: register alias between " << getQualifiedName(R) 459195340Sed << " and " << getQualifiedName(Reg) 460195340Sed << " specified multiple times!\n"; 461193323Sed RegisterAliases[Reg].insert(R); 462193323Sed } 463193323Sed } 464193323Sed 465193323Sed // Process sub-register sets. 466193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 467193323Sed Record *R = Regs[i].TheDef; 468193323Sed std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); 469193323Sed // Process sub-register set and add aliases information. 470193323Sed for (unsigned j = 0, e = LI.size(); j != e; ++j) { 471193323Sed Record *SubReg = LI[j]; 472193323Sed if (RegisterSubRegs[R].count(SubReg)) 473195340Sed errs() << "Warning: register " << getQualifiedName(SubReg) 474195340Sed << " specified as a sub-register of " << getQualifiedName(R) 475195340Sed << " multiple times!\n"; 476193323Sed addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, 477193323Sed RegisterAliases); 478193323Sed } 479193323Sed } 480193323Sed 481193323Sed // Print the SubregHashTable, a simple quadratically probed 482193323Sed // hash table for determining if a register is a subregister 483193323Sed // of another register. 484193323Sed unsigned NumSubRegs = 0; 485193323Sed std::map<Record*, unsigned> RegNo; 486193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 487193323Sed RegNo[Regs[i].TheDef] = i; 488193323Sed NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); 489193323Sed } 490193323Sed 491193323Sed unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); 492193323Sed unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; 493193323Sed std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); 494193323Sed 495193323Sed unsigned hashMisses = 0; 496193323Sed 497193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 498193323Sed Record* R = Regs[i].TheDef; 499193323Sed for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(), 500193323Sed E = RegisterSubRegs[R].end(); I != E; ++I) { 501193323Sed Record* RJ = *I; 502193323Sed // We have to increase the indices of both registers by one when 503193323Sed // computing the hash because, in the generated code, there 504193323Sed // will be an extra empty slot at register 0. 505193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); 506193323Sed unsigned ProbeAmt = 2; 507193323Sed while (SubregHashTable[index*2] != ~0U && 508193323Sed SubregHashTable[index*2+1] != ~0U) { 509193323Sed index = (index + ProbeAmt) & (SubregHashTableSize-1); 510193323Sed ProbeAmt += 2; 511193323Sed 512193323Sed hashMisses++; 513193323Sed } 514193323Sed 515193323Sed SubregHashTable[index*2] = i; 516193323Sed SubregHashTable[index*2+1] = RegNo[RJ]; 517193323Sed } 518193323Sed } 519193323Sed 520193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 521193323Sed 522193323Sed if (SubregHashTableSize) { 523193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 524193323Sed 525193323Sed OS << " const unsigned SubregHashTable[] = { "; 526193323Sed for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { 527193323Sed if (i != 0) 528193323Sed // Insert spaces for nice formatting. 529193323Sed OS << " "; 530193323Sed 531193323Sed if (SubregHashTable[2*i] != ~0U) { 532193323Sed OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " 533193323Sed << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; 534193323Sed } else { 535193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 536193323Sed } 537193323Sed } 538193323Sed 539193323Sed unsigned Idx = SubregHashTableSize*2-2; 540193323Sed if (SubregHashTable[Idx] != ~0U) { 541193323Sed OS << " " 542193323Sed << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " 543193323Sed << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; 544193323Sed } else { 545193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 546193323Sed } 547193323Sed 548193323Sed OS << " const unsigned SubregHashTableSize = " 549193323Sed << SubregHashTableSize << ";\n"; 550193323Sed } else { 551193323Sed OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" 552193323Sed << " const unsigned SubregHashTableSize = 1;\n"; 553193323Sed } 554193323Sed 555193323Sed delete [] SubregHashTable; 556193323Sed 557193323Sed 558193323Sed // Print the SuperregHashTable, a simple quadratically probed 559193323Sed // hash table for determining if a register is a super-register 560193323Sed // of another register. 561193323Sed unsigned NumSupRegs = 0; 562193323Sed RegNo.clear(); 563193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 564193323Sed RegNo[Regs[i].TheDef] = i; 565193323Sed NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size(); 566193323Sed } 567193323Sed 568193323Sed unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs); 569193323Sed unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize]; 570193323Sed std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U); 571193323Sed 572193323Sed hashMisses = 0; 573193323Sed 574193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 575193323Sed Record* R = Regs[i].TheDef; 576193323Sed for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(), 577193323Sed E = RegisterSuperRegs[R].end(); I != E; ++I) { 578193323Sed Record* RJ = *I; 579193323Sed // We have to increase the indices of both registers by one when 580193323Sed // computing the hash because, in the generated code, there 581193323Sed // will be an extra empty slot at register 0. 582193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1); 583193323Sed unsigned ProbeAmt = 2; 584193323Sed while (SuperregHashTable[index*2] != ~0U && 585193323Sed SuperregHashTable[index*2+1] != ~0U) { 586193323Sed index = (index + ProbeAmt) & (SuperregHashTableSize-1); 587193323Sed ProbeAmt += 2; 588193323Sed 589193323Sed hashMisses++; 590193323Sed } 591193323Sed 592193323Sed SuperregHashTable[index*2] = i; 593193323Sed SuperregHashTable[index*2+1] = RegNo[RJ]; 594193323Sed } 595193323Sed } 596193323Sed 597193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 598193323Sed 599193323Sed if (SuperregHashTableSize) { 600193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 601193323Sed 602193323Sed OS << " const unsigned SuperregHashTable[] = { "; 603193323Sed for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) { 604193323Sed if (i != 0) 605193323Sed // Insert spaces for nice formatting. 606193323Sed OS << " "; 607193323Sed 608193323Sed if (SuperregHashTable[2*i] != ~0U) { 609193323Sed OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", " 610193323Sed << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n"; 611193323Sed } else { 612193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 613193323Sed } 614193323Sed } 615193323Sed 616193323Sed unsigned Idx = SuperregHashTableSize*2-2; 617193323Sed if (SuperregHashTable[Idx] != ~0U) { 618193323Sed OS << " " 619193323Sed << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", " 620193323Sed << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n"; 621193323Sed } else { 622193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 623193323Sed } 624193323Sed 625193323Sed OS << " const unsigned SuperregHashTableSize = " 626193323Sed << SuperregHashTableSize << ";\n"; 627193323Sed } else { 628193323Sed OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n" 629193323Sed << " const unsigned SuperregHashTableSize = 1;\n"; 630193323Sed } 631193323Sed 632193323Sed delete [] SuperregHashTable; 633193323Sed 634193323Sed 635193323Sed // Print the AliasHashTable, a simple quadratically probed 636193323Sed // hash table for determining if a register aliases another register. 637193323Sed unsigned NumAliases = 0; 638193323Sed RegNo.clear(); 639193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 640193323Sed RegNo[Regs[i].TheDef] = i; 641193323Sed NumAliases += RegisterAliases[Regs[i].TheDef].size(); 642193323Sed } 643193323Sed 644193323Sed unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); 645193323Sed unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; 646193323Sed std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); 647193323Sed 648193323Sed hashMisses = 0; 649193323Sed 650193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 651193323Sed Record* R = Regs[i].TheDef; 652193323Sed for (std::set<Record*>::iterator I = RegisterAliases[R].begin(), 653193323Sed E = RegisterAliases[R].end(); I != E; ++I) { 654193323Sed Record* RJ = *I; 655193323Sed // We have to increase the indices of both registers by one when 656193323Sed // computing the hash because, in the generated code, there 657193323Sed // will be an extra empty slot at register 0. 658193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1); 659193323Sed unsigned ProbeAmt = 2; 660193323Sed while (AliasesHashTable[index*2] != ~0U && 661193323Sed AliasesHashTable[index*2+1] != ~0U) { 662193323Sed index = (index + ProbeAmt) & (AliasesHashTableSize-1); 663193323Sed ProbeAmt += 2; 664193323Sed 665193323Sed hashMisses++; 666193323Sed } 667193323Sed 668193323Sed AliasesHashTable[index*2] = i; 669193323Sed AliasesHashTable[index*2+1] = RegNo[RJ]; 670193323Sed } 671193323Sed } 672193323Sed 673193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 674193323Sed 675193323Sed if (AliasesHashTableSize) { 676193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 677193323Sed 678193323Sed OS << " const unsigned AliasesHashTable[] = { "; 679193323Sed for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { 680193323Sed if (i != 0) 681193323Sed // Insert spaces for nice formatting. 682193323Sed OS << " "; 683193323Sed 684193323Sed if (AliasesHashTable[2*i] != ~0U) { 685193323Sed OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " 686193323Sed << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; 687193323Sed } else { 688193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 689193323Sed } 690193323Sed } 691193323Sed 692193323Sed unsigned Idx = AliasesHashTableSize*2-2; 693193323Sed if (AliasesHashTable[Idx] != ~0U) { 694193323Sed OS << " " 695193323Sed << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", " 696193323Sed << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n"; 697193323Sed } else { 698193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 699193323Sed } 700193323Sed 701193323Sed OS << " const unsigned AliasesHashTableSize = " 702193323Sed << AliasesHashTableSize << ";\n"; 703193323Sed } else { 704193323Sed OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" 705193323Sed << " const unsigned AliasesHashTableSize = 1;\n"; 706193323Sed } 707193323Sed 708193323Sed delete [] AliasesHashTable; 709193323Sed 710193323Sed if (!RegisterAliases.empty()) 711193323Sed OS << "\n\n // Register Alias Sets...\n"; 712193323Sed 713193323Sed // Emit the empty alias list 714193323Sed OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; 715193323Sed // Loop over all of the registers which have aliases, emitting the alias list 716193323Sed // to memory. 717193323Sed for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 718193323Sed I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { 719193323Sed OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; 720193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 721193323Sed E = I->second.end(); ASI != E; ++ASI) 722193323Sed OS << getQualifiedName(*ASI) << ", "; 723193323Sed OS << "0 };\n"; 724193323Sed } 725193323Sed 726193323Sed if (!RegisterSubRegs.empty()) 727193323Sed OS << "\n\n // Register Sub-registers Sets...\n"; 728193323Sed 729193323Sed // Emit the empty sub-registers list 730193323Sed OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 731193323Sed // Loop over all of the registers which have sub-registers, emitting the 732193323Sed // sub-registers list to memory. 733193323Sed for (std::map<Record*, std::set<Record*>, LessRecord>::iterator 734193323Sed I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { 735193323Sed OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; 736193323Sed std::vector<Record*> SubRegsVector; 737193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 738193323Sed E = I->second.end(); ASI != E; ++ASI) 739193323Sed SubRegsVector.push_back(*ASI); 740193323Sed RegisterSorter RS(RegisterSubRegs); 741193323Sed std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); 742193323Sed for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) 743193323Sed OS << getQualifiedName(SubRegsVector[i]) << ", "; 744193323Sed OS << "0 };\n"; 745193323Sed } 746193323Sed 747193323Sed if (!RegisterSuperRegs.empty()) 748193323Sed OS << "\n\n // Register Super-registers Sets...\n"; 749193323Sed 750193323Sed // Emit the empty super-registers list 751193323Sed OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 752193323Sed // Loop over all of the registers which have super-registers, emitting the 753193323Sed // super-registers list to memory. 754193323Sed for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 755193323Sed I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { 756193323Sed OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; 757193323Sed 758193323Sed std::vector<Record*> SuperRegsVector; 759193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 760193323Sed E = I->second.end(); ASI != E; ++ASI) 761193323Sed SuperRegsVector.push_back(*ASI); 762193323Sed RegisterSorter RS(RegisterSubRegs); 763193323Sed std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); 764193323Sed for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) 765193323Sed OS << getQualifiedName(SuperRegsVector[i]) << ", "; 766193323Sed OS << "0 };\n"; 767193323Sed } 768193323Sed 769193323Sed OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 770193323Sed OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; 771193323Sed 772193323Sed // Now that register alias and sub-registers sets have been emitted, emit the 773193323Sed // register descriptors now. 774193323Sed const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 775193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 776193323Sed const CodeGenRegister &Reg = Registers[i]; 777193323Sed OS << " { \""; 778193323Sed if (!Reg.TheDef->getValueAsString("AsmName").empty()) 779193323Sed OS << Reg.TheDef->getValueAsString("AsmName"); 780193323Sed else 781193323Sed OS << Reg.getName(); 782193323Sed OS << "\",\t\""; 783193323Sed OS << Reg.getName() << "\",\t"; 784193323Sed if (RegisterAliases.count(Reg.TheDef)) 785193323Sed OS << Reg.getName() << "_AliasSet,\t"; 786193323Sed else 787193323Sed OS << "Empty_AliasSet,\t"; 788193323Sed if (RegisterSubRegs.count(Reg.TheDef)) 789193323Sed OS << Reg.getName() << "_SubRegsSet,\t"; 790193323Sed else 791193323Sed OS << "Empty_SubRegsSet,\t"; 792193323Sed if (RegisterSuperRegs.count(Reg.TheDef)) 793193323Sed OS << Reg.getName() << "_SuperRegsSet },\n"; 794193323Sed else 795193323Sed OS << "Empty_SuperRegsSet },\n"; 796193323Sed } 797193323Sed OS << " };\n"; // End of register descriptors... 798193323Sed OS << "}\n\n"; // End of anonymous namespace... 799193323Sed 800193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 801193323Sed 802193323Sed // Calculate the mapping of subregister+index pairs to physical registers. 803193323Sed std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet"); 804193323Sed for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { 805193323Sed int subRegIndex = SubRegs[i]->getValueAsInt("index"); 806193323Sed std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From"); 807193323Sed std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To"); 808193323Sed 809193323Sed if (From.size() != To.size()) { 810195340Sed errs() << "Error: register list and sub-register list not of equal length" 811195340Sed << " in SubRegSet\n"; 812193323Sed exit(1); 813193323Sed } 814193323Sed 815193323Sed // For each entry in from/to vectors, insert the to register at index 816193323Sed for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii) 817193323Sed SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii])); 818193323Sed } 819193323Sed 820193323Sed // Emit the subregister + index mapping function based on the information 821193323Sed // calculated above. 822193323Sed OS << "unsigned " << ClassName 823193323Sed << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 824193323Sed << " switch (RegNo) {\n" 825193323Sed << " default:\n return 0;\n"; 826193323Sed for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator 827193323Sed I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { 828193323Sed OS << " case " << getQualifiedName(I->first) << ":\n"; 829193323Sed OS << " switch (Index) {\n"; 830193323Sed OS << " default: return 0;\n"; 831193323Sed for (unsigned i = 0, e = I->second.size(); i != e; ++i) 832193323Sed OS << " case " << (I->second)[i].first << ": return " 833193323Sed << getQualifiedName((I->second)[i].second) << ";\n"; 834193323Sed OS << " };\n" << " break;\n"; 835193323Sed } 836193323Sed OS << " };\n"; 837193323Sed OS << " return 0;\n"; 838193323Sed OS << "}\n\n"; 839193323Sed 840193323Sed // Emit the constructor of the class... 841193323Sed OS << ClassName << "::" << ClassName 842193323Sed << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 843193323Sed << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 844193323Sed << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " 845193323Sed << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" 846193323Sed << " SubregHashTable, SubregHashTableSize,\n" 847193323Sed << " SuperregHashTable, SuperregHashTableSize,\n" 848193323Sed << " AliasesHashTable, AliasesHashTableSize) {\n" 849193323Sed << "}\n\n"; 850193323Sed 851193323Sed // Collect all information about dwarf register numbers 852193323Sed 853193323Sed // First, just pull all provided information to the map 854193323Sed unsigned maxLength = 0; 855193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 856193323Sed Record *Reg = Registers[i].TheDef; 857193323Sed std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 858193323Sed maxLength = std::max((size_t)maxLength, RegNums.size()); 859193323Sed if (DwarfRegNums.count(Reg)) 860195340Sed errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 861195340Sed << "specified multiple times\n"; 862193323Sed DwarfRegNums[Reg] = RegNums; 863193323Sed } 864193323Sed 865193323Sed // Now we know maximal length of number list. Append -1's, where needed 866193323Sed for (DwarfRegNumsMapTy::iterator 867193323Sed I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 868193323Sed for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 869193323Sed I->second.push_back(-1); 870193323Sed 871193323Sed // Emit information about the dwarf register numbers. 872193323Sed OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " 873193323Sed << "unsigned Flavour) const {\n" 874193323Sed << " switch (Flavour) {\n" 875193323Sed << " default:\n" 876193323Sed << " assert(0 && \"Unknown DWARF flavour\");\n" 877193323Sed << " return -1;\n"; 878193323Sed 879193323Sed for (unsigned i = 0, e = maxLength; i != e; ++i) { 880193323Sed OS << " case " << i << ":\n" 881193323Sed << " switch (RegNum) {\n" 882193323Sed << " default:\n" 883193323Sed << " assert(0 && \"Invalid RegNum\");\n" 884193323Sed << " return -1;\n"; 885193323Sed 886193323Sed // Sort by name to get a stable order. 887193323Sed 888193323Sed 889193323Sed for (DwarfRegNumsMapTy::iterator 890193323Sed I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 891193323Sed int RegNo = I->second[i]; 892193323Sed if (RegNo != -2) 893193323Sed OS << " case " << getQualifiedName(I->first) << ":\n" 894193323Sed << " return " << RegNo << ";\n"; 895193323Sed else 896193323Sed OS << " case " << getQualifiedName(I->first) << ":\n" 897193323Sed << " assert(0 && \"Invalid register for this mode\");\n" 898193323Sed << " return -1;\n"; 899193323Sed } 900193323Sed OS << " };\n"; 901193323Sed } 902193323Sed 903193323Sed OS << " };\n}\n\n"; 904193323Sed 905193323Sed OS << "} // End llvm namespace \n"; 906193323Sed} 907