PseudoLoweringEmitter.cpp revision 224133
1224133Sdim//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim 10224133Sdim#define DEBUG_TYPE "pseudo-lowering" 11224133Sdim#include "Error.h" 12224133Sdim#include "CodeGenInstruction.h" 13224133Sdim#include "PseudoLoweringEmitter.h" 14224133Sdim#include "Record.h" 15224133Sdim#include "llvm/ADT/IndexedMap.h" 16224133Sdim#include "llvm/ADT/StringMap.h" 17224133Sdim#include "llvm/Support/ErrorHandling.h" 18224133Sdim#include "llvm/Support/Debug.h" 19224133Sdim#include <vector> 20224133Sdimusing namespace llvm; 21224133Sdim 22224133Sdim// FIXME: This pass currently can only expand a pseudo to a single instruction. 23224133Sdim// The pseudo expansion really should take a list of dags, not just 24224133Sdim// a single dag, so we can do fancier things. 25224133Sdim 26224133Sdimunsigned PseudoLoweringEmitter:: 27224133SdimaddDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, 28224133Sdim IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 29224133Sdim unsigned OpsAdded = 0; 30224133Sdim for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { 31224133Sdim if (DefInit *DI = dynamic_cast<DefInit*>(Dag->getArg(i))) { 32224133Sdim // Physical register reference. Explicit check for the special case 33224133Sdim // "zero_reg" definition. 34224133Sdim if (DI->getDef()->isSubClassOf("Register") || 35224133Sdim DI->getDef()->getName() == "zero_reg") { 36224133Sdim OperandMap[BaseIdx + i].Kind = OpData::Reg; 37224133Sdim OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 38224133Sdim ++OpsAdded; 39224133Sdim continue; 40224133Sdim } 41224133Sdim 42224133Sdim // Normal operands should always have the same type, or we have a 43224133Sdim // problem. 44224133Sdim // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 45224133Sdim assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 46224133Sdim if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 47224133Sdim throw TGError(Rec->getLoc(), 48224133Sdim "Pseudo operand type '" + DI->getDef()->getName() + 49224133Sdim "' does not match expansion operand type '" + 50224133Sdim Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 51224133Sdim // Source operand maps to destination operand. The Data element 52224133Sdim // will be filled in later, just set the Kind for now. Do it 53224133Sdim // for each corresponding MachineInstr operand, not just the first. 54224133Sdim for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 55224133Sdim OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 56224133Sdim OpsAdded += Insn.Operands[i].MINumOperands; 57224133Sdim } else if (IntInit *II = dynamic_cast<IntInit*>(Dag->getArg(i))) { 58224133Sdim OperandMap[BaseIdx + i].Kind = OpData::Imm; 59224133Sdim OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 60224133Sdim ++OpsAdded; 61224133Sdim } else if (DagInit *SubDag = dynamic_cast<DagInit*>(Dag->getArg(i))) { 62224133Sdim // Just add the operands recursively. This is almost certainly 63224133Sdim // a constant value for a complex operand (> 1 MI operand). 64224133Sdim unsigned NewOps = 65224133Sdim addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 66224133Sdim OpsAdded += NewOps; 67224133Sdim // Since we added more than one, we also need to adjust the base. 68224133Sdim BaseIdx += NewOps - 1; 69224133Sdim } else 70224133Sdim assert(0 && "Unhandled pseudo-expansion argument type!"); 71224133Sdim } 72224133Sdim return OpsAdded; 73224133Sdim} 74224133Sdim 75224133Sdimvoid PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { 76224133Sdim DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); 77224133Sdim 78224133Sdim // Validate that the result pattern has the corrent number and types 79224133Sdim // of arguments for the instruction it references. 80224133Sdim DagInit *Dag = Rec->getValueAsDag("ResultInst"); 81224133Sdim assert(Dag && "Missing result instruction in pseudo expansion!"); 82224133Sdim DEBUG(dbgs() << " Result: " << *Dag << "\n"); 83224133Sdim 84224133Sdim DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator()); 85224133Sdim if (!OpDef) 86224133Sdim throw TGError(Rec->getLoc(), Rec->getName() + 87224133Sdim " has unexpected operator type!"); 88224133Sdim Record *Operator = OpDef->getDef(); 89224133Sdim if (!Operator->isSubClassOf("Instruction")) 90224133Sdim throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 91224133Sdim "' is not an instruction!"); 92224133Sdim 93224133Sdim CodeGenInstruction Insn(Operator); 94224133Sdim 95224133Sdim if (Insn.isCodeGenOnly || Insn.isPseudo) 96224133Sdim throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 97224133Sdim "' cannot be another pseudo instruction!"); 98224133Sdim 99224133Sdim if (Insn.Operands.size() != Dag->getNumArgs()) 100224133Sdim throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 101224133Sdim "' operand count mismatch"); 102224133Sdim 103224133Sdim IndexedMap<OpData> OperandMap; 104224133Sdim OperandMap.grow(Insn.Operands.size()); 105224133Sdim 106224133Sdim addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); 107224133Sdim 108224133Sdim // If there are more operands that weren't in the DAG, they have to 109224133Sdim // be operands that have default values, or we have an error. Currently, 110224133Sdim // PredicateOperand and OptionalDefOperand both have default values. 111224133Sdim 112224133Sdim 113224133Sdim // Validate that each result pattern argument has a matching (by name) 114224133Sdim // argument in the source instruction, in either the (outs) or (ins) list. 115224133Sdim // Also check that the type of the arguments match. 116224133Sdim // 117224133Sdim // Record the mapping of the source to result arguments for use by 118224133Sdim // the lowering emitter. 119224133Sdim CodeGenInstruction SourceInsn(Rec); 120224133Sdim StringMap<unsigned> SourceOperands; 121224133Sdim for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) 122224133Sdim SourceOperands[SourceInsn.Operands[i].Name] = i; 123224133Sdim 124224133Sdim DEBUG(dbgs() << " Operand mapping:\n"); 125224133Sdim for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { 126224133Sdim // We've already handled constant values. Just map instruction operands 127224133Sdim // here. 128224133Sdim if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) 129224133Sdim continue; 130224133Sdim StringMap<unsigned>::iterator SourceOp = 131224133Sdim SourceOperands.find(Dag->getArgName(i)); 132224133Sdim if (SourceOp == SourceOperands.end()) 133224133Sdim throw TGError(Rec->getLoc(), 134224133Sdim "Pseudo output operand '" + Dag->getArgName(i) + 135224133Sdim "' has no matching source operand."); 136224133Sdim // Map the source operand to the destination operand index for each 137224133Sdim // MachineInstr operand. 138224133Sdim for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 139224133Sdim OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = 140224133Sdim SourceOp->getValue(); 141224133Sdim 142224133Sdim DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i << "\n"); 143224133Sdim } 144224133Sdim 145224133Sdim Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); 146224133Sdim} 147224133Sdim 148224133Sdimvoid PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { 149224133Sdim // Emit file header. 150224133Sdim EmitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); 151224133Sdim 152224133Sdim o << "bool " << Target.getName() + "AsmPrinter" << "::\n" 153224133Sdim << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n" 154224133Sdim << " const MachineInstr *MI) {\n" 155224133Sdim << " switch (MI->getOpcode()) {\n" 156224133Sdim << " default: return false;\n"; 157224133Sdim for (unsigned i = 0, e = Expansions.size(); i != e; ++i) { 158224133Sdim PseudoExpansion &Expansion = Expansions[i]; 159224133Sdim CodeGenInstruction &Source = Expansion.Source; 160224133Sdim CodeGenInstruction &Dest = Expansion.Dest; 161224133Sdim o << " case " << Source.Namespace << "::" 162224133Sdim << Source.TheDef->getName() << ": {\n" 163224133Sdim << " MCInst TmpInst;\n" 164224133Sdim << " MCOperand MCOp;\n" 165224133Sdim << " TmpInst.setOpcode(" << Dest.Namespace << "::" 166224133Sdim << Dest.TheDef->getName() << ");\n"; 167224133Sdim 168224133Sdim // Copy the operands from the source instruction. 169224133Sdim // FIXME: Instruction operands with defaults values (predicates and cc_out 170224133Sdim // in ARM, for example shouldn't need explicit values in the 171224133Sdim // expansion DAG. 172224133Sdim unsigned MIOpNo = 0; 173224133Sdim for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E; 174224133Sdim ++OpNo) { 175224133Sdim o << " // Operand: " << Dest.Operands[OpNo].Name << "\n"; 176224133Sdim for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands; 177224133Sdim i != e; ++i) { 178224133Sdim switch (Expansion.OperandMap[MIOpNo + i].Kind) { 179224133Sdim default: 180224133Sdim llvm_unreachable("Unknown operand type?!"); 181224133Sdim case OpData::Operand: 182224133Sdim o << " lowerOperand(MI->getOperand(" 183224133Sdim << Source.Operands[Expansion.OperandMap[MIOpNo].Data 184224133Sdim .Operand].MIOperandNo + i 185224133Sdim << "), MCOp);\n" 186224133Sdim << " TmpInst.addOperand(MCOp);\n"; 187224133Sdim break; 188224133Sdim case OpData::Imm: 189224133Sdim o << " TmpInst.addOperand(MCOperand::CreateImm(" 190224133Sdim << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; 191224133Sdim break; 192224133Sdim case OpData::Reg: { 193224133Sdim Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; 194224133Sdim o << " TmpInst.addOperand(MCOperand::CreateReg("; 195224133Sdim // "zero_reg" is special. 196224133Sdim if (Reg->getName() == "zero_reg") 197224133Sdim o << "0"; 198224133Sdim else 199224133Sdim o << Reg->getValueAsString("Namespace") << "::" << Reg->getName(); 200224133Sdim o << "));\n"; 201224133Sdim break; 202224133Sdim } 203224133Sdim } 204224133Sdim } 205224133Sdim MIOpNo += Dest.Operands[OpNo].MINumOperands; 206224133Sdim } 207224133Sdim if (Dest.Operands.isVariadic) { 208224133Sdim o << " // variable_ops\n"; 209224133Sdim o << " for (unsigned i = " << MIOpNo 210224133Sdim << ", e = MI->getNumOperands(); i != e; ++i)\n" 211224133Sdim << " if (lowerOperand(MI->getOperand(i), MCOp))\n" 212224133Sdim << " TmpInst.addOperand(MCOp);\n"; 213224133Sdim } 214224133Sdim o << " OutStreamer.EmitInstruction(TmpInst);\n" 215224133Sdim << " break;\n" 216224133Sdim << " }\n"; 217224133Sdim } 218224133Sdim o << " }\n return true;\n}\n\n"; 219224133Sdim} 220224133Sdim 221224133Sdimvoid PseudoLoweringEmitter::run(raw_ostream &o) { 222224133Sdim Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); 223224133Sdim Record *InstructionClass = Records.getClass("PseudoInstExpansion"); 224224133Sdim assert(ExpansionClass && "PseudoInstExpansion class definition missing!"); 225224133Sdim assert(InstructionClass && "Instruction class definition missing!"); 226224133Sdim 227224133Sdim std::vector<Record*> Insts; 228224133Sdim for (std::map<std::string, Record*>::const_iterator I = 229224133Sdim Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) { 230224133Sdim if (I->second->isSubClassOf(ExpansionClass) && 231224133Sdim I->second->isSubClassOf(InstructionClass)) 232224133Sdim Insts.push_back(I->second); 233224133Sdim } 234224133Sdim 235224133Sdim // Process the pseudo expansion definitions, validating them as we do so. 236224133Sdim for (unsigned i = 0, e = Insts.size(); i != e; ++i) 237224133Sdim evaluateExpansion(Insts[i]); 238224133Sdim 239224133Sdim // Generate expansion code to lower the pseudo to an MCInst of the real 240224133Sdim // instruction. 241224133Sdim emitLoweringEmitter(o); 242224133Sdim} 243224133Sdim 244