InstrInfoEmitter.cpp revision 203954
1193323Sed//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of the target 11193323Sed// instruction set for the code generator. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#include "InstrInfoEmitter.h" 16193323Sed#include "CodeGenTarget.h" 17193323Sed#include "Record.h" 18198090Srdivacky#include "llvm/ADT/StringExtras.h" 19193323Sed#include <algorithm> 20193323Sedusing namespace llvm; 21193323Sed 22193323Sedstatic void PrintDefList(const std::vector<Record*> &Uses, 23195340Sed unsigned Num, raw_ostream &OS) { 24193323Sed OS << "static const unsigned ImplicitList" << Num << "[] = { "; 25193323Sed for (unsigned i = 0, e = Uses.size(); i != e; ++i) 26193323Sed OS << getQualifiedName(Uses[i]) << ", "; 27193323Sed OS << "0 };\n"; 28193323Sed} 29193323Sed 30193323Sedstatic void PrintBarriers(std::vector<Record*> &Barriers, 31195340Sed unsigned Num, raw_ostream &OS) { 32193323Sed OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; 33193323Sed for (unsigned i = 0, e = Barriers.size(); i != e; ++i) 34193323Sed OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; 35193323Sed OS << "NULL };\n"; 36193323Sed} 37193323Sed 38193323Sed//===----------------------------------------------------------------------===// 39193323Sed// Instruction Itinerary Information. 40193323Sed//===----------------------------------------------------------------------===// 41193323Sed 42193323Sedstruct RecordNameComparator { 43193323Sed bool operator()(const Record *Rec1, const Record *Rec2) const { 44193323Sed return Rec1->getName() < Rec2->getName(); 45193323Sed } 46193323Sed}; 47193323Sed 48193323Sedvoid InstrInfoEmitter::GatherItinClasses() { 49193323Sed std::vector<Record*> DefList = 50193323Sed Records.getAllDerivedDefinitions("InstrItinClass"); 51193323Sed std::sort(DefList.begin(), DefList.end(), RecordNameComparator()); 52193323Sed 53193323Sed for (unsigned i = 0, N = DefList.size(); i < N; i++) 54193323Sed ItinClassMap[DefList[i]->getName()] = i; 55193323Sed} 56193323Sed 57193323Sedunsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { 58193323Sed return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; 59193323Sed} 60193323Sed 61193323Sed//===----------------------------------------------------------------------===// 62193323Sed// Operand Info Emission. 63193323Sed//===----------------------------------------------------------------------===// 64193323Sed 65193323Sedstd::vector<std::string> 66193323SedInstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 67193323Sed std::vector<std::string> Result; 68193323Sed 69193323Sed for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) { 70193323Sed // Handle aggregate operands and normal operands the same way by expanding 71193323Sed // either case into a list of operands for this op. 72193323Sed std::vector<CodeGenInstruction::OperandInfo> OperandList; 73193323Sed 74193323Sed // This might be a multiple operand thing. Targets like X86 have 75193323Sed // registers in their multi-operand operands. It may also be an anonymous 76193323Sed // operand, which has a single operand, but no declared class for the 77193323Sed // operand. 78193323Sed DagInit *MIOI = Inst.OperandList[i].MIOperandInfo; 79193323Sed 80193323Sed if (!MIOI || MIOI->getNumArgs() == 0) { 81193323Sed // Single, anonymous, operand. 82193323Sed OperandList.push_back(Inst.OperandList[i]); 83193323Sed } else { 84193323Sed for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) { 85193323Sed OperandList.push_back(Inst.OperandList[i]); 86193323Sed 87193323Sed Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef(); 88193323Sed OperandList.back().Rec = OpR; 89193323Sed } 90193323Sed } 91193323Sed 92193323Sed for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 93193323Sed Record *OpR = OperandList[j].Rec; 94193323Sed std::string Res; 95193323Sed 96193323Sed if (OpR->isSubClassOf("RegisterClass")) 97193323Sed Res += getQualifiedName(OpR) + "RegClassID, "; 98198090Srdivacky else if (OpR->isSubClassOf("PointerLikeRegClass")) 99198090Srdivacky Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 100193323Sed else 101193323Sed Res += "0, "; 102198090Srdivacky 103193323Sed // Fill in applicable flags. 104193323Sed Res += "0"; 105193323Sed 106193323Sed // Ptr value whose register class is resolved via callback. 107198090Srdivacky if (OpR->isSubClassOf("PointerLikeRegClass")) 108193323Sed Res += "|(1<<TOI::LookupPtrRegClass)"; 109193323Sed 110193323Sed // Predicate operands. Check to see if the original unexpanded operand 111193323Sed // was of type PredicateOperand. 112193323Sed if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand")) 113193323Sed Res += "|(1<<TOI::Predicate)"; 114193323Sed 115193323Sed // Optional def operands. Check to see if the original unexpanded operand 116193323Sed // was of type OptionalDefOperand. 117193323Sed if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand")) 118193323Sed Res += "|(1<<TOI::OptionalDef)"; 119193323Sed 120193323Sed // Fill in constraint info. 121203954Srdivacky Res += ", "; 122203954Srdivacky 123203954Srdivacky const CodeGenInstruction::ConstraintInfo &Constraint = 124203954Srdivacky Inst.OperandList[i].Constraints[j]; 125203954Srdivacky if (Constraint.isNone()) 126203954Srdivacky Res += "0"; 127203954Srdivacky else if (Constraint.isEarlyClobber()) 128203954Srdivacky Res += "(1 << TOI::EARLY_CLOBBER)"; 129203954Srdivacky else { 130203954Srdivacky assert(Constraint.isTied()); 131203954Srdivacky Res += "((" + utostr(Constraint.getTiedOperand()) + 132203954Srdivacky " << 16) | (1 << TOI::TIED_TO))"; 133203954Srdivacky } 134203954Srdivacky 135193323Sed Result.push_back(Res); 136193323Sed } 137193323Sed } 138193323Sed 139193323Sed return Result; 140193323Sed} 141193323Sed 142195340Sedvoid InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 143193323Sed OperandInfoMapTy &OperandInfoIDs) { 144193323Sed // ID #0 is for no operand info. 145193323Sed unsigned OperandListNum = 0; 146193323Sed OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 147193323Sed 148193323Sed OS << "\n"; 149193323Sed const CodeGenTarget &Target = CDP.getTargetInfo(); 150193323Sed for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 151193323Sed E = Target.inst_end(); II != E; ++II) { 152193323Sed std::vector<std::string> OperandInfo = GetOperandInfo(II->second); 153193323Sed unsigned &N = OperandInfoIDs[OperandInfo]; 154193323Sed if (N != 0) continue; 155193323Sed 156193323Sed N = ++OperandListNum; 157193323Sed OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; 158193323Sed for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) 159193323Sed OS << "{ " << OperandInfo[i] << " }, "; 160193323Sed OS << "};\n"; 161193323Sed } 162193323Sed} 163193323Sed 164193323Sedvoid InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs, 165193323Sed const std::vector<CodeGenRegisterClass> &RCs, 166193323Sed std::vector<Record*> &Barriers) { 167193323Sed std::set<Record*> DefSet; 168193323Sed unsigned NumDefs = Defs.size(); 169193323Sed for (unsigned i = 0; i < NumDefs; ++i) 170193323Sed DefSet.insert(Defs[i]); 171193323Sed 172193323Sed for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 173193323Sed const CodeGenRegisterClass &RC = RCs[i]; 174193323Sed unsigned NumRegs = RC.Elements.size(); 175193323Sed if (NumRegs > NumDefs) 176193323Sed continue; // Can't possibly clobber this RC. 177193323Sed 178193323Sed bool Clobber = true; 179193323Sed for (unsigned j = 0; j < NumRegs; ++j) { 180193323Sed Record *Reg = RC.Elements[j]; 181193323Sed if (!DefSet.count(Reg)) { 182193323Sed Clobber = false; 183193323Sed break; 184193323Sed } 185193323Sed } 186193323Sed if (Clobber) 187193323Sed Barriers.push_back(RC.TheDef); 188193323Sed } 189193323Sed} 190193323Sed 191193323Sed//===----------------------------------------------------------------------===// 192193323Sed// Main Output. 193193323Sed//===----------------------------------------------------------------------===// 194193323Sed 195193323Sed// run - Emit the main instruction description records for the target... 196195340Sedvoid InstrInfoEmitter::run(raw_ostream &OS) { 197193323Sed GatherItinClasses(); 198193323Sed 199193323Sed EmitSourceFileHeader("Target Instruction Descriptors", OS); 200193323Sed OS << "namespace llvm {\n\n"; 201193323Sed 202193323Sed CodeGenTarget &Target = CDP.getTargetInfo(); 203193323Sed const std::string &TargetName = Target.getName(); 204193323Sed Record *InstrInfo = Target.getInstructionSet(); 205193323Sed const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses(); 206193323Sed 207193323Sed // Keep track of all of the def lists we have emitted already. 208193323Sed std::map<std::vector<Record*>, unsigned> EmittedLists; 209193323Sed unsigned ListNumber = 0; 210193323Sed std::map<std::vector<Record*>, unsigned> EmittedBarriers; 211193323Sed unsigned BarrierNumber = 0; 212193323Sed std::map<Record*, unsigned> BarriersMap; 213193323Sed 214193323Sed // Emit all of the instruction's implicit uses and defs. 215193323Sed for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 216193323Sed E = Target.inst_end(); II != E; ++II) { 217193323Sed Record *Inst = II->second.TheDef; 218193323Sed std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 219193323Sed if (!Uses.empty()) { 220193323Sed unsigned &IL = EmittedLists[Uses]; 221193323Sed if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 222193323Sed } 223193323Sed std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 224193323Sed if (!Defs.empty()) { 225193323Sed std::vector<Record*> RCBarriers; 226193323Sed DetectRegisterClassBarriers(Defs, RCs, RCBarriers); 227193323Sed if (!RCBarriers.empty()) { 228193323Sed unsigned &IB = EmittedBarriers[RCBarriers]; 229193323Sed if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); 230193323Sed BarriersMap.insert(std::make_pair(Inst, IB)); 231193323Sed } 232193323Sed 233193323Sed unsigned &IL = EmittedLists[Defs]; 234193323Sed if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 235193323Sed } 236193323Sed } 237193323Sed 238193323Sed OperandInfoMapTy OperandInfoIDs; 239193323Sed 240193323Sed // Emit all of the operand info records. 241193323Sed EmitOperandInfo(OS, OperandInfoIDs); 242193323Sed 243193323Sed // Emit all of the TargetInstrDesc records in their ENUM ordering. 244193323Sed // 245193323Sed OS << "\nstatic const TargetInstrDesc " << TargetName 246193323Sed << "Insts[] = {\n"; 247193323Sed std::vector<const CodeGenInstruction*> NumberedInstructions; 248193323Sed Target.getInstructionsByEnumValue(NumberedInstructions); 249193323Sed 250193323Sed for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) 251193323Sed emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, 252193323Sed BarriersMap, OperandInfoIDs, OS); 253193323Sed OS << "};\n"; 254193323Sed OS << "} // End llvm namespace \n"; 255193323Sed} 256193323Sed 257193323Sedvoid InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 258193323Sed Record *InstrInfo, 259193323Sed std::map<std::vector<Record*>, unsigned> &EmittedLists, 260193323Sed std::map<Record*, unsigned> &BarriersMap, 261193323Sed const OperandInfoMapTy &OpInfo, 262195340Sed raw_ostream &OS) { 263193323Sed int MinOperands = 0; 264193323Sed if (!Inst.OperandList.empty()) 265193323Sed // Each logical operand can be multiple MI operands. 266193323Sed MinOperands = Inst.OperandList.back().MIOperandNo + 267193323Sed Inst.OperandList.back().MINumOperands; 268193323Sed 269193323Sed OS << " { "; 270193323Sed OS << Num << ",\t" << MinOperands << ",\t" 271193323Sed << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) 272193323Sed << ",\t\"" << Inst.TheDef->getName() << "\", 0"; 273193323Sed 274193323Sed // Emit all of the target indepedent flags... 275193323Sed if (Inst.isReturn) OS << "|(1<<TID::Return)"; 276193323Sed if (Inst.isBranch) OS << "|(1<<TID::Branch)"; 277193323Sed if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)"; 278193323Sed if (Inst.isBarrier) OS << "|(1<<TID::Barrier)"; 279193323Sed if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)"; 280193323Sed if (Inst.isCall) OS << "|(1<<TID::Call)"; 281193323Sed if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)"; 282193323Sed if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)"; 283193323Sed if (Inst.mayStore) OS << "|(1<<TID::MayStore)"; 284193323Sed if (Inst.isPredicable) OS << "|(1<<TID::Predicable)"; 285193323Sed if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)"; 286193323Sed if (Inst.isCommutable) OS << "|(1<<TID::Commutable)"; 287193323Sed if (Inst.isTerminator) OS << "|(1<<TID::Terminator)"; 288193323Sed if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)"; 289193323Sed if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)"; 290193323Sed if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)"; 291198892Srdivacky if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)"; 292193323Sed if (Inst.isVariadic) OS << "|(1<<TID::Variadic)"; 293193323Sed if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)"; 294193323Sed if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)"; 295198090Srdivacky if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<TID::ExtraSrcRegAllocReq)"; 296198090Srdivacky if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<TID::ExtraDefRegAllocReq)"; 297193323Sed OS << ", 0"; 298193323Sed 299193323Sed // Emit all of the target-specific flags... 300193323Sed ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields"); 301193323Sed ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts"); 302193323Sed if (LI->getSize() != Shift->getSize()) 303193323Sed throw "Lengths of " + InstrInfo->getName() + 304193323Sed ":(TargetInfoFields, TargetInfoPositions) must be equal!"; 305193323Sed 306193323Sed for (unsigned i = 0, e = LI->getSize(); i != e; ++i) 307193323Sed emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)), 308193323Sed dynamic_cast<IntInit*>(Shift->getElement(i)), OS); 309193323Sed 310193323Sed OS << ", "; 311193323Sed 312193323Sed // Emit the implicit uses and defs lists... 313193323Sed std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 314193323Sed if (UseList.empty()) 315193323Sed OS << "NULL, "; 316193323Sed else 317193323Sed OS << "ImplicitList" << EmittedLists[UseList] << ", "; 318193323Sed 319193323Sed std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 320193323Sed if (DefList.empty()) 321193323Sed OS << "NULL, "; 322193323Sed else 323193323Sed OS << "ImplicitList" << EmittedLists[DefList] << ", "; 324193323Sed 325193323Sed std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef); 326193323Sed if (BI == BarriersMap.end()) 327193323Sed OS << "NULL, "; 328193323Sed else 329193323Sed OS << "Barriers" << BI->second << ", "; 330193323Sed 331193323Sed // Emit the operand info. 332193323Sed std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 333193323Sed if (OperandInfo.empty()) 334193323Sed OS << "0"; 335193323Sed else 336193323Sed OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 337193323Sed 338193323Sed OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 339193323Sed} 340193323Sed 341193323Sed 342193323Sedvoid InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, 343195340Sed IntInit *ShiftInt, raw_ostream &OS) { 344193323Sed if (Val == 0 || ShiftInt == 0) 345193323Sed throw std::string("Illegal value or shift amount in TargetInfo*!"); 346193323Sed RecordVal *RV = R->getValue(Val->getValue()); 347193323Sed int Shift = ShiftInt->getValue(); 348193323Sed 349193323Sed if (RV == 0 || RV->getValue() == 0) { 350193323Sed // This isn't an error if this is a builtin instruction. 351193323Sed if (R->getName() != "PHI" && 352193323Sed R->getName() != "INLINEASM" && 353193323Sed R->getName() != "DBG_LABEL" && 354193323Sed R->getName() != "EH_LABEL" && 355193323Sed R->getName() != "GC_LABEL" && 356198090Srdivacky R->getName() != "KILL" && 357193323Sed R->getName() != "EXTRACT_SUBREG" && 358193323Sed R->getName() != "INSERT_SUBREG" && 359193323Sed R->getName() != "IMPLICIT_DEF" && 360193323Sed R->getName() != "SUBREG_TO_REG" && 361202375Srdivacky R->getName() != "COPY_TO_REGCLASS" && 362203954Srdivacky R->getName() != "DBG_VALUE") 363193323Sed throw R->getName() + " doesn't have a field named '" + 364193323Sed Val->getValue() + "'!"; 365193323Sed return; 366193323Sed } 367193323Sed 368193323Sed Init *Value = RV->getValue(); 369193323Sed if (BitInit *BI = dynamic_cast<BitInit*>(Value)) { 370193323Sed if (BI->getValue()) OS << "|(1<<" << Shift << ")"; 371193323Sed return; 372193323Sed } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) { 373193323Sed // Convert the Bits to an integer to print... 374193323Sed Init *I = BI->convertInitializerTo(new IntRecTy()); 375193323Sed if (I) 376193323Sed if (IntInit *II = dynamic_cast<IntInit*>(I)) { 377193323Sed if (II->getValue()) { 378193323Sed if (Shift) 379193323Sed OS << "|(" << II->getValue() << "<<" << Shift << ")"; 380193323Sed else 381193323Sed OS << "|" << II->getValue(); 382193323Sed } 383193323Sed return; 384193323Sed } 385193323Sed 386193323Sed } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) { 387193323Sed if (II->getValue()) { 388193323Sed if (Shift) 389193323Sed OS << "|(" << II->getValue() << "<<" << Shift << ")"; 390193323Sed else 391193323Sed OS << II->getValue(); 392193323Sed } 393193323Sed return; 394193323Sed } 395193323Sed 396195340Sed errs() << "Unhandled initializer: " << *Val << "\n"; 397193323Sed throw "In record '" + R->getName() + "' for TSFlag emission."; 398193323Sed} 399193323Sed 400