FastISelEmitter.cpp revision 221345
1193323Sed//===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend emits code for use by the "fast" instruction 11193323Sed// selection algorithm. See the comments at the top of 12193323Sed// lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13193323Sed// 14193323Sed// This file scans through the target's tablegen instruction-info files 15193323Sed// and extracts instructions with obvious-looking patterns, and it emits 16193323Sed// code to look up these instructions by type and operator. 17193323Sed// 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed 20193323Sed#include "FastISelEmitter.h" 21193323Sed#include "Record.h" 22193323Sed#include "llvm/Support/Debug.h" 23218893Sdim#include "llvm/ADT/SmallString.h" 24193323Sed#include "llvm/ADT/VectorExtras.h" 25193323Sedusing namespace llvm; 26193323Sed 27193323Sednamespace { 28193323Sed 29193323Sed/// InstructionMemo - This class holds additional information about an 30193323Sed/// instruction needed to emit code for it. 31193323Sed/// 32193323Sedstruct InstructionMemo { 33193323Sed std::string Name; 34193323Sed const CodeGenRegisterClass *RC; 35208599Srdivacky std::string SubRegNo; 36193323Sed std::vector<std::string>* PhysRegs; 37193323Sed}; 38221345Sdim 39221345Sdim/// ImmPredicateSet - This uniques predicates (represented as a string) and 40221345Sdim/// gives them unique (small) integer ID's that start at 0. 41221345Sdimclass ImmPredicateSet { 42221345Sdim DenseMap<TreePattern *, unsigned> ImmIDs; 43221345Sdim std::vector<TreePredicateFn> PredsByName; 44221345Sdimpublic: 45221345Sdim 46221345Sdim unsigned getIDFor(TreePredicateFn Pred) { 47221345Sdim unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 48221345Sdim if (Entry == 0) { 49221345Sdim PredsByName.push_back(Pred); 50221345Sdim Entry = PredsByName.size(); 51221345Sdim } 52221345Sdim return Entry-1; 53221345Sdim } 54221345Sdim 55221345Sdim const TreePredicateFn &getPredicate(unsigned i) { 56221345Sdim assert(i < PredsByName.size()); 57221345Sdim return PredsByName[i]; 58221345Sdim } 59221345Sdim 60221345Sdim typedef std::vector<TreePredicateFn>::const_iterator iterator; 61221345Sdim iterator begin() const { return PredsByName.begin(); } 62221345Sdim iterator end() const { return PredsByName.end(); } 63221345Sdim 64221345Sdim}; 65193323Sed 66193323Sed/// OperandsSignature - This class holds a description of a list of operand 67193323Sed/// types. It has utility methods for emitting text based on the operands. 68193323Sed/// 69193323Sedstruct OperandsSignature { 70221345Sdim class OpKind { 71221345Sdim enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 72221345Sdim char Repr; 73221345Sdim public: 74221345Sdim 75221345Sdim OpKind() : Repr(OK_Invalid) {} 76221345Sdim 77221345Sdim bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 78221345Sdim bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 79193323Sed 80221345Sdim static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } 81221345Sdim static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } 82221345Sdim static OpKind getImm(unsigned V) { 83221345Sdim assert((unsigned)OK_Imm+V < 128 && 84221345Sdim "Too many integer predicates for the 'Repr' char"); 85221345Sdim OpKind K; K.Repr = OK_Imm+V; return K; 86221345Sdim } 87221345Sdim 88221345Sdim bool isReg() const { return Repr == OK_Reg; } 89221345Sdim bool isFP() const { return Repr == OK_FP; } 90221345Sdim bool isImm() const { return Repr >= OK_Imm; } 91221345Sdim 92221345Sdim unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } 93221345Sdim 94221345Sdim void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 95221345Sdim bool StripImmCodes) const { 96221345Sdim if (isReg()) 97221345Sdim OS << 'r'; 98221345Sdim else if (isFP()) 99221345Sdim OS << 'f'; 100221345Sdim else { 101221345Sdim OS << 'i'; 102221345Sdim if (!StripImmCodes) 103221345Sdim if (unsigned Code = getImmCode()) 104221345Sdim OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); 105221345Sdim } 106221345Sdim } 107221345Sdim }; 108221345Sdim 109221345Sdim 110221345Sdim SmallVector<OpKind, 3> Operands; 111221345Sdim 112193323Sed bool operator<(const OperandsSignature &O) const { 113193323Sed return Operands < O.Operands; 114193323Sed } 115221345Sdim bool operator==(const OperandsSignature &O) const { 116221345Sdim return Operands == O.Operands; 117221345Sdim } 118193323Sed 119193323Sed bool empty() const { return Operands.empty(); } 120193323Sed 121221345Sdim bool hasAnyImmediateCodes() const { 122221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 123221345Sdim if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 124221345Sdim return true; 125221345Sdim return false; 126221345Sdim } 127221345Sdim 128221345Sdim /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 129221345Sdim /// to zero. 130221345Sdim OperandsSignature getWithoutImmCodes() const { 131221345Sdim OperandsSignature Result; 132221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 133221345Sdim if (!Operands[i].isImm()) 134221345Sdim Result.Operands.push_back(Operands[i]); 135221345Sdim else 136221345Sdim Result.Operands.push_back(OpKind::getImm(0)); 137221345Sdim return Result; 138221345Sdim } 139221345Sdim 140221345Sdim void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 141221345Sdim bool EmittedAnything = false; 142221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 143221345Sdim if (!Operands[i].isImm()) continue; 144221345Sdim 145221345Sdim unsigned Code = Operands[i].getImmCode(); 146221345Sdim if (Code == 0) continue; 147221345Sdim 148221345Sdim if (EmittedAnything) 149221345Sdim OS << " &&\n "; 150221345Sdim 151221345Sdim TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); 152221345Sdim 153221345Sdim // Emit the type check. 154221345Sdim OS << "VT == " 155221345Sdim << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) 156221345Sdim << " && "; 157221345Sdim 158221345Sdim 159221345Sdim OS << PredFn.getFnName() << "(imm" << i <<')'; 160221345Sdim EmittedAnything = true; 161221345Sdim } 162221345Sdim } 163221345Sdim 164193323Sed /// initialize - Examine the given pattern and initialize the contents 165193323Sed /// of the Operands array accordingly. Return true if all the operands 166193323Sed /// are supported, false otherwise. 167193323Sed /// 168221345Sdim bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, 169221345Sdim MVT::SimpleValueType VT, 170221345Sdim ImmPredicateSet &ImmediatePredicates) { 171221345Sdim if (InstPatNode->isLeaf()) 172221345Sdim return false; 173221345Sdim 174221345Sdim if (InstPatNode->getOperator()->getName() == "imm") { 175221345Sdim Operands.push_back(OpKind::getImm(0)); 176221345Sdim return true; 177193323Sed } 178221345Sdim 179221345Sdim if (InstPatNode->getOperator()->getName() == "fpimm") { 180221345Sdim Operands.push_back(OpKind::getFP()); 181221345Sdim return true; 182221345Sdim } 183218893Sdim 184193323Sed const CodeGenRegisterClass *DstRC = 0; 185218893Sdim 186193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 187193323Sed TreePatternNode *Op = InstPatNode->getChild(i); 188218893Sdim 189221345Sdim // Handle imm operands specially. 190221345Sdim if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { 191221345Sdim unsigned PredNo = 0; 192221345Sdim if (!Op->getPredicateFns().empty()) { 193221345Sdim TreePredicateFn PredFn = Op->getPredicateFns()[0]; 194221345Sdim // If there is more than one predicate weighing in on this operand 195221345Sdim // then we don't handle it. This doesn't typically happen for 196221345Sdim // immediates anyway. 197221345Sdim if (Op->getPredicateFns().size() > 1 || 198221345Sdim !PredFn.isImmediatePattern()) 199221345Sdim return false; 200221345Sdim // Ignore any instruction with 'FastIselShouldIgnore', these are 201221345Sdim // not needed and just bloat the fast instruction selector. For 202221345Sdim // example, X86 doesn't need to generate code to match ADD16ri8 since 203221345Sdim // ADD16ri will do just fine. 204221345Sdim Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 205221345Sdim if (Rec->getValueAsBit("FastIselShouldIgnore")) 206221345Sdim return false; 207221345Sdim 208221345Sdim PredNo = ImmediatePredicates.getIDFor(PredFn)+1; 209221345Sdim } 210221345Sdim 211221345Sdim // Handle unmatched immediate sizes here. 212221345Sdim //if (Op->getType(0) != VT) 213221345Sdim // return false; 214221345Sdim 215221345Sdim Operands.push_back(OpKind::getImm(PredNo)); 216221345Sdim continue; 217221345Sdim } 218221345Sdim 219221345Sdim 220193323Sed // For now, filter out any operand with a predicate. 221205407Srdivacky // For now, filter out any operand with multiple values. 222221345Sdim if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) 223193323Sed return false; 224218893Sdim 225193323Sed if (!Op->isLeaf()) { 226221345Sdim if (Op->getOperator()->getName() == "fpimm") { 227221345Sdim Operands.push_back(OpKind::getFP()); 228193323Sed continue; 229193323Sed } 230193323Sed // For now, ignore other non-leaf nodes. 231193323Sed return false; 232193323Sed } 233221345Sdim 234221345Sdim assert(Op->hasTypeSet(0) && "Type infererence not done?"); 235221345Sdim 236221345Sdim // For now, all the operands must have the same type (if they aren't 237221345Sdim // immediates). Note that this causes us to reject variable sized shifts 238221345Sdim // on X86. 239221345Sdim if (Op->getType(0) != VT) 240221345Sdim return false; 241221345Sdim 242193323Sed DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 243193323Sed if (!OpDI) 244193323Sed return false; 245193323Sed Record *OpLeafRec = OpDI->getDef(); 246221345Sdim 247193323Sed // For now, the only other thing we accept is register operands. 248193323Sed const CodeGenRegisterClass *RC = 0; 249193323Sed if (OpLeafRec->isSubClassOf("RegisterClass")) 250193323Sed RC = &Target.getRegisterClass(OpLeafRec); 251193323Sed else if (OpLeafRec->isSubClassOf("Register")) 252193323Sed RC = Target.getRegisterClassForRegister(OpLeafRec); 253193323Sed else 254193323Sed return false; 255218893Sdim 256212904Sdim // For now, this needs to be a register class of some sort. 257193323Sed if (!RC) 258193323Sed return false; 259212904Sdim 260212904Sdim // For now, all the operands must have the same register class or be 261212904Sdim // a strict subclass of the destination. 262193323Sed if (DstRC) { 263212904Sdim if (DstRC != RC && !DstRC->hasSubClass(RC)) 264193323Sed return false; 265193323Sed } else 266193323Sed DstRC = RC; 267221345Sdim Operands.push_back(OpKind::getReg()); 268193323Sed } 269193323Sed return true; 270193323Sed } 271193323Sed 272195340Sed void PrintParameters(raw_ostream &OS) const { 273193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 274221345Sdim if (Operands[i].isReg()) { 275208599Srdivacky OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; 276221345Sdim } else if (Operands[i].isImm()) { 277193323Sed OS << "uint64_t imm" << i; 278221345Sdim } else if (Operands[i].isFP()) { 279193323Sed OS << "ConstantFP *f" << i; 280193323Sed } else { 281193323Sed assert("Unknown operand kind!"); 282193323Sed abort(); 283193323Sed } 284193323Sed if (i + 1 != e) 285193323Sed OS << ", "; 286193323Sed } 287193323Sed } 288193323Sed 289195340Sed void PrintArguments(raw_ostream &OS, 290221345Sdim const std::vector<std::string> &PR) const { 291193323Sed assert(PR.size() == Operands.size()); 292193323Sed bool PrintedArg = false; 293193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 294193323Sed if (PR[i] != "") 295193323Sed // Implicit physical register operand. 296193323Sed continue; 297193323Sed 298193323Sed if (PrintedArg) 299193323Sed OS << ", "; 300221345Sdim if (Operands[i].isReg()) { 301208599Srdivacky OS << "Op" << i << ", Op" << i << "IsKill"; 302193323Sed PrintedArg = true; 303221345Sdim } else if (Operands[i].isImm()) { 304193323Sed OS << "imm" << i; 305193323Sed PrintedArg = true; 306221345Sdim } else if (Operands[i].isFP()) { 307193323Sed OS << "f" << i; 308193323Sed PrintedArg = true; 309193323Sed } else { 310193323Sed assert("Unknown operand kind!"); 311193323Sed abort(); 312193323Sed } 313193323Sed } 314193323Sed } 315193323Sed 316195340Sed void PrintArguments(raw_ostream &OS) const { 317193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 318221345Sdim if (Operands[i].isReg()) { 319208599Srdivacky OS << "Op" << i << ", Op" << i << "IsKill"; 320221345Sdim } else if (Operands[i].isImm()) { 321193323Sed OS << "imm" << i; 322221345Sdim } else if (Operands[i].isFP()) { 323193323Sed OS << "f" << i; 324193323Sed } else { 325193323Sed assert("Unknown operand kind!"); 326193323Sed abort(); 327193323Sed } 328193323Sed if (i + 1 != e) 329193323Sed OS << ", "; 330193323Sed } 331193323Sed } 332193323Sed 333193323Sed 334221345Sdim void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 335221345Sdim ImmPredicateSet &ImmPredicates, 336221345Sdim bool StripImmCodes = false) const { 337193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 338193323Sed if (PR[i] != "") 339193323Sed // Implicit physical register operand. e.g. Instruction::Mul expect to 340193323Sed // select to a binary op. On x86, mul may take a single operand with 341193323Sed // the other operand being implicit. We must emit something that looks 342193323Sed // like a binary instruction except for the very inner FastEmitInst_* 343193323Sed // call. 344193323Sed continue; 345221345Sdim Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 346193323Sed } 347193323Sed } 348193323Sed 349221345Sdim void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 350221345Sdim bool StripImmCodes = false) const { 351221345Sdim for (unsigned i = 0, e = Operands.size(); i != e; ++i) 352221345Sdim Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 353193323Sed } 354193323Sed}; 355193323Sed 356193323Sedclass FastISelMap { 357193323Sed typedef std::map<std::string, InstructionMemo> PredMap; 358193323Sed typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 359193323Sed typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 360193323Sed typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 361218893Sdim typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 362212904Sdim OperandsOpcodeTypeRetPredMap; 363193323Sed 364193323Sed OperandsOpcodeTypeRetPredMap SimplePatterns; 365193323Sed 366221345Sdim std::map<OperandsSignature, std::vector<OperandsSignature> > 367221345Sdim SignaturesWithConstantForms; 368221345Sdim 369193323Sed std::string InstNS; 370221345Sdim ImmPredicateSet ImmediatePredicates; 371193323Sedpublic: 372193323Sed explicit FastISelMap(std::string InstNS); 373193323Sed 374221345Sdim void collectPatterns(CodeGenDAGPatterns &CGP); 375221345Sdim void printImmediatePredicates(raw_ostream &OS); 376221345Sdim void printFunctionDefinitions(raw_ostream &OS); 377193323Sed}; 378193323Sed 379193323Sed} 380193323Sed 381193323Sedstatic std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 382193323Sed return CGP.getSDNodeInfo(Op).getEnumName(); 383193323Sed} 384193323Sed 385193323Sedstatic std::string getLegalCName(std::string OpName) { 386193323Sed std::string::size_type pos = OpName.find("::"); 387193323Sed if (pos != std::string::npos) 388193323Sed OpName.replace(pos, 2, "_"); 389193323Sed return OpName; 390193323Sed} 391193323Sed 392193323SedFastISelMap::FastISelMap(std::string instns) 393193323Sed : InstNS(instns) { 394193323Sed} 395193323Sed 396221345Sdimstatic std::string PhyRegForNode(TreePatternNode *Op, 397221345Sdim const CodeGenTarget &Target) { 398221345Sdim std::string PhysReg; 399221345Sdim 400221345Sdim if (!Op->isLeaf()) 401221345Sdim return PhysReg; 402221345Sdim 403221345Sdim DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 404221345Sdim Record *OpLeafRec = OpDI->getDef(); 405221345Sdim if (!OpLeafRec->isSubClassOf("Register")) 406221345Sdim return PhysReg; 407221345Sdim 408221345Sdim PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 409221345Sdim "Namespace")->getValue())->getValue(); 410221345Sdim PhysReg += "::"; 411221345Sdim 412221345Sdim std::vector<CodeGenRegister> Regs = Target.getRegisters(); 413221345Sdim for (unsigned i = 0; i < Regs.size(); ++i) { 414221345Sdim if (Regs[i].TheDef == OpLeafRec) { 415221345Sdim PhysReg += Regs[i].getName(); 416221345Sdim break; 417221345Sdim } 418221345Sdim } 419221345Sdim 420221345Sdim return PhysReg; 421221345Sdim} 422221345Sdim 423221345Sdimvoid FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { 424193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 425193323Sed 426193323Sed // Determine the target's namespace name. 427193323Sed InstNS = Target.getInstNamespace() + "::"; 428193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 429193323Sed 430193323Sed // Scan through all the patterns and record the simple ones. 431193323Sed for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 432193323Sed E = CGP.ptm_end(); I != E; ++I) { 433193323Sed const PatternToMatch &Pattern = *I; 434193323Sed 435193323Sed // For now, just look at Instructions, so that we don't have to worry 436193323Sed // about emitting multiple instructions for a pattern. 437193323Sed TreePatternNode *Dst = Pattern.getDstPattern(); 438193323Sed if (Dst->isLeaf()) continue; 439193323Sed Record *Op = Dst->getOperator(); 440193323Sed if (!Op->isSubClassOf("Instruction")) 441193323Sed continue; 442205407Srdivacky CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 443221345Sdim if (II.Operands.empty()) 444193323Sed continue; 445218893Sdim 446193323Sed // For now, ignore multi-instruction patterns. 447193323Sed bool MultiInsts = false; 448193323Sed for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 449193323Sed TreePatternNode *ChildOp = Dst->getChild(i); 450193323Sed if (ChildOp->isLeaf()) 451193323Sed continue; 452193323Sed if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 453193323Sed MultiInsts = true; 454193323Sed break; 455193323Sed } 456193323Sed } 457193323Sed if (MultiInsts) 458193323Sed continue; 459193323Sed 460193323Sed // For now, ignore instructions where the first operand is not an 461193323Sed // output register. 462193323Sed const CodeGenRegisterClass *DstRC = 0; 463208599Srdivacky std::string SubRegNo; 464193323Sed if (Op->getName() != "EXTRACT_SUBREG") { 465218893Sdim Record *Op0Rec = II.Operands[0].Rec; 466193323Sed if (!Op0Rec->isSubClassOf("RegisterClass")) 467193323Sed continue; 468193323Sed DstRC = &Target.getRegisterClass(Op0Rec); 469193323Sed if (!DstRC) 470193323Sed continue; 471193323Sed } else { 472212904Sdim // If this isn't a leaf, then continue since the register classes are 473212904Sdim // a bit too complicated for now. 474212904Sdim if (!Dst->getChild(1)->isLeaf()) continue; 475218893Sdim 476208599Srdivacky DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue()); 477208599Srdivacky if (SR) 478208599Srdivacky SubRegNo = getQualifiedName(SR->getDef()); 479208599Srdivacky else 480208599Srdivacky SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); 481193323Sed } 482193323Sed 483193323Sed // Inspect the pattern. 484193323Sed TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 485193323Sed if (!InstPatNode) continue; 486193323Sed if (InstPatNode->isLeaf()) continue; 487193323Sed 488206083Srdivacky // Ignore multiple result nodes for now. 489206083Srdivacky if (InstPatNode->getNumTypes() > 1) continue; 490218893Sdim 491193323Sed Record *InstPatOp = InstPatNode->getOperator(); 492193323Sed std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 493205407Srdivacky MVT::SimpleValueType RetVT = MVT::isVoid; 494205407Srdivacky if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); 495193323Sed MVT::SimpleValueType VT = RetVT; 496205407Srdivacky if (InstPatNode->getNumChildren()) { 497205407Srdivacky assert(InstPatNode->getChild(0)->getNumTypes() == 1); 498205407Srdivacky VT = InstPatNode->getChild(0)->getType(0); 499205407Srdivacky } 500193323Sed 501193323Sed // For now, filter out any instructions with predicates. 502193323Sed if (!InstPatNode->getPredicateFns().empty()) 503193323Sed continue; 504193323Sed 505193323Sed // Check all the operands. 506193323Sed OperandsSignature Operands; 507221345Sdim if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) 508193323Sed continue; 509218893Sdim 510193323Sed std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 511221345Sdim if (InstPatNode->getOperator()->getName() == "imm" || 512221345Sdim InstPatNode->getOperator()->getName() == "fpimmm") 513193323Sed PhysRegInputs->push_back(""); 514221345Sdim else { 515221345Sdim // Compute the PhysRegs used by the given pattern, and check that 516221345Sdim // the mapping from the src to dst patterns is simple. 517221345Sdim bool FoundNonSimplePattern = false; 518221345Sdim unsigned DstIndex = 0; 519193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 520221345Sdim std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 521221345Sdim if (PhysReg.empty()) { 522221345Sdim if (DstIndex >= Dst->getNumChildren() || 523221345Sdim Dst->getChild(DstIndex)->getName() != 524221345Sdim InstPatNode->getChild(i)->getName()) { 525221345Sdim FoundNonSimplePattern = true; 526221345Sdim break; 527193323Sed } 528221345Sdim ++DstIndex; 529193323Sed } 530218893Sdim 531193323Sed PhysRegInputs->push_back(PhysReg); 532193323Sed } 533193323Sed 534221345Sdim if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) 535221345Sdim FoundNonSimplePattern = true; 536221345Sdim 537221345Sdim if (FoundNonSimplePattern) 538221345Sdim continue; 539221345Sdim } 540221345Sdim 541193323Sed // Get the predicate that guards this pattern. 542193323Sed std::string PredicateCheck = Pattern.getPredicateCheck(); 543193323Sed 544193323Sed // Ok, we found a pattern that we can handle. Remember it. 545193323Sed InstructionMemo Memo = { 546193323Sed Pattern.getDstPattern()->getOperator()->getName(), 547193323Sed DstRC, 548193323Sed SubRegNo, 549193323Sed PhysRegInputs 550193323Sed }; 551221345Sdim 552221345Sdim if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) 553221345Sdim throw TGError(Pattern.getSrcRecord()->getLoc(), 554221345Sdim "Duplicate record in FastISel table!"); 555218893Sdim 556193323Sed SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 557221345Sdim 558221345Sdim // If any of the operands were immediates with predicates on them, strip 559221345Sdim // them down to a signature that doesn't have predicates so that we can 560221345Sdim // associate them with the stripped predicate version. 561221345Sdim if (Operands.hasAnyImmediateCodes()) { 562221345Sdim SignaturesWithConstantForms[Operands.getWithoutImmCodes()] 563221345Sdim .push_back(Operands); 564221345Sdim } 565193323Sed } 566193323Sed} 567193323Sed 568221345Sdimvoid FastISelMap::printImmediatePredicates(raw_ostream &OS) { 569221345Sdim if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 570221345Sdim return; 571221345Sdim 572221345Sdim OS << "\n// FastEmit Immediate Predicate functions.\n"; 573221345Sdim for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), 574221345Sdim E = ImmediatePredicates.end(); I != E; ++I) { 575221345Sdim OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; 576221345Sdim OS << I->getImmediatePredicateCode() << "\n}\n"; 577221345Sdim } 578221345Sdim 579221345Sdim OS << "\n\n"; 580221345Sdim} 581221345Sdim 582221345Sdim 583221345Sdimvoid FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 584193323Sed // Now emit code for all the patterns that we collected. 585193323Sed for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 586193323Sed OE = SimplePatterns.end(); OI != OE; ++OI) { 587193323Sed const OperandsSignature &Operands = OI->first; 588193323Sed const OpcodeTypeRetPredMap &OTM = OI->second; 589193323Sed 590193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 591193323Sed I != E; ++I) { 592193323Sed const std::string &Opcode = I->first; 593193323Sed const TypeRetPredMap &TM = I->second; 594193323Sed 595193323Sed OS << "// FastEmit functions for " << Opcode << ".\n"; 596193323Sed OS << "\n"; 597193323Sed 598193323Sed // Emit one function for each opcode,type pair. 599193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 600193323Sed TI != TE; ++TI) { 601193323Sed MVT::SimpleValueType VT = TI->first; 602193323Sed const RetPredMap &RM = TI->second; 603193323Sed if (RM.size() != 1) { 604193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 605193323Sed RI != RE; ++RI) { 606193323Sed MVT::SimpleValueType RetVT = RI->first; 607193323Sed const PredMap &PM = RI->second; 608193323Sed bool HasPred = false; 609193323Sed 610193323Sed OS << "unsigned FastEmit_" 611193323Sed << getLegalCName(Opcode) 612193323Sed << "_" << getLegalCName(getName(VT)) 613193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 614221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 615193323Sed OS << "("; 616193323Sed Operands.PrintParameters(OS); 617193323Sed OS << ") {\n"; 618193323Sed 619193323Sed // Emit code for each possible instruction. There may be 620193323Sed // multiple if there are subtarget concerns. 621193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 622193323Sed PI != PE; ++PI) { 623193323Sed std::string PredicateCheck = PI->first; 624193323Sed const InstructionMemo &Memo = PI->second; 625218893Sdim 626193323Sed if (PredicateCheck.empty()) { 627193323Sed assert(!HasPred && 628193323Sed "Multiple instructions match, at least one has " 629193323Sed "a predicate and at least one doesn't!"); 630193323Sed } else { 631193323Sed OS << " if (" + PredicateCheck + ") {\n"; 632193323Sed OS << " "; 633193323Sed HasPred = true; 634193323Sed } 635218893Sdim 636193323Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 637193323Sed if ((*Memo.PhysRegs)[i] != "") 638210299Sed OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 639210299Sed << "TII.get(TargetOpcode::COPY), " 640210299Sed << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 641193323Sed } 642218893Sdim 643193323Sed OS << " return FastEmitInst_"; 644208599Srdivacky if (Memo.SubRegNo.empty()) { 645221345Sdim Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 646221345Sdim ImmediatePredicates, true); 647193323Sed OS << "(" << InstNS << Memo.Name << ", "; 648193323Sed OS << InstNS << Memo.RC->getName() << "RegisterClass"; 649193323Sed if (!Operands.empty()) 650193323Sed OS << ", "; 651193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 652193323Sed OS << ");\n"; 653193323Sed } else { 654193323Sed OS << "extractsubreg(" << getName(RetVT); 655221345Sdim OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; 656193323Sed } 657218893Sdim 658193323Sed if (HasPred) 659193323Sed OS << " }\n"; 660218893Sdim 661193323Sed } 662193323Sed // Return 0 if none of the predicates were satisfied. 663193323Sed if (HasPred) 664193323Sed OS << " return 0;\n"; 665193323Sed OS << "}\n"; 666193323Sed OS << "\n"; 667193323Sed } 668218893Sdim 669193323Sed // Emit one function for the type that demultiplexes on return type. 670193323Sed OS << "unsigned FastEmit_" 671193323Sed << getLegalCName(Opcode) << "_" 672193323Sed << getLegalCName(getName(VT)) << "_"; 673221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 674198090Srdivacky OS << "(MVT RetVT"; 675193323Sed if (!Operands.empty()) 676193323Sed OS << ", "; 677193323Sed Operands.PrintParameters(OS); 678198090Srdivacky OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 679193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 680193323Sed RI != RE; ++RI) { 681193323Sed MVT::SimpleValueType RetVT = RI->first; 682193323Sed OS << " case " << getName(RetVT) << ": return FastEmit_" 683193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 684193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 685221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 686193323Sed OS << "("; 687193323Sed Operands.PrintArguments(OS); 688193323Sed OS << ");\n"; 689193323Sed } 690193323Sed OS << " default: return 0;\n}\n}\n\n"; 691218893Sdim 692193323Sed } else { 693193323Sed // Non-variadic return type. 694193323Sed OS << "unsigned FastEmit_" 695193323Sed << getLegalCName(Opcode) << "_" 696193323Sed << getLegalCName(getName(VT)) << "_"; 697221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 698198090Srdivacky OS << "(MVT RetVT"; 699193323Sed if (!Operands.empty()) 700193323Sed OS << ", "; 701193323Sed Operands.PrintParameters(OS); 702193323Sed OS << ") {\n"; 703218893Sdim 704198090Srdivacky OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) 705193323Sed << ")\n return 0;\n"; 706218893Sdim 707193323Sed const PredMap &PM = RM.begin()->second; 708193323Sed bool HasPred = false; 709218893Sdim 710193323Sed // Emit code for each possible instruction. There may be 711193323Sed // multiple if there are subtarget concerns. 712193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 713193323Sed ++PI) { 714193323Sed std::string PredicateCheck = PI->first; 715193323Sed const InstructionMemo &Memo = PI->second; 716193323Sed 717193323Sed if (PredicateCheck.empty()) { 718193323Sed assert(!HasPred && 719193323Sed "Multiple instructions match, at least one has " 720193323Sed "a predicate and at least one doesn't!"); 721193323Sed } else { 722193323Sed OS << " if (" + PredicateCheck + ") {\n"; 723193323Sed OS << " "; 724193323Sed HasPred = true; 725193323Sed } 726218893Sdim 727210299Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 728210299Sed if ((*Memo.PhysRegs)[i] != "") 729210299Sed OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " 730210299Sed << "TII.get(TargetOpcode::COPY), " 731210299Sed << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; 732210299Sed } 733218893Sdim 734193323Sed OS << " return FastEmitInst_"; 735218893Sdim 736208599Srdivacky if (Memo.SubRegNo.empty()) { 737221345Sdim Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, 738221345Sdim ImmediatePredicates, true); 739193323Sed OS << "(" << InstNS << Memo.Name << ", "; 740193323Sed OS << InstNS << Memo.RC->getName() << "RegisterClass"; 741193323Sed if (!Operands.empty()) 742193323Sed OS << ", "; 743193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 744193323Sed OS << ");\n"; 745193323Sed } else { 746208599Srdivacky OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; 747208599Srdivacky OS << Memo.SubRegNo; 748193323Sed OS << ");\n"; 749193323Sed } 750218893Sdim 751193323Sed if (HasPred) 752193323Sed OS << " }\n"; 753193323Sed } 754218893Sdim 755193323Sed // Return 0 if none of the predicates were satisfied. 756193323Sed if (HasPred) 757193323Sed OS << " return 0;\n"; 758193323Sed OS << "}\n"; 759193323Sed OS << "\n"; 760193323Sed } 761193323Sed } 762193323Sed 763193323Sed // Emit one function for the opcode that demultiplexes based on the type. 764193323Sed OS << "unsigned FastEmit_" 765193323Sed << getLegalCName(Opcode) << "_"; 766221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 767198090Srdivacky OS << "(MVT VT, MVT RetVT"; 768193323Sed if (!Operands.empty()) 769193323Sed OS << ", "; 770193323Sed Operands.PrintParameters(OS); 771193323Sed OS << ") {\n"; 772198090Srdivacky OS << " switch (VT.SimpleTy) {\n"; 773193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 774193323Sed TI != TE; ++TI) { 775193323Sed MVT::SimpleValueType VT = TI->first; 776193323Sed std::string TypeName = getName(VT); 777193323Sed OS << " case " << TypeName << ": return FastEmit_" 778193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 779221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 780193323Sed OS << "(RetVT"; 781193323Sed if (!Operands.empty()) 782193323Sed OS << ", "; 783193323Sed Operands.PrintArguments(OS); 784193323Sed OS << ");\n"; 785193323Sed } 786193323Sed OS << " default: return 0;\n"; 787193323Sed OS << " }\n"; 788193323Sed OS << "}\n"; 789193323Sed OS << "\n"; 790193323Sed } 791193323Sed 792193323Sed OS << "// Top-level FastEmit function.\n"; 793193323Sed OS << "\n"; 794193323Sed 795193323Sed // Emit one function for the operand signature that demultiplexes based 796193323Sed // on opcode and type. 797193323Sed OS << "unsigned FastEmit_"; 798221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 799202375Srdivacky OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 800193323Sed if (!Operands.empty()) 801193323Sed OS << ", "; 802193323Sed Operands.PrintParameters(OS); 803193323Sed OS << ") {\n"; 804221345Sdim 805221345Sdim // If there are any forms of this signature available that operand on 806221345Sdim // constrained forms of the immediate (e.g. 32-bit sext immediate in a 807221345Sdim // 64-bit operand), check them first. 808221345Sdim 809221345Sdim std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI 810221345Sdim = SignaturesWithConstantForms.find(Operands); 811221345Sdim if (MI != SignaturesWithConstantForms.end()) { 812221345Sdim // Unique any duplicates out of the list. 813221345Sdim std::sort(MI->second.begin(), MI->second.end()); 814221345Sdim MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), 815221345Sdim MI->second.end()); 816221345Sdim 817221345Sdim // Check each in order it was seen. It would be nice to have a good 818221345Sdim // relative ordering between them, but we're not going for optimality 819221345Sdim // here. 820221345Sdim for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 821221345Sdim OS << " if ("; 822221345Sdim MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 823221345Sdim OS << ")\n if (unsigned Reg = FastEmit_"; 824221345Sdim MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 825221345Sdim OS << "(VT, RetVT, Opcode"; 826221345Sdim if (!MI->second[i].empty()) 827221345Sdim OS << ", "; 828221345Sdim MI->second[i].PrintArguments(OS); 829221345Sdim OS << "))\n return Reg;\n\n"; 830221345Sdim } 831221345Sdim 832221345Sdim // Done with this, remove it. 833221345Sdim SignaturesWithConstantForms.erase(MI); 834221345Sdim } 835221345Sdim 836193323Sed OS << " switch (Opcode) {\n"; 837193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 838193323Sed I != E; ++I) { 839193323Sed const std::string &Opcode = I->first; 840193323Sed 841193323Sed OS << " case " << Opcode << ": return FastEmit_" 842193323Sed << getLegalCName(Opcode) << "_"; 843221345Sdim Operands.PrintManglingSuffix(OS, ImmediatePredicates); 844193323Sed OS << "(VT, RetVT"; 845193323Sed if (!Operands.empty()) 846193323Sed OS << ", "; 847193323Sed Operands.PrintArguments(OS); 848193323Sed OS << ");\n"; 849193323Sed } 850193323Sed OS << " default: return 0;\n"; 851193323Sed OS << " }\n"; 852193323Sed OS << "}\n"; 853193323Sed OS << "\n"; 854193323Sed } 855221345Sdim 856221345Sdim // TODO: SignaturesWithConstantForms should be empty here. 857193323Sed} 858193323Sed 859195340Sedvoid FastISelEmitter::run(raw_ostream &OS) { 860193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 861193323Sed 862193323Sed // Determine the target's namespace name. 863193323Sed std::string InstNS = Target.getInstNamespace() + "::"; 864193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 865193323Sed 866193323Sed EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + 867193323Sed Target.getName() + " target", OS); 868193323Sed 869193323Sed FastISelMap F(InstNS); 870221345Sdim F.collectPatterns(CGP); 871221345Sdim F.printImmediatePredicates(OS); 872221345Sdim F.printFunctionDefinitions(OS); 873193323Sed} 874193323Sed 875193323SedFastISelEmitter::FastISelEmitter(RecordKeeper &R) 876221345Sdim : Records(R), CGP(R) { 877193323Sed} 878193323Sed 879