FastISelEmitter.cpp revision 193323
1193323Sed//===- FastISelEmitter.cpp - Generate an instruction selector -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend emits code for use by the "fast" instruction 11193323Sed// selection algorithm. See the comments at the top of 12193323Sed// lib/CodeGen/SelectionDAG/FastISel.cpp for background. 13193323Sed// 14193323Sed// This file scans through the target's tablegen instruction-info files 15193323Sed// and extracts instructions with obvious-looking patterns, and it emits 16193323Sed// code to look up these instructions by type and operator. 17193323Sed// 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed 20193323Sed#include "FastISelEmitter.h" 21193323Sed#include "Record.h" 22193323Sed#include "llvm/Support/Debug.h" 23193323Sed#include "llvm/Support/Streams.h" 24193323Sed#include "llvm/ADT/VectorExtras.h" 25193323Sedusing namespace llvm; 26193323Sed 27193323Sednamespace { 28193323Sed 29193323Sed/// InstructionMemo - This class holds additional information about an 30193323Sed/// instruction needed to emit code for it. 31193323Sed/// 32193323Sedstruct InstructionMemo { 33193323Sed std::string Name; 34193323Sed const CodeGenRegisterClass *RC; 35193323Sed unsigned char SubRegNo; 36193323Sed std::vector<std::string>* PhysRegs; 37193323Sed}; 38193323Sed 39193323Sed/// OperandsSignature - This class holds a description of a list of operand 40193323Sed/// types. It has utility methods for emitting text based on the operands. 41193323Sed/// 42193323Sedstruct OperandsSignature { 43193323Sed std::vector<std::string> Operands; 44193323Sed 45193323Sed bool operator<(const OperandsSignature &O) const { 46193323Sed return Operands < O.Operands; 47193323Sed } 48193323Sed 49193323Sed bool empty() const { return Operands.empty(); } 50193323Sed 51193323Sed /// initialize - Examine the given pattern and initialize the contents 52193323Sed /// of the Operands array accordingly. Return true if all the operands 53193323Sed /// are supported, false otherwise. 54193323Sed /// 55193323Sed bool initialize(TreePatternNode *InstPatNode, 56193323Sed const CodeGenTarget &Target, 57193323Sed MVT::SimpleValueType VT) { 58193323Sed if (!InstPatNode->isLeaf() && 59193323Sed InstPatNode->getOperator()->getName() == "imm") { 60193323Sed Operands.push_back("i"); 61193323Sed return true; 62193323Sed } 63193323Sed if (!InstPatNode->isLeaf() && 64193323Sed InstPatNode->getOperator()->getName() == "fpimm") { 65193323Sed Operands.push_back("f"); 66193323Sed return true; 67193323Sed } 68193323Sed 69193323Sed const CodeGenRegisterClass *DstRC = 0; 70193323Sed 71193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 72193323Sed TreePatternNode *Op = InstPatNode->getChild(i); 73193323Sed // For now, filter out any operand with a predicate. 74193323Sed if (!Op->getPredicateFns().empty()) 75193323Sed return false; 76193323Sed // For now, filter out any operand with multiple values. 77193323Sed if (Op->getExtTypes().size() != 1) 78193323Sed return false; 79193323Sed // For now, all the operands must have the same type. 80193323Sed if (Op->getTypeNum(0) != VT) 81193323Sed return false; 82193323Sed if (!Op->isLeaf()) { 83193323Sed if (Op->getOperator()->getName() == "imm") { 84193323Sed Operands.push_back("i"); 85193323Sed continue; 86193323Sed } 87193323Sed if (Op->getOperator()->getName() == "fpimm") { 88193323Sed Operands.push_back("f"); 89193323Sed continue; 90193323Sed } 91193323Sed // For now, ignore other non-leaf nodes. 92193323Sed return false; 93193323Sed } 94193323Sed DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 95193323Sed if (!OpDI) 96193323Sed return false; 97193323Sed Record *OpLeafRec = OpDI->getDef(); 98193323Sed // For now, the only other thing we accept is register operands. 99193323Sed 100193323Sed const CodeGenRegisterClass *RC = 0; 101193323Sed if (OpLeafRec->isSubClassOf("RegisterClass")) 102193323Sed RC = &Target.getRegisterClass(OpLeafRec); 103193323Sed else if (OpLeafRec->isSubClassOf("Register")) 104193323Sed RC = Target.getRegisterClassForRegister(OpLeafRec); 105193323Sed else 106193323Sed return false; 107193323Sed // For now, require the register operands' register classes to all 108193323Sed // be the same. 109193323Sed if (!RC) 110193323Sed return false; 111193323Sed // For now, all the operands must have the same register class. 112193323Sed if (DstRC) { 113193323Sed if (DstRC != RC) 114193323Sed return false; 115193323Sed } else 116193323Sed DstRC = RC; 117193323Sed Operands.push_back("r"); 118193323Sed } 119193323Sed return true; 120193323Sed } 121193323Sed 122193323Sed void PrintParameters(std::ostream &OS) const { 123193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 124193323Sed if (Operands[i] == "r") { 125193323Sed OS << "unsigned Op" << i; 126193323Sed } else if (Operands[i] == "i") { 127193323Sed OS << "uint64_t imm" << i; 128193323Sed } else if (Operands[i] == "f") { 129193323Sed OS << "ConstantFP *f" << i; 130193323Sed } else { 131193323Sed assert("Unknown operand kind!"); 132193323Sed abort(); 133193323Sed } 134193323Sed if (i + 1 != e) 135193323Sed OS << ", "; 136193323Sed } 137193323Sed } 138193323Sed 139193323Sed void PrintArguments(std::ostream &OS, 140193323Sed const std::vector<std::string>& PR) const { 141193323Sed assert(PR.size() == Operands.size()); 142193323Sed bool PrintedArg = false; 143193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 144193323Sed if (PR[i] != "") 145193323Sed // Implicit physical register operand. 146193323Sed continue; 147193323Sed 148193323Sed if (PrintedArg) 149193323Sed OS << ", "; 150193323Sed if (Operands[i] == "r") { 151193323Sed OS << "Op" << i; 152193323Sed PrintedArg = true; 153193323Sed } else if (Operands[i] == "i") { 154193323Sed OS << "imm" << i; 155193323Sed PrintedArg = true; 156193323Sed } else if (Operands[i] == "f") { 157193323Sed OS << "f" << i; 158193323Sed PrintedArg = true; 159193323Sed } else { 160193323Sed assert("Unknown operand kind!"); 161193323Sed abort(); 162193323Sed } 163193323Sed } 164193323Sed } 165193323Sed 166193323Sed void PrintArguments(std::ostream &OS) const { 167193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 168193323Sed if (Operands[i] == "r") { 169193323Sed OS << "Op" << i; 170193323Sed } else if (Operands[i] == "i") { 171193323Sed OS << "imm" << i; 172193323Sed } else if (Operands[i] == "f") { 173193323Sed OS << "f" << i; 174193323Sed } else { 175193323Sed assert("Unknown operand kind!"); 176193323Sed abort(); 177193323Sed } 178193323Sed if (i + 1 != e) 179193323Sed OS << ", "; 180193323Sed } 181193323Sed } 182193323Sed 183193323Sed 184193323Sed void PrintManglingSuffix(std::ostream &OS, 185193323Sed const std::vector<std::string>& PR) const { 186193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 187193323Sed if (PR[i] != "") 188193323Sed // Implicit physical register operand. e.g. Instruction::Mul expect to 189193323Sed // select to a binary op. On x86, mul may take a single operand with 190193323Sed // the other operand being implicit. We must emit something that looks 191193323Sed // like a binary instruction except for the very inner FastEmitInst_* 192193323Sed // call. 193193323Sed continue; 194193323Sed OS << Operands[i]; 195193323Sed } 196193323Sed } 197193323Sed 198193323Sed void PrintManglingSuffix(std::ostream &OS) const { 199193323Sed for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 200193323Sed OS << Operands[i]; 201193323Sed } 202193323Sed } 203193323Sed}; 204193323Sed 205193323Sedclass FastISelMap { 206193323Sed typedef std::map<std::string, InstructionMemo> PredMap; 207193323Sed typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 208193323Sed typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 209193323Sed typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 210193323Sed typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap; 211193323Sed 212193323Sed OperandsOpcodeTypeRetPredMap SimplePatterns; 213193323Sed 214193323Sed std::string InstNS; 215193323Sed 216193323Sedpublic: 217193323Sed explicit FastISelMap(std::string InstNS); 218193323Sed 219193323Sed void CollectPatterns(CodeGenDAGPatterns &CGP); 220193323Sed void PrintClass(std::ostream &OS); 221193323Sed void PrintFunctionDefinitions(std::ostream &OS); 222193323Sed}; 223193323Sed 224193323Sed} 225193323Sed 226193323Sedstatic std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { 227193323Sed return CGP.getSDNodeInfo(Op).getEnumName(); 228193323Sed} 229193323Sed 230193323Sedstatic std::string getLegalCName(std::string OpName) { 231193323Sed std::string::size_type pos = OpName.find("::"); 232193323Sed if (pos != std::string::npos) 233193323Sed OpName.replace(pos, 2, "_"); 234193323Sed return OpName; 235193323Sed} 236193323Sed 237193323SedFastISelMap::FastISelMap(std::string instns) 238193323Sed : InstNS(instns) { 239193323Sed} 240193323Sed 241193323Sedvoid FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { 242193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 243193323Sed 244193323Sed // Determine the target's namespace name. 245193323Sed InstNS = Target.getInstNamespace() + "::"; 246193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 247193323Sed 248193323Sed // Scan through all the patterns and record the simple ones. 249193323Sed for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), 250193323Sed E = CGP.ptm_end(); I != E; ++I) { 251193323Sed const PatternToMatch &Pattern = *I; 252193323Sed 253193323Sed // For now, just look at Instructions, so that we don't have to worry 254193323Sed // about emitting multiple instructions for a pattern. 255193323Sed TreePatternNode *Dst = Pattern.getDstPattern(); 256193323Sed if (Dst->isLeaf()) continue; 257193323Sed Record *Op = Dst->getOperator(); 258193323Sed if (!Op->isSubClassOf("Instruction")) 259193323Sed continue; 260193323Sed CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName()); 261193323Sed if (II.OperandList.empty()) 262193323Sed continue; 263193323Sed 264193323Sed // For now, ignore multi-instruction patterns. 265193323Sed bool MultiInsts = false; 266193323Sed for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { 267193323Sed TreePatternNode *ChildOp = Dst->getChild(i); 268193323Sed if (ChildOp->isLeaf()) 269193323Sed continue; 270193323Sed if (ChildOp->getOperator()->isSubClassOf("Instruction")) { 271193323Sed MultiInsts = true; 272193323Sed break; 273193323Sed } 274193323Sed } 275193323Sed if (MultiInsts) 276193323Sed continue; 277193323Sed 278193323Sed // For now, ignore instructions where the first operand is not an 279193323Sed // output register. 280193323Sed const CodeGenRegisterClass *DstRC = 0; 281193323Sed unsigned SubRegNo = ~0; 282193323Sed if (Op->getName() != "EXTRACT_SUBREG") { 283193323Sed Record *Op0Rec = II.OperandList[0].Rec; 284193323Sed if (!Op0Rec->isSubClassOf("RegisterClass")) 285193323Sed continue; 286193323Sed DstRC = &Target.getRegisterClass(Op0Rec); 287193323Sed if (!DstRC) 288193323Sed continue; 289193323Sed } else { 290193323Sed SubRegNo = static_cast<IntInit*>( 291193323Sed Dst->getChild(1)->getLeafValue())->getValue(); 292193323Sed } 293193323Sed 294193323Sed // Inspect the pattern. 295193323Sed TreePatternNode *InstPatNode = Pattern.getSrcPattern(); 296193323Sed if (!InstPatNode) continue; 297193323Sed if (InstPatNode->isLeaf()) continue; 298193323Sed 299193323Sed Record *InstPatOp = InstPatNode->getOperator(); 300193323Sed std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 301193323Sed MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0); 302193323Sed MVT::SimpleValueType VT = RetVT; 303193323Sed if (InstPatNode->getNumChildren()) 304193323Sed VT = InstPatNode->getChild(0)->getTypeNum(0); 305193323Sed 306193323Sed // For now, filter out instructions which just set a register to 307193323Sed // an Operand or an immediate, like MOV32ri. 308193323Sed if (InstPatOp->isSubClassOf("Operand")) 309193323Sed continue; 310193323Sed 311193323Sed // For now, filter out any instructions with predicates. 312193323Sed if (!InstPatNode->getPredicateFns().empty()) 313193323Sed continue; 314193323Sed 315193323Sed // Check all the operands. 316193323Sed OperandsSignature Operands; 317193323Sed if (!Operands.initialize(InstPatNode, Target, VT)) 318193323Sed continue; 319193323Sed 320193323Sed std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); 321193323Sed if (!InstPatNode->isLeaf() && 322193323Sed (InstPatNode->getOperator()->getName() == "imm" || 323193323Sed InstPatNode->getOperator()->getName() == "fpimmm")) 324193323Sed PhysRegInputs->push_back(""); 325193323Sed else if (!InstPatNode->isLeaf()) { 326193323Sed for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { 327193323Sed TreePatternNode *Op = InstPatNode->getChild(i); 328193323Sed if (!Op->isLeaf()) { 329193323Sed PhysRegInputs->push_back(""); 330193323Sed continue; 331193323Sed } 332193323Sed 333193323Sed DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue()); 334193323Sed Record *OpLeafRec = OpDI->getDef(); 335193323Sed std::string PhysReg; 336193323Sed if (OpLeafRec->isSubClassOf("Register")) { 337193323Sed PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 338193323Sed "Namespace")->getValue())->getValue(); 339193323Sed PhysReg += "::"; 340193323Sed 341193323Sed std::vector<CodeGenRegister> Regs = Target.getRegisters(); 342193323Sed for (unsigned i = 0; i < Regs.size(); ++i) { 343193323Sed if (Regs[i].TheDef == OpLeafRec) { 344193323Sed PhysReg += Regs[i].getName(); 345193323Sed break; 346193323Sed } 347193323Sed } 348193323Sed } 349193323Sed 350193323Sed PhysRegInputs->push_back(PhysReg); 351193323Sed } 352193323Sed } else 353193323Sed PhysRegInputs->push_back(""); 354193323Sed 355193323Sed // Get the predicate that guards this pattern. 356193323Sed std::string PredicateCheck = Pattern.getPredicateCheck(); 357193323Sed 358193323Sed // Ok, we found a pattern that we can handle. Remember it. 359193323Sed InstructionMemo Memo = { 360193323Sed Pattern.getDstPattern()->getOperator()->getName(), 361193323Sed DstRC, 362193323Sed SubRegNo, 363193323Sed PhysRegInputs 364193323Sed }; 365193323Sed assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) && 366193323Sed "Duplicate pattern!"); 367193323Sed SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; 368193323Sed } 369193323Sed} 370193323Sed 371193323Sedvoid FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { 372193323Sed // Now emit code for all the patterns that we collected. 373193323Sed for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), 374193323Sed OE = SimplePatterns.end(); OI != OE; ++OI) { 375193323Sed const OperandsSignature &Operands = OI->first; 376193323Sed const OpcodeTypeRetPredMap &OTM = OI->second; 377193323Sed 378193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 379193323Sed I != E; ++I) { 380193323Sed const std::string &Opcode = I->first; 381193323Sed const TypeRetPredMap &TM = I->second; 382193323Sed 383193323Sed OS << "// FastEmit functions for " << Opcode << ".\n"; 384193323Sed OS << "\n"; 385193323Sed 386193323Sed // Emit one function for each opcode,type pair. 387193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 388193323Sed TI != TE; ++TI) { 389193323Sed MVT::SimpleValueType VT = TI->first; 390193323Sed const RetPredMap &RM = TI->second; 391193323Sed if (RM.size() != 1) { 392193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 393193323Sed RI != RE; ++RI) { 394193323Sed MVT::SimpleValueType RetVT = RI->first; 395193323Sed const PredMap &PM = RI->second; 396193323Sed bool HasPred = false; 397193323Sed 398193323Sed OS << "unsigned FastEmit_" 399193323Sed << getLegalCName(Opcode) 400193323Sed << "_" << getLegalCName(getName(VT)) 401193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 402193323Sed Operands.PrintManglingSuffix(OS); 403193323Sed OS << "("; 404193323Sed Operands.PrintParameters(OS); 405193323Sed OS << ") {\n"; 406193323Sed 407193323Sed // Emit code for each possible instruction. There may be 408193323Sed // multiple if there are subtarget concerns. 409193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); 410193323Sed PI != PE; ++PI) { 411193323Sed std::string PredicateCheck = PI->first; 412193323Sed const InstructionMemo &Memo = PI->second; 413193323Sed 414193323Sed if (PredicateCheck.empty()) { 415193323Sed assert(!HasPred && 416193323Sed "Multiple instructions match, at least one has " 417193323Sed "a predicate and at least one doesn't!"); 418193323Sed } else { 419193323Sed OS << " if (" + PredicateCheck + ") {\n"; 420193323Sed OS << " "; 421193323Sed HasPred = true; 422193323Sed } 423193323Sed 424193323Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 425193323Sed if ((*Memo.PhysRegs)[i] != "") 426193323Sed OS << " TII.copyRegToReg(*MBB, MBB->end(), " 427193323Sed << (*Memo.PhysRegs)[i] << ", Op" << i << ", " 428193323Sed << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" 429193323Sed << (*Memo.PhysRegs)[i] << "), " 430193323Sed << "MRI.getRegClass(Op" << i << "));\n"; 431193323Sed } 432193323Sed 433193323Sed OS << " return FastEmitInst_"; 434193323Sed if (Memo.SubRegNo == (unsigned char)~0) { 435193323Sed Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); 436193323Sed OS << "(" << InstNS << Memo.Name << ", "; 437193323Sed OS << InstNS << Memo.RC->getName() << "RegisterClass"; 438193323Sed if (!Operands.empty()) 439193323Sed OS << ", "; 440193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 441193323Sed OS << ");\n"; 442193323Sed } else { 443193323Sed OS << "extractsubreg(" << getName(RetVT); 444193323Sed OS << ", Op0, "; 445193323Sed OS << (unsigned)Memo.SubRegNo; 446193323Sed OS << ");\n"; 447193323Sed } 448193323Sed 449193323Sed if (HasPred) 450193323Sed OS << " }\n"; 451193323Sed 452193323Sed } 453193323Sed // Return 0 if none of the predicates were satisfied. 454193323Sed if (HasPred) 455193323Sed OS << " return 0;\n"; 456193323Sed OS << "}\n"; 457193323Sed OS << "\n"; 458193323Sed } 459193323Sed 460193323Sed // Emit one function for the type that demultiplexes on return type. 461193323Sed OS << "unsigned FastEmit_" 462193323Sed << getLegalCName(Opcode) << "_" 463193323Sed << getLegalCName(getName(VT)) << "_"; 464193323Sed Operands.PrintManglingSuffix(OS); 465193323Sed OS << "(MVT::SimpleValueType RetVT"; 466193323Sed if (!Operands.empty()) 467193323Sed OS << ", "; 468193323Sed Operands.PrintParameters(OS); 469193323Sed OS << ") {\nswitch (RetVT) {\n"; 470193323Sed for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); 471193323Sed RI != RE; ++RI) { 472193323Sed MVT::SimpleValueType RetVT = RI->first; 473193323Sed OS << " case " << getName(RetVT) << ": return FastEmit_" 474193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) 475193323Sed << "_" << getLegalCName(getName(RetVT)) << "_"; 476193323Sed Operands.PrintManglingSuffix(OS); 477193323Sed OS << "("; 478193323Sed Operands.PrintArguments(OS); 479193323Sed OS << ");\n"; 480193323Sed } 481193323Sed OS << " default: return 0;\n}\n}\n\n"; 482193323Sed 483193323Sed } else { 484193323Sed // Non-variadic return type. 485193323Sed OS << "unsigned FastEmit_" 486193323Sed << getLegalCName(Opcode) << "_" 487193323Sed << getLegalCName(getName(VT)) << "_"; 488193323Sed Operands.PrintManglingSuffix(OS); 489193323Sed OS << "(MVT::SimpleValueType RetVT"; 490193323Sed if (!Operands.empty()) 491193323Sed OS << ", "; 492193323Sed Operands.PrintParameters(OS); 493193323Sed OS << ") {\n"; 494193323Sed 495193323Sed OS << " if (RetVT != " << getName(RM.begin()->first) 496193323Sed << ")\n return 0;\n"; 497193323Sed 498193323Sed const PredMap &PM = RM.begin()->second; 499193323Sed bool HasPred = false; 500193323Sed 501193323Sed // Emit code for each possible instruction. There may be 502193323Sed // multiple if there are subtarget concerns. 503193323Sed for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; 504193323Sed ++PI) { 505193323Sed std::string PredicateCheck = PI->first; 506193323Sed const InstructionMemo &Memo = PI->second; 507193323Sed 508193323Sed if (PredicateCheck.empty()) { 509193323Sed assert(!HasPred && 510193323Sed "Multiple instructions match, at least one has " 511193323Sed "a predicate and at least one doesn't!"); 512193323Sed } else { 513193323Sed OS << " if (" + PredicateCheck + ") {\n"; 514193323Sed OS << " "; 515193323Sed HasPred = true; 516193323Sed } 517193323Sed 518193323Sed for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { 519193323Sed if ((*Memo.PhysRegs)[i] != "") 520193323Sed OS << " TII.copyRegToReg(*MBB, MBB->end(), " 521193323Sed << (*Memo.PhysRegs)[i] << ", Op" << i << ", " 522193323Sed << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" 523193323Sed << (*Memo.PhysRegs)[i] << "), " 524193323Sed << "MRI.getRegClass(Op" << i << "));\n"; 525193323Sed } 526193323Sed 527193323Sed OS << " return FastEmitInst_"; 528193323Sed 529193323Sed if (Memo.SubRegNo == (unsigned char)~0) { 530193323Sed Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); 531193323Sed OS << "(" << InstNS << Memo.Name << ", "; 532193323Sed OS << InstNS << Memo.RC->getName() << "RegisterClass"; 533193323Sed if (!Operands.empty()) 534193323Sed OS << ", "; 535193323Sed Operands.PrintArguments(OS, *Memo.PhysRegs); 536193323Sed OS << ");\n"; 537193323Sed } else { 538193323Sed OS << "extractsubreg(RetVT, Op0, "; 539193323Sed OS << (unsigned)Memo.SubRegNo; 540193323Sed OS << ");\n"; 541193323Sed } 542193323Sed 543193323Sed if (HasPred) 544193323Sed OS << " }\n"; 545193323Sed } 546193323Sed 547193323Sed // Return 0 if none of the predicates were satisfied. 548193323Sed if (HasPred) 549193323Sed OS << " return 0;\n"; 550193323Sed OS << "}\n"; 551193323Sed OS << "\n"; 552193323Sed } 553193323Sed } 554193323Sed 555193323Sed // Emit one function for the opcode that demultiplexes based on the type. 556193323Sed OS << "unsigned FastEmit_" 557193323Sed << getLegalCName(Opcode) << "_"; 558193323Sed Operands.PrintManglingSuffix(OS); 559193323Sed OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT"; 560193323Sed if (!Operands.empty()) 561193323Sed OS << ", "; 562193323Sed Operands.PrintParameters(OS); 563193323Sed OS << ") {\n"; 564193323Sed OS << " switch (VT) {\n"; 565193323Sed for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); 566193323Sed TI != TE; ++TI) { 567193323Sed MVT::SimpleValueType VT = TI->first; 568193323Sed std::string TypeName = getName(VT); 569193323Sed OS << " case " << TypeName << ": return FastEmit_" 570193323Sed << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 571193323Sed Operands.PrintManglingSuffix(OS); 572193323Sed OS << "(RetVT"; 573193323Sed if (!Operands.empty()) 574193323Sed OS << ", "; 575193323Sed Operands.PrintArguments(OS); 576193323Sed OS << ");\n"; 577193323Sed } 578193323Sed OS << " default: return 0;\n"; 579193323Sed OS << " }\n"; 580193323Sed OS << "}\n"; 581193323Sed OS << "\n"; 582193323Sed } 583193323Sed 584193323Sed OS << "// Top-level FastEmit function.\n"; 585193323Sed OS << "\n"; 586193323Sed 587193323Sed // Emit one function for the operand signature that demultiplexes based 588193323Sed // on opcode and type. 589193323Sed OS << "unsigned FastEmit_"; 590193323Sed Operands.PrintManglingSuffix(OS); 591193323Sed OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode"; 592193323Sed if (!Operands.empty()) 593193323Sed OS << ", "; 594193323Sed Operands.PrintParameters(OS); 595193323Sed OS << ") {\n"; 596193323Sed OS << " switch (Opcode) {\n"; 597193323Sed for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); 598193323Sed I != E; ++I) { 599193323Sed const std::string &Opcode = I->first; 600193323Sed 601193323Sed OS << " case " << Opcode << ": return FastEmit_" 602193323Sed << getLegalCName(Opcode) << "_"; 603193323Sed Operands.PrintManglingSuffix(OS); 604193323Sed OS << "(VT, RetVT"; 605193323Sed if (!Operands.empty()) 606193323Sed OS << ", "; 607193323Sed Operands.PrintArguments(OS); 608193323Sed OS << ");\n"; 609193323Sed } 610193323Sed OS << " default: return 0;\n"; 611193323Sed OS << " }\n"; 612193323Sed OS << "}\n"; 613193323Sed OS << "\n"; 614193323Sed } 615193323Sed} 616193323Sed 617193323Sedvoid FastISelEmitter::run(std::ostream &OS) { 618193323Sed const CodeGenTarget &Target = CGP.getTargetInfo(); 619193323Sed 620193323Sed // Determine the target's namespace name. 621193323Sed std::string InstNS = Target.getInstNamespace() + "::"; 622193323Sed assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); 623193323Sed 624193323Sed EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + 625193323Sed Target.getName() + " target", OS); 626193323Sed 627193323Sed FastISelMap F(InstNS); 628193323Sed F.CollectPatterns(CGP); 629193323Sed F.PrintFunctionDefinitions(OS); 630193323Sed} 631193323Sed 632193323SedFastISelEmitter::FastISelEmitter(RecordKeeper &R) 633193323Sed : Records(R), 634193323Sed CGP(R) { 635193323Sed} 636193323Sed 637