CodeEmitterGen.cpp revision 207618
1193323Sed//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// CodeEmitterGen uses the descriptions of instructions and their fields to 11193323Sed// construct an automated code emitter: a function that, given a MachineInstr, 12193323Sed// returns the (currently, 32-bit unsigned) value of the instruction. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#include "CodeEmitterGen.h" 17193323Sed#include "CodeGenTarget.h" 18193323Sed#include "Record.h" 19193323Sed#include "llvm/ADT/StringExtras.h" 20193323Sed#include "llvm/Support/Debug.h" 21193323Sedusing namespace llvm; 22193323Sed 23193323Sedvoid CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) { 24193323Sed for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end(); 25193323Sed I != E; ++I) { 26193323Sed Record *R = *I; 27193323Sed if (R->getName() == "PHI" || 28193323Sed R->getName() == "INLINEASM" || 29193323Sed R->getName() == "DBG_LABEL" || 30193323Sed R->getName() == "EH_LABEL" || 31193323Sed R->getName() == "GC_LABEL" || 32198090Srdivacky R->getName() == "KILL" || 33193323Sed R->getName() == "EXTRACT_SUBREG" || 34193323Sed R->getName() == "INSERT_SUBREG" || 35193323Sed R->getName() == "IMPLICIT_DEF" || 36193323Sed R->getName() == "SUBREG_TO_REG" || 37202375Srdivacky R->getName() == "COPY_TO_REGCLASS" || 38207618Srdivacky R->getName() == "DBG_VALUE" || 39207618Srdivacky R->getName() == "REG_SEQUENCE") continue; 40193323Sed 41193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 42193323Sed 43193323Sed unsigned numBits = BI->getNumBits(); 44193323Sed BitsInit *NewBI = new BitsInit(numBits); 45193323Sed for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 46193323Sed unsigned bitSwapIdx = numBits - bit - 1; 47193323Sed Init *OrigBit = BI->getBit(bit); 48193323Sed Init *BitSwap = BI->getBit(bitSwapIdx); 49193323Sed NewBI->setBit(bit, BitSwap); 50193323Sed NewBI->setBit(bitSwapIdx, OrigBit); 51193323Sed } 52193323Sed if (numBits % 2) { 53193323Sed unsigned middle = (numBits + 1) / 2; 54193323Sed NewBI->setBit(middle, BI->getBit(middle)); 55193323Sed } 56193323Sed 57193323Sed // Update the bits in reversed order so that emitInstrOpBits will get the 58193323Sed // correct endianness. 59193323Sed R->getValue("Inst")->setValue(NewBI); 60193323Sed } 61193323Sed} 62193323Sed 63193323Sed 64193323Sed// If the VarBitInit at position 'bit' matches the specified variable then 65193323Sed// return the variable bit position. Otherwise return -1. 66201360Srdivackyint CodeEmitterGen::getVariableBit(const std::string &VarName, 67193323Sed BitsInit *BI, int bit) { 68193323Sed if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) { 69193323Sed TypedInit *TI = VBI->getVariable(); 70201360Srdivacky 71201360Srdivacky if (VarInit *VI = dynamic_cast<VarInit*>(TI)) { 72201360Srdivacky if (VI->getName() == VarName) return VBI->getBitNum(); 73201360Srdivacky } 74193323Sed } 75193323Sed 76193323Sed return -1; 77193323Sed} 78193323Sed 79193323Sed 80195340Sedvoid CodeEmitterGen::run(raw_ostream &o) { 81193323Sed CodeGenTarget Target; 82193323Sed std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 83193323Sed 84193323Sed // For little-endian instruction bit encodings, reverse the bit order 85193323Sed if (Target.isLittleEndianEncoding()) reverseBits(Insts); 86193323Sed 87193323Sed EmitSourceFileHeader("Machine Code Emitter", o); 88193323Sed std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; 89193323Sed 90205407Srdivacky const std::vector<const CodeGenInstruction*> &NumberedInstructions = 91205407Srdivacky Target.getInstructionsByEnumValue(); 92193323Sed 93193323Sed // Emit function declaration 94193323Sed o << "unsigned " << Target.getName() << "CodeEmitter::" 95193323Sed << "getBinaryCodeForInstr(const MachineInstr &MI) {\n"; 96193323Sed 97193323Sed // Emit instruction base values 98193323Sed o << " static const unsigned InstBits[] = {\n"; 99205407Srdivacky for (std::vector<const CodeGenInstruction*>::const_iterator 100193323Sed IN = NumberedInstructions.begin(), 101193323Sed EN = NumberedInstructions.end(); 102193323Sed IN != EN; ++IN) { 103193323Sed const CodeGenInstruction *CGI = *IN; 104193323Sed Record *R = CGI->TheDef; 105193323Sed 106193323Sed if (R->getName() == "PHI" || 107193323Sed R->getName() == "INLINEASM" || 108193323Sed R->getName() == "DBG_LABEL" || 109193323Sed R->getName() == "EH_LABEL" || 110193323Sed R->getName() == "GC_LABEL" || 111198090Srdivacky R->getName() == "KILL" || 112193323Sed R->getName() == "EXTRACT_SUBREG" || 113193323Sed R->getName() == "INSERT_SUBREG" || 114193323Sed R->getName() == "IMPLICIT_DEF" || 115193323Sed R->getName() == "SUBREG_TO_REG" || 116202375Srdivacky R->getName() == "COPY_TO_REGCLASS" || 117207618Srdivacky R->getName() == "DBG_VALUE" || 118207618Srdivacky R->getName() == "REG_SEQUENCE") { 119193323Sed o << " 0U,\n"; 120193323Sed continue; 121193323Sed } 122193323Sed 123193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 124193323Sed 125193323Sed // Start by filling in fixed values... 126193323Sed unsigned Value = 0; 127193323Sed for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { 128193323Sed if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) { 129193323Sed Value |= B->getValue() << (e-i-1); 130193323Sed } 131193323Sed } 132193323Sed o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n"; 133193323Sed } 134193323Sed o << " 0U\n };\n"; 135193323Sed 136193323Sed // Map to accumulate all the cases. 137193323Sed std::map<std::string, std::vector<std::string> > CaseMap; 138193323Sed 139193323Sed // Construct all cases statement for each opcode 140193323Sed for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end(); 141193323Sed IC != EC; ++IC) { 142193323Sed Record *R = *IC; 143193323Sed const std::string &InstName = R->getName(); 144193323Sed std::string Case(""); 145193323Sed 146193323Sed if (InstName == "PHI" || 147193323Sed InstName == "INLINEASM" || 148193323Sed InstName == "DBG_LABEL"|| 149193323Sed InstName == "EH_LABEL"|| 150193323Sed InstName == "GC_LABEL"|| 151198090Srdivacky InstName == "KILL"|| 152193323Sed InstName == "EXTRACT_SUBREG" || 153193323Sed InstName == "INSERT_SUBREG" || 154193323Sed InstName == "IMPLICIT_DEF" || 155193323Sed InstName == "SUBREG_TO_REG" || 156202375Srdivacky InstName == "COPY_TO_REGCLASS" || 157207618Srdivacky InstName == "DBG_VALUE" || 158207618Srdivacky InstName == "REG_SEQUENCE") continue; 159193323Sed 160193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 161193323Sed const std::vector<RecordVal> &Vals = R->getValues(); 162205407Srdivacky CodeGenInstruction &CGI = Target.getInstruction(R); 163193323Sed 164193323Sed // Loop over all of the fields in the instruction, determining which are the 165193323Sed // operands to the instruction. 166193323Sed unsigned op = 0; 167193323Sed for (unsigned i = 0, e = Vals.size(); i != e; ++i) { 168193323Sed if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) { 169193323Sed // Is the operand continuous? If so, we can just mask and OR it in 170193323Sed // instead of doing it bit-by-bit, saving a lot in runtime cost. 171201360Srdivacky const std::string &VarName = Vals[i].getName(); 172193323Sed bool gotOp = false; 173193323Sed 174193323Sed for (int bit = BI->getNumBits()-1; bit >= 0; ) { 175201360Srdivacky int varBit = getVariableBit(VarName, BI, bit); 176193323Sed 177193323Sed if (varBit == -1) { 178193323Sed --bit; 179193323Sed } else { 180193323Sed int beginInstBit = bit; 181193323Sed int beginVarBit = varBit; 182193323Sed int N = 1; 183193323Sed 184193323Sed for (--bit; bit >= 0;) { 185201360Srdivacky varBit = getVariableBit(VarName, BI, bit); 186193323Sed if (varBit == -1 || varBit != (beginVarBit - N)) break; 187193323Sed ++N; 188193323Sed --bit; 189193323Sed } 190193323Sed 191193323Sed if (!gotOp) { 192193323Sed /// If this operand is not supposed to be emitted by the generated 193193323Sed /// emitter, skip it. 194193323Sed while (CGI.isFlatOperandNotEmitted(op)) 195193323Sed ++op; 196193323Sed 197201360Srdivacky Case += " // op: " + VarName + "\n" 198193323Sed + " op = getMachineOpValue(MI, MI.getOperand(" 199193323Sed + utostr(op++) + "));\n"; 200193323Sed gotOp = true; 201193323Sed } 202193323Sed 203193323Sed unsigned opMask = ~0U >> (32-N); 204193323Sed int opShift = beginVarBit - N + 1; 205193323Sed opMask <<= opShift; 206193323Sed opShift = beginInstBit - beginVarBit; 207193323Sed 208193323Sed if (opShift > 0) { 209193323Sed Case += " Value |= (op & " + utostr(opMask) + "U) << " 210193323Sed + itostr(opShift) + ";\n"; 211193323Sed } else if (opShift < 0) { 212193323Sed Case += " Value |= (op & " + utostr(opMask) + "U) >> " 213193323Sed + itostr(-opShift) + ";\n"; 214193323Sed } else { 215193323Sed Case += " Value |= op & " + utostr(opMask) + "U;\n"; 216193323Sed } 217193323Sed } 218193323Sed } 219193323Sed } 220193323Sed } 221193323Sed 222193323Sed std::vector<std::string> &InstList = CaseMap[Case]; 223193323Sed InstList.push_back(InstName); 224193323Sed } 225193323Sed 226193323Sed 227193323Sed // Emit initial function code 228193323Sed o << " const unsigned opcode = MI.getOpcode();\n" 229193323Sed << " unsigned Value = InstBits[opcode];\n" 230193323Sed << " unsigned op = 0;\n" 231193323Sed << " op = op; // suppress warning\n" 232193323Sed << " switch (opcode) {\n"; 233193323Sed 234193323Sed // Emit each case statement 235193323Sed std::map<std::string, std::vector<std::string> >::iterator IE, EE; 236193323Sed for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { 237193323Sed const std::string &Case = IE->first; 238193323Sed std::vector<std::string> &InstList = IE->second; 239193323Sed 240193323Sed for (int i = 0, N = InstList.size(); i < N; i++) { 241193323Sed if (i) o << "\n"; 242193323Sed o << " case " << Namespace << InstList[i] << ":"; 243193323Sed } 244193323Sed o << " {\n"; 245193323Sed o << Case; 246193323Sed o << " break;\n" 247193323Sed << " }\n"; 248193323Sed } 249193323Sed 250193323Sed // Default case: unhandled opcode 251193323Sed o << " default:\n" 252198090Srdivacky << " std::string msg;\n" 253198090Srdivacky << " raw_string_ostream Msg(msg);\n" 254198090Srdivacky << " Msg << \"Not supported instr: \" << MI;\n" 255207618Srdivacky << " report_fatal_error(Msg.str());\n" 256193323Sed << " }\n" 257193323Sed << " return Value;\n" 258193323Sed << "}\n\n"; 259193323Sed} 260