CodeEmitterGen.cpp revision 195340
1193323Sed//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// CodeEmitterGen uses the descriptions of instructions and their fields to 11193323Sed// construct an automated code emitter: a function that, given a MachineInstr, 12193323Sed// returns the (currently, 32-bit unsigned) value of the instruction. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#include "CodeEmitterGen.h" 17193323Sed#include "CodeGenTarget.h" 18193323Sed#include "Record.h" 19193323Sed#include "llvm/ADT/StringExtras.h" 20193323Sed#include "llvm/Support/Debug.h" 21193323Sedusing namespace llvm; 22193323Sed 23193323Sedvoid CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) { 24193323Sed for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end(); 25193323Sed I != E; ++I) { 26193323Sed Record *R = *I; 27193323Sed if (R->getName() == "PHI" || 28193323Sed R->getName() == "INLINEASM" || 29193323Sed R->getName() == "DBG_LABEL" || 30193323Sed R->getName() == "EH_LABEL" || 31193323Sed R->getName() == "GC_LABEL" || 32193323Sed R->getName() == "DECLARE" || 33193323Sed R->getName() == "EXTRACT_SUBREG" || 34193323Sed R->getName() == "INSERT_SUBREG" || 35193323Sed R->getName() == "IMPLICIT_DEF" || 36193323Sed R->getName() == "SUBREG_TO_REG" || 37193323Sed R->getName() == "COPY_TO_REGCLASS") continue; 38193323Sed 39193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 40193323Sed 41193323Sed unsigned numBits = BI->getNumBits(); 42193323Sed BitsInit *NewBI = new BitsInit(numBits); 43193323Sed for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 44193323Sed unsigned bitSwapIdx = numBits - bit - 1; 45193323Sed Init *OrigBit = BI->getBit(bit); 46193323Sed Init *BitSwap = BI->getBit(bitSwapIdx); 47193323Sed NewBI->setBit(bit, BitSwap); 48193323Sed NewBI->setBit(bitSwapIdx, OrigBit); 49193323Sed } 50193323Sed if (numBits % 2) { 51193323Sed unsigned middle = (numBits + 1) / 2; 52193323Sed NewBI->setBit(middle, BI->getBit(middle)); 53193323Sed } 54193323Sed 55193323Sed // Update the bits in reversed order so that emitInstrOpBits will get the 56193323Sed // correct endianness. 57193323Sed R->getValue("Inst")->setValue(NewBI); 58193323Sed } 59193323Sed} 60193323Sed 61193323Sed 62193323Sed// If the VarBitInit at position 'bit' matches the specified variable then 63193323Sed// return the variable bit position. Otherwise return -1. 64193323Sedint CodeEmitterGen::getVariableBit(const std::string &VarName, 65193323Sed BitsInit *BI, int bit) { 66193323Sed if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) { 67193323Sed TypedInit *TI = VBI->getVariable(); 68193323Sed 69193323Sed if (VarInit *VI = dynamic_cast<VarInit*>(TI)) { 70193323Sed if (VI->getName() == VarName) return VBI->getBitNum(); 71193323Sed } 72193323Sed } 73193323Sed 74193323Sed return -1; 75193323Sed} 76193323Sed 77193323Sed 78195340Sedvoid CodeEmitterGen::run(raw_ostream &o) { 79193323Sed CodeGenTarget Target; 80193323Sed std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 81193323Sed 82193323Sed // For little-endian instruction bit encodings, reverse the bit order 83193323Sed if (Target.isLittleEndianEncoding()) reverseBits(Insts); 84193323Sed 85193323Sed EmitSourceFileHeader("Machine Code Emitter", o); 86193323Sed std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; 87193323Sed 88193323Sed std::vector<const CodeGenInstruction*> NumberedInstructions; 89193323Sed Target.getInstructionsByEnumValue(NumberedInstructions); 90193323Sed 91193323Sed // Emit function declaration 92193323Sed o << "unsigned " << Target.getName() << "CodeEmitter::" 93193323Sed << "getBinaryCodeForInstr(const MachineInstr &MI) {\n"; 94193323Sed 95193323Sed // Emit instruction base values 96193323Sed o << " static const unsigned InstBits[] = {\n"; 97193323Sed for (std::vector<const CodeGenInstruction*>::iterator 98193323Sed IN = NumberedInstructions.begin(), 99193323Sed EN = NumberedInstructions.end(); 100193323Sed IN != EN; ++IN) { 101193323Sed const CodeGenInstruction *CGI = *IN; 102193323Sed Record *R = CGI->TheDef; 103193323Sed 104193323Sed if (R->getName() == "PHI" || 105193323Sed R->getName() == "INLINEASM" || 106193323Sed R->getName() == "DBG_LABEL" || 107193323Sed R->getName() == "EH_LABEL" || 108193323Sed R->getName() == "GC_LABEL" || 109193323Sed R->getName() == "DECLARE" || 110193323Sed R->getName() == "EXTRACT_SUBREG" || 111193323Sed R->getName() == "INSERT_SUBREG" || 112193323Sed R->getName() == "IMPLICIT_DEF" || 113193323Sed R->getName() == "SUBREG_TO_REG" || 114193323Sed R->getName() == "COPY_TO_REGCLASS") { 115193323Sed o << " 0U,\n"; 116193323Sed continue; 117193323Sed } 118193323Sed 119193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 120193323Sed 121193323Sed // Start by filling in fixed values... 122193323Sed unsigned Value = 0; 123193323Sed for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { 124193323Sed if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) { 125193323Sed Value |= B->getValue() << (e-i-1); 126193323Sed } 127193323Sed } 128193323Sed o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n"; 129193323Sed } 130193323Sed o << " 0U\n };\n"; 131193323Sed 132193323Sed // Map to accumulate all the cases. 133193323Sed std::map<std::string, std::vector<std::string> > CaseMap; 134193323Sed 135193323Sed // Construct all cases statement for each opcode 136193323Sed for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end(); 137193323Sed IC != EC; ++IC) { 138193323Sed Record *R = *IC; 139193323Sed const std::string &InstName = R->getName(); 140193323Sed std::string Case(""); 141193323Sed 142193323Sed if (InstName == "PHI" || 143193323Sed InstName == "INLINEASM" || 144193323Sed InstName == "DBG_LABEL"|| 145193323Sed InstName == "EH_LABEL"|| 146193323Sed InstName == "GC_LABEL"|| 147193323Sed InstName == "DECLARE"|| 148193323Sed InstName == "EXTRACT_SUBREG" || 149193323Sed InstName == "INSERT_SUBREG" || 150193323Sed InstName == "IMPLICIT_DEF" || 151193323Sed InstName == "SUBREG_TO_REG" || 152193323Sed InstName == "COPY_TO_REGCLASS") continue; 153193323Sed 154193323Sed BitsInit *BI = R->getValueAsBitsInit("Inst"); 155193323Sed const std::vector<RecordVal> &Vals = R->getValues(); 156193323Sed CodeGenInstruction &CGI = Target.getInstruction(InstName); 157193323Sed 158193323Sed // Loop over all of the fields in the instruction, determining which are the 159193323Sed // operands to the instruction. 160193323Sed unsigned op = 0; 161193323Sed for (unsigned i = 0, e = Vals.size(); i != e; ++i) { 162193323Sed if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) { 163193323Sed // Is the operand continuous? If so, we can just mask and OR it in 164193323Sed // instead of doing it bit-by-bit, saving a lot in runtime cost. 165193323Sed const std::string &VarName = Vals[i].getName(); 166193323Sed bool gotOp = false; 167193323Sed 168193323Sed for (int bit = BI->getNumBits()-1; bit >= 0; ) { 169193323Sed int varBit = getVariableBit(VarName, BI, bit); 170193323Sed 171193323Sed if (varBit == -1) { 172193323Sed --bit; 173193323Sed } else { 174193323Sed int beginInstBit = bit; 175193323Sed int beginVarBit = varBit; 176193323Sed int N = 1; 177193323Sed 178193323Sed for (--bit; bit >= 0;) { 179193323Sed varBit = getVariableBit(VarName, BI, bit); 180193323Sed if (varBit == -1 || varBit != (beginVarBit - N)) break; 181193323Sed ++N; 182193323Sed --bit; 183193323Sed } 184193323Sed 185193323Sed if (!gotOp) { 186193323Sed /// If this operand is not supposed to be emitted by the generated 187193323Sed /// emitter, skip it. 188193323Sed while (CGI.isFlatOperandNotEmitted(op)) 189193323Sed ++op; 190193323Sed 191193323Sed Case += " // op: " + VarName + "\n" 192193323Sed + " op = getMachineOpValue(MI, MI.getOperand(" 193193323Sed + utostr(op++) + "));\n"; 194193323Sed gotOp = true; 195193323Sed } 196193323Sed 197193323Sed unsigned opMask = ~0U >> (32-N); 198193323Sed int opShift = beginVarBit - N + 1; 199193323Sed opMask <<= opShift; 200193323Sed opShift = beginInstBit - beginVarBit; 201193323Sed 202193323Sed if (opShift > 0) { 203193323Sed Case += " Value |= (op & " + utostr(opMask) + "U) << " 204193323Sed + itostr(opShift) + ";\n"; 205193323Sed } else if (opShift < 0) { 206193323Sed Case += " Value |= (op & " + utostr(opMask) + "U) >> " 207193323Sed + itostr(-opShift) + ";\n"; 208193323Sed } else { 209193323Sed Case += " Value |= op & " + utostr(opMask) + "U;\n"; 210193323Sed } 211193323Sed } 212193323Sed } 213193323Sed } 214193323Sed } 215193323Sed 216193323Sed std::vector<std::string> &InstList = CaseMap[Case]; 217193323Sed InstList.push_back(InstName); 218193323Sed } 219193323Sed 220193323Sed 221193323Sed // Emit initial function code 222193323Sed o << " const unsigned opcode = MI.getOpcode();\n" 223193323Sed << " unsigned Value = InstBits[opcode];\n" 224193323Sed << " unsigned op = 0;\n" 225193323Sed << " op = op; // suppress warning\n" 226193323Sed << " switch (opcode) {\n"; 227193323Sed 228193323Sed // Emit each case statement 229193323Sed std::map<std::string, std::vector<std::string> >::iterator IE, EE; 230193323Sed for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { 231193323Sed const std::string &Case = IE->first; 232193323Sed std::vector<std::string> &InstList = IE->second; 233193323Sed 234193323Sed for (int i = 0, N = InstList.size(); i < N; i++) { 235193323Sed if (i) o << "\n"; 236193323Sed o << " case " << Namespace << InstList[i] << ":"; 237193323Sed } 238193323Sed o << " {\n"; 239193323Sed o << Case; 240193323Sed o << " break;\n" 241193323Sed << " }\n"; 242193323Sed } 243193323Sed 244193323Sed // Default case: unhandled opcode 245193323Sed o << " default:\n" 246193323Sed << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n" 247193323Sed << " abort();\n" 248193323Sed << " }\n" 249193323Sed << " return Value;\n" 250193323Sed << "}\n\n"; 251193323Sed} 252